USBDEV Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 2.070s 250.681us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.080s 92.544us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.130s 80.341us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 4.180s 714.321us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.430s 437.934us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.420s 94.522us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.130s 80.341us 20 20 100.00
usbdev_csr_aliasing 3.430s 437.934us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.110s 777.083us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 1.830s 78.756us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.790s 241.491us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 3.240s 638.304us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 1.180s 85.433us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.720s 218.751us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.113m 22.027ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.670s 329.300us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 1.550s 187.875us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.880s 261.386us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.800s 225.703us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.600s 245.449us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.360s 230.566us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.700s 210.003us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.730s 245.116us 50 50 100.00
usbdev_stream_len_max 6.080s 1.357ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.920s 255.942us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.640s 199.745us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.600s 223.520us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.710s 199.989us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.820s 210.600us 50 50 100.00
V2 out_stall usbdev_out_stall 1.720s 235.307us 50 50 100.00
V2 in_stall usbdev_in_stall 1.620s 203.108us 50 50 100.00
V2 out_iso usbdev_out_iso 1.760s 251.413us 50 50 100.00
V2 in_iso usbdev_in_iso 2.150s 245.663us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.650s 233.799us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.930s 247.019us 50 50 100.00
V2 disconnected usbdev_disconnected 1.490s 169.709us 50 50 100.00
V2 host_lost usbdev_host_lost 13.970s 4.202ms 1 1 100.00
V2 link_reset usbdev_link_reset 1.230s 182.193us 1 1 100.00
V2 link_suspend usbdev_link_suspend 24.130s 9.070ms 50 50 100.00
V2 link_resume usbdev_link_resume 1.220m 31.484ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.490s 179.679us 5 5 100.00
V2 rx_full usbdev_rx_full 2.370s 403.439us 50 50 100.00
V2 av_overflow usbdev_av_overflow 1.560s 147.883us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.810s 245.269us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.720s 251.666us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.580s 195.171us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.560s 169.003us 50 50 100.00
V2 link_out_err usbdev_link_out_err 2.600s 500.545us 1 1 100.00
V2 enable usbdev_enable 1.310s 115.821us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 45.700s 20.158ms 20 20 100.00
V2 device_address usbdev_device_address 1.637m 50.681ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 2.630s 543.306us 1 1 100.00
V2 setup_stage usbdev_setup_stage 1.500s 216.685us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 4.520s 904.134us 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 5.020s 1.151ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 3.180s 862.599us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.670s 237.853us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.520s 162.420us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.940s 258.659us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.710s 223.491us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 2.040s 323.656us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.550s 188.482us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.600s 227.407us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.842m 4.072ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 4.162m 119.209ms 5 5 100.00
usbdev_freq_loclk 4.508m 112.123ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 4.112m 114.316ms 5 5 100.00
usbdev_freq_loclk_max 3.891m 116.007ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.720m 107.114ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 2.014m 4.196ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 2.006m 4.014ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 55.130s 6.144ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 49.930s 8.375ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.113m 22.027ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 2.650s 528.221us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 1.151m 30.147ms 49 50 98.00
V2 aon_wake_reset usbdev_aon_wake_reset 44.850s 21.164ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 22.580s 9.725ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.068m 4.932ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.589m 3.520ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.162m 4.698ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 2.840m 6.592ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 1.594m 3.673ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 5.079m 14.691ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.261m 2.911ms 25 25 100.00
usbdev_max_usb_traffic 1.675m 3.470ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 3.667m 8.855ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.157m 11.023ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 5.160s 1.071ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 2.580s 491.024us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 3.680s 330.763us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 3.080s 636.975us 500 500 100.00
V2 intr_test usbdev_intr_test 0.950s 81.589us 50 50 100.00
V2 alert_test usbdev_alert_test 1.180s 86.005us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.050s 262.440us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.050s 262.440us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.080s 92.544us 5 5 100.00
usbdev_csr_rw 1.130s 80.341us 20 20 100.00
usbdev_csr_aliasing 3.430s 437.934us 5 5 100.00
usbdev_same_csr_outstanding 1.930s 320.051us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.080s 92.544us 5 5 100.00
usbdev_csr_rw 1.130s 80.341us 20 20 100.00
usbdev_csr_aliasing 3.430s 437.934us 5 5 100.00
usbdev_same_csr_outstanding 1.930s 320.051us 20 20 100.00
V2 TOTAL 3598 3599 99.97
V2S tl_intg_err usbdev_sec_cm 3.260s 960.805us 5 5 100.00
usbdev_tl_intg_err 6.290s 2.643ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 6.290s 2.643ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 37.750s 5.137ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 1.070s 53.076us 0 10 0.00
usbdev_stress_all 0.890s 0 50 0.00
TOTAL 3739 3800 98.39

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 84 98.82
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.54 98.11 96.01 97.44 94.92 98.30 98.17 92.85

Failure Buckets

Past Results