USBDEV Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.970s 270.356us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.500s 123.249us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.690s 121.116us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 11.700s 3.502ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 4.540s 131.913us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 3.590s 131.887us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.690s 121.116us 20 20 100.00
usbdev_csr_aliasing 4.540s 131.913us 5 5 100.00
V1 mem_walk usbdev_mem_walk 6.610s 528.170us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 3.540s 195.076us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 2.030s 284.217us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 2.890s 496.661us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 1.190s 67.326us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.580s 207.579us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.084m 21.776ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 2.060s 332.995us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 1.180s 152.980us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.990s 320.597us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.860s 245.766us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.800s 205.414us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.560s 200.391us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.480s 183.194us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.680s 205.113us 50 50 100.00
usbdev_stream_len_max 5.100s 1.018ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.980s 291.830us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.510s 174.733us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.620s 173.722us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.730s 242.898us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.800s 257.535us 50 50 100.00
V2 out_stall usbdev_out_stall 1.750s 212.742us 50 50 100.00
V2 in_stall usbdev_in_stall 1.680s 212.289us 50 50 100.00
V2 out_iso usbdev_out_iso 1.760s 233.038us 50 50 100.00
V2 in_iso usbdev_in_iso 2.170s 260.240us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.790s 215.576us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.870s 246.141us 50 50 100.00
V2 disconnected usbdev_disconnected 1.490s 189.287us 50 50 100.00
V2 host_lost usbdev_host_lost 17.910s 4.216ms 1 1 100.00
V2 link_reset usbdev_link_reset 1.480s 186.397us 1 1 100.00
V2 link_suspend usbdev_link_suspend 26.870s 10.955ms 50 50 100.00
V2 link_resume usbdev_link_resume 1.172m 32.978ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.530s 175.724us 5 5 100.00
V2 rx_full usbdev_rx_full 2.530s 432.443us 50 50 100.00
V2 av_overflow usbdev_av_overflow 1.430s 141.138us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.750s 211.080us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.710s 215.727us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.540s 194.246us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.590s 221.796us 50 50 100.00
V2 link_out_err usbdev_link_out_err 2.660s 497.541us 1 1 100.00
V2 enable usbdev_enable 1.220s 58.071us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 1.120m 20.223ms 20 20 100.00
V2 device_address usbdev_device_address 2.330m 52.598ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 2.850s 510.815us 1 1 100.00
V2 setup_stage usbdev_setup_stage 1.560s 222.478us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 4.630s 941.579us 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 4.650s 1.081ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 2.860s 492.686us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.750s 238.082us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.550s 220.313us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.730s 231.009us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.580s 188.980us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.840s 317.186us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.660s 233.834us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.660s 204.043us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.674m 2.911ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 4.887m 88.187ms 5 5 100.00
usbdev_freq_loclk 3.781m 107.100ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.574m 105.177ms 5 5 100.00
usbdev_freq_loclk_max 4.104m 108.222ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 4.058m 103.122ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.938m 3.708ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.761m 4.126ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 49.250s 6.618ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 1.148m 8.392ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.084m 21.776ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 3.020s 486.108us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 1.089m 28.669ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 40.870s 19.610ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 28.920s 9.771ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.149m 4.871ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.685m 3.057ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.491m 4.356ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 3.587m 10.663ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 1.960m 4.066ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 6.476m 17.506ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.885m 3.433ms 25 25 100.00
usbdev_max_usb_traffic 1.552m 3.156ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 5.064m 11.111ms 10 10 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.615m 13.102ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 5.910s 1.153ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 2.900s 418.549us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 5.020s 454.212us 50 50 100.00
V2 tx_rx_disruption usbdev_tx_rx_disruption 3.220s 569.193us 500 500 100.00
V2 fifo_levels usbdev_fifo_levels 2.060s 315.849us 160 160 100.00
V2 intr_test usbdev_intr_test 1.330s 94.799us 50 50 100.00
V2 alert_test usbdev_alert_test 1.170s 107.281us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 4.490s 302.511us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 4.490s 302.511us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.500s 123.249us 5 5 100.00
usbdev_csr_rw 1.690s 121.116us 20 20 100.00
usbdev_csr_aliasing 4.540s 131.913us 5 5 100.00
usbdev_same_csr_outstanding 2.880s 384.327us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.500s 123.249us 5 5 100.00
usbdev_csr_rw 1.690s 121.116us 20 20 100.00
usbdev_csr_aliasing 4.540s 131.913us 5 5 100.00
usbdev_same_csr_outstanding 2.880s 384.327us 20 20 100.00
V2 TOTAL 3764 3764 100.00
V2S tl_intg_err usbdev_sec_cm 3.040s 1.014ms 5 5 100.00
usbdev_tl_intg_err 7.620s 2.521ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 7.620s 2.521ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 2.631m 5.113ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 1.090s 82.170us 0 10 0.00
usbdev_stress_all 0.890s 0 50 0.00
TOTAL 3905 3965 98.49

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 86 86 86 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.39 98.22 96.08 97.44 94.92 98.38 98.17 98.55

Failure Buckets

Past Results