USBDEV Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 2.210s 333.030us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.150s 153.678us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.290s 67.928us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 5.960s 568.348us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.410s 372.212us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.020s 86.379us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.290s 67.928us 20 20 100.00
usbdev_csr_aliasing 3.410s 372.212us 5 5 100.00
V1 mem_walk usbdev_mem_walk 3.850s 481.369us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.390s 224.235us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.850s 254.094us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 3.560s 662.603us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 1.220s 83.651us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.900s 266.733us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.267m 22.143ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.850s 318.674us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 1.480s 173.730us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 2.180s 311.239us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.980s 289.429us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.400s 201.399us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.660s 215.545us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.580s 193.294us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.810s 226.723us 50 50 100.00
usbdev_stream_len_max 5.930s 1.302ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 2.090s 341.710us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.600s 206.220us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.680s 246.089us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.700s 230.420us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.860s 263.427us 50 50 100.00
V2 out_stall usbdev_out_stall 1.740s 227.337us 50 50 100.00
V2 in_stall usbdev_in_stall 1.600s 210.152us 50 50 100.00
V2 out_iso usbdev_out_iso 1.720s 190.825us 50 50 100.00
V2 in_iso usbdev_in_iso 2.200s 275.792us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.690s 211.344us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.910s 306.518us 50 50 100.00
V2 disconnected usbdev_disconnected 1.540s 190.676us 50 50 100.00
V2 host_lost usbdev_host_lost 10.000s 4.172ms 1 1 100.00
V2 link_reset usbdev_link_reset 1.390s 163.775us 1 1 100.00
V2 link_suspend usbdev_link_suspend 31.080s 10.005ms 50 50 100.00
V2 link_resume usbdev_link_resume 1.378m 30.467ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.710s 239.345us 5 5 100.00
V2 rx_full usbdev_rx_full 2.610s 403.052us 50 50 100.00
V2 av_overflow usbdev_av_overflow 1.500s 163.236us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.950s 268.738us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.640s 197.210us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.520s 171.126us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.590s 157.648us 50 50 100.00
V2 link_out_err usbdev_link_out_err 2.300s 406.920us 1 1 100.00
V2 enable usbdev_enable 1.260s 84.517us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 53.720s 20.216ms 20 20 100.00
V2 device_address usbdev_device_address 2.406m 50.134ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 3.260s 520.245us 1 1 100.00
V2 setup_stage usbdev_setup_stage 1.610s 199.167us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 5.320s 951.356us 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 4.610s 1.127ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 3.380s 673.942us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.770s 251.151us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.580s 178.645us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.860s 272.920us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.690s 219.143us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 2.100s 358.984us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.810s 245.641us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.830s 246.481us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.958m 4.111ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.747m 110.196ms 5 5 100.00
usbdev_freq_loclk 3.824m 100.174ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 4.634m 120.341ms 5 5 100.00
usbdev_freq_loclk_max 4.759m 120.972ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 4.078m 100.176ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 2.073m 3.759ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.914m 3.809ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 56.740s 1.701ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 1.098m 9.059ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.267m 22.143ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 2.870s 510.958us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 1.528m 29.649ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 48.910s 19.135ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 32.100s 12.042ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.821m 5.355ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.912m 3.010ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.559m 4.229ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 2.856m 9.557ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 3.507m 9.711ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 2.786m 10.102ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.626m 3.298ms 25 25 100.00
usbdev_max_usb_traffic 1.713m 2.732ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 6.052m 12.827ms 10 10 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.598m 12.135ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 6.500s 1.375ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 2.890s 440.319us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 5.070s 533.376us 50 50 100.00
V2 tx_rx_disruption usbdev_tx_rx_disruption 1.017m 498 500 99.60
V2 fifo_levels usbdev_fifo_levels 2.070s 284.275us 160 160 100.00
V2 intr_test usbdev_intr_test 0.950s 52.996us 50 50 100.00
V2 alert_test usbdev_alert_test 1.190s 100.999us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.660s 380.898us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.660s 380.898us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.150s 153.678us 5 5 100.00
usbdev_csr_rw 1.290s 67.928us 20 20 100.00
usbdev_csr_aliasing 3.410s 372.212us 5 5 100.00
usbdev_same_csr_outstanding 1.980s 186.458us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.150s 153.678us 5 5 100.00
usbdev_csr_rw 1.290s 67.928us 20 20 100.00
usbdev_csr_aliasing 3.410s 372.212us 5 5 100.00
usbdev_same_csr_outstanding 1.980s 186.458us 20 20 100.00
V2 TOTAL 3762 3764 99.95
V2S tl_intg_err usbdev_sec_cm 4.280s 1.173ms 5 5 100.00
usbdev_tl_intg_err 5.130s 1.362ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.130s 1.362ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 53.760s 5.113ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 1.050s 57.431us 0 10 0.00
usbdev_stress_all 0.870s 0 50 0.00
TOTAL 3903 3965 98.44

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 86 86 85 98.84
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.16 98.22 96.03 97.44 93.22 98.38 98.17 98.64

Failure Buckets

Past Results