e3fb01b5e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 16.140m | 5.750ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 16.140m | 5.750ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 16.568m | 5.437ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 17.317m | 5.627ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 17.746m | 6.169ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 58.116m | 23.436ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 1.074h | 22.863ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 42.333m | 23.820ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 6.947m | 3.828ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 6.947m | 3.828ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 6.947m | 3.828ms | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_flash | 3.855m | 2.486ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.337m | 2.533ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 5.009m | 3.094ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.870m | 2.677ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 35.531m | 8.178ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 6.396m | 7.124ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 10.710m | 4.708ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 50.444m | 26.489ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.216h | 48.907ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 7.182m | 9.153ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.216h | 48.907ms | 5 | 5 | 100.00 |
| chip_csr_rw | 10.710m | 4.708ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 10.380s | 241.992us | 100 | 100 | 100.00 |
| V1 | TOTAL | 223 | 223 | 100.00 | |||
| V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | 8.172m | 3.705ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 3.079h | 70.353ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 12.929m | 7.200ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 10.582m | 4.670ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.913m | 3.045ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.057m | 2.886ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 10.791m | 4.191ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 12.103m | 4.294ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 8.124m | 4.344ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 11.295m | 4.027ms | 3 | 3 | 100.00 |
| V2 | chip_sw_usbdev_dpi | chip_sw_usbdev_dpi | 25.771m | 7.647ms | 1 | 1 | 100.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.641m | 4.806ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.641m | 4.806ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.386m | 3.082ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 4.319m | 2.668ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.925m | 4.274ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 25.703m | 15.030ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 12.383m | 7.530ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 13.572m | 8.587ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 30.889m | 18.956ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.785m | 2.946ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 24.234m | 7.552ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 12.716m | 6.099ms | 5 | 6 | 83.33 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 12.716m | 6.099ms | 5 | 6 | 83.33 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 34.784m | 18.874ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 23.570m | 12.961ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 7.294m | 4.526ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.921m | 4.702ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 7.771m | 6.105ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 13.572m | 8.587ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 10.113m | 17.768ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.532m | 3.361ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 8.740m | 4.226ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 6.924m | 5.954ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 8.740m | 4.226ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 11.418m | 5.403ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.279m | 7.295ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.279m | 7.295ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 8.085m | 7.725ms | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 28.898m | 8.151ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.460m | 2.840ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 10.668m | 5.887ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 3.990m | 2.798ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.740m | 2.667ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 5.317m | 3.227ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.652m | 5.262ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 8.562m | 5.231ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.447m | 5.614ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 8.428m | 3.892ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 29.573m | 9.846ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_lc | 8.076m | 5.817ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.705m | 4.422ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.605m | 4.879ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.425m | 4.122ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.793m | 4.428ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.563m | 4.011ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.666m | 5.081ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 8.076m | 5.817ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.705m | 4.422ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.605m | 4.879ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.425m | 4.122ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.793m | 4.428ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.563m | 4.011ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.666m | 5.081ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 16.462m | 5.066ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.204m | 6.031ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.013h | 20.993ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 3.875m | 2.790ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 16.797m | 5.474ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.267m | 3.053ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 8.983m | 4.964ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.172m | 2.733ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 12.788m | 5.734ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.496m | 2.165ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.162m | 2.591ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 16.403m | 6.452ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 22.477m | 8.346ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 58.265m | 28.914ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.214m | 3.309ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.817m | 3.402ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 8.079m | 3.852ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.016m | 2.730ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 9.357m | 5.733ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 31.758m | 19.636ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 53.797m | 19.344ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 17.954m | 6.661ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.664m | 4.329ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.041m | 3.755ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 13.840m | 4.722ms | 100 | 100 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 9.098m | 8.623ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 27.136m | 19.803ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 6.850m | 7.205ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 14.279m | 7.295ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 28.733m | 17.071ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 33.069m | 16.044ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 39.584m | 22.067ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 8.896m | 5.354ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 9.098m | 8.623ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 9.044m | 4.346ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 56.074m | 31.584ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 8.037m | 6.077ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 8.677m | 6.189ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 55.736m | 35.596ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 15.395m | 7.091ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 39.761m | 21.242ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.560m | 3.181ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 13.840m | 4.722ms | 100 | 100 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 6.924m | 5.954ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 7.294m | 4.526ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 14.901m | 5.668ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 7.259m | 3.565ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 25.545m | 9.247ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 3.867m | 3.336ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 13.840m | 4.722ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.394m | 2.954ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 7.534m | 5.228ms | 3 | 3 | 100.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 13.840m | 4.722ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 28.898m | 8.151ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.126m | 3.774ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 25.545m | 9.247ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 10.326m | 5.053ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.229m | 3.951ms | 90 | 90 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 23.327m | 9.489ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 34.039m | 9.598ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 31.563m | 8.936ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.356h | 254.322ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 7.534m | 5.228ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 25.703m | 15.030ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 13.572m | 8.587ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 30.889m | 18.956ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 5.186m | 2.718ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 20.853m | 9.819ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 20.853m | 9.819ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 20.853m | 9.819ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 9.027m | 4.777ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 8.027m | 4.813ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.269h | 42.774ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.696m | 5.078ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 20.433m | 7.533ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 21.932m | 8.890ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 20.571m | 7.854ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 20.853m | 9.819ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.027m | 4.133ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 11.840m | 8.410ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 15.698m | 7.760ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 4.958m | 7.993ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 8.076m | 5.817ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.705m | 4.422ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.605m | 4.879ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.425m | 4.122ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.793m | 4.428ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.563m | 4.011ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.666m | 5.081ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 25.703m | 15.030ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 13.572m | 8.587ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 30.889m | 18.956ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 10.113m | 17.768ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.274m | 2.939ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 5.732m | 3.571ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 11.176m | 4.924ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 28.900m | 23.287ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | 28.900m | 23.287ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 28.900m | 23.287ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 49.886m | 20.004ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 49.886m | 20.004ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.442m | 6.357ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.936m | 18.226ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.936m | 18.226ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.936m | 18.226ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 4.562m | 2.557ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 3.875m | 2.790ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.975m | 2.885ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 3.990m | 2.798ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 10.204m | 5.433ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.579m | 3.162ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.267m | 3.053ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.740m | 2.667ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.883m | 2.204ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.983m | 2.961ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.172m | 2.733ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 9.027m | 4.133ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 20.853m | 9.819ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.213m | 2.801ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.301m | 3.024ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.317m | 3.227ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.090m | 3.276ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 25.025m | 7.099ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 10.401m | 4.752ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 5.093m | 2.991ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 25.025m | 7.099ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 7.155m | 3.585ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 11.016m | 6.560ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.491m | 2.672ms | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 50.568m | 13.654ms | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 19.342m | 5.131ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 9.027m | 4.133ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 8.983m | 4.964ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 9.313m | 4.710ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 10.204m | 5.433ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 42.828m | 9.540ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 56.191m | 19.977ms | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.013h | 20.993ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 10.668m | 5.887ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 10.668m | 5.887ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 10.668m | 5.887ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 8.042m | 3.467ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 11.840m | 8.410ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 11.840m | 8.410ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 8.811m | 3.488ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 12.788m | 5.734ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 22.309m | 13.411ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 15.698m | 7.760ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 13.840m | 4.722ms | 100 | 100 | 100.00 |
| chip_sw_data_integrity_escalation | 12.716m | 6.099ms | 5 | 6 | 83.33 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 20.853m | 9.819ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 35.165m | 22.741ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.042m | 3.467ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.027m | 4.133ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 8.811m | 3.488ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.150m | 3.157ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 35.165m | 22.741ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.042m | 3.467ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.027m | 4.133ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 8.811m | 3.488ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.150m | 3.157ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 20.853m | 9.819ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 7.798m | 5.000ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 5.186m | 2.718ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.696m | 5.078ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 20.433m | 7.533ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 21.932m | 8.890ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 20.571m | 7.854ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 20.853m | 9.819ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 4.958m | 7.993ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 4.958m | 7.993ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_init | chip_sw_flash_init | 35.165m | 22.741ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 19.622m | 5.839ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.204m | 6.031ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 15.728m | 5.292ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 16.462m | 5.066ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.269h | 42.774ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 35.165m | 22.741ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.115m | 3.373ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 9.027m | 4.133ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 8.027m | 4.813ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.269h | 42.774ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 8.027m | 4.813ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 8.027m | 4.813ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 8.027m | 4.813ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 8.027m | 4.813ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 13.840m | 4.722ms | 100 | 100 | 100.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 4.958m | 7.993ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 19.463m | 6.407ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 12.646m | 5.750ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 17.954m | 6.661ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 13.809m | 11.184ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 16.462m | 5.066ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.204m | 6.031ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.013h | 20.993ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 3.875m | 2.790ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 16.797m | 5.474ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.267m | 3.053ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 8.983m | 4.964ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.172m | 2.733ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 12.788m | 5.734ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.496m | 2.165ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 6.210m | 2.890ms | 1 | 1 | 100.00 |
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 27.450m | 10.786ms | 5 | 5 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 27.450m | 10.786ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.143m | 5.369ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 5.276m | 2.793ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.143m | 5.369ms | 3 | 3 | 100.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 13.331m | 4.831ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 17.873m | 6.032ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 5.216m | 2.221ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 4.150m | 3.157ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 14.901m | 5.668ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 14.901m | 5.668ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.911m | 2.966ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 3.516m | 2.737ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.276m | 3.119ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 3.722m | 2.576ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.257m | 2.819ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 8.428m | 3.274ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.260m | 2.831ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.971m | 3.728ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 5.346m | 2.618ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 33.207m | 11.535ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 5.715m | 2.403ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 6.924m | 5.954ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 9.071m | 5.466ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.545m | 3.288ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 5.270m | 3.221ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.900m | 2.985ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 3.993m | 3.042ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.737m | 2.789ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 12.164m | 4.790ms | 3 | 3 | 100.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 35.531m | 8.178ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.079h | 70.353ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 35.282m | 8.844ms | 3 | 3 | 100.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 3.789m | 3.887ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.830m | 3.556ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.298m | 2.612ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 3.499m | 2.727ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 38.541m | 29.017ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 10.113m | 17.768ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.462h | 51.132ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.423h | 52.154ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 14.994m | 10.645ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.300h | 49.499ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 38.541m | 29.017ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 6.005m | 4.554ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 5.841m | 3.883ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz | 5.898m | 4.487ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 5.351h | 116.490ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 11.454m | 4.591ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 10.351m | 10.349ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.772h | 60.514ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.086h | 65.370ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 8.264m | 5.589ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 8.264m | 5.589ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.216h | 48.907ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.221h | 27.072ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.396m | 7.124ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 10.710m | 4.708ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.216h | 48.907ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.221h | 27.072ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.396m | 7.124ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 10.710m | 4.708ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.674m | 2.502ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.070s | 45.805us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 1.904m | 10.432ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 1.963m | 6.737ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 52.440s | 548.514us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 22.102m | 106.196ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 22.005m | 61.111ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 57.930s | 1.265ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 56.540s | 1.331ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.509m | 2.436ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 56.540s | 1.331ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.671m | 3.883ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 55.893m | 180.581ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.483m | 2.756ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 15.154m | 24.410ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 11.088m | 19.114ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 20.195m | 24.233ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 16.814m | 8.661ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 35.282m | 8.844ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 41.447m | 21.232ms | 2 | 3 | 66.67 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 34.741m | 9.035ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 3.854h | 77.518ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 33.306m | 9.437ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 31.152m | 9.196ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 32.422m | 8.548ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 32.533m | 8.178ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 3.799h | 77.668ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 32.251m | 7.921ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 31.230m | 8.795ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 31.158m | 9.339ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 30.443m | 8.929ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 7.164h | 151.343ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 42.180m | 11.875ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 46.010m | 11.997ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 45.521m | 12.435ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 44.422m | 12.241ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 7.383h | 152.096ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 45.277m | 11.590ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 42.401m | 11.861ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 44.050m | 12.539ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 43.574m | 11.640ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 3.710h | 77.479ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 31.959m | 8.601ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 33.007m | 7.985ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 30.070m | 8.597ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 34.388m | 7.987ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 3.929h | 78.301ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 32.926m | 7.770ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 29.442m | 8.402ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 30.645m | 9.070ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 26.963m | 8.388ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 3.720h | 76.647ms | 3 | 3 | 100.00 |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 3.759h | 76.773ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 31.512m | 8.579ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 35.376m | 8.653ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 35.537m | 8.902ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 32.222m | 8.384ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 33.257m | 8.544ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 35.771m | 9.464ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 29.466m | 8.754ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 35.609m | 9.074ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 3.779h | 77.961ms | 0 | 3 | 0.00 |
| rom_e2e_asm_init_dev | 33.662m | 8.666ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod | 32.298m | 8.652ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod_end | 36.239m | 8.209ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_rma | 31.000m | 9.009ms | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 32.855m | 8.662ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 34.163m | 9.084ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 32.958m | 8.710ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 37.843m | 11.206ms | 3 | 3 | 100.00 |
| V2 | TOTAL | 2634 | 2651 | 99.36 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.042m | 2.805ms | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 4.878m | 2.446ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_usb_fs_tx_rx | chip_sw_usbdev_stream | 48.110m | 13.209ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usb_vbus | chip_sw_usb_vbus | 0 | 0 | -- | ||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_sof | chip_usb_sof | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_usb_enumeration | chip_usb_enumeration | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 34.444m | 11.466ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 32.247m | 11.638ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 29.735m | 11.256ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 10.252m | 5.452ms | 3 | 3 | 100.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 13.840m | 4.722ms | 100 | 100 | 100.00 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 3.985m | 2.680ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 11.277m | 5.816ms | 1 | 1 | 100.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.170s | 0 | 1 | 0.00 | |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 35.809m | 9.503ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 34.444m | 11.466ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 32.247m | 11.638ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 29.735m | 11.256ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 52.622m | 42.854ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 58.286m | 32.395ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 44.423m | 32.883ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | TOTAL | 17 | 18 | 94.44 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 12.122m | 4.969ms | 3 | 3 | 100.00 | |
| TOTAL | 2883 | 2901 | 99.38 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 19 | 19 | 19 | 100.00 |
| V2 | 270 | 270 | 263 | 97.41 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 26 | 12 | 11 | 42.31 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.72 | 95.61 | 94.14 | 98.30 | -- | 94.70 | 97.93 | 99.64 |
UVM_ERROR @ * us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[*] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (* [*] vs * [*]) has 15 failures:
0.rom_e2e_asm_init_test_unlocked0.3995100201
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log
UVM_ERROR @ 78307.090940 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 78307.090940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_test_unlocked0.964846370
Line 1107, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log
UVM_ERROR @ 78186.167424 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 78186.167424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_dev.4256825515
Line 1095, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log
UVM_ERROR @ 8666.247296 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8666.247296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_dev.1471069964
Line 1093, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log
UVM_ERROR @ 8309.283680 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8309.283680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_prod.874685963
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log
UVM_ERROR @ 8651.513130 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8651.513130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_prod.3124781190
Line 1096, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log
UVM_ERROR @ 8586.102968 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8586.102968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_prod_end.2652526909
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log
UVM_ERROR @ 8208.663756 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8208.663756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_prod_end.3679231024
Line 1104, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log
UVM_ERROR @ 8066.405100 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8066.405100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_rma.3632596128
Line 1099, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log
UVM_ERROR @ 9008.505416 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 9008.505416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_rma.2844085801
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log
UVM_ERROR @ 8955.148980 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8955.148980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (uart_logger.sv:25) [m_logger] Check failed (!logs_output_fd) Failed to open log for writing has 1 failures:
0.chip_sw_coremark.4283114775
Line 1047, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
UVM_FATAL @ 0.000000 us: (uart_logger.sv:25) [uvm_test_top.env.m_uart_agent0.m_logger] Check failed (!logs_output_fd) Failed to open uvm_test_top.env.m_uart_agent0.m_logger.log for writing
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
0.rom_e2e_shutdown_output.3515180540
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
Job ID: smart:5157a94c-8920-4e89-845d-08332ca384ee
UVM_ERROR @ * us: (sw_logger_if.sv:523) [data_integrity_escalation_reset_test_prog_sim_dv(sw/device/tests/sim_dv/data_integrity_escalation_reset_test.c:370)] CHECK-fail: Alert handler NMI state not expected: has 1 failures:
5.chip_sw_data_integrity_escalation.792695357
Line 1095, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest/run.log
UVM_ERROR @ 3422.059146 us: (sw_logger_if.sv:523) [data_integrity_escalation_reset_test_prog_sim_dv(sw/device/tests/sim_dv/data_integrity_escalation_reset_test.c:370)] CHECK-fail: Alert handler NMI state not expected:
alert_enable:1
alert_raised:0
UVM_INFO @ 3422.059146 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---