Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.36 88.56 85.90 70.07 86.52 88.35 98.79


Total test records in report: 1927
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T133 /workspace/coverage/cover_reg_top/24.xbar_random.2601601073 Dec 24 02:11:25 PM PST 23 Dec 24 02:12:04 PM PST 23 445026001 ps
T44 /workspace/coverage/cover_reg_top/4.chip_csr_rw.3352131911 Dec 24 02:09:53 PM PST 23 Dec 24 02:15:26 PM PST 23 4639858892 ps
T489 /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.4259740504 Dec 24 02:15:24 PM PST 23 Dec 24 02:15:30 PM PST 23 50286118 ps
T146 /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1193794574 Dec 24 02:09:53 PM PST 23 Dec 24 02:27:41 PM PST 23 60417608758 ps
T34 /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1475240714 Dec 24 02:09:44 PM PST 23 Dec 24 03:02:22 PM PST 23 29136255109 ps
T490 /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2729530135 Dec 24 02:14:26 PM PST 23 Dec 24 02:15:47 PM PST 23 4814591613 ps
T90 /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.896836821 Dec 24 02:16:41 PM PST 23 Dec 24 02:20:18 PM PST 23 2730855655 ps
T491 /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1977741753 Dec 24 02:15:57 PM PST 23 Dec 24 02:17:31 PM PST 23 5612003020 ps
T492 /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2855413841 Dec 24 02:16:41 PM PST 23 Dec 24 02:16:53 PM PST 23 51937749 ps
T493 /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2841328252 Dec 24 02:12:14 PM PST 23 Dec 24 02:12:38 PM PST 23 154349482 ps
T150 /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.1599934093 Dec 24 02:11:10 PM PST 23 Dec 24 02:11:31 PM PST 23 231223737 ps
T327 /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.3722165314 Dec 24 02:13:27 PM PST 23 Dec 24 02:15:12 PM PST 23 6632304922 ps
T494 /workspace/coverage/cover_reg_top/90.xbar_smoke.147947696 Dec 24 02:16:05 PM PST 23 Dec 24 02:16:11 PM PST 23 43202239 ps
T495 /workspace/coverage/cover_reg_top/7.xbar_error_random.30228077 Dec 24 02:10:33 PM PST 23 Dec 24 02:10:42 PM PST 23 152562212 ps
T59 /workspace/coverage/cover_reg_top/16.chip_csr_rw.2834598673 Dec 24 02:10:52 PM PST 23 Dec 24 02:18:59 PM PST 23 5328884324 ps
T294 /workspace/coverage/cover_reg_top/51.xbar_same_source.4264784157 Dec 24 02:13:17 PM PST 23 Dec 24 02:14:02 PM PST 23 1426320554 ps
T380 /workspace/coverage/cover_reg_top/6.xbar_access_same_device.9649969 Dec 24 02:10:09 PM PST 23 Dec 24 02:12:19 PM PST 23 3229198882 ps
T35 /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.346626741 Dec 24 02:09:53 PM PST 23 Dec 24 03:21:01 PM PST 23 34047970695 ps
T369 /workspace/coverage/cover_reg_top/13.xbar_access_same_device.2106005649 Dec 24 02:10:30 PM PST 23 Dec 24 02:12:19 PM PST 23 2419398968 ps
T186 /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.4124040231 Dec 24 02:11:25 PM PST 23 Dec 24 02:22:23 PM PST 23 42293422268 ps
T144 /workspace/coverage/cover_reg_top/32.xbar_random.3774156278 Dec 24 02:11:18 PM PST 23 Dec 24 02:12:12 PM PST 23 629894210 ps
T141 /workspace/coverage/cover_reg_top/66.xbar_same_source.863236743 Dec 24 02:14:27 PM PST 23 Dec 24 02:15:05 PM PST 23 1313358093 ps
T147 /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.2807705420 Dec 24 02:13:45 PM PST 23 Dec 24 02:29:38 PM PST 23 81353563557 ps
T160 /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2190599249 Dec 24 02:14:49 PM PST 23 Dec 24 02:19:02 PM PST 23 549162492 ps
T417 /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3102288858 Dec 24 02:15:59 PM PST 23 Dec 24 02:19:35 PM PST 23 718631401 ps
T233 /workspace/coverage/cover_reg_top/15.xbar_same_source.1799126464 Dec 24 02:10:29 PM PST 23 Dec 24 02:10:53 PM PST 23 647960228 ps
T256 /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.753278513 Dec 24 02:11:11 PM PST 23 Dec 24 02:17:50 PM PST 23 24541982295 ps
T360 /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2164705502 Dec 24 02:13:51 PM PST 23 Dec 24 02:33:56 PM PST 23 70676368092 ps
T496 /workspace/coverage/cover_reg_top/63.xbar_access_same_device.418955848 Dec 24 02:14:29 PM PST 23 Dec 24 02:15:13 PM PST 23 432225791 ps
T60 /workspace/coverage/cover_reg_top/14.chip_csr_rw.3550163183 Dec 24 02:11:21 PM PST 23 Dec 24 02:20:28 PM PST 23 5161221268 ps
T375 /workspace/coverage/cover_reg_top/26.xbar_access_same_device.333043772 Dec 24 02:11:08 PM PST 23 Dec 24 02:12:35 PM PST 23 2290014283 ps
T394 /workspace/coverage/cover_reg_top/94.xbar_access_same_device.1232986209 Dec 24 02:16:38 PM PST 23 Dec 24 02:17:23 PM PST 23 1059392582 ps
T124 /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.296328620 Dec 24 02:10:39 PM PST 23 Dec 24 02:24:46 PM PST 23 8019371783 ps
T497 /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.4079361595 Dec 24 02:12:20 PM PST 23 Dec 24 02:13:56 PM PST 23 8670739004 ps
T498 /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.2912890722 Dec 24 02:11:19 PM PST 23 Dec 24 02:11:48 PM PST 23 205801852 ps
T320 /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.3455686651 Dec 24 02:16:08 PM PST 23 Dec 24 02:17:48 PM PST 23 8483746370 ps
T155 /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3338691883 Dec 24 02:16:57 PM PST 23 Dec 24 02:20:45 PM PST 23 13182584200 ps
T169 /workspace/coverage/cover_reg_top/12.xbar_stress_all.3777637924 Dec 24 02:10:11 PM PST 23 Dec 24 02:18:22 PM PST 23 12948382180 ps
T499 /workspace/coverage/cover_reg_top/57.xbar_smoke.463729383 Dec 24 02:13:39 PM PST 23 Dec 24 02:13:50 PM PST 23 252317006 ps
T500 /workspace/coverage/cover_reg_top/95.xbar_error_random.3641054823 Dec 24 02:16:42 PM PST 23 Dec 24 02:17:29 PM PST 23 1422924532 ps
T501 /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2410927126 Dec 24 02:11:22 PM PST 23 Dec 24 02:12:16 PM PST 23 4968273832 ps
T363 /workspace/coverage/cover_reg_top/98.xbar_access_same_device.25276769 Dec 24 02:16:54 PM PST 23 Dec 24 02:17:56 PM PST 23 929686785 ps
T502 /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.895582394 Dec 24 02:13:22 PM PST 23 Dec 24 02:14:36 PM PST 23 4141766878 ps
T275 /workspace/coverage/cover_reg_top/19.xbar_random.3815214487 Dec 24 02:11:07 PM PST 23 Dec 24 02:11:14 PM PST 23 40314556 ps
T265 /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3751743343 Dec 24 02:13:30 PM PST 23 Dec 24 02:14:32 PM PST 23 128814365 ps
T503 /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.4072044746 Dec 24 02:14:32 PM PST 23 Dec 24 02:14:40 PM PST 23 39734299 ps
T196 /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.2817900511 Dec 24 02:13:27 PM PST 23 Dec 24 02:25:08 PM PST 23 72672444390 ps
T117 /workspace/coverage/cover_reg_top/60.xbar_same_source.3760470980 Dec 24 02:14:01 PM PST 23 Dec 24 02:14:35 PM PST 23 493440376 ps
T504 /workspace/coverage/cover_reg_top/6.xbar_smoke.3976274934 Dec 24 02:09:59 PM PST 23 Dec 24 02:10:08 PM PST 23 44437711 ps
T164 /workspace/coverage/cover_reg_top/13.xbar_stress_all.662122979 Dec 24 02:10:30 PM PST 23 Dec 24 02:15:37 PM PST 23 7829185572 ps
T505 /workspace/coverage/cover_reg_top/42.xbar_access_same_device.867214206 Dec 24 02:12:20 PM PST 23 Dec 24 02:13:28 PM PST 23 912881861 ps
T364 /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2024250988 Dec 24 02:10:29 PM PST 23 Dec 24 02:11:13 PM PST 23 583718340 ps
T94 /workspace/coverage/cover_reg_top/19.chip_csr_rw.3618174824 Dec 24 02:11:10 PM PST 23 Dec 24 02:16:20 PM PST 23 4392030196 ps
T506 /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.2773966911 Dec 24 02:14:29 PM PST 23 Dec 24 02:17:24 PM PST 23 15512234138 ps
T507 /workspace/coverage/cover_reg_top/80.xbar_error_random.2254117230 Dec 24 02:15:41 PM PST 23 Dec 24 02:16:20 PM PST 23 1153479203 ps
T508 /workspace/coverage/cover_reg_top/47.xbar_stress_all.2587089257 Dec 24 02:12:55 PM PST 23 Dec 24 02:12:59 PM PST 23 6318063 ps
T125 /workspace/coverage/cover_reg_top/42.xbar_stress_all.1908265398 Dec 24 02:12:40 PM PST 23 Dec 24 02:14:42 PM PST 23 1392138022 ps
T176 /workspace/coverage/cover_reg_top/20.xbar_smoke.1256986518 Dec 24 02:10:59 PM PST 23 Dec 24 02:11:05 PM PST 23 45242672 ps
T100 /workspace/coverage/cover_reg_top/2.chip_csr_rw.3848512997 Dec 24 02:09:52 PM PST 23 Dec 24 02:19:56 PM PST 23 6485462820 ps
T137 /workspace/coverage/cover_reg_top/52.xbar_stress_all.3807995679 Dec 24 02:13:32 PM PST 23 Dec 24 02:18:29 PM PST 23 3717598156 ps
T315 /workspace/coverage/cover_reg_top/41.xbar_random.4076142413 Dec 24 02:12:41 PM PST 23 Dec 24 02:13:37 PM PST 23 603875727 ps
T174 /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2898117029 Dec 24 02:14:44 PM PST 23 Dec 24 02:33:07 PM PST 23 66317572974 ps
T509 /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2003546017 Dec 24 02:14:44 PM PST 23 Dec 24 02:15:13 PM PST 23 656844518 ps
T510 /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.2679519561 Dec 24 02:15:34 PM PST 23 Dec 24 02:17:23 PM PST 23 9964541483 ps
T511 /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3884872251 Dec 24 02:16:20 PM PST 23 Dec 24 02:21:43 PM PST 23 28624287979 ps
T388 /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2433097066 Dec 24 02:10:48 PM PST 23 Dec 24 02:18:26 PM PST 23 28114968394 ps
T193 /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.1348356313 Dec 24 02:17:01 PM PST 23 Dec 24 02:17:27 PM PST 23 261031553 ps
T512 /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.2773452102 Dec 24 02:15:24 PM PST 23 Dec 24 02:21:38 PM PST 23 11826953778 ps
T266 /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2191335680 Dec 24 02:13:29 PM PST 23 Dec 24 02:15:00 PM PST 23 5010976084 ps
T379 /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1606766040 Dec 24 02:16:07 PM PST 23 Dec 24 02:18:19 PM PST 23 3305822188 ps
T386 /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.282467336 Dec 24 02:16:19 PM PST 23 Dec 24 02:21:46 PM PST 23 2698357952 ps
T373 /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2159464318 Dec 24 02:15:27 PM PST 23 Dec 24 02:48:38 PM PST 23 116224565564 ps
T513 /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.672330580 Dec 24 02:10:16 PM PST 23 Dec 24 02:11:30 PM PST 23 1121868088 ps
T514 /workspace/coverage/cover_reg_top/65.xbar_random.662115485 Dec 24 02:14:28 PM PST 23 Dec 24 02:15:19 PM PST 23 1339024644 ps
T300 /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.3483329695 Dec 24 02:16:06 PM PST 23 Dec 24 02:16:29 PM PST 23 247616990 ps
T297 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.2326818751 Dec 24 02:16:09 PM PST 23 Dec 24 02:22:04 PM PST 23 11216581909 ps
T385 /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1194889009 Dec 24 02:10:12 PM PST 23 Dec 24 02:11:53 PM PST 23 2766860875 ps
T254 /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3020140304 Dec 24 02:09:45 PM PST 23 Dec 24 02:12:42 PM PST 23 1801783859 ps
T515 /workspace/coverage/cover_reg_top/58.xbar_smoke.3727037893 Dec 24 02:13:38 PM PST 23 Dec 24 02:13:48 PM PST 23 130205861 ps
T387 /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.965338845 Dec 24 02:11:20 PM PST 23 Dec 24 02:29:45 PM PST 23 61305577938 ps
T516 /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.68992693 Dec 24 02:13:26 PM PST 23 Dec 24 02:14:55 PM PST 23 5030272825 ps
T138 /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.636475082 Dec 24 02:16:05 PM PST 23 Dec 24 02:16:44 PM PST 23 388107852 ps
T91 /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.391461110 Dec 24 02:10:39 PM PST 23 Dec 24 02:16:26 PM PST 23 8242328313 ps
T517 /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2071652241 Dec 24 02:10:30 PM PST 23 Dec 24 02:10:38 PM PST 23 38922337 ps
T129 /workspace/coverage/cover_reg_top/85.xbar_stress_all.3386758682 Dec 24 02:15:56 PM PST 23 Dec 24 02:27:29 PM PST 23 18059802783 ps
T230 /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.3449078336 Dec 24 02:16:41 PM PST 23 Dec 24 02:26:18 PM PST 23 35192786422 ps
T518 /workspace/coverage/cover_reg_top/11.xbar_error_random.2097583890 Dec 24 02:10:29 PM PST 23 Dec 24 02:11:24 PM PST 23 1568702155 ps
T370 /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3181338157 Dec 24 02:14:25 PM PST 23 Dec 24 02:22:37 PM PST 23 29092903987 ps
T519 /workspace/coverage/cover_reg_top/25.xbar_smoke.4155654805 Dec 24 02:11:04 PM PST 23 Dec 24 02:11:10 PM PST 23 45927842 ps
T520 /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1628795195 Dec 24 02:10:36 PM PST 23 Dec 24 02:11:02 PM PST 23 657101653 ps
T356 /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.622094509 Dec 24 02:12:11 PM PST 23 Dec 24 02:40:45 PM PST 23 99157351454 ps
T409 /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.1486906641 Dec 24 02:16:53 PM PST 23 Dec 24 02:28:28 PM PST 23 11604694775 ps
T279 /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.2565578223 Dec 24 02:16:42 PM PST 23 Dec 24 02:20:35 PM PST 23 20567914094 ps
T192 /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2577407721 Dec 24 02:12:52 PM PST 23 Dec 24 02:33:29 PM PST 23 114013707599 ps
T249 /workspace/coverage/cover_reg_top/77.xbar_same_source.2747189213 Dec 24 02:15:27 PM PST 23 Dec 24 02:16:01 PM PST 23 464252707 ps
T521 /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.632910107 Dec 24 02:14:30 PM PST 23 Dec 24 02:16:04 PM PST 23 5457746160 ps
T522 /workspace/coverage/cover_reg_top/55.xbar_error_random.2841160098 Dec 24 02:13:34 PM PST 23 Dec 24 02:14:47 PM PST 23 2416675962 ps
T414 /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2521211761 Dec 24 02:11:33 PM PST 23 Dec 24 02:14:55 PM PST 23 655238976 ps
T523 /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.2055855468 Dec 24 02:15:41 PM PST 23 Dec 24 02:17:21 PM PST 23 9040455872 ps
T314 /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1515446925 Dec 24 02:14:00 PM PST 23 Dec 24 02:28:37 PM PST 23 54270992578 ps
T153 /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.646020914 Dec 24 02:15:43 PM PST 23 Dec 24 02:16:39 PM PST 23 652003485 ps
T524 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.498164690 Dec 24 02:10:28 PM PST 23 Dec 24 02:13:13 PM PST 23 4287903761 ps
T525 /workspace/coverage/cover_reg_top/25.xbar_random.459625383 Dec 24 02:11:03 PM PST 23 Dec 24 02:11:24 PM PST 23 211834243 ps
T526 /workspace/coverage/cover_reg_top/35.xbar_random.2039185068 Dec 24 02:12:05 PM PST 23 Dec 24 02:12:24 PM PST 23 118520838 ps
T527 /workspace/coverage/cover_reg_top/55.xbar_smoke.666131365 Dec 24 02:13:26 PM PST 23 Dec 24 02:13:33 PM PST 23 43349351 ps
T528 /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2532267539 Dec 24 02:14:30 PM PST 23 Dec 24 02:14:39 PM PST 23 52640950 ps
T529 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.2545125904 Dec 24 02:09:59 PM PST 23 Dec 24 02:16:07 PM PST 23 9976401131 ps
T530 /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2424797733 Dec 24 02:16:55 PM PST 23 Dec 24 02:17:18 PM PST 23 499884838 ps
T531 /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.4147860160 Dec 24 02:11:26 PM PST 23 Dec 24 02:11:35 PM PST 23 59153915 ps
T52 /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2019112899 Dec 24 02:09:42 PM PST 23 Dec 24 02:16:01 PM PST 23 9147364578 ps
T48 /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.2912296311 Dec 24 02:10:46 PM PST 23 Dec 24 02:36:40 PM PST 23 16461636968 ps
T532 /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2949143604 Dec 24 02:12:59 PM PST 23 Dec 24 02:17:09 PM PST 23 3296009113 ps
T151 /workspace/coverage/cover_reg_top/98.xbar_stress_all.1119493460 Dec 24 02:16:56 PM PST 23 Dec 24 02:18:19 PM PST 23 2340054501 ps
T533 /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2534651894 Dec 24 02:11:06 PM PST 23 Dec 24 02:11:28 PM PST 23 66890602 ps
T534 /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1466677817 Dec 24 02:11:15 PM PST 23 Dec 24 02:11:27 PM PST 23 150613862 ps
T415 /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3578764742 Dec 24 02:10:22 PM PST 23 Dec 24 02:11:55 PM PST 23 378701632 ps
T535 /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.3433275416 Dec 24 02:16:01 PM PST 23 Dec 24 02:17:12 PM PST 23 6422205463 ps
T536 /workspace/coverage/cover_reg_top/63.xbar_error_random.1338736066 Dec 24 02:14:30 PM PST 23 Dec 24 02:15:01 PM PST 23 845155787 ps
T537 /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.341579261 Dec 24 02:13:11 PM PST 23 Dec 24 02:14:59 PM PST 23 9908892736 ps
T538 /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.785072071 Dec 24 02:13:22 PM PST 23 Dec 24 02:14:19 PM PST 23 1471718967 ps
T539 /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.304800179 Dec 24 02:15:07 PM PST 23 Dec 24 02:16:16 PM PST 23 3780331191 ps
T540 /workspace/coverage/cover_reg_top/24.xbar_error_random.653875224 Dec 24 02:11:19 PM PST 23 Dec 24 02:11:28 PM PST 23 76731282 ps
T541 /workspace/coverage/cover_reg_top/33.xbar_smoke.2853713529 Dec 24 02:12:00 PM PST 23 Dec 24 02:12:15 PM PST 23 188778673 ps
T542 /workspace/coverage/cover_reg_top/8.xbar_error_random.1025824439 Dec 24 02:10:25 PM PST 23 Dec 24 02:11:51 PM PST 23 2536241280 ps
T543 /workspace/coverage/cover_reg_top/72.xbar_random.1383878446 Dec 24 02:14:48 PM PST 23 Dec 24 02:14:56 PM PST 23 112409796 ps
T152 /workspace/coverage/cover_reg_top/97.xbar_stress_all.2078019493 Dec 24 02:16:53 PM PST 23 Dec 24 02:21:11 PM PST 23 6973602000 ps
T407 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1903373666 Dec 24 02:11:24 PM PST 23 Dec 24 02:15:13 PM PST 23 489690962 ps
T21 /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3995192385 Dec 24 02:09:52 PM PST 23 Dec 24 02:13:12 PM PST 23 4188213894 ps
T376 /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.2316202750 Dec 24 02:12:12 PM PST 23 Dec 24 02:51:35 PM PST 23 158000077077 ps
T282 /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2010221008 Dec 24 02:13:36 PM PST 23 Dec 24 02:18:49 PM PST 23 2703440825 ps
T377 /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1894209664 Dec 24 02:14:24 PM PST 23 Dec 24 02:48:05 PM PST 23 123353334802 ps
T330 /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.3295754835 Dec 24 02:16:37 PM PST 23 Dec 24 02:16:50 PM PST 23 30275932 ps
T544 /workspace/coverage/cover_reg_top/1.xbar_smoke.620378890 Dec 24 02:09:52 PM PST 23 Dec 24 02:10:01 PM PST 23 149835088 ps
T276 /workspace/coverage/cover_reg_top/58.xbar_same_source.3209054192 Dec 24 02:13:39 PM PST 23 Dec 24 02:14:20 PM PST 23 1288007739 ps
T329 /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3234062549 Dec 24 02:12:41 PM PST 23 Dec 24 02:13:18 PM PST 23 835858831 ps
T545 /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1333973679 Dec 24 02:15:57 PM PST 23 Dec 24 02:16:06 PM PST 23 76305051 ps
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