Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.36 88.56 85.90 70.07 86.52 88.35 98.79


Total test records in report: 1927
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T792 /workspace/coverage/cover_reg_top/34.xbar_same_source.2258574202 Dec 24 02:12:01 PM PST 23 Dec 24 02:13:15 PM PST 23 2290456141 ps
T793 /workspace/coverage/cover_reg_top/28.xbar_error_random.2811430562 Dec 24 02:11:19 PM PST 23 Dec 24 02:11:35 PM PST 23 134759057 ps
T794 /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.1175660066 Dec 24 02:15:26 PM PST 23 Dec 24 02:24:58 PM PST 23 34399479988 ps
T795 /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2132571264 Dec 24 02:13:31 PM PST 23 Dec 24 02:15:13 PM PST 23 6121934288 ps
T796 /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2013453237 Dec 24 02:16:54 PM PST 23 Dec 24 02:17:38 PM PST 23 1034212949 ps
T797 /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.747620204 Dec 24 02:11:31 PM PST 23 Dec 24 02:12:05 PM PST 23 46593972 ps
T798 /workspace/coverage/cover_reg_top/46.xbar_access_same_device.4203149651 Dec 24 02:12:42 PM PST 23 Dec 24 02:14:01 PM PST 23 944795205 ps
T92 /workspace/coverage/cover_reg_top/52.xbar_error_random.2968387420 Dec 24 02:13:30 PM PST 23 Dec 24 02:14:08 PM PST 23 495497935 ps
T799 /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2787174594 Dec 24 02:13:36 PM PST 23 Dec 24 02:14:01 PM PST 23 225364661 ps
T800 /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.4058650523 Dec 24 02:12:03 PM PST 23 Dec 24 02:15:53 PM PST 23 12883962170 ps
T801 /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.1972976567 Dec 24 02:16:22 PM PST 23 Dec 24 02:21:10 PM PST 23 17529820274 ps
T802 /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.561203471 Dec 24 02:12:42 PM PST 23 Dec 24 02:13:02 PM PST 23 283862358 ps
T803 /workspace/coverage/cover_reg_top/76.xbar_random.80674055 Dec 24 02:14:58 PM PST 23 Dec 24 02:15:20 PM PST 23 523564343 ps
T260 /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.2511929134 Dec 24 02:15:11 PM PST 23 Dec 24 02:16:06 PM PST 23 602102415 ps
T804 /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.401033998 Dec 24 02:15:26 PM PST 23 Dec 24 02:16:35 PM PST 23 152695846 ps
T805 /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.3642592571 Dec 24 02:12:22 PM PST 23 Dec 24 02:13:40 PM PST 23 4316958546 ps
T806 /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1999818436 Dec 24 02:13:44 PM PST 23 Dec 24 02:18:00 PM PST 23 3786443735 ps
T807 /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.4286488489 Dec 24 02:13:29 PM PST 23 Dec 24 02:27:14 PM PST 23 49540271203 ps
T336 /workspace/coverage/cover_reg_top/15.xbar_stress_all.3788124736 Dec 24 02:10:21 PM PST 23 Dec 24 02:14:48 PM PST 23 7091732020 ps
T808 /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.729209775 Dec 24 02:14:32 PM PST 23 Dec 24 02:14:40 PM PST 23 45245635 ps
T809 /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3809203878 Dec 24 02:10:27 PM PST 23 Dec 24 02:11:47 PM PST 23 4514494358 ps
T810 /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.3120602349 Dec 24 02:10:09 PM PST 23 Dec 24 02:23:59 PM PST 23 74362212735 ps
T811 /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.2281326212 Dec 24 02:11:19 PM PST 23 Dec 24 02:13:30 PM PST 23 7304217880 ps
T258 /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.3625824918 Dec 24 02:16:44 PM PST 23 Dec 24 02:26:37 PM PST 23 33314878404 ps
T51 /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.1111247263 Dec 24 02:10:43 PM PST 23 Dec 24 02:39:45 PM PST 23 16895265960 ps
T812 /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3708025201 Dec 24 02:12:07 PM PST 23 Dec 24 02:12:38 PM PST 23 632428700 ps
T813 /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.1227805957 Dec 24 02:09:49 PM PST 23 Dec 24 02:11:08 PM PST 23 7514369908 ps
T814 /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.4247933599 Dec 24 02:11:21 PM PST 23 Dec 24 02:11:57 PM PST 23 334393878 ps
T815 /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.1895552655 Dec 24 02:12:41 PM PST 23 Dec 24 02:14:01 PM PST 23 4504860001 ps
T816 /workspace/coverage/cover_reg_top/6.chip_tl_errors.4251670047 Dec 24 02:10:06 PM PST 23 Dec 24 02:11:37 PM PST 23 2752518670 ps
T239 /workspace/coverage/cover_reg_top/7.chip_tl_errors.3082309536 Dec 24 02:10:24 PM PST 23 Dec 24 02:16:08 PM PST 23 4218743848 ps
T817 /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.241842100 Dec 24 02:11:20 PM PST 23 Dec 24 02:12:11 PM PST 23 606777998 ps
T818 /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1577100124 Dec 24 02:13:21 PM PST 23 Dec 24 02:14:13 PM PST 23 224301633 ps
T819 /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1742091729 Dec 24 02:12:11 PM PST 23 Dec 24 02:13:56 PM PST 23 8628323602 ps
T820 /workspace/coverage/cover_reg_top/8.xbar_same_source.3852498332 Dec 24 02:10:40 PM PST 23 Dec 24 02:11:19 PM PST 23 548922565 ps
T821 /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3131577625 Dec 24 02:14:13 PM PST 23 Dec 24 02:14:39 PM PST 23 60174035 ps
T822 /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3373392951 Dec 24 02:15:25 PM PST 23 Dec 24 02:15:46 PM PST 23 433015884 ps
T823 /workspace/coverage/cover_reg_top/43.xbar_access_same_device.4004742197 Dec 24 02:12:43 PM PST 23 Dec 24 02:13:21 PM PST 23 676008073 ps
T45 /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.234578732 Dec 24 02:10:21 PM PST 23 Dec 24 02:34:44 PM PST 23 15218951680 ps
T824 /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3394475614 Dec 24 02:11:06 PM PST 23 Dec 24 02:11:14 PM PST 23 47773009 ps
T825 /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.1337173431 Dec 24 02:17:03 PM PST 23 Dec 24 02:17:42 PM PST 23 926683115 ps
T826 /workspace/coverage/cover_reg_top/98.xbar_smoke.1118552035 Dec 24 02:16:54 PM PST 23 Dec 24 02:17:04 PM PST 23 141082181 ps
T827 /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.602246452 Dec 24 02:16:23 PM PST 23 Dec 24 02:17:45 PM PST 23 7624250680 ps
T828 /workspace/coverage/cover_reg_top/41.xbar_smoke.544245643 Dec 24 02:12:20 PM PST 23 Dec 24 02:12:35 PM PST 23 158293517 ps
T829 /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.3005404423 Dec 24 02:13:43 PM PST 23 Dec 24 02:27:22 PM PST 23 52009587530 ps
T830 /workspace/coverage/cover_reg_top/51.xbar_smoke.3000273359 Dec 24 02:13:18 PM PST 23 Dec 24 02:13:30 PM PST 23 240629276 ps
T831 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1659976367 Dec 24 02:14:33 PM PST 23 Dec 24 02:19:05 PM PST 23 4928302586 ps
T832 /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.471958395 Dec 24 02:16:09 PM PST 23 Dec 24 02:16:43 PM PST 23 372213975 ps
T833 /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.4086417531 Dec 24 02:13:42 PM PST 23 Dec 24 02:15:15 PM PST 23 5272329683 ps
T834 /workspace/coverage/cover_reg_top/87.xbar_stress_all.1757500577 Dec 24 02:16:14 PM PST 23 Dec 24 02:20:13 PM PST 23 6677761427 ps
T835 /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3146389351 Dec 24 02:09:43 PM PST 23 Dec 24 02:11:12 PM PST 23 5104025284 ps
T836 /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.4002337236 Dec 24 02:13:29 PM PST 23 Dec 24 02:14:40 PM PST 23 6853441103 ps
T406 /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.516746945 Dec 24 02:13:28 PM PST 23 Dec 24 02:18:55 PM PST 23 3541018092 ps
T837 /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.997371619 Dec 24 02:16:07 PM PST 23 Dec 24 02:16:15 PM PST 23 42461435 ps
T838 /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.814191396 Dec 24 02:09:56 PM PST 23 Dec 24 02:10:04 PM PST 23 47398874 ps
T839 /workspace/coverage/cover_reg_top/53.xbar_stress_all.2182593804 Dec 24 02:13:43 PM PST 23 Dec 24 02:20:14 PM PST 23 11477969168 ps
T840 /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.2256917940 Dec 24 02:16:07 PM PST 23 Dec 24 02:18:25 PM PST 23 12742235335 ps
T841 /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2557535027 Dec 24 02:15:56 PM PST 23 Dec 24 02:18:10 PM PST 23 1810335046 ps
T842 /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.726140692 Dec 24 02:14:38 PM PST 23 Dec 24 02:15:22 PM PST 23 2360898578 ps
T61 /workspace/coverage/cover_reg_top/15.chip_csr_rw.1270806297 Dec 24 02:10:34 PM PST 23 Dec 24 02:20:32 PM PST 23 5020536099 ps
T843 /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3732442588 Dec 24 02:10:19 PM PST 23 Dec 24 02:10:42 PM PST 23 174003947 ps
T844 /workspace/coverage/cover_reg_top/12.xbar_random.3752066696 Dec 24 02:10:19 PM PST 23 Dec 24 02:10:35 PM PST 23 175535287 ps
T411 /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.410614420 Dec 24 02:11:16 PM PST 23 Dec 24 02:21:12 PM PST 23 12525734184 ps
T845 /workspace/coverage/cover_reg_top/48.xbar_error_random.2892286861 Dec 24 02:13:10 PM PST 23 Dec 24 02:13:39 PM PST 23 802784777 ps
T846 /workspace/coverage/cover_reg_top/33.xbar_access_same_device.3773190231 Dec 24 02:11:58 PM PST 23 Dec 24 02:12:06 PM PST 23 41930677 ps
T847 /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2848225331 Dec 24 02:14:57 PM PST 23 Dec 24 02:16:04 PM PST 23 6399819639 ps
T46 /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1177241898 Dec 24 02:09:55 PM PST 23 Dec 24 02:37:37 PM PST 23 15835530890 ps
T848 /workspace/coverage/cover_reg_top/18.xbar_random.1262064032 Dec 24 02:11:06 PM PST 23 Dec 24 02:11:25 PM PST 23 230043479 ps
T849 /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.1360542048 Dec 24 02:16:41 PM PST 23 Dec 24 02:16:56 PM PST 23 89209342 ps
T850 /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1741057125 Dec 24 02:10:03 PM PST 23 Dec 24 02:14:38 PM PST 23 3187882037 ps
T851 /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1792756669 Dec 24 02:14:27 PM PST 23 Dec 24 02:20:33 PM PST 23 20353071789 ps
T852 /workspace/coverage/cover_reg_top/36.xbar_error_random.4216848193 Dec 24 02:12:03 PM PST 23 Dec 24 02:12:32 PM PST 23 270235773 ps
T853 /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2706199161 Dec 24 02:11:24 PM PST 23 Dec 24 02:12:55 PM PST 23 8607575441 ps
T854 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.1429767732 Dec 24 02:11:58 PM PST 23 Dec 24 02:15:08 PM PST 23 2157806082 ps
T855 /workspace/coverage/cover_reg_top/64.xbar_error_random.3070144782 Dec 24 02:14:18 PM PST 23 Dec 24 02:14:28 PM PST 23 85006533 ps
T856 /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.75815300 Dec 24 02:12:02 PM PST 23 Dec 24 02:12:34 PM PST 23 284129397 ps
T857 /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1821631876 Dec 24 02:10:36 PM PST 23 Dec 24 02:11:11 PM PST 23 280569103 ps
T47 /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.1070889713 Dec 24 02:09:53 PM PST 23 Dec 24 02:37:36 PM PST 23 17304791532 ps
T240 /workspace/coverage/cover_reg_top/21.chip_tl_errors.3171482640 Dec 24 02:11:10 PM PST 23 Dec 24 02:17:10 PM PST 23 4625884778 ps
T858 /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.665507741 Dec 24 02:13:17 PM PST 23 Dec 24 02:21:17 PM PST 23 27341595930 ps
T859 /workspace/coverage/cover_reg_top/18.xbar_stress_all.4044599704 Dec 24 02:10:28 PM PST 23 Dec 24 02:11:20 PM PST 23 1144625528 ps
T860 /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.4197218927 Dec 24 02:14:46 PM PST 23 Dec 24 02:15:38 PM PST 23 1250628969 ps
T861 /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.1149919140 Dec 24 02:12:41 PM PST 23 Dec 24 02:13:19 PM PST 23 320349765 ps
T862 /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2108804027 Dec 24 02:11:33 PM PST 23 Dec 24 02:12:17 PM PST 23 1152938079 ps
T863 /workspace/coverage/cover_reg_top/35.xbar_stress_all.3668381943 Dec 24 02:12:05 PM PST 23 Dec 24 02:18:04 PM PST 23 9278779970 ps
T864 /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1378861374 Dec 24 02:16:22 PM PST 23 Dec 24 02:17:54 PM PST 23 5697496374 ps
T865 /workspace/coverage/cover_reg_top/3.xbar_smoke.3884532584 Dec 24 02:09:56 PM PST 23 Dec 24 02:10:06 PM PST 23 157834708 ps
T50 /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1906909977 Dec 24 02:10:45 PM PST 23 Dec 24 03:04:12 PM PST 23 32720828012 ps
T310 /workspace/coverage/cover_reg_top/10.xbar_stress_all.402745156 Dec 24 02:10:39 PM PST 23 Dec 24 02:15:18 PM PST 23 3207549770 ps
T866 /workspace/coverage/cover_reg_top/37.xbar_error_random.2654271203 Dec 24 02:12:03 PM PST 23 Dec 24 02:12:23 PM PST 23 107027221 ps
T867 /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1398284229 Dec 24 02:15:09 PM PST 23 Dec 24 02:29:53 PM PST 23 82474410339 ps
T868 /workspace/coverage/cover_reg_top/99.xbar_access_same_device.2959048973 Dec 24 02:17:16 PM PST 23 Dec 24 02:19:03 PM PST 23 2772346792 ps
T869 /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.1715808030 Dec 24 02:11:59 PM PST 23 Dec 24 02:21:32 PM PST 23 53105415839 ps
T870 /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1140882287 Dec 24 02:11:04 PM PST 23 Dec 24 02:12:28 PM PST 23 7917662566 ps
T871 /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3532601284 Dec 24 02:12:02 PM PST 23 Dec 24 02:14:16 PM PST 23 3606813034 ps
T872 /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3412514045 Dec 24 02:09:51 PM PST 23 Dec 24 02:16:49 PM PST 23 2605528093 ps
T873 /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2431272846 Dec 24 02:10:51 PM PST 23 Dec 24 02:36:16 PM PST 23 16816726660 ps
T874 /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.1390038617 Dec 24 02:11:25 PM PST 23 Dec 24 02:12:16 PM PST 23 4861648587 ps
T875 /workspace/coverage/cover_reg_top/79.xbar_same_source.108310496 Dec 24 02:15:38 PM PST 23 Dec 24 02:16:32 PM PST 23 1755785861 ps
T876 /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.2673096283 Dec 24 02:15:55 PM PST 23 Dec 24 02:19:39 PM PST 23 11855268683 ps
T877 /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1571898151 Dec 24 02:15:10 PM PST 23 Dec 24 02:25:10 PM PST 23 12440329199 ps
T878 /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.1900232965 Dec 24 02:16:06 PM PST 23 Dec 24 02:21:41 PM PST 23 9536654108 ps
T879 /workspace/coverage/cover_reg_top/6.xbar_random.668277680 Dec 24 02:10:14 PM PST 23 Dec 24 02:10:53 PM PST 23 1062350940 ps
T880 /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.2844664288 Dec 24 02:14:36 PM PST 23 Dec 24 02:16:27 PM PST 23 6508097661 ps
T881 /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1146984753 Dec 24 02:15:26 PM PST 23 Dec 24 02:15:32 PM PST 23 25016324 ps
T882 /workspace/coverage/cover_reg_top/57.xbar_access_same_device.1999420846 Dec 24 02:13:35 PM PST 23 Dec 24 02:14:53 PM PST 23 1799072884 ps
T883 /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.842307273 Dec 24 02:11:12 PM PST 23 Dec 24 02:17:45 PM PST 23 9491904064 ps
T884 /workspace/coverage/cover_reg_top/27.chip_tl_errors.3299391015 Dec 24 02:11:15 PM PST 23 Dec 24 02:12:44 PM PST 23 2879426040 ps
T885 /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2653247961 Dec 24 02:17:00 PM PST 23 Dec 24 02:17:08 PM PST 23 48201053 ps
T886 /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.3940851249 Dec 24 02:14:08 PM PST 23 Dec 24 02:15:27 PM PST 23 7251978496 ps
T887 /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.4223619686 Dec 24 02:16:38 PM PST 23 Dec 24 02:19:05 PM PST 23 270263690 ps
T888 /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1232065417 Dec 24 02:13:13 PM PST 23 Dec 24 02:14:44 PM PST 23 181486119 ps
T889 /workspace/coverage/cover_reg_top/87.xbar_same_source.2370064701 Dec 24 02:16:01 PM PST 23 Dec 24 02:17:16 PM PST 23 2469177033 ps
T890 /workspace/coverage/cover_reg_top/74.xbar_stress_all.3026885572 Dec 24 02:15:10 PM PST 23 Dec 24 02:17:56 PM PST 23 4599301346 ps
T891 /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2762390336 Dec 24 02:09:56 PM PST 23 Dec 24 02:10:08 PM PST 23 72534538 ps
T892 /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1445203151 Dec 24 02:15:08 PM PST 23 Dec 24 02:15:28 PM PST 23 185712140 ps
T893 /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.573716727 Dec 24 02:10:01 PM PST 23 Dec 24 02:56:18 PM PST 23 25072309619 ps
T894 /workspace/coverage/cover_reg_top/9.chip_csr_rw.2262403388 Dec 24 02:11:21 PM PST 23 Dec 24 02:16:10 PM PST 23 4419730972 ps
T895 /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2062292720 Dec 24 02:14:34 PM PST 23 Dec 24 02:15:59 PM PST 23 4547600779 ps
T896 /workspace/coverage/cover_reg_top/29.xbar_access_same_device.1460359468 Dec 24 02:11:26 PM PST 23 Dec 24 02:12:25 PM PST 23 1336996678 ps
T897 /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.612324785 Dec 24 02:11:10 PM PST 23 Dec 24 02:11:28 PM PST 23 132804740 ps
T898 /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.2356574783 Dec 24 02:16:06 PM PST 23 Dec 24 02:17:06 PM PST 23 5133755559 ps
T899 /workspace/coverage/cover_reg_top/19.xbar_stress_all.3165748907 Dec 24 02:11:13 PM PST 23 Dec 24 02:12:57 PM PST 23 1348500314 ps
T900 /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.586003335 Dec 24 02:15:14 PM PST 23 Dec 24 02:19:41 PM PST 23 15497927969 ps
T901 /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2960562852 Dec 24 02:13:39 PM PST 23 Dec 24 02:18:35 PM PST 23 1055939469 ps
T902 /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.319688438 Dec 24 02:11:19 PM PST 23 Dec 24 02:11:29 PM PST 23 52558164 ps
T903 /workspace/coverage/cover_reg_top/93.xbar_smoke.1204138219 Dec 24 02:16:19 PM PST 23 Dec 24 02:16:29 PM PST 23 205557452 ps
T904 /workspace/coverage/cover_reg_top/45.xbar_random.1435597328 Dec 24 02:12:41 PM PST 23 Dec 24 02:13:27 PM PST 23 445876306 ps
T905 /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.800298322 Dec 24 02:11:24 PM PST 23 Dec 24 02:15:02 PM PST 23 2302613276 ps
T906 /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.1564057901 Dec 24 02:14:50 PM PST 23 Dec 24 02:19:39 PM PST 23 8551333032 ps
T907 /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.957491806 Dec 24 02:12:13 PM PST 23 Dec 24 02:12:31 PM PST 23 9640705 ps
T908 /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.701148771 Dec 24 02:17:01 PM PST 23 Dec 24 02:18:34 PM PST 23 8002550655 ps
T909 /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.3494078813 Dec 24 02:10:49 PM PST 23 Dec 24 02:12:25 PM PST 23 9558641943 ps
T910 /workspace/coverage/cover_reg_top/16.xbar_smoke.4070258255 Dec 24 02:10:20 PM PST 23 Dec 24 02:10:29 PM PST 23 189988053 ps
T911 /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3333246167 Dec 24 02:12:21 PM PST 23 Dec 24 02:16:57 PM PST 23 2689782923 ps
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