Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.36 88.56 85.90 70.07 86.52 88.35 98.79


Total test records in report: 1927
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T1022 /workspace/coverage/cover_reg_top/92.xbar_same_source.4257467743 Dec 24 02:16:20 PM PST 23 Dec 24 02:16:47 PM PST 23 329860708 ps
T1023 /workspace/coverage/cover_reg_top/61.xbar_error_random.895917154 Dec 24 02:14:15 PM PST 23 Dec 24 02:14:43 PM PST 23 725450426 ps
T1024 /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1167165835 Dec 24 02:11:30 PM PST 23 Dec 24 02:13:01 PM PST 23 5287074646 ps
T1025 /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3213880719 Dec 24 02:15:25 PM PST 23 Dec 24 02:16:26 PM PST 23 404817882 ps
T1026 /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.4286628004 Dec 24 02:11:04 PM PST 23 Dec 24 02:13:16 PM PST 23 227628788 ps
T1027 /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.3687051025 Dec 24 02:16:22 PM PST 23 Dec 24 02:17:51 PM PST 23 2622578130 ps
T1028 /workspace/coverage/cover_reg_top/59.xbar_same_source.1026594840 Dec 24 02:13:43 PM PST 23 Dec 24 02:14:02 PM PST 23 247047284 ps
T1029 /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3067419534 Dec 24 02:10:28 PM PST 23 Dec 24 02:38:41 PM PST 23 16669371918 ps
T1030 /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3324656350 Dec 24 02:16:21 PM PST 23 Dec 24 02:53:31 PM PST 23 126812182161 ps
T1031 /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3471170514 Dec 24 02:14:09 PM PST 23 Dec 24 02:17:32 PM PST 23 2921217276 ps
T1032 /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.65807006 Dec 24 02:10:25 PM PST 23 Dec 24 02:10:54 PM PST 23 707161676 ps
T1033 /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.3438663851 Dec 24 02:12:39 PM PST 23 Dec 24 02:28:19 PM PST 23 92282964689 ps
T1034 /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.851882800 Dec 24 02:10:43 PM PST 23 Dec 24 02:12:16 PM PST 23 8520228346 ps
T1035 /workspace/coverage/cover_reg_top/79.xbar_stress_all.3118120401 Dec 24 02:15:25 PM PST 23 Dec 24 02:18:54 PM PST 23 2178907669 ps
T1036 /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3710672357 Dec 24 02:13:27 PM PST 23 Dec 24 02:14:32 PM PST 23 5679827742 ps
T412 /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2874905757 Dec 24 02:13:33 PM PST 23 Dec 24 02:19:29 PM PST 23 3047898640 ps
T1037 /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2817364211 Dec 24 02:10:04 PM PST 23 Dec 24 02:40:16 PM PST 23 16371129765 ps
T1038 /workspace/coverage/cover_reg_top/84.xbar_smoke.4262097325 Dec 24 02:15:45 PM PST 23 Dec 24 02:15:59 PM PST 23 175191662 ps
T1039 /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3906089933 Dec 24 02:15:43 PM PST 23 Dec 24 02:32:36 PM PST 23 67373261675 ps
T1040 /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.3250815632 Dec 24 02:14:25 PM PST 23 Dec 24 02:33:20 PM PST 23 100086567891 ps
T1041 /workspace/coverage/cover_reg_top/1.xbar_same_source.1892114972 Dec 24 02:09:44 PM PST 23 Dec 24 02:10:00 PM PST 23 190938336 ps
T1042 /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.1988313847 Dec 24 02:10:09 PM PST 23 Dec 24 02:10:30 PM PST 23 503806731 ps
T1043 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3526394013 Dec 24 02:10:00 PM PST 23 Dec 24 02:10:48 PM PST 23 181268457 ps
T1044 /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.3198589274 Dec 24 02:14:45 PM PST 23 Dec 24 02:31:08 PM PST 23 55934577499 ps
T1045 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3865527938 Dec 24 02:10:44 PM PST 23 Dec 24 02:14:35 PM PST 23 1966067617 ps
T1046 /workspace/coverage/cover_reg_top/10.xbar_access_same_device.956983121 Dec 24 02:10:21 PM PST 23 Dec 24 02:10:58 PM PST 23 913098783 ps
T1047 /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3557208007 Dec 24 02:11:23 PM PST 23 Dec 24 02:13:04 PM PST 23 6095916211 ps
T1048 /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.293797064 Dec 24 02:13:34 PM PST 23 Dec 24 02:15:50 PM PST 23 4224500637 ps
T1049 /workspace/coverage/cover_reg_top/34.xbar_access_same_device.2048022390 Dec 24 02:12:02 PM PST 23 Dec 24 02:12:55 PM PST 23 637458008 ps
T1050 /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3754419519 Dec 24 02:14:48 PM PST 23 Dec 24 02:15:05 PM PST 23 135174315 ps
T1051 /workspace/coverage/cover_reg_top/1.chip_csr_rw.1970699223 Dec 24 02:09:53 PM PST 23 Dec 24 02:18:01 PM PST 23 5747774256 ps
T1052 /workspace/coverage/cover_reg_top/2.xbar_stress_all.639940719 Dec 24 02:09:54 PM PST 23 Dec 24 02:10:04 PM PST 23 211719947 ps
T1053 /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.623320651 Dec 24 02:11:14 PM PST 23 Dec 24 02:11:51 PM PST 23 298168214 ps
T1054 /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.4000098127 Dec 24 02:09:44 PM PST 23 Dec 24 02:17:16 PM PST 23 4896371140 ps
T1055 /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1705218469 Dec 24 02:15:58 PM PST 23 Dec 24 02:17:31 PM PST 23 7871643836 ps
T1056 /workspace/coverage/cover_reg_top/53.xbar_access_same_device.2214422336 Dec 24 02:13:29 PM PST 23 Dec 24 02:14:13 PM PST 23 436230276 ps
T1057 /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.29679962 Dec 24 02:15:41 PM PST 23 Dec 24 02:16:34 PM PST 23 1220363614 ps
T1058 /workspace/coverage/cover_reg_top/12.xbar_error_random.590881464 Dec 24 02:10:20 PM PST 23 Dec 24 02:10:35 PM PST 23 153336297 ps
T1059 /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.2206377689 Dec 24 02:12:44 PM PST 23 Dec 24 02:14:17 PM PST 23 8527021943 ps
T1060 /workspace/coverage/cover_reg_top/11.xbar_same_source.658289193 Dec 24 02:10:31 PM PST 23 Dec 24 02:11:06 PM PST 23 495296606 ps
T1061 /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.3386958186 Dec 24 02:13:16 PM PST 23 Dec 24 02:16:42 PM PST 23 2519816560 ps
T344 /workspace/coverage/cover_reg_top/24.chip_tl_errors.3392792222 Dec 24 02:11:04 PM PST 23 Dec 24 02:14:52 PM PST 23 3730740750 ps
T1062 /workspace/coverage/cover_reg_top/99.xbar_smoke.3065668784 Dec 24 02:17:00 PM PST 23 Dec 24 02:17:08 PM PST 23 42046329 ps
T1063 /workspace/coverage/cover_reg_top/78.xbar_error_random.3135463984 Dec 24 02:15:25 PM PST 23 Dec 24 02:16:21 PM PST 23 1640850377 ps
T1064 /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.939931680 Dec 24 02:09:43 PM PST 23 Dec 24 02:09:51 PM PST 23 44645246 ps
T1065 /workspace/coverage/cover_reg_top/16.xbar_error_random.1835201704 Dec 24 02:10:37 PM PST 23 Dec 24 02:11:14 PM PST 23 1009360807 ps
T1066 /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.4149822347 Dec 24 02:14:01 PM PST 23 Dec 24 02:15:01 PM PST 23 5892085421 ps
T1067 /workspace/coverage/cover_reg_top/11.xbar_access_same_device.4201318918 Dec 24 02:10:19 PM PST 23 Dec 24 02:11:02 PM PST 23 536643312 ps
T1068 /workspace/coverage/cover_reg_top/71.xbar_random.1316668468 Dec 24 02:14:48 PM PST 23 Dec 24 02:15:58 PM PST 23 1939654587 ps
T1069 /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1643853900 Dec 24 02:15:45 PM PST 23 Dec 24 02:16:03 PM PST 23 106825727 ps
T1070 /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.831206132 Dec 24 02:15:43 PM PST 23 Dec 24 02:22:09 PM PST 23 3804328493 ps
T1071 /workspace/coverage/cover_reg_top/49.xbar_same_source.1327452044 Dec 24 02:13:00 PM PST 23 Dec 24 02:13:24 PM PST 23 303824906 ps
T1072 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2533247513 Dec 24 02:09:58 PM PST 23 Dec 24 02:10:45 PM PST 23 156097469 ps
T1073 /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2043747045 Dec 24 02:14:35 PM PST 23 Dec 24 02:15:08 PM PST 23 342101865 ps
T1074 /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.2303624503 Dec 24 02:16:10 PM PST 23 Dec 24 02:21:58 PM PST 23 21464403433 ps
T1075 /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.1385639376 Dec 24 02:13:18 PM PST 23 Dec 24 02:13:37 PM PST 23 379405599 ps
T1076 /workspace/coverage/cover_reg_top/65.xbar_same_source.1414156852 Dec 24 02:14:26 PM PST 23 Dec 24 02:14:50 PM PST 23 763104912 ps
T1077 /workspace/coverage/cover_reg_top/29.xbar_stress_all.3977313366 Dec 24 02:11:32 PM PST 23 Dec 24 02:12:24 PM PST 23 1459954232 ps
T1078 /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2087091134 Dec 24 02:12:03 PM PST 23 Dec 24 02:15:06 PM PST 23 2711929433 ps
T1079 /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3406213059 Dec 24 02:13:38 PM PST 23 Dec 24 02:35:57 PM PST 23 88565828145 ps
T1080 /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3741155351 Dec 24 02:12:03 PM PST 23 Dec 24 02:12:41 PM PST 23 440512904 ps
T1081 /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.1745395286 Dec 24 02:11:08 PM PST 23 Dec 24 02:11:49 PM PST 23 527552090 ps
T1082 /workspace/coverage/cover_reg_top/49.xbar_error_random.2687022697 Dec 24 02:12:59 PM PST 23 Dec 24 02:14:24 PM PST 23 2422903327 ps
T1083 /workspace/coverage/cover_reg_top/97.xbar_access_same_device.1058600908 Dec 24 02:16:53 PM PST 23 Dec 24 02:17:26 PM PST 23 897450975 ps
T1084 /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1961897127 Dec 24 02:10:43 PM PST 23 Dec 24 02:12:41 PM PST 23 1031742576 ps
T1085 /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.4005898523 Dec 24 02:13:32 PM PST 23 Dec 24 02:13:40 PM PST 23 49549558 ps
T1086 /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3801778696 Dec 24 02:10:24 PM PST 23 Dec 24 02:16:22 PM PST 23 9743362040 ps
T1087 /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2071391572 Dec 24 02:10:49 PM PST 23 Dec 24 02:19:07 PM PST 23 2647969401 ps
T1088 /workspace/coverage/cover_reg_top/39.xbar_error_random.1792456944 Dec 24 02:12:16 PM PST 23 Dec 24 02:12:45 PM PST 23 606089214 ps
T1089 /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.3392366881 Dec 24 02:16:57 PM PST 23 Dec 24 02:22:02 PM PST 23 4088496314 ps
T1090 /workspace/coverage/cover_reg_top/28.xbar_smoke.2754182660 Dec 24 02:11:14 PM PST 23 Dec 24 02:11:26 PM PST 23 196848453 ps
T1091 /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2286761422 Dec 24 02:12:01 PM PST 23 Dec 24 02:13:29 PM PST 23 203359884 ps
T1092 /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.346880203 Dec 24 02:16:12 PM PST 23 Dec 24 02:16:39 PM PST 23 620456802 ps
T1093 /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.723532507 Dec 24 02:16:00 PM PST 23 Dec 24 02:18:50 PM PST 23 413897310 ps
T1094 /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.3578183146 Dec 24 02:14:29 PM PST 23 Dec 24 02:16:32 PM PST 23 11596357158 ps
T1095 /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2569002970 Dec 24 02:12:44 PM PST 23 Dec 24 02:20:39 PM PST 23 27272221695 ps
T1096 /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.2286416897 Dec 24 02:16:42 PM PST 23 Dec 24 02:29:02 PM PST 23 42048821286 ps
T345 /workspace/coverage/cover_reg_top/2.chip_tl_errors.2951012178 Dec 24 02:09:53 PM PST 23 Dec 24 02:15:23 PM PST 23 4579431038 ps
T338 /workspace/coverage/cover_reg_top/4.chip_tl_errors.85771077 Dec 24 02:09:56 PM PST 23 Dec 24 02:16:55 PM PST 23 4701097383 ps
T1097 /workspace/coverage/cover_reg_top/19.xbar_smoke.2333209569 Dec 24 02:11:01 PM PST 23 Dec 24 02:11:09 PM PST 23 42258070 ps
T1098 /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.4251284253 Dec 24 02:12:01 PM PST 23 Dec 24 02:22:59 PM PST 23 35507753610 ps
T1099 /workspace/coverage/cover_reg_top/81.xbar_access_same_device.2366100365 Dec 24 02:15:45 PM PST 23 Dec 24 02:16:33 PM PST 23 1118037589 ps
T1100 /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3834130367 Dec 24 02:11:19 PM PST 23 Dec 24 02:11:28 PM PST 23 38876204 ps
T418 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2800660171 Dec 24 02:11:18 PM PST 23 Dec 24 02:11:36 PM PST 23 10845094 ps
T1101 /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.153600871 Dec 24 02:09:45 PM PST 23 Dec 24 02:10:20 PM PST 23 369519560 ps
T1102 /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1482624302 Dec 24 02:16:40 PM PST 23 Dec 24 02:34:09 PM PST 23 65164458834 ps
T1103 /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.596473283 Dec 24 02:11:33 PM PST 23 Dec 24 02:12:18 PM PST 23 466947666 ps
T1104 /workspace/coverage/cover_reg_top/94.xbar_smoke.1767680396 Dec 24 02:16:38 PM PST 23 Dec 24 02:16:50 PM PST 23 42274919 ps
T1105 /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.2742111518 Dec 24 02:12:07 PM PST 23 Dec 24 02:12:40 PM PST 23 272390574 ps
T1106 /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.238163450 Dec 24 02:11:04 PM PST 23 Dec 24 02:12:43 PM PST 23 9846978578 ps
T1107 /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.1140050893 Dec 24 02:15:13 PM PST 23 Dec 24 02:21:01 PM PST 23 9762864457 ps
T1108 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2949490296 Dec 24 02:09:56 PM PST 23 Dec 24 02:14:44 PM PST 23 2823311035 ps
T1109 /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1406170406 Dec 24 02:10:17 PM PST 23 Dec 24 02:22:02 PM PST 23 44813824985 ps
T1110 /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2102425296 Dec 24 02:14:28 PM PST 23 Dec 24 02:15:25 PM PST 23 1364340803 ps
T1111 /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.117197015 Dec 24 02:16:23 PM PST 23 Dec 24 02:24:19 PM PST 23 6790015704 ps
T1112 /workspace/coverage/cover_reg_top/81.xbar_error_random.2865172239 Dec 24 02:15:43 PM PST 23 Dec 24 02:16:24 PM PST 23 1064979634 ps
T1113 /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.991412408 Dec 24 02:10:27 PM PST 23 Dec 24 02:49:52 PM PST 23 133211160236 ps
T1114 /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.1596897343 Dec 24 02:13:38 PM PST 23 Dec 24 02:15:29 PM PST 23 10095176341 ps
T1115 /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.3738471010 Dec 24 02:13:25 PM PST 23 Dec 24 02:14:54 PM PST 23 2937510307 ps
T1116 /workspace/coverage/cover_reg_top/60.xbar_access_same_device.3872803791 Dec 24 02:13:51 PM PST 23 Dec 24 02:14:15 PM PST 23 200255133 ps
T1117 /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.1669480998 Dec 24 02:10:23 PM PST 23 Dec 24 02:39:48 PM PST 23 16785204251 ps
T1118 /workspace/coverage/cover_reg_top/52.xbar_access_same_device.1105430344 Dec 24 02:13:30 PM PST 23 Dec 24 02:14:02 PM PST 23 501558457 ps
T1119 /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.4020937214 Dec 24 02:10:03 PM PST 23 Dec 24 02:10:10 PM PST 23 47355686 ps
T1120 /workspace/coverage/cover_reg_top/38.xbar_access_same_device.3719187873 Dec 24 02:12:08 PM PST 23 Dec 24 02:13:44 PM PST 23 2133048162 ps
T1121 /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3978615558 Dec 24 02:09:45 PM PST 23 Dec 24 02:11:12 PM PST 23 8259706487 ps
T1122 /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.2509305749 Dec 24 02:16:33 PM PST 23 Dec 24 02:22:21 PM PST 23 4850554059 ps
T1123 /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2957172326 Dec 24 02:10:08 PM PST 23 Dec 24 02:23:50 PM PST 23 82232243003 ps
T1124 /workspace/coverage/cover_reg_top/87.xbar_smoke.303888271 Dec 24 02:16:07 PM PST 23 Dec 24 02:16:18 PM PST 23 212164553 ps
T1125 /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3924005886 Dec 24 02:11:11 PM PST 23 Dec 24 02:54:31 PM PST 23 152768904957 ps
T1126 /workspace/coverage/cover_reg_top/83.xbar_stress_all.172489130 Dec 24 02:15:47 PM PST 23 Dec 24 02:22:15 PM PST 23 12061743433 ps
T1127 /workspace/coverage/cover_reg_top/49.xbar_random.930894548 Dec 24 02:13:19 PM PST 23 Dec 24 02:15:01 PM PST 23 2462951052 ps
T1128 /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2944046466 Dec 24 02:11:21 PM PST 23 Dec 24 02:38:45 PM PST 23 16484808517 ps
T1129 /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.163744364 Dec 24 02:13:40 PM PST 23 Dec 24 02:16:14 PM PST 23 4454943575 ps
T1130 /workspace/coverage/cover_reg_top/93.xbar_random.2974082108 Dec 24 02:16:41 PM PST 23 Dec 24 02:18:14 PM PST 23 2273278530 ps
T1131 /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.464068013 Dec 24 02:12:13 PM PST 23 Dec 24 02:20:28 PM PST 23 44316510583 ps
T1132 /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.1937385809 Dec 24 02:14:26 PM PST 23 Dec 24 02:15:23 PM PST 23 3362341834 ps
T1133 /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2723894404 Dec 24 02:16:10 PM PST 23 Dec 24 02:17:29 PM PST 23 4565373329 ps
T1134 /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3040116508 Dec 24 02:12:44 PM PST 23 Dec 24 02:20:27 PM PST 23 27587424796 ps
T1135 /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.74838490 Dec 24 02:13:17 PM PST 23 Dec 24 02:14:02 PM PST 23 1100150026 ps
T1136 /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2668428830 Dec 24 02:11:14 PM PST 23 Dec 24 02:12:13 PM PST 23 3508127354 ps
T1137 /workspace/coverage/cover_reg_top/34.xbar_smoke.3865396519 Dec 24 02:11:58 PM PST 23 Dec 24 02:12:06 PM PST 23 32870380 ps
T1138 /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.793276757 Dec 24 02:10:50 PM PST 23 Dec 24 02:11:08 PM PST 23 185153564 ps
T1139 /workspace/coverage/cover_reg_top/56.xbar_error_random.1469491076 Dec 24 02:13:36 PM PST 23 Dec 24 02:14:45 PM PST 23 2113310293 ps
T1140 /workspace/coverage/cover_reg_top/11.xbar_stress_all.2489155583 Dec 24 02:10:23 PM PST 23 Dec 24 02:14:31 PM PST 23 6474673729 ps
T1141 /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3548977062 Dec 24 02:16:54 PM PST 23 Dec 24 02:21:43 PM PST 23 3488913261 ps
T1142 /workspace/coverage/cover_reg_top/84.xbar_access_same_device.3530573720 Dec 24 02:15:45 PM PST 23 Dec 24 02:15:57 PM PST 23 18827230 ps
T1143 /workspace/coverage/cover_reg_top/54.xbar_stress_all.3011404597 Dec 24 02:13:42 PM PST 23 Dec 24 02:19:46 PM PST 23 4990017021 ps
T1144 /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.683533988 Dec 24 02:10:01 PM PST 23 Dec 24 02:10:13 PM PST 23 75674275 ps
T1145 /workspace/coverage/cover_reg_top/72.xbar_access_same_device.2573038423 Dec 24 02:14:57 PM PST 23 Dec 24 02:15:13 PM PST 23 139221975 ps
T1146 /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.645823960 Dec 24 02:16:38 PM PST 23 Dec 24 02:31:19 PM PST 23 50667546436 ps
T1147 /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.982081704 Dec 24 02:10:27 PM PST 23 Dec 24 02:24:50 PM PST 23 51178827302 ps
T1148 /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.1401770020 Dec 24 02:10:27 PM PST 23 Dec 24 02:12:09 PM PST 23 10307104071 ps
T1149 /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3483635138 Dec 24 02:10:22 PM PST 23 Dec 24 02:14:44 PM PST 23 5632318752 ps
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