Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.36 88.56 85.90 70.07 86.52 88.35 98.79


Total test records in report: 1927
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T274 /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.4247494124 Dec 24 02:09:55 PM PST 23 Dec 24 02:11:28 PM PST 23 5259304282 ps
T614 /workspace/coverage/cover_reg_top/0.xbar_access_same_device.4028950895 Dec 24 02:09:40 PM PST 23 Dec 24 02:10:29 PM PST 23 1150898425 ps
T298 /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.440349391 Dec 24 02:09:41 PM PST 23 Dec 24 02:11:58 PM PST 23 8809114527 ps
T209 /workspace/coverage/cover_reg_top/5.chip_csr_rw.2956503382 Dec 24 02:10:00 PM PST 23 Dec 24 02:16:20 PM PST 23 5069171393 ps
T615 /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.833575908 Dec 24 02:12:44 PM PST 23 Dec 24 02:13:05 PM PST 23 287809898 ps
T305 /workspace/coverage/cover_reg_top/31.xbar_random.656028727 Dec 24 02:11:30 PM PST 23 Dec 24 02:12:32 PM PST 23 1871356855 ps
T616 /workspace/coverage/cover_reg_top/92.xbar_smoke.1680626491 Dec 24 02:16:21 PM PST 23 Dec 24 02:16:32 PM PST 23 190588906 ps
T617 /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.3428636277 Dec 24 02:10:23 PM PST 23 Dec 24 02:24:50 PM PST 23 87056180931 ps
T618 /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.3258835055 Dec 24 02:16:08 PM PST 23 Dec 24 02:16:35 PM PST 23 256966611 ps
T185 /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2671097064 Dec 24 02:10:39 PM PST 23 Dec 24 02:28:35 PM PST 23 62038038890 ps
T619 /workspace/coverage/cover_reg_top/75.xbar_smoke.3439175985 Dec 24 02:14:58 PM PST 23 Dec 24 02:15:07 PM PST 23 172436646 ps
T389 /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2571329255 Dec 24 02:10:44 PM PST 23 Dec 24 02:51:34 PM PST 23 154656400520 ps
T191 /workspace/coverage/cover_reg_top/77.xbar_random.2150652692 Dec 24 02:15:38 PM PST 23 Dec 24 02:16:56 PM PST 23 2136255563 ps
T113 /workspace/coverage/cover_reg_top/7.chip_csr_rw.3596017228 Dec 24 02:10:09 PM PST 23 Dec 24 02:14:45 PM PST 23 4004751798 ps
T401 /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3045516070 Dec 24 02:12:50 PM PST 23 Dec 24 02:18:31 PM PST 23 5564524669 ps
T620 /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.3977625542 Dec 24 02:12:03 PM PST 23 Dec 24 02:12:44 PM PST 23 395596181 ps
T621 /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2158835796 Dec 24 02:16:09 PM PST 23 Dec 24 02:17:29 PM PST 23 4601831787 ps
T622 /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2943139556 Dec 24 02:13:00 PM PST 23 Dec 24 02:16:15 PM PST 23 11196201326 ps
T184 /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.1426955068 Dec 24 02:14:26 PM PST 23 Dec 24 02:19:31 PM PST 23 17210058438 ps
T623 /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.3618116468 Dec 24 02:16:52 PM PST 23 Dec 24 02:17:10 PM PST 23 345955009 ps
T624 /workspace/coverage/cover_reg_top/14.xbar_smoke.1747494842 Dec 24 02:10:40 PM PST 23 Dec 24 02:10:48 PM PST 23 133457649 ps
T625 /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1130174555 Dec 24 02:09:42 PM PST 23 Dec 24 02:13:49 PM PST 23 14710037027 ps
T626 /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3098579736 Dec 24 02:09:45 PM PST 23 Dec 24 02:11:21 PM PST 23 5821928221 ps
T627 /workspace/coverage/cover_reg_top/43.xbar_smoke.3900687380 Dec 24 02:12:52 PM PST 23 Dec 24 02:13:00 PM PST 23 44565819 ps
T299 /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.165263429 Dec 24 02:14:57 PM PST 23 Dec 24 02:23:38 PM PST 23 47617935739 ps
T628 /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1815088851 Dec 24 02:12:21 PM PST 23 Dec 24 02:31:17 PM PST 23 68406436701 ps
T629 /workspace/coverage/cover_reg_top/61.xbar_access_same_device.2778035128 Dec 24 02:14:18 PM PST 23 Dec 24 02:15:03 PM PST 23 577213584 ps
T630 /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.631876490 Dec 24 02:15:25 PM PST 23 Dec 24 02:15:55 PM PST 23 689434428 ps
T631 /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.487804634 Dec 24 02:12:45 PM PST 23 Dec 24 02:13:03 PM PST 23 227665204 ps
T632 /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1712521308 Dec 24 02:15:08 PM PST 23 Dec 24 02:15:30 PM PST 23 174345498 ps
T633 /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.6203616 Dec 24 02:11:14 PM PST 23 Dec 24 02:11:23 PM PST 23 43194148 ps
T232 /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.1921231018 Dec 24 02:13:51 PM PST 23 Dec 24 02:14:31 PM PST 23 391742791 ps
T341 /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2449811667 Dec 24 02:09:52 PM PST 23 Dec 24 02:14:05 PM PST 23 4593179846 ps
T381 /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2854153859 Dec 24 02:15:12 PM PST 23 Dec 24 02:28:05 PM PST 23 45450192906 ps
T634 /workspace/coverage/cover_reg_top/43.xbar_random.2118704270 Dec 24 02:12:42 PM PST 23 Dec 24 02:14:00 PM PST 23 1740117807 ps
T139 /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.2175950266 Dec 24 02:11:57 PM PST 23 Dec 24 02:49:24 PM PST 23 137594193947 ps
T635 /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2638421859 Dec 24 02:12:44 PM PST 23 Dec 24 02:35:41 PM PST 23 81762023436 ps
T636 /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.2554119600 Dec 24 02:12:20 PM PST 23 Dec 24 02:12:59 PM PST 23 900182296 ps
T637 /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.156737364 Dec 24 02:15:10 PM PST 23 Dec 24 02:16:48 PM PST 23 9444503445 ps
T638 /workspace/coverage/cover_reg_top/89.xbar_random.2258280315 Dec 24 02:16:12 PM PST 23 Dec 24 02:16:22 PM PST 23 171338739 ps
T639 /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1709658783 Dec 24 02:13:43 PM PST 23 Dec 24 02:26:25 PM PST 23 65112632185 ps
T640 /workspace/coverage/cover_reg_top/39.xbar_same_source.3061078942 Dec 24 02:12:14 PM PST 23 Dec 24 02:12:46 PM PST 23 780959617 ps
T641 /workspace/coverage/cover_reg_top/61.xbar_smoke.2701656245 Dec 24 02:13:45 PM PST 23 Dec 24 02:13:55 PM PST 23 212331173 ps
T642 /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1840496028 Dec 24 02:14:49 PM PST 23 Dec 24 02:15:08 PM PST 23 215826969 ps
T226 /workspace/coverage/cover_reg_top/16.chip_tl_errors.381984188 Dec 24 02:10:45 PM PST 23 Dec 24 02:13:52 PM PST 23 3408432658 ps
T285 /workspace/coverage/cover_reg_top/4.xbar_same_source.276325887 Dec 24 02:09:53 PM PST 23 Dec 24 02:10:21 PM PST 23 769376949 ps
T643 /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1228577842 Dec 24 02:11:57 PM PST 23 Dec 24 02:20:22 PM PST 23 4978061466 ps
T88 /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3163587159 Dec 24 02:10:59 PM PST 23 Dec 24 02:18:38 PM PST 23 9324709504 ps
T644 /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.3963439087 Dec 24 02:14:28 PM PST 23 Dec 24 02:14:35 PM PST 23 39630619 ps
T324 /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1538972956 Dec 24 02:15:41 PM PST 23 Dec 24 02:15:53 PM PST 23 51162888 ps
T645 /workspace/coverage/cover_reg_top/11.xbar_smoke.2238136135 Dec 24 02:11:08 PM PST 23 Dec 24 02:11:18 PM PST 23 193305845 ps
T646 /workspace/coverage/cover_reg_top/83.xbar_random.3687609993 Dec 24 02:15:56 PM PST 23 Dec 24 02:17:23 PM PST 23 2239722135 ps
T241 /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2661992788 Dec 24 02:10:02 PM PST 23 Dec 24 02:11:29 PM PST 23 5356152827 ps
T647 /workspace/coverage/cover_reg_top/2.xbar_error_random.708520622 Dec 24 02:09:56 PM PST 23 Dec 24 02:10:14 PM PST 23 431363649 ps
T259 /workspace/coverage/cover_reg_top/55.xbar_same_source.65237459 Dec 24 02:13:30 PM PST 23 Dec 24 02:14:12 PM PST 23 580012611 ps
T242 /workspace/coverage/cover_reg_top/50.xbar_random.3533653810 Dec 24 02:12:58 PM PST 23 Dec 24 02:13:43 PM PST 23 526537953 ps
T162 /workspace/coverage/cover_reg_top/89.xbar_stress_all.2134885583 Dec 24 02:16:15 PM PST 23 Dec 24 02:26:24 PM PST 23 19522802601 ps
T648 /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.1706709949 Dec 24 02:16:05 PM PST 23 Dec 24 02:19:49 PM PST 23 20810782210 ps
T649 /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.2611013699 Dec 24 02:12:40 PM PST 23 Dec 24 02:13:21 PM PST 23 324076571 ps
T650 /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.480205771 Dec 24 02:14:16 PM PST 23 Dec 24 02:14:24 PM PST 23 50151895 ps
T651 /workspace/coverage/cover_reg_top/62.xbar_random.814207184 Dec 24 02:14:16 PM PST 23 Dec 24 02:14:59 PM PST 23 1009886197 ps
T199 /workspace/coverage/cover_reg_top/2.xbar_smoke.402923769 Dec 24 02:09:50 PM PST 23 Dec 24 02:09:57 PM PST 23 55334871 ps
T652 /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.3573183174 Dec 24 02:11:25 PM PST 23 Dec 24 02:12:36 PM PST 23 6480169272 ps
T653 /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.187206511 Dec 24 02:13:42 PM PST 23 Dec 24 02:13:50 PM PST 23 40218595 ps
T654 /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2860168807 Dec 24 02:09:55 PM PST 23 Dec 24 02:11:30 PM PST 23 5342154042 ps
T655 /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.3449882996 Dec 24 02:10:41 PM PST 23 Dec 24 02:41:01 PM PST 23 107228322396 ps
T656 /workspace/coverage/cover_reg_top/12.xbar_smoke.993514165 Dec 24 02:10:11 PM PST 23 Dec 24 02:10:21 PM PST 23 220134847 ps
T657 /workspace/coverage/cover_reg_top/62.xbar_access_same_device.866560096 Dec 24 02:14:16 PM PST 23 Dec 24 02:16:39 PM PST 23 3513298119 ps
T194 /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.512757876 Dec 24 02:16:21 PM PST 23 Dec 24 02:16:48 PM PST 23 254280775 ps
T658 /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.446511805 Dec 24 02:14:25 PM PST 23 Dec 24 02:17:08 PM PST 23 9522083946 ps
T659 /workspace/coverage/cover_reg_top/88.xbar_smoke.3862491774 Dec 24 02:16:12 PM PST 23 Dec 24 02:16:22 PM PST 23 171699356 ps
T660 /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.2835936327 Dec 24 02:13:32 PM PST 23 Dec 24 02:13:53 PM PST 23 168977543 ps
T661 /workspace/coverage/cover_reg_top/90.xbar_random.1920944576 Dec 24 02:16:23 PM PST 23 Dec 24 02:16:52 PM PST 23 693369296 ps
T662 /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2119802688 Dec 24 02:11:19 PM PST 23 Dec 24 02:12:44 PM PST 23 975408689 ps
T663 /workspace/coverage/cover_reg_top/88.xbar_error_random.3291597341 Dec 24 02:16:07 PM PST 23 Dec 24 02:17:20 PM PST 23 2004315143 ps
T664 /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.872956054 Dec 24 02:16:11 PM PST 23 Dec 24 02:16:51 PM PST 23 482023833 ps
T665 /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3977679468 Dec 24 02:13:37 PM PST 23 Dec 24 02:45:38 PM PST 23 115847734369 ps
T666 /workspace/coverage/cover_reg_top/61.xbar_same_source.3443915440 Dec 24 02:14:18 PM PST 23 Dec 24 02:14:57 PM PST 23 1361520705 ps
T235 /workspace/coverage/cover_reg_top/20.chip_tl_errors.2765692801 Dec 24 02:11:11 PM PST 23 Dec 24 02:13:39 PM PST 23 2472445775 ps
T667 /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1019502653 Dec 24 02:09:54 PM PST 23 Dec 24 02:10:03 PM PST 23 49038615 ps
T668 /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2283125177 Dec 24 02:15:28 PM PST 23 Dec 24 02:15:48 PM PST 23 482215966 ps
T669 /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.997524313 Dec 24 02:12:16 PM PST 23 Dec 24 02:25:49 PM PST 23 67056061992 ps
T670 /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.948113668 Dec 24 02:11:33 PM PST 23 Dec 24 02:22:31 PM PST 23 36622387028 ps
T671 /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.118880613 Dec 24 02:13:45 PM PST 23 Dec 24 02:14:34 PM PST 23 587361054 ps
T672 /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.274037533 Dec 24 02:13:30 PM PST 23 Dec 24 02:15:53 PM PST 23 1475072576 ps
T167 /workspace/coverage/cover_reg_top/36.xbar_stress_all.2328640129 Dec 24 02:12:00 PM PST 23 Dec 24 02:14:41 PM PST 23 4192817718 ps
T673 /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.631899521 Dec 24 02:12:21 PM PST 23 Dec 24 02:12:34 PM PST 23 95378954 ps
T674 /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2149288382 Dec 24 02:10:31 PM PST 23 Dec 24 02:24:34 PM PST 23 86925458298 ps
T675 /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2951961642 Dec 24 02:14:26 PM PST 23 Dec 24 02:21:25 PM PST 23 9851400260 ps
T313 /workspace/coverage/cover_reg_top/75.xbar_same_source.4269216479 Dec 24 02:15:12 PM PST 23 Dec 24 02:15:55 PM PST 23 593817156 ps
T676 /workspace/coverage/cover_reg_top/5.xbar_access_same_device.3067697890 Dec 24 02:09:58 PM PST 23 Dec 24 02:10:29 PM PST 23 375516453 ps
T677 /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.1229144423 Dec 24 02:12:44 PM PST 23 Dec 24 02:13:49 PM PST 23 3525587078 ps
T678 /workspace/coverage/cover_reg_top/26.xbar_smoke.2463429664 Dec 24 02:11:14 PM PST 23 Dec 24 02:11:27 PM PST 23 215944692 ps
T679 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1811208185 Dec 24 02:14:46 PM PST 23 Dec 24 02:15:05 PM PST 23 97919574 ps
T680 /workspace/coverage/cover_reg_top/14.xbar_error_random.1290971300 Dec 24 02:11:15 PM PST 23 Dec 24 02:11:58 PM PST 23 1109040737 ps
T316 /workspace/coverage/cover_reg_top/93.xbar_same_source.2614136016 Dec 24 02:16:37 PM PST 23 Dec 24 02:17:13 PM PST 23 948169660 ps
T681 /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.1958378488 Dec 24 02:15:59 PM PST 23 Dec 24 02:16:41 PM PST 23 3914795549 ps
T382 /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.1121372767 Dec 24 02:09:54 PM PST 23 Dec 24 02:17:49 PM PST 23 26384031292 ps
T682 /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.4127195952 Dec 24 02:15:39 PM PST 23 Dec 24 02:24:51 PM PST 23 13102325401 ps
T683 /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.87322111 Dec 24 02:13:43 PM PST 23 Dec 24 02:17:44 PM PST 23 7662057242 ps
T684 /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.3580380303 Dec 24 02:13:40 PM PST 23 Dec 24 02:13:48 PM PST 23 90963310 ps
T685 /workspace/coverage/cover_reg_top/94.xbar_random.2247883415 Dec 24 02:16:46 PM PST 23 Dec 24 02:17:14 PM PST 23 591506117 ps
T311 /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.234049592 Dec 24 02:10:25 PM PST 23 Dec 24 02:19:18 PM PST 23 54042685097 ps
T309 /workspace/coverage/cover_reg_top/41.xbar_same_source.288743923 Dec 24 02:12:20 PM PST 23 Dec 24 02:12:43 PM PST 23 278733101 ps
T195 /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.3359072665 Dec 24 02:16:20 PM PST 23 Dec 24 02:33:32 PM PST 23 67831066992 ps
T686 /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3458857743 Dec 24 02:11:10 PM PST 23 Dec 24 02:12:21 PM PST 23 4394522846 ps
T687 /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3121477089 Dec 24 02:11:04 PM PST 23 Dec 24 02:19:51 PM PST 23 52540514127 ps
T189 /workspace/coverage/cover_reg_top/30.xbar_same_source.417599295 Dec 24 02:11:20 PM PST 23 Dec 24 02:11:46 PM PST 23 337012992 ps
T688 /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.1259645547 Dec 24 02:10:37 PM PST 23 Dec 24 02:17:50 PM PST 23 7727446456 ps
T148 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.267229651 Dec 24 02:09:41 PM PST 23 Dec 24 02:15:42 PM PST 23 2383220875 ps
T689 /workspace/coverage/cover_reg_top/70.xbar_random.4051337866 Dec 24 02:14:34 PM PST 23 Dec 24 02:15:00 PM PST 23 656210485 ps
T690 /workspace/coverage/cover_reg_top/70.xbar_smoke.1169169680 Dec 24 02:14:33 PM PST 23 Dec 24 02:14:41 PM PST 23 49840867 ps
T691 /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.809547862 Dec 24 02:12:40 PM PST 23 Dec 24 02:14:19 PM PST 23 5330765116 ps
T171 /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1789617897 Dec 24 02:11:32 PM PST 23 Dec 24 02:20:55 PM PST 23 14479293879 ps
T692 /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1763605617 Dec 24 02:12:04 PM PST 23 Dec 24 02:13:25 PM PST 23 4341736429 ps
T331 /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.1763595820 Dec 24 02:13:36 PM PST 23 Dec 24 02:28:54 PM PST 23 58212817473 ps
T328 /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3913750976 Dec 24 02:12:01 PM PST 23 Dec 24 02:12:13 PM PST 23 45492019 ps
T693 /workspace/coverage/cover_reg_top/18.xbar_smoke.3586304745 Dec 24 02:10:45 PM PST 23 Dec 24 02:10:58 PM PST 23 241228362 ps
T224 /workspace/coverage/cover_reg_top/18.chip_tl_errors.2641374655 Dec 24 02:11:17 PM PST 23 Dec 24 02:14:00 PM PST 23 3098515272 ps
T694 /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3374486496 Dec 24 02:16:56 PM PST 23 Dec 24 02:33:36 PM PST 23 100943244585 ps
T695 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2881717788 Dec 24 02:11:13 PM PST 23 Dec 24 02:15:34 PM PST 23 7899587516 ps
T696 /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1794608874 Dec 24 02:14:28 PM PST 23 Dec 24 02:18:40 PM PST 23 2421858747 ps
T697 /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.4056520577 Dec 24 02:11:23 PM PST 23 Dec 24 02:11:44 PM PST 23 212224242 ps
T698 /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.4163261638 Dec 24 02:14:34 PM PST 23 Dec 24 02:15:47 PM PST 23 4107579162 ps
T699 /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2799249826 Dec 24 02:10:26 PM PST 23 Dec 24 02:11:31 PM PST 23 3712464507 ps
T53 /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.235306446 Dec 24 02:09:55 PM PST 23 Dec 24 02:15:48 PM PST 23 7289454184 ps
T700 /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1678404143 Dec 24 02:15:05 PM PST 23 Dec 24 02:16:34 PM PST 23 5130264498 ps
T84 /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2926544506 Dec 24 02:10:12 PM PST 23 Dec 24 02:37:57 PM PST 23 16670306876 ps
T701 /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1612821365 Dec 24 02:13:35 PM PST 23 Dec 24 02:15:07 PM PST 23 5534852438 ps
T702 /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2025882739 Dec 24 02:13:18 PM PST 23 Dec 24 02:14:16 PM PST 23 617669916 ps
T703 /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2893927291 Dec 24 02:15:57 PM PST 23 Dec 24 02:16:47 PM PST 23 1171267124 ps
T704 /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.3386890545 Dec 24 02:16:08 PM PST 23 Dec 24 02:16:26 PM PST 23 156156819 ps
T227 /workspace/coverage/cover_reg_top/14.chip_tl_errors.2019795806 Dec 24 02:11:10 PM PST 23 Dec 24 02:14:45 PM PST 23 3226686594 ps
T705 /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.1262434506 Dec 24 02:16:42 PM PST 23 Dec 24 02:30:22 PM PST 23 53591472339 ps
T225 /workspace/coverage/cover_reg_top/25.chip_tl_errors.3092019980 Dec 24 02:11:22 PM PST 23 Dec 24 02:18:03 PM PST 23 4480299568 ps
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