Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.37 88.78 85.73 70.11 86.46 88.35 98.80


Total test records in report: 1927
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T411 /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.2392957956 Dec 27 01:49:37 PM PST 23 Dec 27 01:51:27 PM PST 23 10145196101 ps
T412 /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.563475769 Dec 27 01:47:46 PM PST 23 Dec 27 01:47:56 PM PST 23 71806645 ps
T413 /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1066750069 Dec 27 01:40:27 PM PST 23 Dec 27 01:40:57 PM PST 23 821842836 ps
T414 /workspace/coverage/cover_reg_top/36.xbar_smoke.4170253131 Dec 27 01:44:55 PM PST 23 Dec 27 01:45:05 PM PST 23 37516813 ps
T415 /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3604691718 Dec 27 01:48:53 PM PST 23 Dec 27 01:49:23 PM PST 23 77765044 ps
T416 /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.2070992932 Dec 27 01:47:30 PM PST 23 Dec 27 01:47:46 PM PST 23 154776457 ps
T136 /workspace/coverage/cover_reg_top/90.xbar_stress_all.342219563 Dec 27 01:49:44 PM PST 23 Dec 27 01:57:04 PM PST 23 11870829632 ps
T232 /workspace/coverage/cover_reg_top/17.xbar_same_source.176867756 Dec 27 01:43:12 PM PST 23 Dec 27 01:43:46 PM PST 23 465250455 ps
T417 /workspace/coverage/cover_reg_top/92.xbar_error_random.3850855140 Dec 27 01:49:31 PM PST 23 Dec 27 01:49:43 PM PST 23 215672924 ps
T418 /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.1327793102 Dec 27 01:40:41 PM PST 23 Dec 27 01:41:32 PM PST 23 1266234000 ps
T419 /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2121189795 Dec 27 01:46:31 PM PST 23 Dec 27 01:49:29 PM PST 23 5064290230 ps
T250 /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.4262370692 Dec 27 01:46:20 PM PST 23 Dec 27 01:47:53 PM PST 23 5675638740 ps
T210 /workspace/coverage/cover_reg_top/19.chip_tl_errors.1838051087 Dec 27 01:43:12 PM PST 23 Dec 27 01:49:44 PM PST 23 4808130869 ps
T217 /workspace/coverage/cover_reg_top/15.chip_tl_errors.978926958 Dec 27 01:43:01 PM PST 23 Dec 27 01:48:31 PM PST 23 3971873800 ps
T420 /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1100469426 Dec 27 01:42:55 PM PST 23 Dec 27 01:44:18 PM PST 23 257958346 ps
T166 /workspace/coverage/cover_reg_top/56.xbar_random.3753477391 Dec 27 01:47:04 PM PST 23 Dec 27 01:48:08 PM PST 23 1686644325 ps
T421 /workspace/coverage/cover_reg_top/11.xbar_error_random.2511553427 Dec 27 01:41:53 PM PST 23 Dec 27 01:43:19 PM PST 23 2169056650 ps
T422 /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3717154047 Dec 27 01:48:39 PM PST 23 Dec 27 01:49:04 PM PST 23 165377835 ps
T121 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.1946752520 Dec 27 01:44:10 PM PST 23 Dec 27 01:55:24 PM PST 23 5371147824 ps
T310 /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2471128259 Dec 27 01:48:35 PM PST 23 Dec 27 02:24:14 PM PST 23 121821274999 ps
T423 /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1535916300 Dec 27 01:40:24 PM PST 23 Dec 27 01:42:01 PM PST 23 9005710102 ps
T305 /workspace/coverage/cover_reg_top/19.xbar_access_same_device.3921272988 Dec 27 01:42:26 PM PST 23 Dec 27 01:43:26 PM PST 23 703960184 ps
T424 /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4000263516 Dec 27 01:42:17 PM PST 23 Dec 27 01:42:25 PM PST 23 52625200 ps
T425 /workspace/coverage/cover_reg_top/55.xbar_smoke.2845665454 Dec 27 01:46:01 PM PST 23 Dec 27 01:46:08 PM PST 23 45422511 ps
T426 /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.3192643293 Dec 27 01:46:35 PM PST 23 Dec 27 01:47:23 PM PST 23 962018330 ps
T427 /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3315810068 Dec 27 01:43:58 PM PST 23 Dec 27 01:44:05 PM PST 23 50873166 ps
T306 /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.824091369 Dec 27 01:42:15 PM PST 23 Dec 27 01:50:05 PM PST 23 4102427357 ps
T277 /workspace/coverage/cover_reg_top/71.xbar_access_same_device.3952128778 Dec 27 01:47:36 PM PST 23 Dec 27 01:47:54 PM PST 23 311525763 ps
T428 /workspace/coverage/cover_reg_top/19.xbar_error_random.1464660924 Dec 27 01:42:58 PM PST 23 Dec 27 01:43:17 PM PST 23 474974521 ps
T256 /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3469336002 Dec 27 01:48:38 PM PST 23 Dec 27 02:07:39 PM PST 23 66195785878 ps
T65 /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.784672536 Dec 27 01:41:48 PM PST 23 Dec 27 02:09:34 PM PST 23 14746410213 ps
T235 /workspace/coverage/cover_reg_top/79.xbar_same_source.2115124421 Dec 27 01:48:52 PM PST 23 Dec 27 01:50:11 PM PST 23 2473889949 ps
T151 /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.1726820706 Dec 27 01:40:54 PM PST 23 Dec 27 01:41:44 PM PST 23 1261231526 ps
T55 /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1397238657 Dec 27 01:40:37 PM PST 23 Dec 27 02:35:52 PM PST 23 31281333989 ps
T429 /workspace/coverage/cover_reg_top/33.xbar_smoke.2963916528 Dec 27 01:44:03 PM PST 23 Dec 27 01:44:10 PM PST 23 55373244 ps
T430 /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2569583140 Dec 27 01:47:47 PM PST 23 Dec 27 01:49:07 PM PST 23 4499663824 ps
T431 /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.2589422166 Dec 27 01:42:15 PM PST 23 Dec 27 01:43:55 PM PST 23 10097947010 ps
T282 /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.438134333 Dec 27 01:49:13 PM PST 23 Dec 27 02:04:22 PM PST 23 51766636965 ps
T432 /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.3306207589 Dec 27 01:49:33 PM PST 23 Dec 27 02:04:06 PM PST 23 51091740489 ps
T66 /workspace/coverage/cover_reg_top/7.chip_csr_rw.1744019681 Dec 27 01:42:08 PM PST 23 Dec 27 01:48:16 PM PST 23 3844391216 ps
T433 /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.379184855 Dec 27 01:49:29 PM PST 23 Dec 27 01:51:18 PM PST 23 5973825152 ps
T434 /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.1362474261 Dec 27 01:49:39 PM PST 23 Dec 27 01:59:24 PM PST 23 16193429218 ps
T435 /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1680349867 Dec 27 01:42:57 PM PST 23 Dec 27 01:43:05 PM PST 23 48091405 ps
T436 /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2942447984 Dec 27 01:44:10 PM PST 23 Dec 27 01:45:31 PM PST 23 5293596396 ps
T255 /workspace/coverage/cover_reg_top/52.xbar_random.800074949 Dec 27 01:45:35 PM PST 23 Dec 27 01:46:02 PM PST 23 323498107 ps
T437 /workspace/coverage/cover_reg_top/82.xbar_same_source.1851829919 Dec 27 01:48:55 PM PST 23 Dec 27 01:49:33 PM PST 23 536844551 ps
T438 /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3209546082 Dec 27 01:40:25 PM PST 23 Dec 27 01:42:16 PM PST 23 6431519479 ps
T439 /workspace/coverage/cover_reg_top/8.xbar_access_same_device.931890754 Dec 27 01:41:45 PM PST 23 Dec 27 01:41:58 PM PST 23 261252617 ps
T162 /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.982557362 Dec 27 01:49:05 PM PST 23 Dec 27 02:07:59 PM PST 23 104752910137 ps
T440 /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2074852240 Dec 27 01:47:37 PM PST 23 Dec 27 01:48:12 PM PST 23 283615874 ps
T441 /workspace/coverage/cover_reg_top/10.xbar_random.867524285 Dec 27 01:41:46 PM PST 23 Dec 27 01:41:56 PM PST 23 176568443 ps
T122 /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.2997294200 Dec 27 01:40:30 PM PST 23 Dec 27 01:41:05 PM PST 23 406351128 ps
T327 /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.1918867467 Dec 27 01:49:45 PM PST 23 Dec 27 01:53:22 PM PST 23 466278262 ps
T181 /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.1719118606 Dec 27 01:47:34 PM PST 23 Dec 27 01:48:20 PM PST 23 513083353 ps
T442 /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.2562596253 Dec 27 01:47:41 PM PST 23 Dec 27 01:47:59 PM PST 23 142436800 ps
T443 /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2274134581 Dec 27 01:46:33 PM PST 23 Dec 27 01:50:40 PM PST 23 24747585446 ps
T156 /workspace/coverage/cover_reg_top/18.xbar_stress_all.2667127730 Dec 27 01:43:08 PM PST 23 Dec 27 01:49:57 PM PST 23 10630477940 ps
T245 /workspace/coverage/cover_reg_top/47.xbar_random.3472869417 Dec 27 01:45:30 PM PST 23 Dec 27 01:46:18 PM PST 23 547774199 ps
T444 /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1196136952 Dec 27 01:42:54 PM PST 23 Dec 27 01:43:17 PM PST 23 554317199 ps
T445 /workspace/coverage/cover_reg_top/67.xbar_random.1512218287 Dec 27 01:47:28 PM PST 23 Dec 27 01:48:23 PM PST 23 1570506409 ps
T446 /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2822469497 Dec 27 01:49:38 PM PST 23 Dec 27 01:49:55 PM PST 23 286227097 ps
T447 /workspace/coverage/cover_reg_top/44.xbar_same_source.1626995992 Dec 27 01:44:58 PM PST 23 Dec 27 01:45:24 PM PST 23 802999133 ps
T448 /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.370158428 Dec 27 01:42:08 PM PST 23 Dec 27 01:42:17 PM PST 23 128739277 ps
T449 /workspace/coverage/cover_reg_top/88.xbar_error_random.3430639920 Dec 27 01:48:57 PM PST 23 Dec 27 01:49:37 PM PST 23 1259403683 ps
T450 /workspace/coverage/cover_reg_top/48.xbar_error_random.1603018983 Dec 27 01:45:35 PM PST 23 Dec 27 01:46:21 PM PST 23 589189789 ps
T280 /workspace/coverage/cover_reg_top/46.xbar_access_same_device.432851508 Dec 27 01:45:24 PM PST 23 Dec 27 01:46:15 PM PST 23 1187472229 ps
T214 /workspace/coverage/cover_reg_top/27.chip_tl_errors.2238679981 Dec 27 01:43:02 PM PST 23 Dec 27 01:47:38 PM PST 23 3641036396 ps
T176 /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1629869441 Dec 27 01:42:41 PM PST 23 Dec 27 01:55:58 PM PST 23 52081566682 ps
T223 /workspace/coverage/cover_reg_top/26.chip_tl_errors.2874688794 Dec 27 01:43:10 PM PST 23 Dec 27 01:46:27 PM PST 23 3287933190 ps
T301 /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.3596838567 Dec 27 01:44:47 PM PST 23 Dec 27 02:07:49 PM PST 23 76630707413 ps
T451 /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.260304784 Dec 27 01:47:39 PM PST 23 Dec 27 01:49:34 PM PST 23 421057340 ps
T452 /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.2868068185 Dec 27 01:47:24 PM PST 23 Dec 27 02:05:27 PM PST 23 109011621906 ps
T453 /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.979582945 Dec 27 01:49:46 PM PST 23 Dec 27 01:49:55 PM PST 23 50376145 ps
T454 /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.2296629965 Dec 27 01:47:32 PM PST 23 Dec 27 01:48:59 PM PST 23 8166996265 ps
T455 /workspace/coverage/cover_reg_top/86.xbar_same_source.679120329 Dec 27 01:49:45 PM PST 23 Dec 27 01:50:08 PM PST 23 587695910 ps
T456 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.32060080 Dec 27 01:42:55 PM PST 23 Dec 27 01:47:35 PM PST 23 3294277134 ps
T185 /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.3993447339 Dec 27 01:43:00 PM PST 23 Dec 27 01:54:48 PM PST 23 42681465192 ps
T457 /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.3225879818 Dec 27 01:45:28 PM PST 23 Dec 27 01:45:38 PM PST 23 92878826 ps
T458 /workspace/coverage/cover_reg_top/14.xbar_error_random.729569519 Dec 27 01:42:44 PM PST 23 Dec 27 01:43:13 PM PST 23 293521221 ps
T459 /workspace/coverage/cover_reg_top/84.xbar_random.4100891054 Dec 27 01:48:40 PM PST 23 Dec 27 01:48:53 PM PST 23 253657453 ps
T177 /workspace/coverage/cover_reg_top/13.xbar_stress_all.196286869 Dec 27 01:41:51 PM PST 23 Dec 27 01:46:25 PM PST 23 3171744376 ps
T127 /workspace/coverage/cover_reg_top/57.xbar_stress_all.3710018905 Dec 27 01:46:22 PM PST 23 Dec 27 01:54:52 PM PST 23 13720278888 ps
T460 /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.999002217 Dec 27 01:49:47 PM PST 23 Dec 27 02:07:41 PM PST 23 61160818167 ps
T461 /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.1646792971 Dec 27 01:42:48 PM PST 23 Dec 27 01:43:06 PM PST 23 164002136 ps
T462 /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.465983264 Dec 27 01:40:34 PM PST 23 Dec 27 01:40:57 PM PST 23 182476579 ps
T463 /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3865560801 Dec 27 01:40:36 PM PST 23 Dec 27 01:53:52 PM PST 23 44814410253 ps
T464 /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.3717114914 Dec 27 01:42:44 PM PST 23 Dec 27 01:44:19 PM PST 23 8792856494 ps
T465 /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4210946681 Dec 27 01:42:13 PM PST 23 Dec 27 01:50:44 PM PST 23 31920900256 ps
T224 /workspace/coverage/cover_reg_top/6.chip_tl_errors.1644918333 Dec 27 01:41:19 PM PST 23 Dec 27 01:43:20 PM PST 23 3338802992 ps
T466 /workspace/coverage/cover_reg_top/9.xbar_same_source.2520479944 Dec 27 01:41:44 PM PST 23 Dec 27 01:42:03 PM PST 23 255720533 ps
T44 /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.1959104007 Dec 27 01:40:28 PM PST 23 Dec 27 01:48:34 PM PST 23 11899642912 ps
T467 /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.1336864041 Dec 27 01:47:05 PM PST 23 Dec 27 01:48:00 PM PST 23 1218316538 ps
T194 /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.1554000474 Dec 27 01:49:28 PM PST 23 Dec 27 01:49:55 PM PST 23 292609225 ps
T468 /workspace/coverage/cover_reg_top/17.xbar_smoke.552751683 Dec 27 01:42:54 PM PST 23 Dec 27 01:43:05 PM PST 23 245422533 ps
T469 /workspace/coverage/cover_reg_top/3.xbar_error_random.2699119261 Dec 27 01:40:29 PM PST 23 Dec 27 01:40:53 PM PST 23 661691002 ps
T470 /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.193616591 Dec 27 01:47:05 PM PST 23 Dec 27 01:47:14 PM PST 23 47955989 ps
T471 /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3744460711 Dec 27 01:48:17 PM PST 23 Dec 27 01:50:06 PM PST 23 9972052340 ps
T278 /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2269055479 Dec 27 01:44:32 PM PST 23 Dec 27 02:07:28 PM PST 23 90243744865 ps
T283 /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3625565614 Dec 27 01:40:42 PM PST 23 Dec 27 02:16:33 PM PST 23 139208179409 ps
T472 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.2267321860 Dec 27 01:44:46 PM PST 23 Dec 27 01:48:03 PM PST 23 5930402131 ps
T473 /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.3531643821 Dec 27 01:40:43 PM PST 23 Dec 27 01:45:43 PM PST 23 17367933412 ps
T144 /workspace/coverage/cover_reg_top/54.xbar_stress_all.2903347805 Dec 27 01:46:10 PM PST 23 Dec 27 01:49:08 PM PST 23 5366293420 ps
T474 /workspace/coverage/cover_reg_top/10.xbar_smoke.3872842507 Dec 27 01:41:21 PM PST 23 Dec 27 01:41:32 PM PST 23 244653652 ps
T475 /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.4048029999 Dec 27 01:44:55 PM PST 23 Dec 27 01:46:18 PM PST 23 1115309238 ps
T476 /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3905359454 Dec 27 01:47:26 PM PST 23 Dec 27 01:48:24 PM PST 23 213608444 ps
T477 /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2484290943 Dec 27 01:42:16 PM PST 23 Dec 27 01:43:46 PM PST 23 5457877678 ps
T54 /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.3436049884 Dec 27 01:42:13 PM PST 23 Dec 27 01:45:57 PM PST 23 5049875446 ps
T36 /workspace/coverage/cover_reg_top/0.chip_csr_rw.3205668802 Dec 27 01:40:36 PM PST 23 Dec 27 01:49:39 PM PST 23 5567080808 ps
T478 /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.2689215475 Dec 27 01:50:00 PM PST 23 Dec 27 01:51:27 PM PST 23 8142148461 ps
T479 /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3349465782 Dec 27 01:42:09 PM PST 23 Dec 27 01:42:35 PM PST 23 253231109 ps
T135 /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.3548891191 Dec 27 01:45:25 PM PST 23 Dec 27 01:55:49 PM PST 23 58995702902 ps
T480 /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1924851325 Dec 27 01:46:37 PM PST 23 Dec 27 02:03:50 PM PST 23 64022207077 ps
T481 /workspace/coverage/cover_reg_top/41.xbar_random.1807184180 Dec 27 01:44:50 PM PST 23 Dec 27 01:45:40 PM PST 23 1409264184 ps
T482 /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.1232899554 Dec 27 01:42:50 PM PST 23 Dec 27 01:49:16 PM PST 23 7620859546 ps
T483 /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3516552979 Dec 27 01:41:48 PM PST 23 Dec 27 01:43:11 PM PST 23 5062928816 ps
T484 /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.832186287 Dec 27 01:42:46 PM PST 23 Dec 27 02:11:41 PM PST 23 103863543002 ps
T485 /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.827017444 Dec 27 01:47:39 PM PST 23 Dec 27 01:49:40 PM PST 23 10182201336 ps
T486 /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2014935298 Dec 27 01:46:03 PM PST 23 Dec 27 01:52:01 PM PST 23 18516859862 ps
T487 /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.2390553222 Dec 27 01:48:51 PM PST 23 Dec 27 01:58:33 PM PST 23 35649599650 ps
T295 /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3489228185 Dec 27 01:47:41 PM PST 23 Dec 27 02:28:27 PM PST 23 140356254653 ps
T488 /workspace/coverage/cover_reg_top/12.xbar_random.283689564 Dec 27 01:42:12 PM PST 23 Dec 27 01:42:46 PM PST 23 1015914121 ps
T489 /workspace/coverage/cover_reg_top/33.xbar_error_random.781563578 Dec 27 01:44:08 PM PST 23 Dec 27 01:45:15 PM PST 23 2042794455 ps
T180 /workspace/coverage/cover_reg_top/53.xbar_same_source.3166852066 Dec 27 01:45:58 PM PST 23 Dec 27 01:46:24 PM PST 23 356826546 ps
T490 /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1450306433 Dec 27 01:49:50 PM PST 23 Dec 27 02:25:13 PM PST 23 124013794043 ps
T491 /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1808003172 Dec 27 01:43:00 PM PST 23 Dec 27 01:43:42 PM PST 23 627853843 ps
T157 /workspace/coverage/cover_reg_top/10.xbar_stress_all.3700613681 Dec 27 01:41:18 PM PST 23 Dec 27 01:50:49 PM PST 23 14606380064 ps
T492 /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.3159820042 Dec 27 01:49:27 PM PST 23 Dec 27 01:49:35 PM PST 23 64103104 ps
T493 /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.120507683 Dec 27 01:47:27 PM PST 23 Dec 27 01:47:34 PM PST 23 72837912 ps
T494 /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.493232667 Dec 27 01:44:44 PM PST 23 Dec 27 01:44:51 PM PST 23 45587929 ps
T495 /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1183674533 Dec 27 01:49:59 PM PST 23 Dec 27 01:50:47 PM PST 23 1028294752 ps
T496 /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2756760939 Dec 27 01:45:01 PM PST 23 Dec 27 01:45:37 PM PST 23 301497076 ps
T497 /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.1435262288 Dec 27 01:47:27 PM PST 23 Dec 27 01:48:00 PM PST 23 785994683 ps
T498 /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.158193996 Dec 27 01:43:03 PM PST 23 Dec 27 01:43:53 PM PST 23 566187602 ps
T499 /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2139449851 Dec 27 01:49:52 PM PST 23 Dec 27 01:51:05 PM PST 23 4475528840 ps
T221 /workspace/coverage/cover_reg_top/0.chip_tl_errors.2720323628 Dec 27 01:40:07 PM PST 23 Dec 27 01:44:33 PM PST 23 3862173908 ps
T159 /workspace/coverage/cover_reg_top/33.xbar_stress_all.2603288587 Dec 27 01:44:01 PM PST 23 Dec 27 01:47:48 PM PST 23 2098271376 ps
T500 /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.340910054 Dec 27 01:44:45 PM PST 23 Dec 27 01:51:20 PM PST 23 10331777529 ps
T501 /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.1258625377 Dec 27 01:45:43 PM PST 23 Dec 27 01:49:55 PM PST 23 7220167062 ps
T153 /workspace/coverage/cover_reg_top/77.xbar_access_same_device.3613775562 Dec 27 01:47:44 PM PST 23 Dec 27 01:49:15 PM PST 23 1010286309 ps
T502 /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.554916376 Dec 27 01:41:51 PM PST 23 Dec 27 01:41:57 PM PST 23 64030099 ps
T296 /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3375057093 Dec 27 01:48:30 PM PST 23 Dec 27 02:10:20 PM PST 23 74946140515 ps
T503 /workspace/coverage/cover_reg_top/94.xbar_same_source.3931818131 Dec 27 01:49:39 PM PST 23 Dec 27 01:50:20 PM PST 23 498880371 ps
T186 /workspace/coverage/cover_reg_top/88.xbar_same_source.3622462794 Dec 27 01:49:30 PM PST 23 Dec 27 01:50:44 PM PST 23 2346218127 ps
T504 /workspace/coverage/cover_reg_top/8.xbar_random.1642208857 Dec 27 01:42:11 PM PST 23 Dec 27 01:42:27 PM PST 23 350438827 ps
T505 /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.2580643490 Dec 27 01:44:51 PM PST 23 Dec 27 01:46:24 PM PST 23 5296160659 ps
T46 /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.4071792246 Dec 27 01:40:39 PM PST 23 Dec 27 01:44:11 PM PST 23 5604368344 ps
T211 /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.3530723352 Dec 27 01:49:38 PM PST 23 Dec 27 01:50:06 PM PST 23 538180586 ps
T506 /workspace/coverage/cover_reg_top/86.xbar_random.447242578 Dec 27 01:50:08 PM PST 23 Dec 27 01:50:35 PM PST 23 717582874 ps
T507 /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.1581279002 Dec 27 01:44:49 PM PST 23 Dec 27 01:51:12 PM PST 23 20959439409 ps
T508 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3142938040 Dec 27 01:40:30 PM PST 23 Dec 27 01:49:28 PM PST 23 5302859207 ps
T509 /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.2586123429 Dec 27 01:45:37 PM PST 23 Dec 27 01:45:44 PM PST 23 48045361 ps
T510 /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.439416923 Dec 27 01:41:50 PM PST 23 Dec 27 01:44:02 PM PST 23 345123058 ps
T511 /workspace/coverage/cover_reg_top/88.xbar_random.2094922363 Dec 27 01:49:13 PM PST 23 Dec 27 01:50:32 PM PST 23 2370353194 ps
T40 /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3684138218 Dec 27 01:40:34 PM PST 23 Dec 27 03:11:31 PM PST 23 38751620362 ps
T512 /workspace/coverage/cover_reg_top/44.xbar_random.4140856348 Dec 27 01:45:27 PM PST 23 Dec 27 01:46:13 PM PST 23 532262819 ps
T513 /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.2098866644 Dec 27 01:44:47 PM PST 23 Dec 27 01:45:33 PM PST 23 474099356 ps
T514 /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2063794023 Dec 27 01:44:48 PM PST 23 Dec 27 01:47:25 PM PST 23 14412641023 ps
T170 /workspace/coverage/cover_reg_top/49.xbar_stress_all.3178760484 Dec 27 01:45:40 PM PST 23 Dec 27 01:50:24 PM PST 23 7734485220 ps
T515 /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.1596472456 Dec 27 01:44:45 PM PST 23 Dec 27 01:45:06 PM PST 23 154722724 ps
T234 /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.2152140370 Dec 27 01:47:57 PM PST 23 Dec 27 01:51:27 PM PST 23 7296885764 ps
T516 /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.3451329300 Dec 27 01:49:27 PM PST 23 Dec 27 01:49:54 PM PST 23 285752431 ps
T517 /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.1848569280 Dec 27 01:42:59 PM PST 23 Dec 27 01:43:06 PM PST 23 32829758 ps
T518 /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.486914709 Dec 27 01:42:47 PM PST 23 Dec 27 01:44:25 PM PST 23 8680524235 ps
T139 /workspace/coverage/cover_reg_top/69.xbar_access_same_device.1748663084 Dec 27 01:47:26 PM PST 23 Dec 27 01:48:53 PM PST 23 1893009640 ps
T519 /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.2540497513 Dec 27 01:47:05 PM PST 23 Dec 27 01:47:14 PM PST 23 69186949 ps
T229 /workspace/coverage/cover_reg_top/21.chip_tl_errors.3065331567 Dec 27 01:43:03 PM PST 23 Dec 27 01:48:53 PM PST 23 4695626843 ps
T520 /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.864746224 Dec 27 01:46:18 PM PST 23 Dec 27 01:46:38 PM PST 23 394366089 ps
T161 /workspace/coverage/cover_reg_top/68.xbar_stress_all.2824341291 Dec 27 01:47:23 PM PST 23 Dec 27 01:49:39 PM PST 23 1569686896 ps
T521 /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.4099432320 Dec 27 01:49:16 PM PST 23 Dec 27 02:34:46 PM PST 23 163139266816 ps
T522 /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1030750802 Dec 27 01:47:37 PM PST 23 Dec 27 01:49:10 PM PST 23 4935833060 ps
T523 /workspace/coverage/cover_reg_top/82.xbar_error_random.2109383030 Dec 27 01:49:13 PM PST 23 Dec 27 01:49:50 PM PST 23 488477734 ps
T524 /workspace/coverage/cover_reg_top/8.xbar_same_source.2331229759 Dec 27 01:41:44 PM PST 23 Dec 27 01:41:51 PM PST 23 46855022 ps
T525 /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.2562624093 Dec 27 01:44:48 PM PST 23 Dec 27 01:45:16 PM PST 23 315411303 ps
T526 /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.117947253 Dec 27 01:41:50 PM PST 23 Dec 27 01:54:58 PM PST 23 46822992485 ps
T172 /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2152637008 Dec 27 01:46:34 PM PST 23 Dec 27 01:50:47 PM PST 23 6016111744 ps
T527 /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3730790948 Dec 27 01:44:47 PM PST 23 Dec 27 01:45:31 PM PST 23 1199904653 ps
T528 /workspace/coverage/cover_reg_top/4.xbar_access_same_device.1742350746 Dec 27 01:40:32 PM PST 23 Dec 27 01:41:21 PM PST 23 576537745 ps
T56 /workspace/coverage/cover_reg_top/8.chip_csr_rw.1158228588 Dec 27 01:41:17 PM PST 23 Dec 27 01:50:19 PM PST 23 5161862573 ps
T297 /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.16876129 Dec 27 01:43:24 PM PST 23 Dec 27 01:51:14 PM PST 23 27907076470 ps
T529 /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2939116948 Dec 27 01:43:00 PM PST 23 Dec 27 01:43:21 PM PST 23 155049572 ps
T337 /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.4210706899 Dec 27 01:44:49 PM PST 23 Dec 27 01:46:36 PM PST 23 404244818 ps
T530 /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.2477817495 Dec 27 01:47:32 PM PST 23 Dec 27 01:47:44 PM PST 23 46614530 ps
T531 /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1938207892 Dec 27 01:47:00 PM PST 23 Dec 27 01:49:16 PM PST 23 349151364 ps
T307 /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.217710021 Dec 27 01:47:04 PM PST 23 Dec 27 02:11:17 PM PST 23 88176214869 ps
T532 /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.714048730 Dec 27 01:48:40 PM PST 23 Dec 27 02:02:15 PM PST 23 50680143949 ps
T533 /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.1836107236 Dec 27 01:47:25 PM PST 23 Dec 27 01:54:28 PM PST 23 12365038095 ps
T534 /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.3622284544 Dec 27 01:47:28 PM PST 23 Dec 27 01:47:37 PM PST 23 55306579 ps
T535 /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2062042279 Dec 27 01:46:45 PM PST 23 Dec 27 01:48:33 PM PST 23 6323859302 ps
T57 /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2477135043 Dec 27 01:42:13 PM PST 23 Dec 27 02:09:52 PM PST 23 14097995786 ps
T536 /workspace/coverage/cover_reg_top/51.xbar_random.1461557638 Dec 27 01:45:40 PM PST 23 Dec 27 01:45:48 PM PST 23 59052479 ps
T106 /workspace/coverage/cover_reg_top/19.chip_csr_rw.4122266267 Dec 27 01:42:13 PM PST 23 Dec 27 01:47:24 PM PST 23 4136416760 ps
T537 /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2133251405 Dec 27 01:48:39 PM PST 23 Dec 27 01:49:12 PM PST 23 761142797 ps
T321 /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2210690034 Dec 27 01:44:36 PM PST 23 Dec 27 01:48:46 PM PST 23 4406201746 ps
T538 /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3188667824 Dec 27 01:49:39 PM PST 23 Dec 27 01:57:25 PM PST 23 27919563527 ps
T41 /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1613131443 Dec 27 01:40:31 PM PST 23 Dec 27 02:29:13 PM PST 23 31631130975 ps
T160 /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.2521644444 Dec 27 01:44:28 PM PST 23 Dec 27 02:07:01 PM PST 23 121278061823 ps
T539 /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.308449488 Dec 27 01:41:18 PM PST 23 Dec 27 01:59:30 PM PST 23 66161454334 ps
T540 /workspace/coverage/cover_reg_top/11.xbar_smoke.450758915 Dec 27 01:42:14 PM PST 23 Dec 27 01:42:23 PM PST 23 226709181 ps
T541 /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.3189097161 Dec 27 01:47:58 PM PST 23 Dec 27 01:48:04 PM PST 23 39044870 ps
T542 /workspace/coverage/cover_reg_top/13.xbar_same_source.3211268626 Dec 27 01:42:09 PM PST 23 Dec 27 01:42:29 PM PST 23 254365418 ps
T543 /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1544983923 Dec 27 01:47:57 PM PST 23 Dec 27 01:48:41 PM PST 23 979918306 ps
T544 /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.3850554366 Dec 27 01:49:46 PM PST 23 Dec 27 01:51:26 PM PST 23 551702543 ps
T545 /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.206452790 Dec 27 01:49:42 PM PST 23 Dec 27 01:50:17 PM PST 23 211203582 ps
T546 /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1913627866 Dec 27 01:42:51 PM PST 23 Dec 27 01:43:44 PM PST 23 591497865 ps
T267 /workspace/coverage/cover_reg_top/2.chip_csr_rw.929792637 Dec 27 01:40:29 PM PST 23 Dec 27 01:45:32 PM PST 23 3551471227 ps
T547 /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.3277147172 Dec 27 01:47:28 PM PST 23 Dec 27 01:48:11 PM PST 23 919190180 ps
T339 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1522016988 Dec 27 01:42:59 PM PST 23 Dec 27 01:45:01 PM PST 23 268393269 ps
T336 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.414678685 Dec 27 01:43:36 PM PST 23 Dec 27 01:54:15 PM PST 23 9165355952 ps
T548 /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.3219349135 Dec 27 01:46:19 PM PST 23 Dec 27 01:51:08 PM PST 23 24121784632 ps
T257 /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1565989165 Dec 27 01:42:57 PM PST 23 Dec 27 01:48:04 PM PST 23 3850306246 ps
T549 /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2877522312 Dec 27 01:45:35 PM PST 23 Dec 27 02:04:52 PM PST 23 69667378037 ps
T550 /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.2016803827 Dec 27 01:40:55 PM PST 23 Dec 27 01:42:25 PM PST 23 5129545800 ps
T551 /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.821257981 Dec 27 01:49:10 PM PST 23 Dec 27 01:49:22 PM PST 23 80268924 ps
T552 /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.2468926486 Dec 27 01:40:37 PM PST 23 Dec 27 01:40:44 PM PST 23 48132546 ps
T553 /workspace/coverage/cover_reg_top/38.xbar_error_random.2229958882 Dec 27 01:44:50 PM PST 23 Dec 27 01:46:09 PM PST 23 2305187067 ps
T554 /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2937780347 Dec 27 01:46:34 PM PST 23 Dec 27 01:47:37 PM PST 23 5922611489 ps
T555 /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1369641291 Dec 27 01:43:39 PM PST 23 Dec 27 01:44:25 PM PST 23 1065793336 ps
T556 /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.4116930213 Dec 27 01:43:37 PM PST 23 Dec 27 01:45:26 PM PST 23 6302466650 ps
T557 /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.427921102 Dec 27 01:49:14 PM PST 23 Dec 27 01:50:08 PM PST 23 3277448886 ps
T558 /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.1929610938 Dec 27 01:43:00 PM PST 23 Dec 27 01:44:03 PM PST 23 1381894889 ps
T187 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3641079748 Dec 27 01:47:27 PM PST 23 Dec 27 01:56:47 PM PST 23 3790964924 ps
T559 /workspace/coverage/cover_reg_top/84.xbar_error_random.541723490 Dec 27 01:48:59 PM PST 23 Dec 27 01:49:07 PM PST 23 117692543 ps
T560 /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.3110600483 Dec 27 01:46:58 PM PST 23 Dec 27 01:52:18 PM PST 23 9104637845 ps
T561 /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.208533016 Dec 27 01:45:37 PM PST 23 Dec 27 01:46:08 PM PST 23 158752829 ps
T325 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2814315657 Dec 27 01:43:02 PM PST 23 Dec 27 01:48:26 PM PST 23 6230760960 ps
T562 /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.777888414 Dec 27 01:43:29 PM PST 23 Dec 27 01:45:38 PM PST 23 7459690298 ps
T563 /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.1068833044 Dec 27 01:45:21 PM PST 23 Dec 27 01:46:01 PM PST 23 455189996 ps
T183 /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.2356017332 Dec 27 01:49:38 PM PST 23 Dec 27 01:58:58 PM PST 23 34224783126 ps
T564 /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.3223146558 Dec 27 01:48:55 PM PST 23 Dec 27 02:05:23 PM PST 23 57054129458 ps
T565 /workspace/coverage/cover_reg_top/6.xbar_stress_all.2761783355 Dec 27 01:41:12 PM PST 23 Dec 27 01:41:23 PM PST 23 256687176 ps
T566 /workspace/coverage/cover_reg_top/32.xbar_error_random.629031243 Dec 27 01:44:09 PM PST 23 Dec 27 01:45:16 PM PST 23 2142061342 ps
T567 /workspace/coverage/cover_reg_top/39.xbar_same_source.2219459251 Dec 27 01:44:49 PM PST 23 Dec 27 01:45:58 PM PST 23 2056090410 ps
T322 /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.4168173742 Dec 27 01:42:53 PM PST 23 Dec 27 01:47:23 PM PST 23 1832261257 ps
T568 /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.204418978 Dec 27 01:45:40 PM PST 23 Dec 27 01:46:01 PM PST 23 515798956 ps
T326 /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1624306560 Dec 27 01:49:11 PM PST 23 Dec 27 01:53:19 PM PST 23 689521645 ps
T569 /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.3613590400 Dec 27 01:43:10 PM PST 23 Dec 27 01:44:45 PM PST 23 5743581381 ps
T570 /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2545353510 Dec 27 01:45:49 PM PST 23 Dec 27 01:45:56 PM PST 23 38741303 ps
T222 /workspace/coverage/cover_reg_top/80.xbar_random.72905365 Dec 27 01:49:15 PM PST 23 Dec 27 01:50:21 PM PST 23 1873744024 ps
T571 /workspace/coverage/cover_reg_top/69.xbar_smoke.1499537370 Dec 27 01:47:29 PM PST 23 Dec 27 01:47:36 PM PST 23 45547043 ps
T572 /workspace/coverage/cover_reg_top/74.xbar_error_random.3385032558 Dec 27 01:47:36 PM PST 23 Dec 27 01:47:47 PM PST 23 157174883 ps
T573 /workspace/coverage/cover_reg_top/85.xbar_smoke.931510466 Dec 27 01:48:58 PM PST 23 Dec 27 01:49:10 PM PST 23 237873901 ps
T574 /workspace/coverage/cover_reg_top/28.xbar_same_source.3184966096 Dec 27 01:43:29 PM PST 23 Dec 27 01:43:44 PM PST 23 203896921 ps
T575 /workspace/coverage/cover_reg_top/45.xbar_smoke.100140758 Dec 27 01:45:00 PM PST 23 Dec 27 01:45:07 PM PST 23 49005575 ps
T576 /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.2490038558 Dec 27 01:49:09 PM PST 23 Dec 27 01:49:31 PM PST 23 193569061 ps
T577 /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.656687201 Dec 27 01:49:59 PM PST 23 Dec 27 01:51:51 PM PST 23 6139991201 ps
T578 /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3954895574 Dec 27 01:45:46 PM PST 23 Dec 27 02:26:38 PM PST 23 148576072260 ps
T579 /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2722011487 Dec 27 01:42:55 PM PST 23 Dec 27 01:47:17 PM PST 23 6782187221 ps
T580 /workspace/coverage/cover_reg_top/43.xbar_error_random.134997937 Dec 27 01:44:48 PM PST 23 Dec 27 01:45:30 PM PST 23 1317245809 ps
T581 /workspace/coverage/cover_reg_top/5.xbar_smoke.2869078631 Dec 27 01:40:38 PM PST 23 Dec 27 01:40:45 PM PST 23 57495443 ps
T582 /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.2665289170 Dec 27 01:49:37 PM PST 23 Dec 27 01:49:57 PM PST 23 131143668 ps
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