| T23 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1534581635 |
|
|
Mar 12 03:44:05 PM PDT 24 |
Mar 12 03:52:08 PM PDT 24 |
4223655800 ps |
| T367 |
/workspace/coverage/default/0.chip_sw_example_rom.2474413135 |
|
|
Mar 12 03:43:27 PM PDT 24 |
Mar 12 03:45:58 PM PDT 24 |
1968831348 ps |
| T94 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.162194199 |
|
|
Mar 12 03:47:17 PM PDT 24 |
Mar 12 04:23:43 PM PDT 24 |
24123379510 ps |
| T368 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3062434862 |
|
|
Mar 12 03:57:36 PM PDT 24 |
Mar 12 04:01:52 PM PDT 24 |
2733555376 ps |
| T78 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.3233318767 |
|
|
Mar 12 03:46:03 PM PDT 24 |
Mar 12 03:49:45 PM PDT 24 |
2484169736 ps |
| T369 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2779636694 |
|
|
Mar 12 04:13:21 PM PDT 24 |
Mar 12 04:19:41 PM PDT 24 |
3372469146 ps |
| T370 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3518346782 |
|
|
Mar 12 03:51:13 PM PDT 24 |
Mar 12 03:54:41 PM PDT 24 |
2326079960 ps |
| T371 |
/workspace/coverage/default/2.rom_e2e_static_critical.3850085578 |
|
|
Mar 12 04:10:01 PM PDT 24 |
Mar 12 04:40:19 PM PDT 24 |
10668440498 ps |
| T372 |
/workspace/coverage/default/2.chip_sw_kmac_idle.1399698864 |
|
|
Mar 12 04:02:17 PM PDT 24 |
Mar 12 04:05:43 PM PDT 24 |
3010735134 ps |
| T896 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2093007948 |
|
|
Mar 12 03:49:03 PM PDT 24 |
Mar 12 04:09:20 PM PDT 24 |
6136880300 ps |
| T648 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.713462787 |
|
|
Mar 12 03:50:35 PM PDT 24 |
Mar 12 03:52:22 PM PDT 24 |
2396646249 ps |
| T897 |
/workspace/coverage/default/2.chip_sw_aes_idle.992026428 |
|
|
Mar 12 04:01:04 PM PDT 24 |
Mar 12 04:04:29 PM PDT 24 |
2683034744 ps |
| T898 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1762225144 |
|
|
Mar 12 03:44:42 PM PDT 24 |
Mar 12 03:51:17 PM PDT 24 |
3941662440 ps |
| T899 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.407513103 |
|
|
Mar 12 03:59:05 PM PDT 24 |
Mar 12 04:12:46 PM PDT 24 |
6845084796 ps |
| T732 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.974207920 |
|
|
Mar 12 04:13:04 PM PDT 24 |
Mar 12 04:21:16 PM PDT 24 |
5391655450 ps |
| T711 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2011642593 |
|
|
Mar 12 03:50:56 PM PDT 24 |
Mar 12 04:04:46 PM PDT 24 |
5590769672 ps |
| T900 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.177353727 |
|
|
Mar 12 03:46:45 PM PDT 24 |
Mar 12 03:50:50 PM PDT 24 |
2973614404 ps |
| T901 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.369585175 |
|
|
Mar 12 04:00:45 PM PDT 24 |
Mar 12 04:08:07 PM PDT 24 |
3965424966 ps |
| T902 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1954791770 |
|
|
Mar 12 03:53:24 PM PDT 24 |
Mar 12 04:03:58 PM PDT 24 |
4913144740 ps |
| T903 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2197040863 |
|
|
Mar 12 03:49:37 PM PDT 24 |
Mar 12 03:58:33 PM PDT 24 |
4835846262 ps |
| T106 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1158178779 |
|
|
Mar 12 04:01:11 PM PDT 24 |
Mar 12 04:21:26 PM PDT 24 |
5989213712 ps |
| T904 |
/workspace/coverage/default/1.rom_e2e_static_critical.832013256 |
|
|
Mar 12 03:59:38 PM PDT 24 |
Mar 12 04:35:03 PM PDT 24 |
10797948810 ps |
| T905 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2374118121 |
|
|
Mar 12 04:07:42 PM PDT 24 |
Mar 12 04:10:21 PM PDT 24 |
2538589750 ps |
| T906 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3729862373 |
|
|
Mar 12 03:48:11 PM PDT 24 |
Mar 12 03:58:35 PM PDT 24 |
4927315960 ps |
| T286 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.52766623 |
|
|
Mar 12 04:03:10 PM PDT 24 |
Mar 12 04:21:59 PM PDT 24 |
6145341112 ps |
| T270 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.1681491065 |
|
|
Mar 12 03:49:41 PM PDT 24 |
Mar 12 03:58:59 PM PDT 24 |
4728492300 ps |
| T274 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.2467837278 |
|
|
Mar 12 04:02:20 PM PDT 24 |
Mar 12 04:08:04 PM PDT 24 |
2954524308 ps |
| T275 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.24632693 |
|
|
Mar 12 03:58:10 PM PDT 24 |
Mar 12 04:18:04 PM PDT 24 |
6796390920 ps |
| T276 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1246434192 |
|
|
Mar 12 03:49:17 PM PDT 24 |
Mar 12 03:53:37 PM PDT 24 |
2664592347 ps |
| T277 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1559243969 |
|
|
Mar 12 04:01:00 PM PDT 24 |
Mar 12 04:16:45 PM PDT 24 |
8068754554 ps |
| T278 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3199197634 |
|
|
Mar 12 04:12:01 PM PDT 24 |
Mar 12 04:21:54 PM PDT 24 |
5462071176 ps |
| T279 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1110738205 |
|
|
Mar 12 04:12:27 PM PDT 24 |
Mar 12 04:22:38 PM PDT 24 |
5546520872 ps |
| T135 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.414161918 |
|
|
Mar 12 03:54:26 PM PDT 24 |
Mar 12 03:58:35 PM PDT 24 |
2741523772 ps |
| T280 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.2864232240 |
|
|
Mar 12 03:52:12 PM PDT 24 |
Mar 12 04:23:40 PM PDT 24 |
8564716648 ps |
| T281 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2453089341 |
|
|
Mar 12 04:01:48 PM PDT 24 |
Mar 12 04:38:40 PM PDT 24 |
9176265024 ps |
| T27 |
/workspace/coverage/default/2.chip_sw_gpio.1128565464 |
|
|
Mar 12 03:58:31 PM PDT 24 |
Mar 12 04:07:36 PM PDT 24 |
4294618300 ps |
| T212 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3106528924 |
|
|
Mar 12 03:51:31 PM PDT 24 |
Mar 12 04:05:38 PM PDT 24 |
4812007710 ps |
| T907 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4246750460 |
|
|
Mar 12 04:02:04 PM PDT 24 |
Mar 12 04:11:00 PM PDT 24 |
3829455568 ps |
| T908 |
/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.360954488 |
|
|
Mar 12 03:55:18 PM PDT 24 |
Mar 12 04:32:57 PM PDT 24 |
8867078156 ps |
| T661 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2667877310 |
|
|
Mar 12 04:06:54 PM PDT 24 |
Mar 12 04:18:08 PM PDT 24 |
5287135490 ps |
| T909 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2347680312 |
|
|
Mar 12 04:02:36 PM PDT 24 |
Mar 12 04:29:42 PM PDT 24 |
9059848794 ps |
| T221 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1558374466 |
|
|
Mar 12 04:09:19 PM PDT 24 |
Mar 12 04:18:55 PM PDT 24 |
4689981768 ps |
| T666 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3632539070 |
|
|
Mar 12 04:09:48 PM PDT 24 |
Mar 12 04:15:18 PM PDT 24 |
3637145352 ps |
| T910 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.1371704664 |
|
|
Mar 12 03:57:04 PM PDT 24 |
Mar 12 04:01:30 PM PDT 24 |
3083535422 ps |
| T112 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3291694956 |
|
|
Mar 12 03:46:48 PM PDT 24 |
Mar 12 03:54:11 PM PDT 24 |
3325771055 ps |
| T911 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3107412982 |
|
|
Mar 12 03:54:07 PM PDT 24 |
Mar 12 04:28:26 PM PDT 24 |
8607124380 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.1987888127 |
|
|
Mar 12 03:45:38 PM PDT 24 |
Mar 12 05:04:16 PM PDT 24 |
19187159364 ps |
| T912 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.4226694385 |
|
|
Mar 12 04:07:56 PM PDT 24 |
Mar 12 04:18:26 PM PDT 24 |
6626110919 ps |
| T108 |
/workspace/coverage/default/0.rom_raw_unlock.76100633 |
|
|
Mar 12 03:48:11 PM PDT 24 |
Mar 12 04:21:44 PM PDT 24 |
15574815477 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_alert_test.3172141230 |
|
|
Mar 12 03:46:10 PM PDT 24 |
Mar 12 03:51:57 PM PDT 24 |
3622721400 ps |
| T913 |
/workspace/coverage/default/0.chip_sw_hmac_enc.168622474 |
|
|
Mar 12 03:46:58 PM PDT 24 |
Mar 12 03:51:09 PM PDT 24 |
2650403088 ps |
| T756 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4170492551 |
|
|
Mar 12 04:11:17 PM PDT 24 |
Mar 12 04:18:14 PM PDT 24 |
3271518000 ps |
| T914 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.1721788993 |
|
|
Mar 12 03:49:28 PM PDT 24 |
Mar 12 03:54:05 PM PDT 24 |
2577013656 ps |
| T915 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.622596490 |
|
|
Mar 12 03:53:02 PM PDT 24 |
Mar 12 04:01:48 PM PDT 24 |
3635001032 ps |
| T757 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.960753839 |
|
|
Mar 12 04:12:46 PM PDT 24 |
Mar 12 04:17:26 PM PDT 24 |
2993479560 ps |
| T916 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.3873149145 |
|
|
Mar 12 03:47:33 PM PDT 24 |
Mar 12 03:59:19 PM PDT 24 |
5804508664 ps |
| T917 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.315363936 |
|
|
Mar 12 03:48:06 PM PDT 24 |
Mar 12 03:52:29 PM PDT 24 |
2458150198 ps |
| T255 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.225348444 |
|
|
Mar 12 04:11:53 PM PDT 24 |
Mar 12 04:23:52 PM PDT 24 |
6007355356 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.850502896 |
|
|
Mar 12 03:46:51 PM PDT 24 |
Mar 12 04:17:56 PM PDT 24 |
18270924833 ps |
| T667 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.736655301 |
|
|
Mar 12 03:47:00 PM PDT 24 |
Mar 12 03:52:35 PM PDT 24 |
3135803934 ps |
| T249 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.681221254 |
|
|
Mar 12 03:54:49 PM PDT 24 |
Mar 12 04:08:00 PM PDT 24 |
4952098230 ps |
| T305 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1929379922 |
|
|
Mar 12 03:43:36 PM PDT 24 |
Mar 12 03:54:19 PM PDT 24 |
5251601192 ps |
| T918 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2747856499 |
|
|
Mar 12 03:49:02 PM PDT 24 |
Mar 12 04:24:49 PM PDT 24 |
26025773250 ps |
| T22 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.683514547 |
|
|
Mar 12 04:00:47 PM PDT 24 |
Mar 12 04:33:15 PM PDT 24 |
23325221050 ps |
| T919 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.4113065324 |
|
|
Mar 12 03:45:56 PM PDT 24 |
Mar 12 04:24:54 PM PDT 24 |
24416446019 ps |
| T308 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.724750536 |
|
|
Mar 12 03:44:43 PM PDT 24 |
Mar 12 03:53:12 PM PDT 24 |
4215016070 ps |
| T414 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.3417760972 |
|
|
Mar 12 03:59:07 PM PDT 24 |
Mar 12 04:04:05 PM PDT 24 |
2917663976 ps |
| T920 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.4016504302 |
|
|
Mar 12 03:48:51 PM PDT 24 |
Mar 12 03:52:21 PM PDT 24 |
2310971944 ps |
| T921 |
/workspace/coverage/default/1.chip_sival_flash_info_access.3396936997 |
|
|
Mar 12 03:50:13 PM PDT 24 |
Mar 12 03:55:06 PM PDT 24 |
3287684912 ps |
| T922 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1810279570 |
|
|
Mar 12 04:05:31 PM PDT 24 |
Mar 12 04:10:13 PM PDT 24 |
3306825786 ps |
| T337 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.196693947 |
|
|
Mar 12 04:06:39 PM PDT 24 |
Mar 12 04:10:41 PM PDT 24 |
2873057032 ps |
| T923 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.729919180 |
|
|
Mar 12 03:52:10 PM PDT 24 |
Mar 12 04:24:13 PM PDT 24 |
8523575576 ps |
| T924 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3877433876 |
|
|
Mar 12 03:52:10 PM PDT 24 |
Mar 12 04:43:35 PM PDT 24 |
24996811256 ps |
| T653 |
/workspace/coverage/default/1.chip_sw_power_idle_load.3498012014 |
|
|
Mar 12 03:57:51 PM PDT 24 |
Mar 12 04:11:02 PM PDT 24 |
4411711710 ps |
| T925 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3245354120 |
|
|
Mar 12 03:44:00 PM PDT 24 |
Mar 12 03:53:32 PM PDT 24 |
7477917962 ps |
| T926 |
/workspace/coverage/default/3.chip_tap_straps_prod.1918378150 |
|
|
Mar 12 04:05:16 PM PDT 24 |
Mar 12 04:08:33 PM PDT 24 |
3479746375 ps |
| T927 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2133296861 |
|
|
Mar 12 03:53:49 PM PDT 24 |
Mar 12 04:46:34 PM PDT 24 |
12124367753 ps |
| T928 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1439799931 |
|
|
Mar 12 04:07:16 PM PDT 24 |
Mar 12 04:11:33 PM PDT 24 |
3149636054 ps |
| T777 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1865963736 |
|
|
Mar 12 04:13:54 PM PDT 24 |
Mar 12 04:24:47 PM PDT 24 |
4729463380 ps |
| T929 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1432923200 |
|
|
Mar 12 04:00:48 PM PDT 24 |
Mar 12 04:10:57 PM PDT 24 |
4731527804 ps |
| T930 |
/workspace/coverage/default/0.rom_e2e_static_critical.3547207333 |
|
|
Mar 12 03:52:06 PM PDT 24 |
Mar 12 04:29:09 PM PDT 24 |
10979684096 ps |
| T331 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.3324552177 |
|
|
Mar 12 04:03:21 PM PDT 24 |
Mar 12 04:15:51 PM PDT 24 |
2658699160 ps |
| T931 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.305423881 |
|
|
Mar 12 03:49:31 PM PDT 24 |
Mar 12 03:53:49 PM PDT 24 |
2861871448 ps |
| T195 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1661095629 |
|
|
Mar 12 04:02:45 PM PDT 24 |
Mar 12 04:13:27 PM PDT 24 |
4631755450 ps |
| T764 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1855282539 |
|
|
Mar 12 04:13:55 PM PDT 24 |
Mar 12 04:20:13 PM PDT 24 |
4271427880 ps |
| T215 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4101147313 |
|
|
Mar 12 03:44:55 PM PDT 24 |
Mar 12 03:57:21 PM PDT 24 |
4990723940 ps |
| T932 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3927828015 |
|
|
Mar 12 03:47:01 PM PDT 24 |
Mar 12 04:03:44 PM PDT 24 |
5287989286 ps |
| T933 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.700489304 |
|
|
Mar 12 04:06:47 PM PDT 24 |
Mar 12 04:39:40 PM PDT 24 |
12673688380 ps |
| T332 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.3091554644 |
|
|
Mar 12 03:45:33 PM PDT 24 |
Mar 12 03:55:57 PM PDT 24 |
2687995160 ps |
| T136 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1703832109 |
|
|
Mar 12 03:52:49 PM PDT 24 |
Mar 12 03:57:53 PM PDT 24 |
2637786426 ps |
| T348 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.423694560 |
|
|
Mar 12 03:44:02 PM PDT 24 |
Mar 12 04:05:26 PM PDT 24 |
7580639084 ps |
| T349 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.496533218 |
|
|
Mar 12 04:10:04 PM PDT 24 |
Mar 12 04:16:36 PM PDT 24 |
3505989454 ps |
| T350 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1806082076 |
|
|
Mar 12 04:11:58 PM PDT 24 |
Mar 12 04:23:54 PM PDT 24 |
5512601210 ps |
| T351 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.4131358 |
|
|
Mar 12 03:49:45 PM PDT 24 |
Mar 12 03:54:58 PM PDT 24 |
3216626064 ps |
| T352 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3353257679 |
|
|
Mar 12 04:02:58 PM PDT 24 |
Mar 12 04:12:13 PM PDT 24 |
9123941638 ps |
| T28 |
/workspace/coverage/default/1.chip_sw_gpio.2013179809 |
|
|
Mar 12 03:51:42 PM PDT 24 |
Mar 12 04:00:17 PM PDT 24 |
4557274580 ps |
| T353 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2766455184 |
|
|
Mar 12 03:57:18 PM PDT 24 |
Mar 12 04:02:04 PM PDT 24 |
3091167403 ps |
| T256 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1775679953 |
|
|
Mar 12 04:05:54 PM PDT 24 |
Mar 12 04:16:49 PM PDT 24 |
5778038796 ps |
| T354 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2327738877 |
|
|
Mar 12 04:00:22 PM PDT 24 |
Mar 12 05:02:29 PM PDT 24 |
20650027494 ps |
| T934 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1974319477 |
|
|
Mar 12 04:10:50 PM PDT 24 |
Mar 12 04:52:04 PM PDT 24 |
14591703720 ps |
| T935 |
/workspace/coverage/default/2.chip_sw_aes_enc.2916806425 |
|
|
Mar 12 04:01:35 PM PDT 24 |
Mar 12 04:07:07 PM PDT 24 |
2653500760 ps |
| T216 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.231203963 |
|
|
Mar 12 04:11:31 PM PDT 24 |
Mar 12 04:20:40 PM PDT 24 |
5242113960 ps |
| T936 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3654491097 |
|
|
Mar 12 04:02:22 PM PDT 24 |
Mar 12 04:34:54 PM PDT 24 |
20722046946 ps |
| T937 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.4106004439 |
|
|
Mar 12 03:59:13 PM PDT 24 |
Mar 12 04:05:53 PM PDT 24 |
3719824160 ps |
| T938 |
/workspace/coverage/default/2.chip_tap_straps_dev.171542898 |
|
|
Mar 12 04:02:23 PM PDT 24 |
Mar 12 04:04:44 PM PDT 24 |
2377311120 ps |
| T727 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.792780552 |
|
|
Mar 12 04:12:56 PM PDT 24 |
Mar 12 04:19:10 PM PDT 24 |
3369644780 ps |
| T939 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2214174700 |
|
|
Mar 12 03:52:07 PM PDT 24 |
Mar 12 04:19:21 PM PDT 24 |
6946640264 ps |
| T940 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.825783984 |
|
|
Mar 12 03:48:54 PM PDT 24 |
Mar 12 03:55:53 PM PDT 24 |
8275584820 ps |
| T683 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3470151892 |
|
|
Mar 12 03:46:37 PM PDT 24 |
Mar 12 03:52:52 PM PDT 24 |
4629371146 ps |
| T47 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.4195749389 |
|
|
Mar 12 03:51:10 PM PDT 24 |
Mar 12 03:56:34 PM PDT 24 |
3914515934 ps |
| T65 |
/workspace/coverage/default/2.chip_tap_straps_rma.1817069499 |
|
|
Mar 12 04:02:41 PM PDT 24 |
Mar 12 04:18:00 PM PDT 24 |
8303522490 ps |
| T389 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.338506675 |
|
|
Mar 12 04:06:45 PM PDT 24 |
Mar 12 04:14:27 PM PDT 24 |
5648695274 ps |
| T250 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.691517551 |
|
|
Mar 12 03:57:09 PM PDT 24 |
Mar 12 04:09:04 PM PDT 24 |
6322671940 ps |
| T390 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.1731631459 |
|
|
Mar 12 04:08:43 PM PDT 24 |
Mar 12 04:33:09 PM PDT 24 |
8321422164 ps |
| T391 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.740412068 |
|
|
Mar 12 04:12:46 PM PDT 24 |
Mar 12 04:17:23 PM PDT 24 |
4059995864 ps |
| T392 |
/workspace/coverage/default/3.chip_tap_straps_dev.770136555 |
|
|
Mar 12 04:05:21 PM PDT 24 |
Mar 12 04:26:12 PM PDT 24 |
13006673297 ps |
| T393 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1834241172 |
|
|
Mar 12 04:11:14 PM PDT 24 |
Mar 12 04:16:57 PM PDT 24 |
3761770632 ps |
| T394 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3052435225 |
|
|
Mar 12 04:03:02 PM PDT 24 |
Mar 12 04:11:08 PM PDT 24 |
4235457836 ps |
| T51 |
/workspace/coverage/default/1.chip_sw_alert_test.2112365861 |
|
|
Mar 12 03:53:18 PM PDT 24 |
Mar 12 03:57:32 PM PDT 24 |
2873534480 ps |
| T207 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1552537590 |
|
|
Mar 12 03:45:27 PM PDT 24 |
Mar 12 05:13:38 PM PDT 24 |
45369952056 ps |
| T941 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2460021265 |
|
|
Mar 12 04:08:49 PM PDT 24 |
Mar 12 05:10:45 PM PDT 24 |
23218089556 ps |
| T176 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3875826286 |
|
|
Mar 12 03:45:22 PM PDT 24 |
Mar 12 06:48:42 PM PDT 24 |
59866753890 ps |
| T284 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.1534940615 |
|
|
Mar 12 03:46:16 PM PDT 24 |
Mar 12 04:05:54 PM PDT 24 |
5936010312 ps |
| T942 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2687174415 |
|
|
Mar 12 04:06:58 PM PDT 24 |
Mar 12 04:21:24 PM PDT 24 |
10099612510 ps |
| T943 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1838217272 |
|
|
Mar 12 03:45:44 PM PDT 24 |
Mar 12 03:56:46 PM PDT 24 |
4781225224 ps |
| T139 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.875206802 |
|
|
Mar 12 04:00:50 PM PDT 24 |
Mar 12 04:50:06 PM PDT 24 |
18479763908 ps |
| T944 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.1637979754 |
|
|
Mar 12 03:54:58 PM PDT 24 |
Mar 12 04:00:17 PM PDT 24 |
2898216509 ps |
| T640 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.1036910931 |
|
|
Mar 12 04:03:41 PM PDT 24 |
Mar 12 04:30:03 PM PDT 24 |
5746326600 ps |
| T945 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.914086983 |
|
|
Mar 12 03:54:11 PM PDT 24 |
Mar 12 04:03:02 PM PDT 24 |
5164496815 ps |
| T946 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.470740234 |
|
|
Mar 12 04:07:20 PM PDT 24 |
Mar 12 04:14:25 PM PDT 24 |
5374578599 ps |
| T743 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.1175933843 |
|
|
Mar 12 04:09:04 PM PDT 24 |
Mar 12 04:22:08 PM PDT 24 |
5186484792 ps |
| T947 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.1819851907 |
|
|
Mar 12 03:48:26 PM PDT 24 |
Mar 12 03:54:10 PM PDT 24 |
2795029880 ps |
| T251 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.635955943 |
|
|
Mar 12 03:54:28 PM PDT 24 |
Mar 12 04:04:38 PM PDT 24 |
4940616270 ps |
| T948 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.714470370 |
|
|
Mar 12 03:51:19 PM PDT 24 |
Mar 12 04:00:02 PM PDT 24 |
5274394834 ps |
| T949 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.935364627 |
|
|
Mar 12 03:44:33 PM PDT 24 |
Mar 12 03:57:59 PM PDT 24 |
5276248532 ps |
| T252 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3949259329 |
|
|
Mar 12 03:46:45 PM PDT 24 |
Mar 12 03:55:37 PM PDT 24 |
3555809800 ps |
| T668 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3058383756 |
|
|
Mar 12 04:00:20 PM PDT 24 |
Mar 12 04:05:02 PM PDT 24 |
2957888480 ps |
| T261 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2014738210 |
|
|
Mar 12 03:49:20 PM PDT 24 |
Mar 12 03:53:37 PM PDT 24 |
2537216946 ps |
| T701 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.3769551191 |
|
|
Mar 12 04:09:24 PM PDT 24 |
Mar 12 04:22:10 PM PDT 24 |
5446661560 ps |
| T271 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3721002293 |
|
|
Mar 12 04:16:03 PM PDT 24 |
Mar 12 04:20:48 PM PDT 24 |
2926939964 ps |
| T95 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3338517037 |
|
|
Mar 12 04:03:48 PM PDT 24 |
Mar 12 04:32:39 PM PDT 24 |
24447579240 ps |
| T950 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3155328143 |
|
|
Mar 12 03:52:36 PM PDT 24 |
Mar 12 04:34:33 PM PDT 24 |
11787312570 ps |
| T951 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.3900313829 |
|
|
Mar 12 03:51:34 PM PDT 24 |
Mar 12 03:57:07 PM PDT 24 |
3083537564 ps |
| T952 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2197742288 |
|
|
Mar 12 03:49:42 PM PDT 24 |
Mar 12 03:57:06 PM PDT 24 |
3211390786 ps |
| T7 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.742421561 |
|
|
Mar 12 03:58:28 PM PDT 24 |
Mar 12 04:02:09 PM PDT 24 |
2260065020 ps |
| T48 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.323656542 |
|
|
Mar 12 04:03:09 PM PDT 24 |
Mar 12 04:35:43 PM PDT 24 |
17979528042 ps |
| T953 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.1883886460 |
|
|
Mar 12 03:48:11 PM PDT 24 |
Mar 12 03:55:26 PM PDT 24 |
3073324322 ps |
| T954 |
/workspace/coverage/default/0.chip_sw_aes_enc.1080218601 |
|
|
Mar 12 03:44:32 PM PDT 24 |
Mar 12 03:49:32 PM PDT 24 |
3256801470 ps |
| T746 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.423563627 |
|
|
Mar 12 04:11:24 PM PDT 24 |
Mar 12 04:17:23 PM PDT 24 |
3782222600 ps |
| T955 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.3399581127 |
|
|
Mar 12 03:50:52 PM PDT 24 |
Mar 12 03:54:41 PM PDT 24 |
3103764140 ps |
| T956 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2362878900 |
|
|
Mar 12 03:57:03 PM PDT 24 |
Mar 12 04:01:46 PM PDT 24 |
3152106040 ps |
| T700 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3768785204 |
|
|
Mar 12 04:12:01 PM PDT 24 |
Mar 12 04:25:41 PM PDT 24 |
4921222884 ps |
| T957 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.249628236 |
|
|
Mar 12 03:49:03 PM PDT 24 |
Mar 12 04:52:58 PM PDT 24 |
17109616338 ps |
| T728 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2081290477 |
|
|
Mar 12 04:11:53 PM PDT 24 |
Mar 12 04:19:22 PM PDT 24 |
3696398360 ps |
| T230 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.518950047 |
|
|
Mar 12 04:01:45 PM PDT 24 |
Mar 12 07:30:02 PM PDT 24 |
254698420264 ps |
| T309 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.398007439 |
|
|
Mar 12 03:51:44 PM PDT 24 |
Mar 12 03:55:28 PM PDT 24 |
2794928421 ps |
| T958 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3890613969 |
|
|
Mar 12 04:02:26 PM PDT 24 |
Mar 12 04:05:55 PM PDT 24 |
2431322696 ps |
| T415 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1262355495 |
|
|
Mar 12 04:05:09 PM PDT 24 |
Mar 12 04:20:30 PM PDT 24 |
5663581950 ps |
| T959 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3523231712 |
|
|
Mar 12 04:00:55 PM PDT 24 |
Mar 12 04:20:01 PM PDT 24 |
5299765644 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1015816447 |
|
|
Mar 12 03:48:53 PM PDT 24 |
Mar 12 04:00:40 PM PDT 24 |
4161029200 ps |
| T289 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3770127973 |
|
|
Mar 12 03:50:25 PM PDT 24 |
Mar 12 04:00:53 PM PDT 24 |
4532744247 ps |
| T58 |
/workspace/coverage/default/1.chip_tap_straps_rma.2279051702 |
|
|
Mar 12 03:52:43 PM PDT 24 |
Mar 12 04:06:39 PM PDT 24 |
7448736661 ps |
| T703 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.649578755 |
|
|
Mar 12 04:08:47 PM PDT 24 |
Mar 12 04:15:14 PM PDT 24 |
3296854760 ps |
| T961 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3036914047 |
|
|
Mar 12 03:52:18 PM PDT 24 |
Mar 12 04:03:05 PM PDT 24 |
4535116936 ps |
| T767 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2948960300 |
|
|
Mar 12 04:10:25 PM PDT 24 |
Mar 12 04:16:38 PM PDT 24 |
3669842950 ps |
| T962 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3232237046 |
|
|
Mar 12 03:58:01 PM PDT 24 |
Mar 12 04:03:42 PM PDT 24 |
2676812954 ps |
| T124 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2801254980 |
|
|
Mar 12 04:13:58 PM PDT 24 |
Mar 12 04:24:47 PM PDT 24 |
4871036624 ps |
| T963 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3232734511 |
|
|
Mar 12 03:44:57 PM PDT 24 |
Mar 12 04:24:59 PM PDT 24 |
12659977601 ps |
| T964 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1387991532 |
|
|
Mar 12 03:56:46 PM PDT 24 |
Mar 12 04:02:14 PM PDT 24 |
2380771628 ps |
| T208 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1456584730 |
|
|
Mar 12 03:49:40 PM PDT 24 |
Mar 12 05:09:25 PM PDT 24 |
44940239320 ps |
| T965 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.121427218 |
|
|
Mar 12 03:52:27 PM PDT 24 |
Mar 12 04:42:33 PM PDT 24 |
27806542680 ps |
| T966 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.43507027 |
|
|
Mar 12 04:02:12 PM PDT 24 |
Mar 12 04:07:41 PM PDT 24 |
3229558700 ps |
| T967 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.1123705963 |
|
|
Mar 12 04:05:35 PM PDT 24 |
Mar 12 04:09:17 PM PDT 24 |
3090612440 ps |
| T968 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2725927366 |
|
|
Mar 12 03:53:39 PM PDT 24 |
Mar 12 04:00:14 PM PDT 24 |
4924206712 ps |
| T745 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.4178603345 |
|
|
Mar 12 04:09:22 PM PDT 24 |
Mar 12 04:16:03 PM PDT 24 |
3125417910 ps |
| T969 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.382495733 |
|
|
Mar 12 03:47:14 PM PDT 24 |
Mar 12 04:03:13 PM PDT 24 |
5080722572 ps |
| T36 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.1749823058 |
|
|
Mar 12 03:48:41 PM PDT 24 |
Mar 12 03:55:14 PM PDT 24 |
3129810412 ps |
| T769 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.2283337989 |
|
|
Mar 12 04:09:45 PM PDT 24 |
Mar 12 04:19:56 PM PDT 24 |
5348823180 ps |
| T970 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3752066167 |
|
|
Mar 12 03:53:37 PM PDT 24 |
Mar 12 03:57:50 PM PDT 24 |
2626197663 ps |
| T971 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3510073720 |
|
|
Mar 12 03:56:44 PM PDT 24 |
Mar 12 04:01:59 PM PDT 24 |
3160298728 ps |
| T972 |
/workspace/coverage/default/2.chip_sw_example_flash.3541089453 |
|
|
Mar 12 03:56:53 PM PDT 24 |
Mar 12 03:59:34 PM PDT 24 |
3005755990 ps |
| T973 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2612289028 |
|
|
Mar 12 03:47:46 PM PDT 24 |
Mar 12 04:30:15 PM PDT 24 |
11053199000 ps |
| T714 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1198221895 |
|
|
Mar 12 04:11:40 PM PDT 24 |
Mar 12 04:22:19 PM PDT 24 |
5276649364 ps |
| T734 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.107474803 |
|
|
Mar 12 04:12:31 PM PDT 24 |
Mar 12 04:19:36 PM PDT 24 |
3860892968 ps |
| T974 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1683689341 |
|
|
Mar 12 03:53:12 PM PDT 24 |
Mar 12 04:10:17 PM PDT 24 |
6581820310 ps |
| T642 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3229287081 |
|
|
Mar 12 03:50:23 PM PDT 24 |
Mar 12 03:55:37 PM PDT 24 |
3443249483 ps |
| T42 |
/workspace/coverage/default/0.chip_jtag_csr_rw.4221349481 |
|
|
Mar 12 03:37:25 PM PDT 24 |
Mar 12 04:15:35 PM PDT 24 |
18263994556 ps |
| T374 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3803877761 |
|
|
Mar 12 03:50:01 PM PDT 24 |
Mar 12 04:17:21 PM PDT 24 |
13222205231 ps |
| T375 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.570026943 |
|
|
Mar 12 03:50:28 PM PDT 24 |
Mar 12 03:57:35 PM PDT 24 |
5260528712 ps |
| T376 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3488623050 |
|
|
Mar 12 04:05:00 PM PDT 24 |
Mar 12 04:09:46 PM PDT 24 |
3113931582 ps |
| T377 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2862912833 |
|
|
Mar 12 03:57:10 PM PDT 24 |
Mar 12 06:34:55 PM PDT 24 |
59115420054 ps |
| T378 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.569468500 |
|
|
Mar 12 04:08:41 PM PDT 24 |
Mar 12 04:20:13 PM PDT 24 |
5547689998 ps |
| T379 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2082216224 |
|
|
Mar 12 04:03:30 PM PDT 24 |
Mar 12 04:57:48 PM PDT 24 |
14039298040 ps |
| T380 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1307251293 |
|
|
Mar 12 03:44:13 PM PDT 24 |
Mar 12 03:46:15 PM PDT 24 |
2655992673 ps |
| T211 |
/workspace/coverage/default/1.chip_sw_flash_init.2791248521 |
|
|
Mar 12 03:53:06 PM PDT 24 |
Mar 12 04:28:41 PM PDT 24 |
23194657477 ps |
| T381 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3028253650 |
|
|
Mar 12 04:01:14 PM PDT 24 |
Mar 12 04:20:02 PM PDT 24 |
5727781370 ps |
| T282 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.323445918 |
|
|
Mar 12 03:59:18 PM PDT 24 |
Mar 12 04:21:03 PM PDT 24 |
13101833688 ps |
| T150 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.734207439 |
|
|
Mar 12 03:47:32 PM PDT 24 |
Mar 12 03:56:34 PM PDT 24 |
5068728568 ps |
| T975 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3335980007 |
|
|
Mar 12 03:49:22 PM PDT 24 |
Mar 12 03:53:58 PM PDT 24 |
3042840187 ps |
| T976 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3505786336 |
|
|
Mar 12 03:51:54 PM PDT 24 |
Mar 12 04:06:41 PM PDT 24 |
7787998572 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.3392176047 |
|
|
Mar 12 03:48:58 PM PDT 24 |
Mar 12 03:53:57 PM PDT 24 |
2935159488 ps |
| T978 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1142037540 |
|
|
Mar 12 03:44:40 PM PDT 24 |
Mar 12 04:02:27 PM PDT 24 |
11296591319 ps |
| T979 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1616703144 |
|
|
Mar 12 04:07:12 PM PDT 24 |
Mar 12 04:47:11 PM PDT 24 |
13376270460 ps |
| T980 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1624914241 |
|
|
Mar 12 03:48:35 PM PDT 24 |
Mar 12 03:53:59 PM PDT 24 |
3240890788 ps |
| T981 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.302250566 |
|
|
Mar 12 03:46:46 PM PDT 24 |
Mar 12 03:57:41 PM PDT 24 |
4829786034 ps |
| T59 |
/workspace/coverage/default/0.chip_tap_straps_rma.1326251668 |
|
|
Mar 12 03:46:32 PM PDT 24 |
Mar 12 03:49:37 PM PDT 24 |
2406813085 ps |
| T982 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.369157995 |
|
|
Mar 12 04:09:28 PM PDT 24 |
Mar 12 04:20:44 PM PDT 24 |
5736261440 ps |
| T983 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.4179245397 |
|
|
Mar 12 04:12:00 PM PDT 24 |
Mar 12 04:22:22 PM PDT 24 |
5726042844 ps |
| T984 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.4076100657 |
|
|
Mar 12 04:00:12 PM PDT 24 |
Mar 12 06:49:42 PM PDT 24 |
65864376847 ps |
| T985 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3078097636 |
|
|
Mar 12 03:44:42 PM PDT 24 |
Mar 12 04:28:43 PM PDT 24 |
13534242008 ps |
| T297 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.435403485 |
|
|
Mar 12 03:51:48 PM PDT 24 |
Mar 12 04:05:08 PM PDT 24 |
5078539200 ps |
| T710 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1715619107 |
|
|
Mar 12 04:11:49 PM PDT 24 |
Mar 12 04:17:18 PM PDT 24 |
4051919112 ps |
| T986 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2786558332 |
|
|
Mar 12 03:52:25 PM PDT 24 |
Mar 12 04:16:59 PM PDT 24 |
9481009950 ps |
| T987 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2901708817 |
|
|
Mar 12 03:47:22 PM PDT 24 |
Mar 12 03:52:39 PM PDT 24 |
2915830666 ps |
| T988 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.943073454 |
|
|
Mar 12 03:48:34 PM PDT 24 |
Mar 12 04:33:05 PM PDT 24 |
14284665500 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1346103445 |
|
|
Mar 12 03:56:37 PM PDT 24 |
Mar 12 04:07:42 PM PDT 24 |
6255582522 ps |
| T990 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1082132670 |
|
|
Mar 12 03:51:41 PM PDT 24 |
Mar 12 04:25:35 PM PDT 24 |
8975820344 ps |
| T283 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2346153521 |
|
|
Mar 12 03:52:16 PM PDT 24 |
Mar 12 04:23:12 PM PDT 24 |
11631470356 ps |
| T304 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.3089214869 |
|
|
Mar 12 03:56:38 PM PDT 24 |
Mar 12 04:00:47 PM PDT 24 |
3163327800 ps |
| T991 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3947364027 |
|
|
Mar 12 03:50:59 PM PDT 24 |
Mar 12 03:57:28 PM PDT 24 |
6625049032 ps |
| T992 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.2982297547 |
|
|
Mar 12 03:57:05 PM PDT 24 |
Mar 12 04:21:08 PM PDT 24 |
6748184290 ps |
| T262 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1610579228 |
|
|
Mar 12 04:04:36 PM PDT 24 |
Mar 12 04:09:57 PM PDT 24 |
2658186190 ps |
| T993 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1577191187 |
|
|
Mar 12 04:01:20 PM PDT 24 |
Mar 12 04:04:43 PM PDT 24 |
2165653664 ps |
| T994 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.932430470 |
|
|
Mar 12 04:08:41 PM PDT 24 |
Mar 12 04:52:57 PM PDT 24 |
14390060422 ps |
| T995 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1837724978 |
|
|
Mar 12 04:02:36 PM PDT 24 |
Mar 12 04:12:39 PM PDT 24 |
3645121724 ps |
| T996 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1129309582 |
|
|
Mar 12 04:06:28 PM PDT 24 |
Mar 12 04:20:45 PM PDT 24 |
5304122700 ps |
| T205 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.751136873 |
|
|
Mar 12 03:58:10 PM PDT 24 |
Mar 12 05:30:46 PM PDT 24 |
46470530400 ps |
| T697 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3303216739 |
|
|
Mar 12 04:16:53 PM PDT 24 |
Mar 12 04:26:23 PM PDT 24 |
5467755172 ps |
| T189 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3903863799 |
|
|
Mar 12 03:51:19 PM PDT 24 |
Mar 12 04:02:18 PM PDT 24 |
4220731389 ps |
| T997 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.664820162 |
|
|
Mar 12 03:59:52 PM PDT 24 |
Mar 12 04:04:03 PM PDT 24 |
3130899233 ps |
| T998 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.478745239 |
|
|
Mar 12 04:06:57 PM PDT 24 |
Mar 12 04:18:57 PM PDT 24 |
8974132320 ps |
| T151 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3337516989 |
|
|
Mar 12 04:05:19 PM PDT 24 |
Mar 12 04:14:17 PM PDT 24 |
5155834964 ps |
| T999 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3644195798 |
|
|
Mar 12 03:47:43 PM PDT 24 |
Mar 12 04:16:07 PM PDT 24 |
11099280287 ps |
| T96 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2806765326 |
|
|
Mar 12 03:54:48 PM PDT 24 |
Mar 12 04:22:48 PM PDT 24 |
21231914232 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3760166138 |
|
|
Mar 12 03:48:53 PM PDT 24 |
Mar 12 04:12:55 PM PDT 24 |
9036435996 ps |
| T1001 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2730418235 |
|
|
Mar 12 04:00:09 PM PDT 24 |
Mar 12 04:39:01 PM PDT 24 |
27034073504 ps |
| T748 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3448112663 |
|
|
Mar 12 04:11:32 PM PDT 24 |
Mar 12 04:21:22 PM PDT 24 |
4972333700 ps |
| T152 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3707782477 |
|
|
Mar 12 03:52:27 PM PDT 24 |
Mar 12 04:05:25 PM PDT 24 |
7307749062 ps |
| T1002 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.321976893 |
|
|
Mar 12 03:44:46 PM PDT 24 |
Mar 12 04:05:52 PM PDT 24 |
7414990268 ps |
| T1003 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.2001150693 |
|
|
Mar 12 03:44:17 PM PDT 24 |
Mar 12 03:48:35 PM PDT 24 |
3066619308 ps |
| T1004 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.561461844 |
|
|
Mar 12 03:59:36 PM PDT 24 |
Mar 12 04:34:01 PM PDT 24 |
9235241645 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.2466327031 |
|
|
Mar 12 03:56:31 PM PDT 24 |
Mar 12 04:11:54 PM PDT 24 |
5526317732 ps |
| T770 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2449845696 |
|
|
Mar 12 04:08:37 PM PDT 24 |
Mar 12 04:13:57 PM PDT 24 |
3492242930 ps |
| T285 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1143440634 |
|
|
Mar 12 03:54:55 PM PDT 24 |
Mar 12 04:15:45 PM PDT 24 |
6439332104 ps |
| T1006 |
/workspace/coverage/default/1.chip_sw_aes_enc.1012620382 |
|
|
Mar 12 03:50:09 PM PDT 24 |
Mar 12 03:53:11 PM PDT 24 |
2726893928 ps |
| T322 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.4259658961 |
|
|
Mar 12 03:46:19 PM PDT 24 |
Mar 12 03:58:01 PM PDT 24 |
4453246464 ps |
| T1007 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1350384124 |
|
|
Mar 12 03:45:55 PM PDT 24 |
Mar 12 03:49:42 PM PDT 24 |
2964420116 ps |
| T1008 |
/workspace/coverage/default/0.chip_sw_aes_idle.647686917 |
|
|
Mar 12 03:46:54 PM PDT 24 |
Mar 12 03:52:02 PM PDT 24 |
3584424378 ps |
| T1009 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3676848579 |
|
|
Mar 12 03:50:23 PM PDT 24 |
Mar 12 04:36:35 PM PDT 24 |
11567500661 ps |
| T334 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3997109779 |
|
|
Mar 12 03:54:29 PM PDT 24 |
Mar 12 04:43:00 PM PDT 24 |
12495528480 ps |