Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 95.43 94.14 95.01 94.90 97.38 99.49


Total test records in report: 2846
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T1299 /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.81095948 Mar 12 03:26:50 PM PDT 24 Mar 12 03:28:01 PM PDT 24 4448963203 ps
T512 /workspace/coverage/cover_reg_top/1.chip_tl_errors.3009292583 Mar 12 03:24:38 PM PDT 24 Mar 12 03:31:25 PM PDT 24 5131152190 ps
T796 /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.83674440 Mar 12 03:32:28 PM PDT 24 Mar 12 03:34:08 PM PDT 24 3113043021 ps
T397 /workspace/coverage/cover_reg_top/29.xbar_access_same_device.509892518 Mar 12 03:27:14 PM PDT 24 Mar 12 03:28:04 PM PDT 24 1449167401 ps
T420 /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.618585270 Mar 12 03:26:04 PM PDT 24 Mar 12 03:33:37 PM PDT 24 3638091228 ps
T591 /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.274606869 Mar 12 03:24:40 PM PDT 24 Mar 12 03:27:25 PM PDT 24 9823165578 ps
T398 /workspace/coverage/cover_reg_top/45.xbar_stress_all.2189364584 Mar 12 03:29:22 PM PDT 24 Mar 12 03:37:14 PM PDT 24 5401606073 ps
T1300 /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2807262103 Mar 12 03:30:42 PM PDT 24 Mar 12 03:31:19 PM PDT 24 1048679189 ps
T461 /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3504020928 Mar 12 03:25:20 PM PDT 24 Mar 12 03:25:55 PM PDT 24 432037286 ps
T623 /workspace/coverage/cover_reg_top/17.xbar_smoke.3915471695 Mar 12 03:25:38 PM PDT 24 Mar 12 03:25:47 PM PDT 24 213842131 ps
T654 /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.3842933017 Mar 12 03:30:41 PM PDT 24 Mar 12 03:31:48 PM PDT 24 1717805117 ps
T808 /workspace/coverage/cover_reg_top/10.xbar_access_same_device.1145323172 Mar 12 03:25:23 PM PDT 24 Mar 12 03:25:45 PM PDT 24 416918054 ps
T604 /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.3681605013 Mar 12 03:32:49 PM PDT 24 Mar 12 03:35:46 PM PDT 24 16476102726 ps
T462 /workspace/coverage/cover_reg_top/44.xbar_random.1841126710 Mar 12 03:29:13 PM PDT 24 Mar 12 03:29:46 PM PDT 24 325698276 ps
T463 /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1561474832 Mar 12 03:36:05 PM PDT 24 Mar 12 03:36:22 PM PDT 24 180439382 ps
T526 /workspace/coverage/cover_reg_top/97.xbar_same_source.3264418232 Mar 12 03:35:53 PM PDT 24 Mar 12 03:36:22 PM PDT 24 345434784 ps
T493 /workspace/coverage/cover_reg_top/8.xbar_same_source.3518056176 Mar 12 03:25:09 PM PDT 24 Mar 12 03:25:55 PM PDT 24 1550674908 ps
T480 /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.1358612206 Mar 12 03:35:42 PM PDT 24 Mar 12 03:37:48 PM PDT 24 10501552823 ps
T450 /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.2808878095 Mar 12 03:35:12 PM PDT 24 Mar 12 03:50:40 PM PDT 24 82173607883 ps
T571 /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.3538873939 Mar 12 03:28:43 PM PDT 24 Mar 12 03:35:15 PM PDT 24 34839767871 ps
T471 /workspace/coverage/cover_reg_top/24.xbar_same_source.3684607200 Mar 12 03:26:38 PM PDT 24 Mar 12 03:27:18 PM PDT 24 573234866 ps
T1301 /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1971485318 Mar 12 03:32:24 PM PDT 24 Mar 12 03:32:33 PM PDT 24 132725029 ps
T602 /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.333450554 Mar 12 03:25:25 PM PDT 24 Mar 12 03:35:45 PM PDT 24 34915831034 ps
T780 /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.896095809 Mar 12 03:33:04 PM PDT 24 Mar 12 04:07:31 PM PDT 24 107551876525 ps
T607 /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.1662249899 Mar 12 03:25:40 PM PDT 24 Mar 12 03:25:56 PM PDT 24 312273797 ps
T570 /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2766425746 Mar 12 03:24:52 PM PDT 24 Mar 12 03:36:02 PM PDT 24 58167948490 ps
T1302 /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2024052577 Mar 12 03:34:58 PM PDT 24 Mar 12 03:35:27 PM PDT 24 238765038 ps
T619 /workspace/coverage/cover_reg_top/94.xbar_smoke.2590564628 Mar 12 03:35:27 PM PDT 24 Mar 12 03:35:37 PM PDT 24 243642826 ps
T401 /workspace/coverage/cover_reg_top/57.xbar_stress_all.4099442338 Mar 12 03:30:50 PM PDT 24 Mar 12 03:35:52 PM PDT 24 3516764620 ps
T431 /workspace/coverage/cover_reg_top/29.xbar_random.618219929 Mar 12 03:27:17 PM PDT 24 Mar 12 03:28:32 PM PDT 24 2105749485 ps
T636 /workspace/coverage/cover_reg_top/55.xbar_error_random.4241641842 Mar 12 03:30:34 PM PDT 24 Mar 12 03:31:25 PM PDT 24 601597236 ps
T563 /workspace/coverage/cover_reg_top/31.xbar_same_source.2185414375 Mar 12 03:27:33 PM PDT 24 Mar 12 03:27:53 PM PDT 24 672888557 ps
T597 /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1467264496 Mar 12 03:25:11 PM PDT 24 Mar 12 03:35:59 PM PDT 24 35358685514 ps
T582 /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.233696538 Mar 12 03:34:57 PM PDT 24 Mar 12 03:41:33 PM PDT 24 7333109631 ps
T481 /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.540796408 Mar 12 03:33:12 PM PDT 24 Mar 12 03:34:03 PM PDT 24 546654668 ps
T497 /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2616692286 Mar 12 03:34:44 PM PDT 24 Mar 12 03:34:51 PM PDT 24 47226061 ps
T1303 /workspace/coverage/cover_reg_top/31.xbar_error_random.2684397646 Mar 12 03:27:34 PM PDT 24 Mar 12 03:27:49 PM PDT 24 151618489 ps
T785 /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1725709887 Mar 12 03:35:36 PM PDT 24 Mar 12 03:40:27 PM PDT 24 5865907970 ps
T587 /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.565279304 Mar 12 03:28:02 PM PDT 24 Mar 12 03:28:26 PM PDT 24 190191191 ps
T444 /workspace/coverage/cover_reg_top/45.xbar_same_source.3674158433 Mar 12 03:29:27 PM PDT 24 Mar 12 03:30:32 PM PDT 24 2103077420 ps
T600 /workspace/coverage/cover_reg_top/70.xbar_random.3106110104 Mar 12 03:32:35 PM PDT 24 Mar 12 03:33:14 PM PDT 24 1014759430 ps
T165 /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.856231232 Mar 12 03:25:25 PM PDT 24 Mar 12 04:35:32 PM PDT 24 31068002270 ps
T470 /workspace/coverage/cover_reg_top/43.xbar_random.379872773 Mar 12 03:29:01 PM PDT 24 Mar 12 03:30:09 PM PDT 24 1733157150 ps
T1304 /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1426767749 Mar 12 03:28:02 PM PDT 24 Mar 12 03:28:11 PM PDT 24 44332072 ps
T166 /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3556976738 Mar 12 03:24:49 PM PDT 24 Mar 12 03:45:53 PM PDT 24 14405822183 ps
T1305 /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.1591023947 Mar 12 03:29:38 PM PDT 24 Mar 12 03:30:54 PM PDT 24 7611286434 ps
T559 /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.2703397450 Mar 12 03:28:19 PM PDT 24 Mar 12 03:29:03 PM PDT 24 524152131 ps
T520 /workspace/coverage/cover_reg_top/5.chip_tl_errors.399859934 Mar 12 03:24:42 PM PDT 24 Mar 12 03:28:37 PM PDT 24 3202673626 ps
T558 /workspace/coverage/cover_reg_top/88.xbar_smoke.185397080 Mar 12 03:34:42 PM PDT 24 Mar 12 03:34:50 PM PDT 24 58424495 ps
T1306 /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4231163125 Mar 12 03:25:27 PM PDT 24 Mar 12 03:25:49 PM PDT 24 214377811 ps
T794 /workspace/coverage/cover_reg_top/67.xbar_access_same_device.836548202 Mar 12 03:31:59 PM PDT 24 Mar 12 03:32:18 PM PDT 24 261869984 ps
T323 /workspace/coverage/cover_reg_top/16.chip_csr_rw.1035342975 Mar 12 03:25:27 PM PDT 24 Mar 12 03:30:11 PM PDT 24 4322227709 ps
T786 /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1356340377 Mar 12 03:30:43 PM PDT 24 Mar 12 03:35:59 PM PDT 24 5104802745 ps
T424 /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.721314848 Mar 12 03:35:37 PM PDT 24 Mar 12 03:45:29 PM PDT 24 46028879930 ps
T1307 /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1134067197 Mar 12 03:31:46 PM PDT 24 Mar 12 03:33:13 PM PDT 24 5149022816 ps
T1308 /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2860117235 Mar 12 03:24:54 PM PDT 24 Mar 12 03:25:00 PM PDT 24 50701987 ps
T1309 /workspace/coverage/cover_reg_top/65.xbar_smoke.1550521860 Mar 12 03:31:47 PM PDT 24 Mar 12 03:31:56 PM PDT 24 226506877 ps
T781 /workspace/coverage/cover_reg_top/31.xbar_access_same_device.3795317831 Mar 12 03:27:25 PM PDT 24 Mar 12 03:28:53 PM PDT 24 1246024104 ps
T850 /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.4209459839 Mar 12 03:34:15 PM PDT 24 Mar 12 03:34:52 PM PDT 24 97604914 ps
T611 /workspace/coverage/cover_reg_top/46.xbar_random.1023589169 Mar 12 03:29:17 PM PDT 24 Mar 12 03:30:10 PM PDT 24 542393242 ps
T1310 /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.671594278 Mar 12 03:25:26 PM PDT 24 Mar 12 03:26:12 PM PDT 24 1312307833 ps
T324 /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2110490404 Mar 12 03:25:10 PM PDT 24 Mar 12 04:00:57 PM PDT 24 15195255485 ps
T1311 /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.578429835 Mar 12 03:25:30 PM PDT 24 Mar 12 03:25:52 PM PDT 24 502656025 ps
T425 /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2562428510 Mar 12 03:30:27 PM PDT 24 Mar 12 03:34:36 PM PDT 24 609498368 ps
T1312 /workspace/coverage/cover_reg_top/26.xbar_smoke.2867382474 Mar 12 03:27:00 PM PDT 24 Mar 12 03:27:07 PM PDT 24 54619283 ps
T592 /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1826364671 Mar 12 03:34:23 PM PDT 24 Mar 12 03:34:54 PM PDT 24 293135607 ps
T532 /workspace/coverage/cover_reg_top/1.xbar_random.3129666718 Mar 12 03:24:31 PM PDT 24 Mar 12 03:25:18 PM PDT 24 541679541 ps
T1313 /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.285691700 Mar 12 03:24:31 PM PDT 24 Mar 12 03:30:28 PM PDT 24 9536714532 ps
T1314 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3483256498 Mar 12 03:28:54 PM PDT 24 Mar 12 03:29:37 PM PDT 24 58650787 ps
T578 /workspace/coverage/cover_reg_top/11.xbar_random.4161729729 Mar 12 03:25:22 PM PDT 24 Mar 12 03:26:44 PM PDT 24 2060063842 ps
T1315 /workspace/coverage/cover_reg_top/96.xbar_stress_all.756235209 Mar 12 03:35:47 PM PDT 24 Mar 12 03:35:53 PM PDT 24 46830160 ps
T792 /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2281381865 Mar 12 03:31:45 PM PDT 24 Mar 12 03:38:18 PM PDT 24 10047228073 ps
T803 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1172714574 Mar 12 03:28:52 PM PDT 24 Mar 12 03:30:33 PM PDT 24 1410529319 ps
T782 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.345913275 Mar 12 03:25:09 PM PDT 24 Mar 12 03:35:13 PM PDT 24 6120632853 ps
T1316 /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3308407247 Mar 12 03:26:06 PM PDT 24 Mar 12 03:29:41 PM PDT 24 12130417452 ps
T373 /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1044446345 Mar 12 03:24:52 PM PDT 24 Mar 12 03:49:19 PM PDT 24 14753627659 ps
T423 /workspace/coverage/cover_reg_top/5.xbar_access_same_device.3250354540 Mar 12 03:25:07 PM PDT 24 Mar 12 03:26:02 PM PDT 24 1210876311 ps
T593 /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3872334279 Mar 12 03:33:38 PM PDT 24 Mar 12 03:39:08 PM PDT 24 19075649981 ps
T798 /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.171907635 Mar 12 03:31:16 PM PDT 24 Mar 12 03:34:17 PM PDT 24 4546776388 ps
T809 /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1215363026 Mar 12 03:33:17 PM PDT 24 Mar 12 03:35:43 PM PDT 24 3764324451 ps
T1317 /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.3432475179 Mar 12 03:25:09 PM PDT 24 Mar 12 03:26:35 PM PDT 24 5287481902 ps
T494 /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.8173884 Mar 12 03:24:36 PM PDT 24 Mar 12 03:40:07 PM PDT 24 96019958005 ps
T441 /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.2770548097 Mar 12 03:35:17 PM PDT 24 Mar 12 03:42:58 PM PDT 24 9181582699 ps
T1318 /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2629106753 Mar 12 03:28:10 PM PDT 24 Mar 12 03:29:40 PM PDT 24 5212906101 ps
T811 /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2737095201 Mar 12 03:24:57 PM PDT 24 Mar 12 03:38:43 PM PDT 24 44146480516 ps
T542 /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.2561210782 Mar 12 03:24:54 PM PDT 24 Mar 12 03:39:43 PM PDT 24 77208736569 ps
T159 /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.760871059 Mar 12 03:25:00 PM PDT 24 Mar 12 03:32:14 PM PDT 24 7289847960 ps
T609 /workspace/coverage/cover_reg_top/41.xbar_random.4094689827 Mar 12 03:28:45 PM PDT 24 Mar 12 03:29:10 PM PDT 24 248174855 ps
T1319 /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1818614034 Mar 12 03:27:49 PM PDT 24 Mar 12 03:27:55 PM PDT 24 55687374 ps
T594 /workspace/coverage/cover_reg_top/34.xbar_random.3121598872 Mar 12 03:27:59 PM PDT 24 Mar 12 03:28:20 PM PDT 24 497199559 ps
T1320 /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1070289343 Mar 12 03:29:37 PM PDT 24 Mar 12 03:29:43 PM PDT 24 37240881 ps
T426 /workspace/coverage/cover_reg_top/0.xbar_stress_all.3355335976 Mar 12 03:24:40 PM PDT 24 Mar 12 03:28:28 PM PDT 24 2809326686 ps
T1321 /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.480319081 Mar 12 03:27:26 PM PDT 24 Mar 12 03:29:18 PM PDT 24 9917837214 ps
T531 /workspace/coverage/cover_reg_top/20.xbar_random.115913349 Mar 12 03:26:07 PM PDT 24 Mar 12 03:27:01 PM PDT 24 580080272 ps
T1322 /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.1835240861 Mar 12 03:32:29 PM PDT 24 Mar 12 03:32:44 PM PDT 24 325157826 ps
T1323 /workspace/coverage/cover_reg_top/49.xbar_smoke.3990816559 Mar 12 03:29:40 PM PDT 24 Mar 12 03:29:49 PM PDT 24 176341036 ps
T517 /workspace/coverage/cover_reg_top/3.chip_tl_errors.1372357298 Mar 12 03:24:35 PM PDT 24 Mar 12 03:27:41 PM PDT 24 3702480590 ps
T1324 /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3616502513 Mar 12 03:26:59 PM PDT 24 Mar 12 03:27:06 PM PDT 24 54942728 ps
T783 /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1721980698 Mar 12 03:25:20 PM PDT 24 Mar 12 03:33:22 PM PDT 24 30287452318 ps
T804 /workspace/coverage/cover_reg_top/4.xbar_access_same_device.624664106 Mar 12 03:24:49 PM PDT 24 Mar 12 03:25:05 PM PDT 24 316889742 ps
T1325 /workspace/coverage/cover_reg_top/22.xbar_smoke.2821875232 Mar 12 03:26:28 PM PDT 24 Mar 12 03:26:34 PM PDT 24 36802572 ps
T478 /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.4290716179 Mar 12 03:34:59 PM PDT 24 Mar 12 04:18:05 PM PDT 24 131764194117 ps
T438 /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.3501865543 Mar 12 03:28:26 PM PDT 24 Mar 12 03:44:08 PM PDT 24 85670047560 ps
T1326 /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.3115719838 Mar 12 03:34:12 PM PDT 24 Mar 12 03:35:31 PM PDT 24 7465346931 ps
T789 /workspace/coverage/cover_reg_top/17.xbar_access_same_device.507226007 Mar 12 03:25:28 PM PDT 24 Mar 12 03:26:37 PM PDT 24 1846061832 ps
T479 /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.3550645919 Mar 12 03:31:44 PM PDT 24 Mar 12 03:48:07 PM PDT 24 52816040090 ps
T513 /workspace/coverage/cover_reg_top/14.chip_tl_errors.1174715490 Mar 12 03:25:23 PM PDT 24 Mar 12 03:30:10 PM PDT 24 4306150336 ps
T1327 /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.1316477036 Mar 12 03:34:28 PM PDT 24 Mar 12 03:36:13 PM PDT 24 9417842186 ps
T800 /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1419439687 Mar 12 03:25:26 PM PDT 24 Mar 12 04:04:47 PM PDT 24 123334377083 ps
T561 /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.4051880677 Mar 12 03:31:58 PM PDT 24 Mar 12 03:32:23 PM PDT 24 258135427 ps
T442 /workspace/coverage/cover_reg_top/39.xbar_access_same_device.2110579538 Mar 12 03:28:31 PM PDT 24 Mar 12 03:29:24 PM PDT 24 651682892 ps
T605 /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.523098680 Mar 12 03:31:25 PM PDT 24 Mar 12 03:32:08 PM PDT 24 958992662 ps
T363 /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3018749587 Mar 12 03:24:50 PM PDT 24 Mar 12 04:47:19 PM PDT 24 25383815838 ps
T1328 /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3680447586 Mar 12 03:26:56 PM PDT 24 Mar 12 03:31:54 PM PDT 24 8245257105 ps
T1329 /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1648270439 Mar 12 03:29:40 PM PDT 24 Mar 12 03:29:51 PM PDT 24 82850401 ps
T1330 /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.2394773976 Mar 12 03:31:52 PM PDT 24 Mar 12 03:32:07 PM PDT 24 326831935 ps
T1331 /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.2162996364 Mar 12 03:33:35 PM PDT 24 Mar 12 03:34:08 PM PDT 24 311928855 ps
T544 /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.1863614006 Mar 12 03:33:45 PM PDT 24 Mar 12 03:50:14 PM PDT 24 79024261945 ps
T1332 /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.4077206398 Mar 12 03:35:29 PM PDT 24 Mar 12 03:36:34 PM PDT 24 5835457131 ps
T465 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2276891084 Mar 12 03:32:39 PM PDT 24 Mar 12 03:41:22 PM PDT 24 7389317260 ps
T681 /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.367980967 Mar 12 03:31:41 PM PDT 24 Mar 12 03:32:21 PM PDT 24 992942194 ps
T1333 /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3969899449 Mar 12 03:32:36 PM PDT 24 Mar 12 03:33:28 PM PDT 24 2936274907 ps
T839 /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.764537095 Mar 12 03:29:27 PM PDT 24 Mar 12 03:32:03 PM PDT 24 351588049 ps
T1334 /workspace/coverage/cover_reg_top/48.xbar_error_random.4235850137 Mar 12 03:29:41 PM PDT 24 Mar 12 03:30:14 PM PDT 24 365839648 ps
T1335 /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.1379518379 Mar 12 03:27:11 PM PDT 24 Mar 12 03:46:30 PM PDT 24 103749469361 ps
T562 /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.1682726166 Mar 12 03:31:33 PM PDT 24 Mar 12 03:32:57 PM PDT 24 8449166081 ps
T590 /workspace/coverage/cover_reg_top/24.xbar_smoke.1199131396 Mar 12 03:26:38 PM PDT 24 Mar 12 03:26:48 PM PDT 24 245877901 ps
T552 /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1727326535 Mar 12 03:25:38 PM PDT 24 Mar 12 03:32:04 PM PDT 24 3044984104 ps
T1336 /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.788079489 Mar 12 03:35:54 PM PDT 24 Mar 12 03:42:30 PM PDT 24 21689638327 ps
T793 /workspace/coverage/cover_reg_top/13.xbar_access_same_device.3346320589 Mar 12 03:25:20 PM PDT 24 Mar 12 03:26:37 PM PDT 24 1066014450 ps
T553 /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.3139881476 Mar 12 03:28:57 PM PDT 24 Mar 12 03:29:33 PM PDT 24 372887229 ps
T498 /workspace/coverage/cover_reg_top/9.xbar_same_source.2566380691 Mar 12 03:25:20 PM PDT 24 Mar 12 03:25:40 PM PDT 24 257400963 ps
T541 /workspace/coverage/cover_reg_top/78.xbar_random.2278185616 Mar 12 03:33:33 PM PDT 24 Mar 12 03:34:15 PM PDT 24 441804244 ps
T625 /workspace/coverage/cover_reg_top/92.xbar_same_source.588234759 Mar 12 03:35:14 PM PDT 24 Mar 12 03:35:51 PM PDT 24 1365866267 ps
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T1344 /workspace/coverage/cover_reg_top/91.xbar_error_random.1941881631 Mar 12 03:35:05 PM PDT 24 Mar 12 03:35:44 PM PDT 24 1148371091 ps
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T1347 /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2897597696 Mar 12 03:25:27 PM PDT 24 Mar 12 03:30:47 PM PDT 24 20153118181 ps
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T1348 /workspace/coverage/cover_reg_top/76.xbar_random.3857299637 Mar 12 03:33:09 PM PDT 24 Mar 12 03:33:16 PM PDT 24 42485502 ps
T1349 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1789460628 Mar 12 03:29:00 PM PDT 24 Mar 12 03:29:12 PM PDT 24 90590887 ps
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T1350 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3703827010 Mar 12 03:27:47 PM PDT 24 Mar 12 03:28:35 PM PDT 24 635791756 ps
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T1352 /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.4011896163 Mar 12 03:34:18 PM PDT 24 Mar 12 03:34:26 PM PDT 24 52676086 ps
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T1353 /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.1014655205 Mar 12 03:27:39 PM PDT 24 Mar 12 03:29:09 PM PDT 24 8486934089 ps
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T1354 /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1699617512 Mar 12 03:31:32 PM PDT 24 Mar 12 03:31:39 PM PDT 24 44414159 ps
T595 /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.3945453665 Mar 12 03:28:11 PM PDT 24 Mar 12 03:28:54 PM PDT 24 448341467 ps
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T1355 /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.2618455975 Mar 12 03:30:21 PM PDT 24 Mar 12 03:31:43 PM PDT 24 5257361250 ps
T489 /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.1904711653 Mar 12 03:30:53 PM PDT 24 Mar 12 03:44:39 PM PDT 24 46726959322 ps
T1356 /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.3938776563 Mar 12 03:28:10 PM PDT 24 Mar 12 03:29:51 PM PDT 24 9240233605 ps
T1357 /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.1767892432 Mar 12 03:28:45 PM PDT 24 Mar 12 03:30:03 PM PDT 24 7126764770 ps
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T1363 /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3630898074 Mar 12 03:35:46 PM PDT 24 Mar 12 03:36:15 PM PDT 24 305017725 ps
T1364 /workspace/coverage/cover_reg_top/76.xbar_error_random.1671942632 Mar 12 03:33:18 PM PDT 24 Mar 12 03:33:40 PM PDT 24 523828726 ps
T1365 /workspace/coverage/cover_reg_top/53.xbar_error_random.2729925815 Mar 12 03:30:18 PM PDT 24 Mar 12 03:31:32 PM PDT 24 2186808470 ps
T1366 /workspace/coverage/cover_reg_top/28.chip_tl_errors.283907026 Mar 12 03:27:02 PM PDT 24 Mar 12 03:28:33 PM PDT 24 2441591811 ps
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T788 /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1919096067 Mar 12 03:25:21 PM PDT 24 Mar 12 03:32:04 PM PDT 24 11802691286 ps
T1368 /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1683103487 Mar 12 03:35:12 PM PDT 24 Mar 12 03:49:33 PM PDT 24 46408515211 ps
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T1369 /workspace/coverage/cover_reg_top/22.xbar_error_random.392258671 Mar 12 03:26:34 PM PDT 24 Mar 12 03:27:12 PM PDT 24 1166587352 ps
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T1370 /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.2905540432 Mar 12 03:27:00 PM PDT 24 Mar 12 03:28:23 PM PDT 24 8134536287 ps
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T486 /workspace/coverage/cover_reg_top/87.xbar_random.2162690480 Mar 12 03:34:32 PM PDT 24 Mar 12 03:35:00 PM PDT 24 315696053 ps
T1371 /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1404467725 Mar 12 03:33:48 PM PDT 24 Mar 12 03:34:23 PM PDT 24 446607546 ps
T428 /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3332188006 Mar 12 03:26:57 PM PDT 24 Mar 12 03:32:15 PM PDT 24 1376657446 ps
T579 /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.1734532640 Mar 12 03:24:58 PM PDT 24 Mar 12 03:25:37 PM PDT 24 1096572605 ps
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T1372 /workspace/coverage/cover_reg_top/84.xbar_smoke.437737183 Mar 12 03:34:09 PM PDT 24 Mar 12 03:34:16 PM PDT 24 38860964 ps
T824 /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2443261872 Mar 12 03:25:21 PM PDT 24 Mar 12 03:28:55 PM PDT 24 4360859934 ps
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T1375 /workspace/coverage/cover_reg_top/50.xbar_smoke.403744762 Mar 12 03:29:46 PM PDT 24 Mar 12 03:29:52 PM PDT 24 45720034 ps
T1376 /workspace/coverage/cover_reg_top/20.xbar_access_same_device.2161781654 Mar 12 03:26:05 PM PDT 24 Mar 12 03:26:15 PM PDT 24 189270567 ps
T1377 /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.2242301675 Mar 12 03:28:23 PM PDT 24 Mar 12 03:28:48 PM PDT 24 195179612 ps
T1378 /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.2658411028 Mar 12 03:26:41 PM PDT 24 Mar 12 03:27:17 PM PDT 24 3361678991 ps
T1379 /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.927088842 Mar 12 03:30:34 PM PDT 24 Mar 12 03:42:17 PM PDT 24 61431797903 ps
T614 /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3617832670 Mar 12 03:34:07 PM PDT 24 Mar 12 03:48:50 PM PDT 24 50458239033 ps
T1380 /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1403071065 Mar 12 03:29:50 PM PDT 24 Mar 12 03:30:16 PM PDT 24 535680676 ps
T1381 /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.3024163655 Mar 12 03:28:32 PM PDT 24 Mar 12 03:30:06 PM PDT 24 5667104070 ps
T1382 /workspace/coverage/cover_reg_top/53.xbar_stress_all.2326432150 Mar 12 03:30:28 PM PDT 24 Mar 12 03:32:34 PM PDT 24 3416345188 ps
T1383 /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1770146081 Mar 12 03:25:00 PM PDT 24 Mar 12 03:25:05 PM PDT 24 38964815 ps
T1384 /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.1882041547 Mar 12 03:26:47 PM PDT 24 Mar 12 03:27:01 PM PDT 24 103037011 ps
T488 /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3492168726 Mar 12 03:27:00 PM PDT 24 Mar 12 03:27:41 PM PDT 24 427904182 ps
T1385 /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.430177447 Mar 12 03:34:53 PM PDT 24 Mar 12 03:38:42 PM PDT 24 2933485001 ps
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T624 /workspace/coverage/cover_reg_top/55.xbar_stress_all.3949282771 Mar 12 03:30:36 PM PDT 24 Mar 12 03:34:16 PM PDT 24 6249638629 ps
T557 /workspace/coverage/cover_reg_top/32.xbar_random.3251234086 Mar 12 03:27:42 PM PDT 24 Mar 12 03:28:27 PM PDT 24 487583089 ps
T621 /workspace/coverage/cover_reg_top/62.xbar_random.343023880 Mar 12 03:31:27 PM PDT 24 Mar 12 03:31:53 PM PDT 24 709929111 ps
T1387 /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2750815167 Mar 12 03:25:39 PM PDT 24 Mar 12 03:25:46 PM PDT 24 57036571 ps
T820 /workspace/coverage/cover_reg_top/59.xbar_stress_all.385344018 Mar 12 03:31:05 PM PDT 24 Mar 12 03:33:18 PM PDT 24 2937066970 ps
T1388 /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.2516245732 Mar 12 03:30:25 PM PDT 24 Mar 12 03:34:18 PM PDT 24 7055320460 ps
T1389 /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.3229954836 Mar 12 03:33:09 PM PDT 24 Mar 12 03:33:31 PM PDT 24 172273581 ps
T801 /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3441518014 Mar 12 03:29:47 PM PDT 24 Mar 12 03:40:35 PM PDT 24 36580247375 ps
T617 /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2901368649 Mar 12 03:29:01 PM PDT 24 Mar 12 03:29:38 PM PDT 24 914107759 ps
T452 /workspace/coverage/cover_reg_top/42.xbar_stress_all.2400848566 Mar 12 03:28:57 PM PDT 24 Mar 12 03:37:42 PM PDT 24 12808304123 ps
T1390 /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.4022503648 Mar 12 03:34:09 PM PDT 24 Mar 12 03:35:32 PM PDT 24 936780108 ps
T556 /workspace/coverage/cover_reg_top/69.xbar_stress_all.622653378 Mar 12 03:32:25 PM PDT 24 Mar 12 03:33:09 PM PDT 24 534760506 ps
T1391 /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3393822256 Mar 12 03:33:33 PM PDT 24 Mar 12 03:35:05 PM PDT 24 8906464783 ps
T827 /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1614355750 Mar 12 03:24:38 PM PDT 24 Mar 12 03:25:54 PM PDT 24 239978059 ps
T160 /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.278554156 Mar 12 03:24:58 PM PDT 24 Mar 12 03:29:12 PM PDT 24 5825732542 ps
T1392 /workspace/coverage/cover_reg_top/66.xbar_access_same_device.73210015 Mar 12 03:31:52 PM PDT 24 Mar 12 03:32:01 PM PDT 24 90948150 ps
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