| T1010 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.2697050753 |
|
|
Mar 12 03:49:39 PM PDT 24 |
Mar 12 03:53:57 PM PDT 24 |
3341851228 ps |
| T1011 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1124316531 |
|
|
Mar 12 03:53:21 PM PDT 24 |
Mar 12 04:37:29 PM PDT 24 |
11026983726 ps |
| T1012 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.767221353 |
|
|
Mar 12 04:05:14 PM PDT 24 |
Mar 12 04:50:43 PM PDT 24 |
13923129808 ps |
| T1013 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3981847939 |
|
|
Mar 12 03:44:45 PM PDT 24 |
Mar 12 03:58:16 PM PDT 24 |
4756559450 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3045224968 |
|
|
Mar 12 03:52:52 PM PDT 24 |
Mar 12 04:16:26 PM PDT 24 |
11715641854 ps |
| T1015 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1015356533 |
|
|
Mar 12 04:10:21 PM PDT 24 |
Mar 12 05:25:30 PM PDT 24 |
22922909136 ps |
| T680 |
/workspace/coverage/default/0.chip_sw_power_idle_load.4264448200 |
|
|
Mar 12 03:47:03 PM PDT 24 |
Mar 12 03:57:15 PM PDT 24 |
4180337016 ps |
| T754 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1702339142 |
|
|
Mar 12 04:10:43 PM PDT 24 |
Mar 12 04:18:05 PM PDT 24 |
3686778468 ps |
| T110 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.2143415720 |
|
|
Mar 12 03:52:12 PM PDT 24 |
Mar 12 04:04:41 PM PDT 24 |
3395718796 ps |
| T744 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3153709588 |
|
|
Mar 12 04:09:48 PM PDT 24 |
Mar 12 04:15:46 PM PDT 24 |
3244306948 ps |
| T1016 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1958457538 |
|
|
Mar 12 03:58:22 PM PDT 24 |
Mar 12 04:03:33 PM PDT 24 |
3568400000 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3010276444 |
|
|
Mar 12 04:03:41 PM PDT 24 |
Mar 12 04:12:02 PM PDT 24 |
5108023500 ps |
| T645 |
/workspace/coverage/default/4.chip_tap_straps_dev.1962559007 |
|
|
Mar 12 04:05:05 PM PDT 24 |
Mar 12 04:18:14 PM PDT 24 |
8523365875 ps |
| T1018 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1743619593 |
|
|
Mar 12 04:03:34 PM PDT 24 |
Mar 12 04:13:09 PM PDT 24 |
7624060804 ps |
| T1019 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.714455225 |
|
|
Mar 12 03:51:57 PM PDT 24 |
Mar 12 04:00:23 PM PDT 24 |
4710961600 ps |
| T723 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3999951552 |
|
|
Mar 12 04:12:46 PM PDT 24 |
Mar 12 04:21:39 PM PDT 24 |
5147250104 ps |
| T752 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.2611748615 |
|
|
Mar 12 04:07:24 PM PDT 24 |
Mar 12 04:17:46 PM PDT 24 |
5173934088 ps |
| T772 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3431281265 |
|
|
Mar 12 04:11:00 PM PDT 24 |
Mar 12 04:17:47 PM PDT 24 |
3907216826 ps |
| T43 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2040556962 |
|
|
Mar 12 04:04:35 PM PDT 24 |
Mar 12 04:11:58 PM PDT 24 |
4562231800 ps |
| T1020 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2725445305 |
|
|
Mar 12 04:01:45 PM PDT 24 |
Mar 12 04:09:58 PM PDT 24 |
3682456696 ps |
| T759 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1168390150 |
|
|
Mar 12 04:15:32 PM PDT 24 |
Mar 12 04:21:15 PM PDT 24 |
4054000664 ps |
| T1021 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.2548843162 |
|
|
Mar 12 03:45:14 PM PDT 24 |
Mar 12 03:56:04 PM PDT 24 |
5862529954 ps |
| T691 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1833388061 |
|
|
Mar 12 03:47:16 PM PDT 24 |
Mar 12 04:44:59 PM PDT 24 |
20872257261 ps |
| T1022 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.525813327 |
|
|
Mar 12 03:46:18 PM PDT 24 |
Mar 12 03:54:28 PM PDT 24 |
4118683180 ps |
| T1023 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4025043133 |
|
|
Mar 12 04:02:12 PM PDT 24 |
Mar 12 04:07:47 PM PDT 24 |
3559618998 ps |
| T1024 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2254758882 |
|
|
Mar 12 03:58:19 PM PDT 24 |
Mar 12 04:23:21 PM PDT 24 |
7982376030 ps |
| T119 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2378686161 |
|
|
Mar 12 03:44:20 PM PDT 24 |
Mar 12 03:48:57 PM PDT 24 |
3247965629 ps |
| T1025 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2429017433 |
|
|
Mar 12 03:51:28 PM PDT 24 |
Mar 12 04:01:18 PM PDT 24 |
3660232932 ps |
| T739 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3772733302 |
|
|
Mar 12 04:14:01 PM PDT 24 |
Mar 12 04:19:55 PM PDT 24 |
4043870640 ps |
| T1026 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2294528603 |
|
|
Mar 12 03:45:59 PM PDT 24 |
Mar 12 03:50:39 PM PDT 24 |
2887200945 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.75204748 |
|
|
Mar 12 03:46:18 PM PDT 24 |
Mar 12 04:17:19 PM PDT 24 |
7572707958 ps |
| T1027 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1264659097 |
|
|
Mar 12 03:51:43 PM PDT 24 |
Mar 12 04:00:35 PM PDT 24 |
4841887216 ps |
| T1028 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.2793761327 |
|
|
Mar 12 03:48:15 PM PDT 24 |
Mar 12 03:56:45 PM PDT 24 |
4312727944 ps |
| T771 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.48975763 |
|
|
Mar 12 04:09:09 PM PDT 24 |
Mar 12 04:15:20 PM PDT 24 |
3950372440 ps |
| T287 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.549752143 |
|
|
Mar 12 03:45:00 PM PDT 24 |
Mar 12 03:57:06 PM PDT 24 |
4106768597 ps |
| T325 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.1524691276 |
|
|
Mar 12 04:09:52 PM PDT 24 |
Mar 12 04:20:32 PM PDT 24 |
5233289328 ps |
| T340 |
/workspace/coverage/default/0.chip_tap_straps_dev.2787090687 |
|
|
Mar 12 03:48:09 PM PDT 24 |
Mar 12 04:02:46 PM PDT 24 |
7741864371 ps |
| T341 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.895561664 |
|
|
Mar 12 04:12:43 PM PDT 24 |
Mar 12 04:19:53 PM PDT 24 |
3834128492 ps |
| T342 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1198474375 |
|
|
Mar 12 04:09:15 PM PDT 24 |
Mar 12 04:24:49 PM PDT 24 |
6522600144 ps |
| T343 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1944565020 |
|
|
Mar 12 04:05:15 PM PDT 24 |
Mar 12 04:14:01 PM PDT 24 |
4678344432 ps |
| T344 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1930881324 |
|
|
Mar 12 03:54:05 PM PDT 24 |
Mar 12 04:03:32 PM PDT 24 |
5443807256 ps |
| T345 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2469375773 |
|
|
Mar 12 03:46:15 PM PDT 24 |
Mar 12 03:52:57 PM PDT 24 |
3628862866 ps |
| T346 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1404171584 |
|
|
Mar 12 03:45:25 PM PDT 24 |
Mar 12 04:01:01 PM PDT 24 |
5151724364 ps |
| T231 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.1976086765 |
|
|
Mar 12 04:12:26 PM PDT 24 |
Mar 12 04:23:08 PM PDT 24 |
5027448840 ps |
| T347 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2942837704 |
|
|
Mar 12 04:04:23 PM PDT 24 |
Mar 12 04:11:08 PM PDT 24 |
4885377090 ps |
| T1029 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1034685602 |
|
|
Mar 12 03:46:29 PM PDT 24 |
Mar 12 04:29:28 PM PDT 24 |
25614810073 ps |
| T1030 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.955664341 |
|
|
Mar 12 04:10:59 PM PDT 24 |
Mar 12 04:18:34 PM PDT 24 |
3841704050 ps |
| T1031 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.294229652 |
|
|
Mar 12 03:51:09 PM PDT 24 |
Mar 12 04:28:55 PM PDT 24 |
8704502808 ps |
| T1032 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.771045800 |
|
|
Mar 12 03:46:53 PM PDT 24 |
Mar 12 03:50:33 PM PDT 24 |
2406960282 ps |
| T1033 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3350162337 |
|
|
Mar 12 04:05:57 PM PDT 24 |
Mar 12 04:40:55 PM PDT 24 |
14453098265 ps |
| T155 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.948116867 |
|
|
Mar 12 04:06:31 PM PDT 24 |
Mar 12 04:20:46 PM PDT 24 |
6249065444 ps |
| T1034 |
/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.2748930713 |
|
|
Mar 12 04:10:42 PM PDT 24 |
Mar 12 04:40:04 PM PDT 24 |
8378239590 ps |
| T730 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3342565683 |
|
|
Mar 12 04:09:50 PM PDT 24 |
Mar 12 04:16:43 PM PDT 24 |
3922451672 ps |
| T1035 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1058082426 |
|
|
Mar 12 03:48:36 PM PDT 24 |
Mar 12 07:20:00 PM PDT 24 |
64687902758 ps |
| T1036 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2640728810 |
|
|
Mar 12 03:55:33 PM PDT 24 |
Mar 12 03:58:49 PM PDT 24 |
3245979574 ps |
| T1037 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3230686961 |
|
|
Mar 12 04:05:47 PM PDT 24 |
Mar 12 04:13:32 PM PDT 24 |
5226843914 ps |
| T715 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3615797369 |
|
|
Mar 12 04:06:39 PM PDT 24 |
Mar 12 04:19:34 PM PDT 24 |
6018750936 ps |
| T1038 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1047516342 |
|
|
Mar 12 03:49:36 PM PDT 24 |
Mar 12 03:53:33 PM PDT 24 |
2497297156 ps |
| T1039 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1781175109 |
|
|
Mar 12 03:46:44 PM PDT 24 |
Mar 12 03:57:54 PM PDT 24 |
4033869416 ps |
| T1040 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.436558743 |
|
|
Mar 12 03:49:57 PM PDT 24 |
Mar 12 04:08:48 PM PDT 24 |
9741470124 ps |
| T1041 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3868033246 |
|
|
Mar 12 04:13:53 PM PDT 24 |
Mar 12 04:22:56 PM PDT 24 |
5580883920 ps |
| T773 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.45154163 |
|
|
Mar 12 04:09:49 PM PDT 24 |
Mar 12 04:19:48 PM PDT 24 |
4773111302 ps |
| T693 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2013055798 |
|
|
Mar 12 04:17:04 PM PDT 24 |
Mar 12 04:25:55 PM PDT 24 |
5577677564 ps |
| T1042 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.539027212 |
|
|
Mar 12 03:50:15 PM PDT 24 |
Mar 12 03:57:01 PM PDT 24 |
4955704476 ps |
| T326 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3820746704 |
|
|
Mar 12 04:14:59 PM PDT 24 |
Mar 12 04:24:14 PM PDT 24 |
4400944760 ps |
| T1043 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1474069653 |
|
|
Mar 12 03:46:34 PM PDT 24 |
Mar 12 04:01:29 PM PDT 24 |
6869510145 ps |
| T1044 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2207818370 |
|
|
Mar 12 04:13:41 PM PDT 24 |
Mar 12 04:22:23 PM PDT 24 |
5517445028 ps |
| T1045 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2902579244 |
|
|
Mar 12 04:08:51 PM PDT 24 |
Mar 12 04:15:23 PM PDT 24 |
3768239782 ps |
| T1046 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3782813507 |
|
|
Mar 12 03:45:20 PM PDT 24 |
Mar 12 03:57:54 PM PDT 24 |
5080671382 ps |
| T1047 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.51801653 |
|
|
Mar 12 03:46:10 PM PDT 24 |
Mar 12 03:53:25 PM PDT 24 |
4031811764 ps |
| T1048 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.505535059 |
|
|
Mar 12 04:02:38 PM PDT 24 |
Mar 12 04:17:13 PM PDT 24 |
3683094898 ps |
| T1049 |
/workspace/coverage/default/2.rom_raw_unlock.85403967 |
|
|
Mar 12 04:06:21 PM PDT 24 |
Mar 12 04:30:26 PM PDT 24 |
15882029166 ps |
| T1050 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.2458391610 |
|
|
Mar 12 04:03:05 PM PDT 24 |
Mar 12 04:32:07 PM PDT 24 |
9163669532 ps |
| T1051 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2255812940 |
|
|
Mar 12 04:02:28 PM PDT 24 |
Mar 12 04:12:27 PM PDT 24 |
4392362176 ps |
| T1052 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.859561311 |
|
|
Mar 12 03:47:42 PM PDT 24 |
Mar 12 03:52:35 PM PDT 24 |
3131799358 ps |
| T1053 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.1866644647 |
|
|
Mar 12 04:06:32 PM PDT 24 |
Mar 12 04:14:15 PM PDT 24 |
4234824292 ps |
| T1054 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3728263352 |
|
|
Mar 12 04:04:34 PM PDT 24 |
Mar 12 04:13:07 PM PDT 24 |
4936898600 ps |
| T726 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.924177286 |
|
|
Mar 12 04:12:53 PM PDT 24 |
Mar 12 04:18:10 PM PDT 24 |
3551294600 ps |
| T301 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.2423889825 |
|
|
Mar 12 03:52:04 PM PDT 24 |
Mar 12 04:08:06 PM PDT 24 |
5139886092 ps |
| T210 |
/workspace/coverage/default/2.chip_sw_flash_init.2923454568 |
|
|
Mar 12 03:56:59 PM PDT 24 |
Mar 12 04:32:27 PM PDT 24 |
18243063245 ps |
| T501 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.196900044 |
|
|
Mar 12 03:50:19 PM PDT 24 |
Mar 12 04:00:49 PM PDT 24 |
4596468194 ps |
| T206 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1324211836 |
|
|
Mar 12 03:50:13 PM PDT 24 |
Mar 12 03:59:04 PM PDT 24 |
5306868727 ps |
| T1055 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3752409718 |
|
|
Mar 12 03:44:16 PM PDT 24 |
Mar 12 04:02:20 PM PDT 24 |
6500943821 ps |
| T201 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3421546763 |
|
|
Mar 12 04:04:18 PM PDT 24 |
Mar 12 04:32:16 PM PDT 24 |
18473594585 ps |
| T1056 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.2572016470 |
|
|
Mar 12 04:05:23 PM PDT 24 |
Mar 12 04:12:29 PM PDT 24 |
2900814568 ps |
| T1057 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1068949643 |
|
|
Mar 12 03:51:49 PM PDT 24 |
Mar 12 04:02:56 PM PDT 24 |
4498968210 ps |
| T1058 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2281614088 |
|
|
Mar 12 03:52:26 PM PDT 24 |
Mar 12 04:31:00 PM PDT 24 |
8396255680 ps |
| T321 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.969620093 |
|
|
Mar 12 03:57:43 PM PDT 24 |
Mar 12 04:09:32 PM PDT 24 |
4852839290 ps |
| T1059 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.3431212164 |
|
|
Mar 12 03:44:34 PM PDT 24 |
Mar 12 03:48:36 PM PDT 24 |
2555650552 ps |
| T1060 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3381362290 |
|
|
Mar 12 04:00:55 PM PDT 24 |
Mar 12 04:07:00 PM PDT 24 |
2684249986 ps |
| T765 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1713814155 |
|
|
Mar 12 04:10:14 PM PDT 24 |
Mar 12 04:17:06 PM PDT 24 |
3924601624 ps |
| T82 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.793679424 |
|
|
Mar 12 04:13:14 PM PDT 24 |
Mar 12 04:18:38 PM PDT 24 |
3290615268 ps |
| T1061 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.849852869 |
|
|
Mar 12 04:03:52 PM PDT 24 |
Mar 12 05:01:55 PM PDT 24 |
21254644355 ps |
| T1062 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2794258559 |
|
|
Mar 12 03:54:46 PM PDT 24 |
Mar 12 04:09:22 PM PDT 24 |
6394823170 ps |
| T738 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1724374684 |
|
|
Mar 12 04:11:23 PM PDT 24 |
Mar 12 04:18:36 PM PDT 24 |
4046114520 ps |
| T1063 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.475276696 |
|
|
Mar 12 04:02:03 PM PDT 24 |
Mar 12 04:06:44 PM PDT 24 |
2306181956 ps |
| T1064 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.393404335 |
|
|
Mar 12 04:06:11 PM PDT 24 |
Mar 12 04:15:52 PM PDT 24 |
6632836118 ps |
| T1065 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.4101755740 |
|
|
Mar 12 04:00:11 PM PDT 24 |
Mar 12 04:20:46 PM PDT 24 |
8981961750 ps |
| T1066 |
/workspace/coverage/default/1.chip_sw_example_flash.3449006683 |
|
|
Mar 12 03:50:04 PM PDT 24 |
Mar 12 03:53:10 PM PDT 24 |
2667040892 ps |
| T716 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3758506729 |
|
|
Mar 12 04:12:47 PM PDT 24 |
Mar 12 04:24:17 PM PDT 24 |
4691507998 ps |
| T400 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2282740496 |
|
|
Mar 12 03:57:19 PM PDT 24 |
Mar 12 04:02:18 PM PDT 24 |
3274449340 ps |
| T1067 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.3164830279 |
|
|
Mar 12 03:47:17 PM PDT 24 |
Mar 12 03:51:35 PM PDT 24 |
2502759068 ps |
| T37 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.663850948 |
|
|
Mar 12 03:57:11 PM PDT 24 |
Mar 12 04:04:27 PM PDT 24 |
3605786131 ps |
| T694 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2234008008 |
|
|
Mar 12 04:14:34 PM PDT 24 |
Mar 12 04:24:45 PM PDT 24 |
4922026160 ps |
| T1068 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.1497696405 |
|
|
Mar 12 03:45:16 PM PDT 24 |
Mar 12 04:02:24 PM PDT 24 |
5396763864 ps |
| T1069 |
/workspace/coverage/default/2.chip_sw_power_idle_load.385052779 |
|
|
Mar 12 04:04:43 PM PDT 24 |
Mar 12 04:13:52 PM PDT 24 |
3916600060 ps |
| T293 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3631183194 |
|
|
Mar 12 03:52:35 PM PDT 24 |
Mar 12 04:17:57 PM PDT 24 |
6871408104 ps |
| T1070 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2566191461 |
|
|
Mar 12 03:44:30 PM PDT 24 |
Mar 12 04:42:27 PM PDT 24 |
18697264869 ps |
| T312 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.354052035 |
|
|
Mar 12 03:48:50 PM PDT 24 |
Mar 12 03:53:44 PM PDT 24 |
2808368874 ps |
| T1071 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.789982220 |
|
|
Mar 12 03:50:17 PM PDT 24 |
Mar 12 04:02:11 PM PDT 24 |
5437035384 ps |
| T749 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2423347249 |
|
|
Mar 12 04:09:33 PM PDT 24 |
Mar 12 04:15:46 PM PDT 24 |
3400578696 ps |
| T1072 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.222172256 |
|
|
Mar 12 03:57:44 PM PDT 24 |
Mar 12 04:05:07 PM PDT 24 |
3629769980 ps |
| T1073 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.4282048644 |
|
|
Mar 12 03:52:52 PM PDT 24 |
Mar 12 04:02:26 PM PDT 24 |
7001292122 ps |
| T1074 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4016469659 |
|
|
Mar 12 03:55:45 PM PDT 24 |
Mar 12 04:08:46 PM PDT 24 |
5284366677 ps |
| T1075 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3744578103 |
|
|
Mar 12 04:04:31 PM PDT 24 |
Mar 12 04:56:48 PM PDT 24 |
16887170992 ps |
| T747 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.4274327596 |
|
|
Mar 12 04:09:14 PM PDT 24 |
Mar 12 04:20:14 PM PDT 24 |
5757023636 ps |
| T1076 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1566020370 |
|
|
Mar 12 03:54:27 PM PDT 24 |
Mar 12 04:16:39 PM PDT 24 |
9791764536 ps |
| T1077 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.793006322 |
|
|
Mar 12 04:02:20 PM PDT 24 |
Mar 12 04:12:25 PM PDT 24 |
5149604264 ps |
| T1078 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.658670043 |
|
|
Mar 12 03:51:17 PM PDT 24 |
Mar 12 04:09:27 PM PDT 24 |
5814501966 ps |
| T702 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1765766053 |
|
|
Mar 12 04:07:41 PM PDT 24 |
Mar 12 04:14:07 PM PDT 24 |
3498175230 ps |
| T83 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4064972092 |
|
|
Mar 12 04:12:23 PM PDT 24 |
Mar 12 04:17:35 PM PDT 24 |
3267421624 ps |
| T111 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.586563123 |
|
|
Mar 12 03:48:54 PM PDT 24 |
Mar 12 03:58:47 PM PDT 24 |
3652580510 ps |
| T1079 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1568847626 |
|
|
Mar 12 03:51:23 PM PDT 24 |
Mar 12 04:21:03 PM PDT 24 |
9043614055 ps |
| T684 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1697686537 |
|
|
Mar 12 03:44:38 PM PDT 24 |
Mar 12 04:14:50 PM PDT 24 |
23198552660 ps |
| T1080 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3364734551 |
|
|
Mar 12 03:46:11 PM PDT 24 |
Mar 12 04:41:11 PM PDT 24 |
17710050504 ps |
| T232 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2920714959 |
|
|
Mar 12 04:00:45 PM PDT 24 |
Mar 12 04:09:04 PM PDT 24 |
4774906680 ps |
| T1081 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.3500680522 |
|
|
Mar 12 03:47:36 PM PDT 24 |
Mar 12 03:52:21 PM PDT 24 |
3199170276 ps |
| T1082 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.127093606 |
|
|
Mar 12 03:45:21 PM PDT 24 |
Mar 12 03:49:33 PM PDT 24 |
2102930992 ps |
| T218 |
/workspace/coverage/default/2.chip_sw_alert_test.1112246329 |
|
|
Mar 12 04:00:38 PM PDT 24 |
Mar 12 04:05:56 PM PDT 24 |
2784099918 ps |
| T676 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.3265355234 |
|
|
Mar 12 03:49:17 PM PDT 24 |
Mar 12 03:55:56 PM PDT 24 |
4557505178 ps |
| T1083 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2785665749 |
|
|
Mar 12 03:56:01 PM PDT 24 |
Mar 12 04:01:24 PM PDT 24 |
3052340650 ps |
| T320 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.1287669909 |
|
|
Mar 12 04:00:50 PM PDT 24 |
Mar 12 04:09:58 PM PDT 24 |
4320297780 ps |
| T182 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4162586891 |
|
|
Mar 12 03:54:54 PM PDT 24 |
Mar 12 04:05:27 PM PDT 24 |
4027337242 ps |
| T34 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1496525175 |
|
|
Mar 12 03:58:15 PM PDT 24 |
Mar 12 04:04:13 PM PDT 24 |
3443497800 ps |
| T762 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2049566344 |
|
|
Mar 12 04:11:48 PM PDT 24 |
Mar 12 04:21:21 PM PDT 24 |
5967018700 ps |
| T1084 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1999924060 |
|
|
Mar 12 03:55:51 PM PDT 24 |
Mar 12 04:05:21 PM PDT 24 |
4145994720 ps |
| T1085 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.564591251 |
|
|
Mar 12 03:54:06 PM PDT 24 |
Mar 12 03:59:01 PM PDT 24 |
2739169108 ps |
| T774 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2616243551 |
|
|
Mar 12 04:12:10 PM PDT 24 |
Mar 12 04:22:34 PM PDT 24 |
5641322096 ps |
| T1086 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.3221469200 |
|
|
Mar 12 03:52:39 PM PDT 24 |
Mar 12 04:02:27 PM PDT 24 |
6160807995 ps |
| T1087 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1070683564 |
|
|
Mar 12 03:44:33 PM PDT 24 |
Mar 12 04:01:44 PM PDT 24 |
5158971316 ps |
| T1088 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3166259479 |
|
|
Mar 12 03:46:26 PM PDT 24 |
Mar 12 03:55:45 PM PDT 24 |
5845890800 ps |
| T1089 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1069428764 |
|
|
Mar 12 03:52:51 PM PDT 24 |
Mar 12 04:37:50 PM PDT 24 |
9869816790 ps |
| T263 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.443644891 |
|
|
Mar 12 03:47:12 PM PDT 24 |
Mar 12 03:52:54 PM PDT 24 |
2931460540 ps |
| T1090 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.327201320 |
|
|
Mar 12 04:16:05 PM PDT 24 |
Mar 12 04:22:50 PM PDT 24 |
3430883386 ps |
| T1091 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1835875174 |
|
|
Mar 12 03:51:19 PM PDT 24 |
Mar 12 04:16:20 PM PDT 24 |
7591942762 ps |
| T1092 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4107949908 |
|
|
Mar 12 04:06:20 PM PDT 24 |
Mar 12 04:43:27 PM PDT 24 |
14295949704 ps |
| T649 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1139316317 |
|
|
Mar 12 03:49:12 PM PDT 24 |
Mar 12 03:50:48 PM PDT 24 |
2157965047 ps |
| T1093 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1862676259 |
|
|
Mar 12 03:53:45 PM PDT 24 |
Mar 12 04:15:29 PM PDT 24 |
9431717480 ps |
| T1094 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2980478547 |
|
|
Mar 12 03:48:20 PM PDT 24 |
Mar 12 04:22:56 PM PDT 24 |
8375056296 ps |
| T740 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.917408979 |
|
|
Mar 12 04:09:48 PM PDT 24 |
Mar 12 04:21:41 PM PDT 24 |
5916446334 ps |
| T335 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2644626450 |
|
|
Mar 12 03:55:34 PM PDT 24 |
Mar 12 04:39:01 PM PDT 24 |
11435094968 ps |
| T1095 |
/workspace/coverage/default/2.chip_sw_aes_entropy.4188575111 |
|
|
Mar 12 04:01:34 PM PDT 24 |
Mar 12 04:07:22 PM PDT 24 |
2988180936 ps |
| T253 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.730492803 |
|
|
Mar 12 04:00:47 PM PDT 24 |
Mar 12 04:08:25 PM PDT 24 |
5799691744 ps |
| T1096 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.772266982 |
|
|
Mar 12 04:00:24 PM PDT 24 |
Mar 12 04:04:27 PM PDT 24 |
2995484648 ps |
| T1097 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3591052218 |
|
|
Mar 12 03:54:57 PM PDT 24 |
Mar 12 04:16:31 PM PDT 24 |
6614422296 ps |
| T1098 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.496508218 |
|
|
Mar 12 03:49:54 PM PDT 24 |
Mar 12 03:56:58 PM PDT 24 |
4056562088 ps |
| T196 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1203439698 |
|
|
Mar 12 03:44:32 PM PDT 24 |
Mar 12 03:54:52 PM PDT 24 |
4071772350 ps |
| T1099 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1466605589 |
|
|
Mar 12 03:44:45 PM PDT 24 |
Mar 12 03:59:01 PM PDT 24 |
5436831216 ps |
| T502 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1747921950 |
|
|
Mar 12 03:47:31 PM PDT 24 |
Mar 12 04:01:57 PM PDT 24 |
4565023000 ps |
| T1100 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3184949101 |
|
|
Mar 12 03:51:51 PM PDT 24 |
Mar 12 04:13:29 PM PDT 24 |
13819456434 ps |
| T1101 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.4212352722 |
|
|
Mar 12 03:53:41 PM PDT 24 |
Mar 12 04:00:27 PM PDT 24 |
3636001420 ps |
| T1102 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3210689234 |
|
|
Mar 12 04:06:42 PM PDT 24 |
Mar 12 04:10:58 PM PDT 24 |
3229294324 ps |
| T758 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3494116312 |
|
|
Mar 12 04:13:48 PM PDT 24 |
Mar 12 04:21:37 PM PDT 24 |
3188200764 ps |
| T1103 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2309537213 |
|
|
Mar 12 04:02:36 PM PDT 24 |
Mar 12 04:08:31 PM PDT 24 |
2771341586 ps |
| T1104 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1721811674 |
|
|
Mar 12 04:14:13 PM PDT 24 |
Mar 12 04:24:14 PM PDT 24 |
5215527840 ps |
| T1105 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.218716395 |
|
|
Mar 12 04:10:04 PM PDT 24 |
Mar 12 04:38:35 PM PDT 24 |
8851616200 ps |
| T1106 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2487299389 |
|
|
Mar 12 04:06:19 PM PDT 24 |
Mar 12 04:40:08 PM PDT 24 |
12895553580 ps |
| T1107 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2495062516 |
|
|
Mar 12 04:05:52 PM PDT 24 |
Mar 12 04:22:01 PM PDT 24 |
6168747004 ps |
| T1108 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1126440290 |
|
|
Mar 12 04:06:17 PM PDT 24 |
Mar 12 04:22:41 PM PDT 24 |
5373204890 ps |
| T1109 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4272374818 |
|
|
Mar 12 04:05:05 PM PDT 24 |
Mar 12 04:10:24 PM PDT 24 |
3382831048 ps |
| T1110 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2118893155 |
|
|
Mar 12 04:03:55 PM PDT 24 |
Mar 12 04:12:31 PM PDT 24 |
4724516216 ps |
| T1111 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2270218233 |
|
|
Mar 12 03:54:25 PM PDT 24 |
Mar 12 04:26:31 PM PDT 24 |
9184168108 ps |
| T8 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4196144335 |
|
|
Mar 12 03:49:31 PM PDT 24 |
Mar 12 03:54:51 PM PDT 24 |
3078574699 ps |
| T1112 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3539501724 |
|
|
Mar 12 04:08:41 PM PDT 24 |
Mar 12 04:15:16 PM PDT 24 |
3861250916 ps |
| T1113 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2697140235 |
|
|
Mar 12 04:09:05 PM PDT 24 |
Mar 12 04:14:33 PM PDT 24 |
3258937096 ps |
| T254 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1761256940 |
|
|
Mar 12 03:46:45 PM PDT 24 |
Mar 12 03:57:38 PM PDT 24 |
5042653514 ps |
| T45 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1414727976 |
|
|
Mar 12 03:45:28 PM PDT 24 |
Mar 12 03:49:10 PM PDT 24 |
3170223852 ps |
| T1114 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2493138134 |
|
|
Mar 12 04:02:31 PM PDT 24 |
Mar 12 04:07:09 PM PDT 24 |
2884232236 ps |
| T1115 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2127988324 |
|
|
Mar 12 03:51:21 PM PDT 24 |
Mar 12 04:25:07 PM PDT 24 |
8768935276 ps |
| T1116 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.451353505 |
|
|
Mar 12 04:04:03 PM PDT 24 |
Mar 12 04:09:47 PM PDT 24 |
3912214377 ps |
| T1117 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1479623869 |
|
|
Mar 12 04:09:03 PM PDT 24 |
Mar 12 04:16:13 PM PDT 24 |
3972099888 ps |
| T1118 |
/workspace/coverage/default/1.chip_sw_aes_idle.3370014467 |
|
|
Mar 12 03:50:22 PM PDT 24 |
Mar 12 03:54:20 PM PDT 24 |
2447255100 ps |
| T1119 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2890727205 |
|
|
Mar 12 04:07:01 PM PDT 24 |
Mar 12 04:16:12 PM PDT 24 |
4823254696 ps |
| T1120 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3976670161 |
|
|
Mar 12 03:47:41 PM PDT 24 |
Mar 12 03:50:50 PM PDT 24 |
2837072000 ps |
| T1121 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.165373080 |
|
|
Mar 12 04:00:48 PM PDT 24 |
Mar 12 04:14:17 PM PDT 24 |
4469717072 ps |
| T1122 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.987104702 |
|
|
Mar 12 03:43:40 PM PDT 24 |
Mar 12 03:46:30 PM PDT 24 |
3052209830 ps |
| T1123 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3450348224 |
|
|
Mar 12 03:49:26 PM PDT 24 |
Mar 12 03:53:56 PM PDT 24 |
3181396520 ps |
| T1124 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2197592653 |
|
|
Mar 12 03:51:10 PM PDT 24 |
Mar 12 04:23:59 PM PDT 24 |
8829083340 ps |
| T233 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.465651572 |
|
|
Mar 12 03:49:19 PM PDT 24 |
Mar 12 04:00:47 PM PDT 24 |
6128658656 ps |
| T705 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.546060418 |
|
|
Mar 12 04:10:41 PM PDT 24 |
Mar 12 04:18:36 PM PDT 24 |
4152055714 ps |
| T1125 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3124865706 |
|
|
Mar 12 03:58:19 PM PDT 24 |
Mar 12 04:08:05 PM PDT 24 |
5515732500 ps |
| T682 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.2136798959 |
|
|
Mar 12 03:44:26 PM PDT 24 |
Mar 12 03:49:16 PM PDT 24 |
3278310184 ps |
| T1126 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1963590165 |
|
|
Mar 12 03:58:02 PM PDT 24 |
Mar 12 04:22:10 PM PDT 24 |
8077296200 ps |
| T1127 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2883619954 |
|
|
Mar 12 03:58:19 PM PDT 24 |
Mar 12 04:14:44 PM PDT 24 |
5088729940 ps |
| T1128 |
/workspace/coverage/default/2.rom_keymgr_functest.344253789 |
|
|
Mar 12 04:06:49 PM PDT 24 |
Mar 12 04:16:21 PM PDT 24 |
4504412236 ps |
| T292 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2050711577 |
|
|
Mar 12 03:49:08 PM PDT 24 |
Mar 12 04:04:59 PM PDT 24 |
4333244850 ps |
| T1129 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1747958919 |
|
|
Mar 12 03:52:05 PM PDT 24 |
Mar 12 04:19:07 PM PDT 24 |
6775721542 ps |
| T311 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2232041386 |
|
|
Mar 12 03:53:53 PM PDT 24 |
Mar 12 04:06:50 PM PDT 24 |
5555567176 ps |
| T736 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.3044287040 |
|
|
Mar 12 04:08:09 PM PDT 24 |
Mar 12 04:16:50 PM PDT 24 |
4626453444 ps |
| T750 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.433810792 |
|
|
Mar 12 04:10:02 PM PDT 24 |
Mar 12 04:19:19 PM PDT 24 |
4393060896 ps |
| T299 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2481957015 |
|
|
Mar 12 03:51:57 PM PDT 24 |
Mar 12 04:08:18 PM PDT 24 |
5383794440 ps |
| T1130 |
/workspace/coverage/default/0.chip_tap_straps_prod.1236756562 |
|
|
Mar 12 03:45:12 PM PDT 24 |
Mar 12 03:47:42 PM PDT 24 |
2404606933 ps |
| T1131 |
/workspace/coverage/default/1.chip_sw_example_rom.4031174157 |
|
|
Mar 12 03:46:55 PM PDT 24 |
Mar 12 03:49:36 PM PDT 24 |
2936497880 ps |
| T696 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3968768482 |
|
|
Mar 12 04:12:23 PM PDT 24 |
Mar 12 04:17:49 PM PDT 24 |
4101739960 ps |
| T1132 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3673083843 |
|
|
Mar 12 03:58:27 PM PDT 24 |
Mar 12 04:15:51 PM PDT 24 |
6263222901 ps |
| T1133 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.3206237198 |
|
|
Mar 12 04:10:43 PM PDT 24 |
Mar 12 04:36:33 PM PDT 24 |
8166152333 ps |
| T1134 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.298877648 |
|
|
Mar 12 03:49:59 PM PDT 24 |
Mar 12 03:59:53 PM PDT 24 |
4324447488 ps |
| T1135 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2706485797 |
|
|
Mar 12 03:47:37 PM PDT 24 |
Mar 12 03:52:17 PM PDT 24 |
3444867850 ps |
| T1136 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2499011458 |
|
|
Mar 12 03:59:20 PM PDT 24 |
Mar 12 04:25:20 PM PDT 24 |
6697009456 ps |
| T1137 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3600647978 |
|
|
Mar 12 03:53:29 PM PDT 24 |
Mar 12 04:03:24 PM PDT 24 |
6997972306 ps |
| T1138 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1414167687 |
|
|
Mar 12 03:47:15 PM PDT 24 |
Mar 12 04:02:35 PM PDT 24 |
7428315016 ps |
| T1139 |
/workspace/coverage/default/0.rom_keymgr_functest.101633005 |
|
|
Mar 12 03:49:30 PM PDT 24 |
Mar 12 04:00:43 PM PDT 24 |
4840080988 ps |
| T1140 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1949848411 |
|
|
Mar 12 04:01:25 PM PDT 24 |
Mar 12 04:10:01 PM PDT 24 |
4713379428 ps |
| T753 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.324131774 |
|
|
Mar 12 04:08:32 PM PDT 24 |
Mar 12 04:17:33 PM PDT 24 |
4736335292 ps |
| T1141 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.7493122 |
|
|
Mar 12 04:06:32 PM PDT 24 |
Mar 12 04:13:13 PM PDT 24 |
3244299252 ps |
| T183 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4224437666 |
|
|
Mar 12 03:45:39 PM PDT 24 |
Mar 12 03:53:46 PM PDT 24 |
4439352876 ps |
| T1142 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1122205058 |
|
|
Mar 12 03:48:05 PM PDT 24 |
Mar 12 03:54:09 PM PDT 24 |
2952615528 ps |
| T1143 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1988116968 |
|
|
Mar 12 03:55:44 PM PDT 24 |
Mar 12 04:02:47 PM PDT 24 |
5326544472 ps |
| T695 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3457543658 |
|
|
Mar 12 04:09:16 PM PDT 24 |
Mar 12 04:19:14 PM PDT 24 |
4494234412 ps |
| T638 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.354433097 |
|
|
Mar 12 04:04:05 PM PDT 24 |
Mar 12 05:05:41 PM PDT 24 |
24667984053 ps |
| T1144 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.243256202 |
|
|
Mar 12 03:47:27 PM PDT 24 |
Mar 12 04:05:32 PM PDT 24 |
5452120202 ps |
| T1145 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3884109437 |
|
|
Mar 12 03:51:26 PM PDT 24 |
Mar 12 04:00:37 PM PDT 24 |
5563247192 ps |
| T1146 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.3980060654 |
|
|
Mar 12 03:47:09 PM PDT 24 |
Mar 12 03:55:29 PM PDT 24 |
4866874042 ps |
| T1147 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.195644300 |
|
|
Mar 12 03:53:53 PM PDT 24 |
Mar 12 04:09:26 PM PDT 24 |
6141076978 ps |
| T724 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.855024141 |
|
|
Mar 12 04:06:07 PM PDT 24 |
Mar 12 04:19:13 PM PDT 24 |
6263956120 ps |
| T650 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.1027727830 |
|
|
Mar 12 03:55:10 PM PDT 24 |
Mar 12 03:56:58 PM PDT 24 |
2322908368 ps |
| T199 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3103765470 |
|
|
Mar 12 03:47:18 PM PDT 24 |
Mar 12 04:51:33 PM PDT 24 |
15896197610 ps |
| T1148 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.2828467721 |
|
|
Mar 12 03:46:37 PM PDT 24 |
Mar 12 03:49:42 PM PDT 24 |
3244931308 ps |
| T1149 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3490332904 |
|
|
Mar 12 03:52:29 PM PDT 24 |
Mar 12 04:00:51 PM PDT 24 |
4480656616 ps |
| T1150 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3836911825 |
|
|
Mar 12 03:50:50 PM PDT 24 |
Mar 12 03:55:28 PM PDT 24 |
2941848916 ps |
| T1151 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.460342221 |
|
|
Mar 12 04:02:29 PM PDT 24 |
Mar 12 04:24:00 PM PDT 24 |
12878367026 ps |
| T125 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1915417858 |
|
|
Mar 12 03:44:29 PM PDT 24 |
Mar 12 03:52:20 PM PDT 24 |
4430652024 ps |
| T704 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1834334972 |
|
|
Mar 12 04:13:17 PM PDT 24 |
Mar 12 04:22:24 PM PDT 24 |
4821561396 ps |
| T1152 |
/workspace/coverage/default/0.chip_sw_aes_entropy.3041334081 |
|
|
Mar 12 03:46:24 PM PDT 24 |
Mar 12 03:51:41 PM PDT 24 |
2839632642 ps |
| T153 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2460052823 |
|
|
Mar 12 03:49:29 PM PDT 24 |
Mar 12 03:58:36 PM PDT 24 |
5916270296 ps |
| T46 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1815286334 |
|
|
Mar 12 03:48:35 PM PDT 24 |
Mar 12 03:53:40 PM PDT 24 |
3694801812 ps |
| T1153 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2696642191 |
|
|
Mar 12 03:50:18 PM PDT 24 |
Mar 12 04:02:06 PM PDT 24 |
3916113736 ps |
| T1154 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.656727645 |
|
|
Mar 12 03:46:41 PM PDT 24 |
Mar 12 04:11:44 PM PDT 24 |
10196383488 ps |
| T1155 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3540675445 |
|
|
Mar 12 03:46:38 PM PDT 24 |
Mar 12 04:06:05 PM PDT 24 |
7814692490 ps |
| T1156 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1541196142 |
|
|
Mar 12 03:49:38 PM PDT 24 |
Mar 12 03:54:05 PM PDT 24 |
2774525888 ps |
| T646 |
/workspace/coverage/default/1.chip_tap_straps_dev.901051517 |
|
|
Mar 12 03:52:41 PM PDT 24 |
Mar 12 04:17:27 PM PDT 24 |
13226111548 ps |
| T223 |
/workspace/coverage/default/0.chip_jtag_mem_access.2472000264 |
|
|
Mar 12 03:37:26 PM PDT 24 |
Mar 12 04:02:32 PM PDT 24 |
13832885944 ps |
| T1157 |
/workspace/coverage/default/1.chip_sw_example_concurrency.830191493 |
|
|
Mar 12 03:50:17 PM PDT 24 |
Mar 12 03:54:46 PM PDT 24 |
3011613960 ps |
| T272 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1461585406 |
|
|
Mar 12 04:13:54 PM PDT 24 |
Mar 12 04:24:22 PM PDT 24 |
6539744280 ps |
| T1158 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.2273121555 |
|
|
Mar 12 03:59:23 PM PDT 24 |
Mar 12 04:45:12 PM PDT 24 |
24271337804 ps |
| T1159 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1836157198 |
|
|
Mar 12 03:45:30 PM PDT 24 |
Mar 12 03:59:02 PM PDT 24 |
4010145204 ps |
| T1160 |
/workspace/coverage/default/4.chip_tap_straps_prod.3040180541 |
|
|
Mar 12 04:07:02 PM PDT 24 |
Mar 12 04:29:22 PM PDT 24 |
11786094195 ps |
| T775 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.4058798262 |
|
|
Mar 12 03:56:44 PM PDT 24 |
Mar 12 04:09:08 PM PDT 24 |
5186018640 ps |
| T1161 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.791804869 |
|
|
Mar 12 03:51:00 PM PDT 24 |
Mar 12 04:55:21 PM PDT 24 |
19133740476 ps |
| T1162 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2362732000 |
|
|
Mar 12 03:45:51 PM PDT 24 |
Mar 12 03:51:36 PM PDT 24 |
3592659870 ps |