| T158 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1355738409 |
|
|
Mar 12 03:50:48 PM PDT 24 |
Mar 12 03:58:55 PM PDT 24 |
4899410936 ps |
| T1163 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.714833776 |
|
|
Mar 12 04:01:20 PM PDT 24 |
Mar 12 04:06:48 PM PDT 24 |
2663149126 ps |
| T733 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3424042917 |
|
|
Mar 12 04:13:22 PM PDT 24 |
Mar 12 04:21:34 PM PDT 24 |
5625864290 ps |
| T718 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1503387797 |
|
|
Mar 12 04:11:05 PM PDT 24 |
Mar 12 04:17:32 PM PDT 24 |
3881521344 ps |
| T1164 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4208972158 |
|
|
Mar 12 03:59:03 PM PDT 24 |
Mar 12 04:05:48 PM PDT 24 |
6107319400 ps |
| T1165 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3152107674 |
|
|
Mar 12 03:53:28 PM PDT 24 |
Mar 12 04:10:46 PM PDT 24 |
5393143910 ps |
| T643 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.418071432 |
|
|
Mar 12 03:52:45 PM PDT 24 |
Mar 12 04:04:01 PM PDT 24 |
4654071162 ps |
| T1166 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.813764331 |
|
|
Mar 12 03:45:35 PM PDT 24 |
Mar 12 03:58:05 PM PDT 24 |
4350639288 ps |
| T1167 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4250427365 |
|
|
Mar 12 04:13:03 PM PDT 24 |
Mar 12 04:19:32 PM PDT 24 |
4060783200 ps |
| T1168 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.1664610470 |
|
|
Mar 12 03:48:28 PM PDT 24 |
Mar 12 03:52:10 PM PDT 24 |
2728037112 ps |
| T651 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3306420087 |
|
|
Mar 12 03:44:23 PM PDT 24 |
Mar 12 03:48:54 PM PDT 24 |
3431981777 ps |
| T778 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1403276851 |
|
|
Mar 12 04:13:54 PM PDT 24 |
Mar 12 04:24:07 PM PDT 24 |
5771910306 ps |
| T234 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1595586838 |
|
|
Mar 12 04:08:08 PM PDT 24 |
Mar 12 04:18:42 PM PDT 24 |
5581109884 ps |
| T1169 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2525987110 |
|
|
Mar 12 04:12:12 PM PDT 24 |
Mar 12 04:18:14 PM PDT 24 |
3645697690 ps |
| T227 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2000378019 |
|
|
Mar 12 04:02:57 PM PDT 24 |
Mar 12 04:11:21 PM PDT 24 |
4696411400 ps |
| T156 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.104212788 |
|
|
Mar 12 04:08:14 PM PDT 24 |
Mar 12 04:23:26 PM PDT 24 |
6072974440 ps |
| T1170 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3383983308 |
|
|
Mar 12 04:01:00 PM PDT 24 |
Mar 12 04:08:24 PM PDT 24 |
4331984986 ps |
| T1171 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.662350349 |
|
|
Mar 12 03:46:54 PM PDT 24 |
Mar 12 04:10:34 PM PDT 24 |
8971181424 ps |
| T1172 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3917431082 |
|
|
Mar 12 03:46:01 PM PDT 24 |
Mar 12 03:48:12 PM PDT 24 |
2586558444 ps |
| T1173 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2565833268 |
|
|
Mar 12 04:13:45 PM PDT 24 |
Mar 12 04:23:24 PM PDT 24 |
4569844872 ps |
| T1174 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.166033356 |
|
|
Mar 12 04:04:45 PM PDT 24 |
Mar 12 04:09:12 PM PDT 24 |
2746265056 ps |
| T698 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3234080327 |
|
|
Mar 12 04:13:55 PM PDT 24 |
Mar 12 04:19:44 PM PDT 24 |
3267853848 ps |
| T1175 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.440414531 |
|
|
Mar 12 03:56:57 PM PDT 24 |
Mar 12 04:01:12 PM PDT 24 |
2816944036 ps |
| T327 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1145421986 |
|
|
Mar 12 04:13:46 PM PDT 24 |
Mar 12 04:21:40 PM PDT 24 |
4906102272 ps |
| T1176 |
/workspace/coverage/default/0.chip_sw_example_concurrency.1947513415 |
|
|
Mar 12 03:46:29 PM PDT 24 |
Mar 12 03:49:37 PM PDT 24 |
2896671736 ps |
| T9 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.304346763 |
|
|
Mar 12 03:43:10 PM PDT 24 |
Mar 12 03:49:06 PM PDT 24 |
2621353111 ps |
| T1177 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.3070922834 |
|
|
Mar 12 03:59:59 PM PDT 24 |
Mar 12 04:38:06 PM PDT 24 |
9136960078 ps |
| T1178 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3440493684 |
|
|
Mar 12 04:09:28 PM PDT 24 |
Mar 12 04:18:23 PM PDT 24 |
4325989488 ps |
| T1179 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2741563797 |
|
|
Mar 12 03:48:22 PM PDT 24 |
Mar 12 03:56:33 PM PDT 24 |
3659805894 ps |
| T200 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3453747603 |
|
|
Mar 12 03:50:54 PM PDT 24 |
Mar 12 04:43:46 PM PDT 24 |
12211354600 ps |
| T1180 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.4126376708 |
|
|
Mar 12 03:50:52 PM PDT 24 |
Mar 12 03:59:41 PM PDT 24 |
5702210794 ps |
| T1181 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2014108526 |
|
|
Mar 12 04:07:18 PM PDT 24 |
Mar 12 04:10:43 PM PDT 24 |
2727354703 ps |
| T1182 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.3120762782 |
|
|
Mar 12 03:56:01 PM PDT 24 |
Mar 12 04:02:19 PM PDT 24 |
3292547288 ps |
| T294 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2932120339 |
|
|
Mar 12 03:47:36 PM PDT 24 |
Mar 12 04:12:02 PM PDT 24 |
5981457436 ps |
| T317 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1149196418 |
|
|
Mar 12 03:59:36 PM PDT 24 |
Mar 12 04:10:14 PM PDT 24 |
19346611668 ps |
| T729 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2433561501 |
|
|
Mar 12 04:14:23 PM PDT 24 |
Mar 12 04:24:21 PM PDT 24 |
5045286816 ps |
| T1183 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1086782345 |
|
|
Mar 12 04:11:11 PM PDT 24 |
Mar 12 04:17:42 PM PDT 24 |
4049063256 ps |
| T1184 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.4076804646 |
|
|
Mar 12 03:46:32 PM PDT 24 |
Mar 12 04:05:19 PM PDT 24 |
4978646088 ps |
| T751 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.991879487 |
|
|
Mar 12 04:12:09 PM PDT 24 |
Mar 12 04:22:03 PM PDT 24 |
5253794342 ps |
| T1185 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.233087771 |
|
|
Mar 12 03:45:31 PM PDT 24 |
Mar 12 04:08:27 PM PDT 24 |
6939982760 ps |
| T1186 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2714568156 |
|
|
Mar 12 03:44:21 PM PDT 24 |
Mar 12 04:03:15 PM PDT 24 |
5524283862 ps |
| T1187 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.4240206945 |
|
|
Mar 12 04:07:08 PM PDT 24 |
Mar 12 04:13:50 PM PDT 24 |
5739195881 ps |
| T1188 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.3593486586 |
|
|
Mar 12 03:58:34 PM PDT 24 |
Mar 12 04:26:59 PM PDT 24 |
8667177132 ps |
| T1189 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.1215258213 |
|
|
Mar 12 04:05:39 PM PDT 24 |
Mar 12 04:07:24 PM PDT 24 |
2025183203 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1307412541 |
|
|
Mar 12 04:07:27 PM PDT 24 |
Mar 12 04:15:00 PM PDT 24 |
4838297420 ps |
| T235 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3720485955 |
|
|
Mar 12 04:11:41 PM PDT 24 |
Mar 12 04:21:42 PM PDT 24 |
5743326860 ps |
| T1191 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4252460372 |
|
|
Mar 12 04:07:20 PM PDT 24 |
Mar 12 04:14:09 PM PDT 24 |
5197525670 ps |
| T1192 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.94912775 |
|
|
Mar 12 04:05:45 PM PDT 24 |
Mar 12 04:19:53 PM PDT 24 |
5294500320 ps |
| T1193 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.4239745811 |
|
|
Mar 12 04:05:02 PM PDT 24 |
Mar 12 04:09:19 PM PDT 24 |
3067986428 ps |
| T1194 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3225462591 |
|
|
Mar 12 04:10:35 PM PDT 24 |
Mar 12 04:16:34 PM PDT 24 |
3162954204 ps |
| T1195 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1450896047 |
|
|
Mar 12 03:46:40 PM PDT 24 |
Mar 12 04:07:01 PM PDT 24 |
5279917600 ps |
| T639 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3993047808 |
|
|
Mar 12 03:54:06 PM PDT 24 |
Mar 12 04:53:22 PM PDT 24 |
24915134764 ps |
| T720 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1331902141 |
|
|
Mar 12 04:09:43 PM PDT 24 |
Mar 12 04:15:41 PM PDT 24 |
4146421618 ps |
| T1196 |
/workspace/coverage/default/1.rom_e2e_smoke.2519352420 |
|
|
Mar 12 03:58:15 PM PDT 24 |
Mar 12 04:32:40 PM PDT 24 |
8689957680 ps |
| T362 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1258005213 |
|
|
Mar 12 03:45:36 PM PDT 24 |
Mar 12 03:49:56 PM PDT 24 |
2933159544 ps |
| T760 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.243066710 |
|
|
Mar 12 04:10:28 PM PDT 24 |
Mar 12 04:16:55 PM PDT 24 |
3764892880 ps |
| T1197 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3778080366 |
|
|
Mar 12 03:49:33 PM PDT 24 |
Mar 12 03:59:32 PM PDT 24 |
4910074332 ps |
| T300 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2814005 |
|
|
Mar 12 03:58:33 PM PDT 24 |
Mar 12 04:14:35 PM PDT 24 |
5509131618 ps |
| T407 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1996470299 |
|
|
Mar 12 03:50:38 PM PDT 24 |
Mar 12 04:00:58 PM PDT 24 |
9816575672 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3240585628 |
|
|
Mar 12 03:53:00 PM PDT 24 |
Mar 12 04:35:47 PM PDT 24 |
26033560583 ps |
| T1199 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1896571156 |
|
|
Mar 12 03:48:35 PM PDT 24 |
Mar 12 03:54:05 PM PDT 24 |
3301206266 ps |
| T318 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3413721582 |
|
|
Mar 12 03:49:53 PM PDT 24 |
Mar 12 03:55:16 PM PDT 24 |
18172226530 ps |
| T1200 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3154123135 |
|
|
Mar 12 04:00:38 PM PDT 24 |
Mar 12 04:07:37 PM PDT 24 |
7097996864 ps |
| T167 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.42315038 |
|
|
Mar 12 03:46:29 PM PDT 24 |
Mar 12 04:35:03 PM PDT 24 |
12019361228 ps |
| T361 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3573710300 |
|
|
Mar 12 03:50:19 PM PDT 24 |
Mar 12 03:55:51 PM PDT 24 |
3168066734 ps |
| T1201 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3786829098 |
|
|
Mar 12 03:44:42 PM PDT 24 |
Mar 12 05:04:36 PM PDT 24 |
49089458432 ps |
| T1202 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3737797900 |
|
|
Mar 12 03:45:31 PM PDT 24 |
Mar 12 03:58:46 PM PDT 24 |
5248030936 ps |
| T761 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3532089519 |
|
|
Mar 12 04:11:29 PM PDT 24 |
Mar 12 04:17:56 PM PDT 24 |
3372412848 ps |
| T1203 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.2914423725 |
|
|
Mar 12 03:45:24 PM PDT 24 |
Mar 12 03:50:11 PM PDT 24 |
3519889930 ps |
| T1204 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.134908652 |
|
|
Mar 12 03:46:25 PM PDT 24 |
Mar 12 03:57:27 PM PDT 24 |
19116419324 ps |
| T60 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.391279730 |
|
|
Mar 12 04:06:17 PM PDT 24 |
Mar 12 04:09:54 PM PDT 24 |
3187788397 ps |
| T1205 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2792882708 |
|
|
Mar 12 03:46:15 PM PDT 24 |
Mar 12 03:51:40 PM PDT 24 |
3082215226 ps |
| T1206 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2062309006 |
|
|
Mar 12 03:57:09 PM PDT 24 |
Mar 12 07:41:47 PM PDT 24 |
79174159079 ps |
| T67 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1111749399 |
|
|
Mar 12 03:44:12 PM PDT 24 |
Mar 12 05:34:40 PM PDT 24 |
31424360608 ps |
| T1207 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3205342814 |
|
|
Mar 12 03:46:07 PM PDT 24 |
Mar 12 03:57:27 PM PDT 24 |
3810056568 ps |
| T1208 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1533046983 |
|
|
Mar 12 04:15:23 PM PDT 24 |
Mar 12 04:26:56 PM PDT 24 |
5338265448 ps |
| T1209 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3404722921 |
|
|
Mar 12 03:48:59 PM PDT 24 |
Mar 12 03:52:53 PM PDT 24 |
2804840938 ps |
| T1210 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3884377603 |
|
|
Mar 12 03:53:27 PM PDT 24 |
Mar 12 04:26:14 PM PDT 24 |
8756362354 ps |
| T755 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1829648740 |
|
|
Mar 12 04:16:01 PM PDT 24 |
Mar 12 04:23:04 PM PDT 24 |
4108151136 ps |
| T699 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.4208809398 |
|
|
Mar 12 04:10:13 PM PDT 24 |
Mar 12 04:14:46 PM PDT 24 |
3618495900 ps |
| T1211 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2589099393 |
|
|
Mar 12 03:56:07 PM PDT 24 |
Mar 12 03:59:16 PM PDT 24 |
2919219048 ps |
| T1212 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.280516430 |
|
|
Mar 12 03:46:40 PM PDT 24 |
Mar 12 04:05:06 PM PDT 24 |
5251061408 ps |
| T1213 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3593328686 |
|
|
Mar 12 03:51:55 PM PDT 24 |
Mar 12 04:05:46 PM PDT 24 |
7886090877 ps |
| T1214 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.3495727884 |
|
|
Mar 12 03:59:36 PM PDT 24 |
Mar 12 04:31:49 PM PDT 24 |
8362801964 ps |
| T241 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.397523249 |
|
|
Mar 12 04:07:50 PM PDT 24 |
Mar 12 04:22:49 PM PDT 24 |
5367687600 ps |
| T1215 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2192510160 |
|
|
Mar 12 03:57:07 PM PDT 24 |
Mar 12 04:02:21 PM PDT 24 |
5733585752 ps |
| T731 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.4194047119 |
|
|
Mar 12 04:12:00 PM PDT 24 |
Mar 12 04:18:44 PM PDT 24 |
3894279976 ps |
| T1216 |
/workspace/coverage/default/1.chip_tap_straps_prod.3223029940 |
|
|
Mar 12 03:52:50 PM PDT 24 |
Mar 12 04:17:32 PM PDT 24 |
13531668018 ps |
| T1217 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.191558831 |
|
|
Mar 12 04:05:38 PM PDT 24 |
Mar 12 04:09:45 PM PDT 24 |
2375656360 ps |
| T1218 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2024729088 |
|
|
Mar 12 04:01:13 PM PDT 24 |
Mar 12 04:03:05 PM PDT 24 |
2292362357 ps |
| T766 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2595184633 |
|
|
Mar 12 04:09:28 PM PDT 24 |
Mar 12 04:15:15 PM PDT 24 |
3739526540 ps |
| T1219 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2370207495 |
|
|
Mar 12 04:13:51 PM PDT 24 |
Mar 12 04:18:35 PM PDT 24 |
3605097544 ps |
| T157 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1552419315 |
|
|
Mar 12 04:02:23 PM PDT 24 |
Mar 12 04:23:26 PM PDT 24 |
7566245600 ps |
| T120 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.95508301 |
|
|
Mar 12 04:00:53 PM PDT 24 |
Mar 12 04:04:48 PM PDT 24 |
2652662015 ps |
| T737 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1490544650 |
|
|
Mar 12 04:12:11 PM PDT 24 |
Mar 12 04:19:43 PM PDT 24 |
4346913912 ps |
| T257 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1569999401 |
|
|
Mar 12 04:13:39 PM PDT 24 |
Mar 12 04:24:40 PM PDT 24 |
6452204910 ps |
| T1220 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.2006388539 |
|
|
Mar 12 03:52:12 PM PDT 24 |
Mar 12 04:33:58 PM PDT 24 |
8628931368 ps |
| T1221 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1014977112 |
|
|
Mar 12 04:13:49 PM PDT 24 |
Mar 12 04:21:26 PM PDT 24 |
4484157812 ps |
| T721 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.4130062862 |
|
|
Mar 12 04:10:17 PM PDT 24 |
Mar 12 04:21:54 PM PDT 24 |
5343368184 ps |
| T644 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.661828470 |
|
|
Mar 12 03:45:41 PM PDT 24 |
Mar 12 03:55:24 PM PDT 24 |
5539871070 ps |
| T1222 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.3201791944 |
|
|
Mar 12 03:54:31 PM PDT 24 |
Mar 12 04:07:11 PM PDT 24 |
4494501288 ps |
| T302 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.2453968208 |
|
|
Mar 12 04:03:52 PM PDT 24 |
Mar 12 04:16:02 PM PDT 24 |
4599311020 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2857713618 |
|
|
Mar 12 03:44:41 PM PDT 24 |
Mar 12 04:08:20 PM PDT 24 |
6987450656 ps |
| T1224 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2447216745 |
|
|
Mar 12 03:52:39 PM PDT 24 |
Mar 12 04:25:25 PM PDT 24 |
8775418343 ps |
| T1225 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2679244554 |
|
|
Mar 12 03:52:20 PM PDT 24 |
Mar 12 04:36:12 PM PDT 24 |
10023504240 ps |
| T1226 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3369894967 |
|
|
Mar 12 03:46:32 PM PDT 24 |
Mar 12 03:51:16 PM PDT 24 |
3186250744 ps |
| T1227 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3241666420 |
|
|
Mar 12 03:59:15 PM PDT 24 |
Mar 12 04:29:40 PM PDT 24 |
11250594011 ps |
| T735 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.961192270 |
|
|
Mar 12 04:08:17 PM PDT 24 |
Mar 12 04:21:40 PM PDT 24 |
5609422924 ps |
| T197 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1000327618 |
|
|
Mar 12 03:50:22 PM PDT 24 |
Mar 12 04:00:40 PM PDT 24 |
5354430520 ps |
| T1228 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1601732052 |
|
|
Mar 12 04:13:01 PM PDT 24 |
Mar 12 04:21:37 PM PDT 24 |
5257355144 ps |
| T1229 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.102474234 |
|
|
Mar 12 03:46:08 PM PDT 24 |
Mar 12 04:57:43 PM PDT 24 |
23482496943 ps |
| T615 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.102343910 |
|
|
Mar 12 03:52:31 PM PDT 24 |
Mar 12 04:04:59 PM PDT 24 |
4500181243 ps |
| T1230 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.249141967 |
|
|
Mar 12 03:47:02 PM PDT 24 |
Mar 12 03:49:00 PM PDT 24 |
3004664640 ps |
| T722 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718536714 |
|
|
Mar 12 04:12:34 PM PDT 24 |
Mar 12 04:20:04 PM PDT 24 |
4001653984 ps |
| T1231 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4155150248 |
|
|
Mar 12 03:47:08 PM PDT 24 |
Mar 12 04:05:30 PM PDT 24 |
10891615210 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.897680752 |
|
|
Mar 12 04:03:18 PM PDT 24 |
Mar 12 04:10:49 PM PDT 24 |
4343830816 ps |
| T1233 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2176494694 |
|
|
Mar 12 04:06:15 PM PDT 24 |
Mar 12 04:11:31 PM PDT 24 |
2926693410 ps |
| T1234 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.3894932510 |
|
|
Mar 12 04:10:30 PM PDT 24 |
Mar 12 04:50:57 PM PDT 24 |
20564043478 ps |
| T1235 |
/workspace/coverage/default/2.rom_e2e_smoke.3416147806 |
|
|
Mar 12 04:04:57 PM PDT 24 |
Mar 12 04:34:32 PM PDT 24 |
9023003390 ps |
| T295 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.830306619 |
|
|
Mar 12 04:00:59 PM PDT 24 |
Mar 12 04:23:05 PM PDT 24 |
6816797184 ps |
| T1236 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2787142562 |
|
|
Mar 12 04:03:52 PM PDT 24 |
Mar 12 04:28:31 PM PDT 24 |
12072962660 ps |
| T1237 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.878545835 |
|
|
Mar 12 04:01:59 PM PDT 24 |
Mar 12 04:13:07 PM PDT 24 |
4213199560 ps |
| T1238 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.272271523 |
|
|
Mar 12 04:10:45 PM PDT 24 |
Mar 12 04:16:52 PM PDT 24 |
2948603240 ps |
| T1239 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3867644477 |
|
|
Mar 12 03:52:30 PM PDT 24 |
Mar 12 04:00:44 PM PDT 24 |
3380500460 ps |
| T1240 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1314782307 |
|
|
Mar 12 03:49:50 PM PDT 24 |
Mar 12 04:04:03 PM PDT 24 |
4775551476 ps |
| T1241 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3616634714 |
|
|
Mar 12 03:51:20 PM PDT 24 |
Mar 12 03:58:46 PM PDT 24 |
4929628950 ps |
| T1242 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2062792451 |
|
|
Mar 12 03:51:54 PM PDT 24 |
Mar 12 04:28:08 PM PDT 24 |
9069437076 ps |
| T1243 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2725745797 |
|
|
Mar 12 04:13:43 PM PDT 24 |
Mar 12 04:23:26 PM PDT 24 |
5459233384 ps |
| T1244 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3206827053 |
|
|
Mar 12 03:51:56 PM PDT 24 |
Mar 12 03:56:06 PM PDT 24 |
3043976219 ps |
| T68 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1349119653 |
|
|
Mar 12 03:45:25 PM PDT 24 |
Mar 12 03:56:08 PM PDT 24 |
3546135272 ps |
| T1245 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3462560135 |
|
|
Mar 12 03:50:58 PM PDT 24 |
Mar 12 03:58:03 PM PDT 24 |
5901122048 ps |
| T1246 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1427073497 |
|
|
Mar 12 04:07:20 PM PDT 24 |
Mar 12 04:15:00 PM PDT 24 |
5639088154 ps |
| T1247 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2086784766 |
|
|
Mar 12 03:53:20 PM PDT 24 |
Mar 12 04:37:20 PM PDT 24 |
12158731496 ps |
| T1248 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1932747917 |
|
|
Mar 12 04:07:11 PM PDT 24 |
Mar 12 04:46:29 PM PDT 24 |
23928962303 ps |
| T1249 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.4289637791 |
|
|
Mar 12 04:08:29 PM PDT 24 |
Mar 12 04:24:45 PM PDT 24 |
5729753736 ps |
| T1250 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1515678791 |
|
|
Mar 12 04:06:30 PM PDT 24 |
Mar 12 04:09:37 PM PDT 24 |
2863722480 ps |
| T1251 |
/workspace/coverage/default/1.rom_keymgr_functest.3792760227 |
|
|
Mar 12 03:55:45 PM PDT 24 |
Mar 12 04:07:11 PM PDT 24 |
3956199512 ps |
| T1252 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.91030972 |
|
|
Mar 12 03:49:41 PM PDT 24 |
Mar 12 03:51:58 PM PDT 24 |
2786649054 ps |
| T338 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.120934136 |
|
|
Mar 12 04:08:34 PM PDT 24 |
Mar 12 04:21:09 PM PDT 24 |
6071770540 ps |
| T1253 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3728471457 |
|
|
Mar 12 03:58:48 PM PDT 24 |
Mar 12 04:08:41 PM PDT 24 |
4903696944 ps |
| T1254 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.996043327 |
|
|
Mar 12 03:47:52 PM PDT 24 |
Mar 12 03:55:10 PM PDT 24 |
4895796600 ps |
| T1255 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2384593699 |
|
|
Mar 12 03:52:23 PM PDT 24 |
Mar 12 03:59:39 PM PDT 24 |
4809502390 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.694677505 |
|
|
Mar 12 03:48:22 PM PDT 24 |
Mar 12 04:01:39 PM PDT 24 |
5107533820 ps |
| T1257 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1470784870 |
|
|
Mar 12 03:52:22 PM PDT 24 |
Mar 12 04:04:31 PM PDT 24 |
5031806948 ps |
| T1258 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3963917687 |
|
|
Mar 12 04:12:54 PM PDT 24 |
Mar 12 04:19:19 PM PDT 24 |
3666339220 ps |
| T1259 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2065572920 |
|
|
Mar 12 03:47:23 PM PDT 24 |
Mar 12 03:57:10 PM PDT 24 |
7612951470 ps |
| T1260 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2563300797 |
|
|
Mar 12 04:03:20 PM PDT 24 |
Mar 12 04:13:41 PM PDT 24 |
4514420096 ps |
| T1261 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3164095272 |
|
|
Mar 12 03:55:05 PM PDT 24 |
Mar 12 04:12:33 PM PDT 24 |
5131631968 ps |
| T768 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1108886541 |
|
|
Mar 12 04:11:55 PM PDT 24 |
Mar 12 04:24:34 PM PDT 24 |
6790613722 ps |
| T1262 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.345330406 |
|
|
Mar 12 03:52:21 PM PDT 24 |
Mar 12 04:16:34 PM PDT 24 |
6512122676 ps |
| T1263 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3664348580 |
|
|
Mar 12 03:49:25 PM PDT 24 |
Mar 12 03:56:40 PM PDT 24 |
4087234370 ps |
| T1264 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.959008707 |
|
|
Mar 12 03:57:05 PM PDT 24 |
Mar 12 04:17:36 PM PDT 24 |
5422884264 ps |
| T1265 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.3643891048 |
|
|
Mar 12 04:05:13 PM PDT 24 |
Mar 12 04:33:29 PM PDT 24 |
8551602056 ps |
| T618 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1333035058 |
|
|
Mar 12 03:46:52 PM PDT 24 |
Mar 12 03:55:33 PM PDT 24 |
4602363136 ps |
| T1266 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1173520180 |
|
|
Mar 12 03:59:03 PM PDT 24 |
Mar 12 04:22:06 PM PDT 24 |
10096620448 ps |
| T706 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1897596246 |
|
|
Mar 12 04:10:31 PM PDT 24 |
Mar 12 04:19:05 PM PDT 24 |
5814541640 ps |
| T1267 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.2800160600 |
|
|
Mar 12 04:02:39 PM PDT 24 |
Mar 12 04:18:55 PM PDT 24 |
6929896810 ps |
| T1268 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.659420307 |
|
|
Mar 12 03:47:13 PM PDT 24 |
Mar 12 03:56:08 PM PDT 24 |
8866664321 ps |
| T1269 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.2258508114 |
|
|
Mar 12 03:44:27 PM PDT 24 |
Mar 12 04:18:52 PM PDT 24 |
9093150636 ps |
| T1270 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1072047577 |
|
|
Mar 12 03:52:51 PM PDT 24 |
Mar 12 04:01:09 PM PDT 24 |
5804274280 ps |
| T763 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2277819118 |
|
|
Mar 12 04:12:51 PM PDT 24 |
Mar 12 04:23:30 PM PDT 24 |
5232723104 ps |
| T1271 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2398923015 |
|
|
Mar 12 04:08:42 PM PDT 24 |
Mar 12 04:42:52 PM PDT 24 |
12798076504 ps |
| T1272 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1123987367 |
|
|
Mar 12 03:48:27 PM PDT 24 |
Mar 12 04:21:48 PM PDT 24 |
9858351387 ps |
| T1273 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.517581003 |
|
|
Mar 12 04:13:39 PM PDT 24 |
Mar 12 04:19:42 PM PDT 24 |
5345272576 ps |
| T1274 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3053462207 |
|
|
Mar 12 03:53:43 PM PDT 24 |
Mar 12 04:35:33 PM PDT 24 |
8481012440 ps |
| T679 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.844158559 |
|
|
Mar 12 04:04:04 PM PDT 24 |
Mar 12 04:15:52 PM PDT 24 |
5193948572 ps |
| T1275 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.332789791 |
|
|
Mar 12 04:07:18 PM PDT 24 |
Mar 12 04:11:33 PM PDT 24 |
2636633106 ps |
| T1276 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2390130403 |
|
|
Mar 12 03:52:12 PM PDT 24 |
Mar 12 03:55:55 PM PDT 24 |
2655139644 ps |
| T652 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.934068898 |
|
|
Mar 12 04:14:30 PM PDT 24 |
Mar 12 04:23:14 PM PDT 24 |
4211977728 ps |
| T84 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.902597816 |
|
|
Mar 12 04:11:30 PM PDT 24 |
Mar 12 04:21:10 PM PDT 24 |
4555045944 ps |
| T1277 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.936991119 |
|
|
Mar 12 03:58:43 PM PDT 24 |
Mar 12 04:10:16 PM PDT 24 |
12683975228 ps |
| T395 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.542794525 |
|
|
Mar 12 03:46:55 PM PDT 24 |
Mar 12 03:53:35 PM PDT 24 |
6949904730 ps |
| T685 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.642199871 |
|
|
Mar 12 03:48:27 PM PDT 24 |
Mar 12 04:21:52 PM PDT 24 |
22601903190 ps |
| T1278 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1458681964 |
|
|
Mar 12 04:10:01 PM PDT 24 |
Mar 12 04:21:39 PM PDT 24 |
6224698050 ps |
| T1279 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1710125476 |
|
|
Mar 12 03:50:29 PM PDT 24 |
Mar 12 03:56:27 PM PDT 24 |
2942958659 ps |
| T779 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3297326618 |
|
|
Mar 12 04:08:46 PM PDT 24 |
Mar 12 04:15:11 PM PDT 24 |
3332272348 ps |
| T1280 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3122018660 |
|
|
Mar 12 04:13:56 PM PDT 24 |
Mar 12 04:18:59 PM PDT 24 |
4130701848 ps |
| T708 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2623333897 |
|
|
Mar 12 04:14:45 PM PDT 24 |
Mar 12 04:26:41 PM PDT 24 |
5099099640 ps |
| T396 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1297829550 |
|
|
Mar 12 04:03:33 PM PDT 24 |
Mar 12 04:11:01 PM PDT 24 |
7654253244 ps |
| T339 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1192095834 |
|
|
Mar 12 04:11:29 PM PDT 24 |
Mar 12 04:19:41 PM PDT 24 |
3607917520 ps |
| T725 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2444701645 |
|
|
Mar 12 04:10:44 PM PDT 24 |
Mar 12 04:18:25 PM PDT 24 |
3829517358 ps |
| T1281 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1999612667 |
|
|
Mar 12 04:01:15 PM PDT 24 |
Mar 12 04:13:34 PM PDT 24 |
7332236598 ps |
| T1282 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2702351338 |
|
|
Mar 12 04:00:12 PM PDT 24 |
Mar 12 04:18:36 PM PDT 24 |
5682664280 ps |
| T1283 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1870032340 |
|
|
Mar 12 03:47:05 PM PDT 24 |
Mar 12 03:58:29 PM PDT 24 |
3442595962 ps |
| T692 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.1003240975 |
|
|
Mar 12 04:10:57 PM PDT 24 |
Mar 12 04:21:16 PM PDT 24 |
4468781430 ps |
| T776 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.18623306 |
|
|
Mar 12 04:13:41 PM PDT 24 |
Mar 12 04:21:39 PM PDT 24 |
5989476764 ps |
| T1284 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1166897704 |
|
|
Mar 12 04:04:12 PM PDT 24 |
Mar 12 04:16:44 PM PDT 24 |
4697620155 ps |
| T1285 |
/workspace/coverage/default/0.chip_sw_flash_init.504140162 |
|
|
Mar 12 03:43:37 PM PDT 24 |
Mar 12 04:16:07 PM PDT 24 |
23771173378 ps |
| T1286 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1597414947 |
|
|
Mar 12 03:50:43 PM PDT 24 |
Mar 12 04:10:49 PM PDT 24 |
11847370417 ps |
| T1287 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2297357253 |
|
|
Mar 12 03:46:10 PM PDT 24 |
Mar 12 03:53:05 PM PDT 24 |
3222328400 ps |
| T273 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.3735177137 |
|
|
Mar 12 04:13:50 PM PDT 24 |
Mar 12 04:22:38 PM PDT 24 |
5949083370 ps |
| T1288 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.2424503566 |
|
|
Mar 12 04:01:30 PM PDT 24 |
Mar 12 04:05:47 PM PDT 24 |
2820025240 ps |
| T1289 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.506402198 |
|
|
Mar 12 04:09:30 PM PDT 24 |
Mar 12 04:17:38 PM PDT 24 |
5227432496 ps |
| T1290 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3512548442 |
|
|
Mar 12 04:12:33 PM PDT 24 |
Mar 12 04:22:40 PM PDT 24 |
4845072312 ps |
| T1291 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2544178690 |
|
|
Mar 12 03:59:36 PM PDT 24 |
Mar 12 04:10:53 PM PDT 24 |
4522097694 ps |
| T69 |
/workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2502615506 |
|
|
Mar 12 03:30:55 PM PDT 24 |
Mar 12 03:31:02 PM PDT 24 |
51799130 ps |
| T70 |
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2959649363 |
|
|
Mar 12 03:25:29 PM PDT 24 |
Mar 12 03:39:10 PM PDT 24 |
45250835219 ps |
| T71 |
/workspace/coverage/cover_reg_top/27.xbar_access_same_device.3465635458 |
|
|
Mar 12 03:27:06 PM PDT 24 |
Mar 12 03:27:30 PM PDT 24 |
293800786 ps |
| T73 |
/workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.1180018835 |
|
|
Mar 12 03:28:48 PM PDT 24 |
Mar 12 03:29:23 PM PDT 24 |
266623324 ps |
| T74 |
/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.352397954 |
|
|
Mar 12 03:30:56 PM PDT 24 |
Mar 12 03:35:54 PM PDT 24 |
3519898625 ps |
| T416 |
/workspace/coverage/cover_reg_top/43.xbar_smoke.1064794113 |
|
|
Mar 12 03:28:55 PM PDT 24 |
Mar 12 03:29:02 PM PDT 24 |
44822289 ps |
| T222 |
/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.4210867500 |
|
|
Mar 12 03:28:18 PM PDT 24 |
Mar 12 03:31:29 PM PDT 24 |
2319642059 ps |
| T506 |
/workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2545334404 |
|
|
Mar 12 03:28:18 PM PDT 24 |
Mar 12 03:28:24 PM PDT 24 |
46551314 ps |
| T418 |
/workspace/coverage/cover_reg_top/39.xbar_same_source.385792666 |
|
|
Mar 12 03:28:31 PM PDT 24 |
Mar 12 03:28:56 PM PDT 24 |
370451750 ps |
| T402 |
/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.277409047 |
|
|
Mar 12 03:35:39 PM PDT 24 |
Mar 12 03:37:02 PM PDT 24 |
119658832 ps |
| T388 |
/workspace/coverage/cover_reg_top/77.xbar_stress_all.1985681447 |
|
|
Mar 12 03:33:30 PM PDT 24 |
Mar 12 03:36:17 PM PDT 24 |
2276418956 ps |
| T510 |
/workspace/coverage/cover_reg_top/47.xbar_smoke.2020967454 |
|
|
Mar 12 03:29:28 PM PDT 24 |
Mar 12 03:29:34 PM PDT 24 |
40421532 ps |
| T403 |
/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2519772187 |
|
|
Mar 12 03:34:41 PM PDT 24 |
Mar 12 03:43:16 PM PDT 24 |
11833418401 ps |
| T417 |
/workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1315498027 |
|
|
Mar 12 03:25:45 PM PDT 24 |
Mar 12 03:26:05 PM PDT 24 |
160813873 ps |
| T505 |
/workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3931307778 |
|
|
Mar 12 03:27:40 PM PDT 24 |
Mar 12 03:27:57 PM PDT 24 |
136923385 ps |
| T1292 |
/workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.904221351 |
|
|
Mar 12 03:25:34 PM PDT 24 |
Mar 12 03:25:40 PM PDT 24 |
38003835 ps |
| T500 |
/workspace/coverage/cover_reg_top/27.xbar_random.3832165683 |
|
|
Mar 12 03:27:01 PM PDT 24 |
Mar 12 03:27:17 PM PDT 24 |
283710403 ps |
| T419 |
/workspace/coverage/cover_reg_top/79.xbar_same_source.2068986826 |
|
|
Mar 12 03:33:47 PM PDT 24 |
Mar 12 03:33:59 PM PDT 24 |
139574710 ps |
| T508 |
/workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.3149748560 |
|
|
Mar 12 03:35:43 PM PDT 24 |
Mar 12 03:36:02 PM PDT 24 |
226061933 ps |
| T448 |
/workspace/coverage/cover_reg_top/72.xbar_random.2191536281 |
|
|
Mar 12 03:32:44 PM PDT 24 |
Mar 12 03:33:49 PM PDT 24 |
1898586486 ps |
| T504 |
/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.77597462 |
|
|
Mar 12 03:31:47 PM PDT 24 |
Mar 12 03:38:24 PM PDT 24 |
7705397971 ps |
| T511 |
/workspace/coverage/cover_reg_top/20.xbar_error_random.818568436 |
|
|
Mar 12 03:26:07 PM PDT 24 |
Mar 12 03:26:41 PM PDT 24 |
905968626 ps |
| T577 |
/workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2768706794 |
|
|
Mar 12 03:35:03 PM PDT 24 |
Mar 12 03:36:24 PM PDT 24 |
4755362021 ps |
| T802 |
/workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.197090349 |
|
|
Mar 12 03:34:31 PM PDT 24 |
Mar 12 03:37:49 PM PDT 24 |
11462561374 ps |
| T539 |
/workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.4066849366 |
|
|
Mar 12 03:33:31 PM PDT 24 |
Mar 12 03:33:37 PM PDT 24 |
38451600 ps |
| T525 |
/workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.4230433680 |
|
|
Mar 12 03:33:50 PM PDT 24 |
Mar 12 03:33:56 PM PDT 24 |
44116483 ps |
| T507 |
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.4168342982 |
|
|
Mar 12 03:25:38 PM PDT 24 |
Mar 12 03:29:06 PM PDT 24 |
5792034785 ps |
| T509 |
/workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.4287893523 |
|
|
Mar 12 03:31:46 PM PDT 24 |
Mar 12 03:31:56 PM PDT 24 |
74102220 ps |
| T817 |
/workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3582987311 |
|
|
Mar 12 03:28:15 PM PDT 24 |
Mar 12 03:29:42 PM PDT 24 |
5207436330 ps |
| T518 |
/workspace/coverage/cover_reg_top/82.xbar_same_source.2258581144 |
|
|
Mar 12 03:34:17 PM PDT 24 |
Mar 12 03:35:01 PM PDT 24 |
1570517180 ps |
| T399 |
/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.372431379 |
|
|
Mar 12 03:25:14 PM PDT 24 |
Mar 12 03:36:26 PM PDT 24 |
10653647786 ps |
| T475 |
/workspace/coverage/cover_reg_top/65.xbar_same_source.1169345731 |
|
|
Mar 12 03:31:59 PM PDT 24 |
Mar 12 03:32:34 PM PDT 24 |
1216820996 ps |
| T503 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2961391814 |
|
|
Mar 12 03:24:57 PM PDT 24 |
Mar 12 03:29:42 PM PDT 24 |
8358967592 ps |
| T1293 |
/workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.750834905 |
|
|
Mar 12 03:29:13 PM PDT 24 |
Mar 12 03:29:31 PM PDT 24 |
379797860 ps |
| T637 |
/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.650224685 |
|
|
Mar 12 03:29:57 PM PDT 24 |
Mar 12 03:32:37 PM PDT 24 |
2558776072 ps |
| T1294 |
/workspace/coverage/cover_reg_top/86.xbar_smoke.1281621325 |
|
|
Mar 12 03:34:21 PM PDT 24 |
Mar 12 03:34:27 PM PDT 24 |
45150498 ps |
| T382 |
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1118463216 |
|
|
Mar 12 03:25:22 PM PDT 24 |
Mar 12 04:06:34 PM PDT 24 |
140550242118 ps |
| T464 |
/workspace/coverage/cover_reg_top/72.xbar_same_source.3794261711 |
|
|
Mar 12 03:32:46 PM PDT 24 |
Mar 12 03:33:23 PM PDT 24 |
1319402266 ps |
| T686 |
/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2666004700 |
|
|
Mar 12 03:25:03 PM PDT 24 |
Mar 12 03:28:35 PM PDT 24 |
1316037378 ps |
| T606 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3365618250 |
|
|
Mar 12 03:25:22 PM PDT 24 |
Mar 12 03:25:28 PM PDT 24 |
43777889 ps |
| T806 |
/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2166887645 |
|
|
Mar 12 03:26:54 PM PDT 24 |
Mar 12 03:30:03 PM PDT 24 |
805456136 ps |
| T1295 |
/workspace/coverage/cover_reg_top/73.xbar_smoke.3804214582 |
|
|
Mar 12 03:32:46 PM PDT 24 |
Mar 12 03:32:52 PM PDT 24 |
48153079 ps |
| T1296 |
/workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2591674334 |
|
|
Mar 12 03:30:56 PM PDT 24 |
Mar 12 03:31:44 PM PDT 24 |
1269068761 ps |
| T466 |
/workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.2300475548 |
|
|
Mar 12 03:31:35 PM PDT 24 |
Mar 12 03:55:10 PM PDT 24 |
70848449790 ps |
| T476 |
/workspace/coverage/cover_reg_top/71.xbar_random.3101034082 |
|
|
Mar 12 03:32:38 PM PDT 24 |
Mar 12 03:33:44 PM PDT 24 |
1808491592 ps |
| T487 |
/workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2470882347 |
|
|
Mar 12 03:29:21 PM PDT 24 |
Mar 12 03:49:37 PM PDT 24 |
60740963243 ps |
| T164 |
/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1232608279 |
|
|
Mar 12 03:25:33 PM PDT 24 |
Mar 12 04:25:26 PM PDT 24 |
29564060484 ps |
| T588 |
/workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.637528170 |
|
|
Mar 12 03:25:17 PM PDT 24 |
Mar 12 03:26:54 PM PDT 24 |
5935407028 ps |
| T1297 |
/workspace/coverage/cover_reg_top/5.xbar_error_random.560220505 |
|
|
Mar 12 03:25:07 PM PDT 24 |
Mar 12 03:25:41 PM PDT 24 |
932217549 ps |
| T612 |
/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2843006165 |
|
|
Mar 12 03:30:53 PM PDT 24 |
Mar 12 03:36:00 PM PDT 24 |
2344920997 ps |
| T687 |
/workspace/coverage/cover_reg_top/93.xbar_error_random.2752078449 |
|
|
Mar 12 03:35:17 PM PDT 24 |
Mar 12 03:35:46 PM PDT 24 |
787314735 ps |
| T823 |
/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2259949956 |
|
|
Mar 12 03:27:48 PM PDT 24 |
Mar 12 03:29:11 PM PDT 24 |
273893450 ps |
| T1298 |
/workspace/coverage/cover_reg_top/59.xbar_smoke.970577550 |
|
|
Mar 12 03:30:55 PM PDT 24 |
Mar 12 03:31:05 PM PDT 24 |
224169486 ps |
| T527 |
/workspace/coverage/cover_reg_top/42.xbar_same_source.4101211386 |
|
|
Mar 12 03:28:53 PM PDT 24 |
Mar 12 03:29:28 PM PDT 24 |
449337863 ps |
| T404 |
/workspace/coverage/cover_reg_top/75.xbar_stress_all.3624527717 |
|
|
Mar 12 03:33:10 PM PDT 24 |
Mar 12 03:35:41 PM PDT 24 |
2007744080 ps |