| T36 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.3466798989 |
|
|
Mar 26 03:50:02 PM PDT 24 |
Mar 26 03:56:46 PM PDT 24 |
3673678566 ps |
| T627 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1827418773 |
|
|
Mar 26 03:51:52 PM PDT 24 |
Mar 26 04:50:47 PM PDT 24 |
24183004284 ps |
| T748 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3318804978 |
|
|
Mar 26 04:13:32 PM PDT 24 |
Mar 26 04:20:23 PM PDT 24 |
4162783084 ps |
| T406 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.543808054 |
|
|
Mar 26 04:09:30 PM PDT 24 |
Mar 26 04:14:07 PM PDT 24 |
2976842004 ps |
| T678 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.463167372 |
|
|
Mar 26 04:09:25 PM PDT 24 |
Mar 26 04:21:30 PM PDT 24 |
6310599114 ps |
| T712 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2738957918 |
|
|
Mar 26 04:06:18 PM PDT 24 |
Mar 26 04:13:15 PM PDT 24 |
4096408820 ps |
| T47 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3938325125 |
|
|
Mar 26 03:50:05 PM PDT 24 |
Mar 26 04:18:06 PM PDT 24 |
22005983376 ps |
| T862 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.367140060 |
|
|
Mar 26 03:57:28 PM PDT 24 |
Mar 26 04:03:36 PM PDT 24 |
3252730176 ps |
| T863 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.1583041276 |
|
|
Mar 26 03:54:06 PM PDT 24 |
Mar 26 03:57:24 PM PDT 24 |
2590556880 ps |
| T113 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2146222200 |
|
|
Mar 26 04:07:19 PM PDT 24 |
Mar 26 04:39:09 PM PDT 24 |
15080090422 ps |
| T864 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2709691925 |
|
|
Mar 26 04:06:07 PM PDT 24 |
Mar 26 04:23:11 PM PDT 24 |
5796038716 ps |
| T865 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2772780484 |
|
|
Mar 26 03:57:39 PM PDT 24 |
Mar 26 04:34:48 PM PDT 24 |
8270778454 ps |
| T149 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.2775417720 |
|
|
Mar 26 04:04:22 PM PDT 24 |
Mar 26 04:16:32 PM PDT 24 |
3479708156 ps |
| T181 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2136077493 |
|
|
Mar 26 03:50:45 PM PDT 24 |
Mar 26 03:55:11 PM PDT 24 |
2826316680 ps |
| T866 |
/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.1531312827 |
|
|
Mar 26 03:51:20 PM PDT 24 |
Mar 26 04:29:42 PM PDT 24 |
9445339944 ps |
| T867 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2023130242 |
|
|
Mar 26 03:59:26 PM PDT 24 |
Mar 26 04:05:47 PM PDT 24 |
3917849310 ps |
| T868 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3341117591 |
|
|
Mar 26 03:58:34 PM PDT 24 |
Mar 26 04:23:50 PM PDT 24 |
9818756736 ps |
| T869 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3700496769 |
|
|
Mar 26 03:46:26 PM PDT 24 |
Mar 26 03:55:57 PM PDT 24 |
4244986200 ps |
| T870 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.176036742 |
|
|
Mar 26 04:09:55 PM PDT 24 |
Mar 26 04:41:06 PM PDT 24 |
8969571343 ps |
| T318 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2399593884 |
|
|
Mar 26 03:53:44 PM PDT 24 |
Mar 26 03:58:40 PM PDT 24 |
2328784376 ps |
| T684 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.782719469 |
|
|
Mar 26 04:10:35 PM PDT 24 |
Mar 26 04:22:41 PM PDT 24 |
4334274400 ps |
| T673 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.331910663 |
|
|
Mar 26 04:09:38 PM PDT 24 |
Mar 26 04:19:27 PM PDT 24 |
5584046802 ps |
| T756 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119147200 |
|
|
Mar 26 04:11:29 PM PDT 24 |
Mar 26 04:18:36 PM PDT 24 |
3337096672 ps |
| T871 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1349528920 |
|
|
Mar 26 03:49:49 PM PDT 24 |
Mar 26 04:51:08 PM PDT 24 |
18500857920 ps |
| T741 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1741376621 |
|
|
Mar 26 04:10:21 PM PDT 24 |
Mar 26 04:19:41 PM PDT 24 |
5141979080 ps |
| T872 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1052232193 |
|
|
Mar 26 04:04:07 PM PDT 24 |
Mar 26 04:13:00 PM PDT 24 |
4102694872 ps |
| T873 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.762471399 |
|
|
Mar 26 03:52:33 PM PDT 24 |
Mar 26 04:21:40 PM PDT 24 |
12164115686 ps |
| T374 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1905182612 |
|
|
Mar 26 03:49:15 PM PDT 24 |
Mar 26 03:56:19 PM PDT 24 |
4677380210 ps |
| T672 |
/workspace/coverage/default/1.chip_tap_straps_dev.2308178656 |
|
|
Mar 26 03:51:18 PM PDT 24 |
Mar 26 03:54:40 PM PDT 24 |
2883070713 ps |
| T874 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.392691617 |
|
|
Mar 26 03:55:17 PM PDT 24 |
Mar 26 03:58:24 PM PDT 24 |
2351830194 ps |
| T61 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.217219735 |
|
|
Mar 26 04:05:45 PM PDT 24 |
Mar 26 04:11:01 PM PDT 24 |
3828611804 ps |
| T875 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.4286024515 |
|
|
Mar 26 04:10:03 PM PDT 24 |
Mar 26 04:41:25 PM PDT 24 |
8568611880 ps |
| T876 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1372464885 |
|
|
Mar 26 04:01:48 PM PDT 24 |
Mar 26 04:10:39 PM PDT 24 |
7162280558 ps |
| T174 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.4161717887 |
|
|
Mar 26 03:58:11 PM PDT 24 |
Mar 26 04:12:24 PM PDT 24 |
9692214004 ps |
| T877 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3762816201 |
|
|
Mar 26 04:05:43 PM PDT 24 |
Mar 26 04:09:25 PM PDT 24 |
2767745686 ps |
| T266 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1350046810 |
|
|
Mar 26 03:56:07 PM PDT 24 |
Mar 26 04:30:02 PM PDT 24 |
8358151955 ps |
| T56 |
/workspace/coverage/default/0.chip_sw_alert_test.363646497 |
|
|
Mar 26 03:47:00 PM PDT 24 |
Mar 26 03:53:09 PM PDT 24 |
3180673362 ps |
| T726 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.870813225 |
|
|
Mar 26 04:09:49 PM PDT 24 |
Mar 26 04:22:44 PM PDT 24 |
5303981012 ps |
| T730 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.501500184 |
|
|
Mar 26 04:07:11 PM PDT 24 |
Mar 26 04:13:47 PM PDT 24 |
3392158544 ps |
| T878 |
/workspace/coverage/default/1.rom_e2e_smoke.731547139 |
|
|
Mar 26 03:54:38 PM PDT 24 |
Mar 26 04:33:11 PM PDT 24 |
8655506550 ps |
| T879 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3951860569 |
|
|
Mar 26 03:57:01 PM PDT 24 |
Mar 26 04:00:07 PM PDT 24 |
2749440550 ps |
| T880 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4004835793 |
|
|
Mar 26 03:46:14 PM PDT 24 |
Mar 26 03:54:35 PM PDT 24 |
6007548240 ps |
| T249 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3807570972 |
|
|
Mar 26 04:02:50 PM PDT 24 |
Mar 26 04:28:07 PM PDT 24 |
11163341746 ps |
| T881 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3507779025 |
|
|
Mar 26 04:03:28 PM PDT 24 |
Mar 26 04:14:19 PM PDT 24 |
4178341000 ps |
| T656 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.4161251072 |
|
|
Mar 26 03:55:11 PM PDT 24 |
Mar 26 04:25:43 PM PDT 24 |
6737362444 ps |
| T882 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.26123336 |
|
|
Mar 26 03:47:30 PM PDT 24 |
Mar 26 04:15:29 PM PDT 24 |
16257749304 ps |
| T883 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2575735240 |
|
|
Mar 26 03:54:23 PM PDT 24 |
Mar 26 04:00:35 PM PDT 24 |
5738815850 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2150777716 |
|
|
Mar 26 03:48:27 PM PDT 24 |
Mar 26 05:46:37 PM PDT 24 |
31349906714 ps |
| T884 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.1107373886 |
|
|
Mar 26 03:56:38 PM PDT 24 |
Mar 26 04:31:31 PM PDT 24 |
9107840456 ps |
| T11 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1706464781 |
|
|
Mar 26 03:45:02 PM PDT 24 |
Mar 26 03:57:04 PM PDT 24 |
6442148145 ps |
| T360 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1185789964 |
|
|
Mar 26 03:59:05 PM PDT 24 |
Mar 26 04:55:50 PM PDT 24 |
11929334948 ps |
| T693 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2173578591 |
|
|
Mar 26 04:06:15 PM PDT 24 |
Mar 26 04:12:40 PM PDT 24 |
3431614974 ps |
| T885 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3367785020 |
|
|
Mar 26 04:08:24 PM PDT 24 |
Mar 26 04:18:29 PM PDT 24 |
4812623496 ps |
| T279 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3544907337 |
|
|
Mar 26 04:08:08 PM PDT 24 |
Mar 26 04:18:24 PM PDT 24 |
5986577224 ps |
| T267 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.4201732763 |
|
|
Mar 26 04:05:39 PM PDT 24 |
Mar 26 04:18:17 PM PDT 24 |
5207242038 ps |
| T269 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.4273738881 |
|
|
Mar 26 03:46:30 PM PDT 24 |
Mar 26 03:57:22 PM PDT 24 |
5350591832 ps |
| T270 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.156874582 |
|
|
Mar 26 03:47:39 PM PDT 24 |
Mar 26 04:48:30 PM PDT 24 |
16754073966 ps |
| T271 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1194755051 |
|
|
Mar 26 04:07:35 PM PDT 24 |
Mar 26 04:17:15 PM PDT 24 |
5706449800 ps |
| T193 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3727154958 |
|
|
Mar 26 03:56:41 PM PDT 24 |
Mar 26 07:00:15 PM PDT 24 |
63947489672 ps |
| T272 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3137166067 |
|
|
Mar 26 04:05:50 PM PDT 24 |
Mar 26 04:11:51 PM PDT 24 |
3754884696 ps |
| T273 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1255533652 |
|
|
Mar 26 03:48:42 PM PDT 24 |
Mar 26 04:07:42 PM PDT 24 |
10970063474 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_gpio.738847330 |
|
|
Mar 26 03:47:14 PM PDT 24 |
Mar 26 03:54:18 PM PDT 24 |
3413296598 ps |
| T190 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.415128494 |
|
|
Mar 26 04:08:27 PM PDT 24 |
Mar 26 04:20:44 PM PDT 24 |
5310609205 ps |
| T274 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1707522211 |
|
|
Mar 26 04:12:19 PM PDT 24 |
Mar 26 04:25:39 PM PDT 24 |
6245002488 ps |
| T886 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.3530176409 |
|
|
Mar 26 03:45:37 PM PDT 24 |
Mar 26 03:49:49 PM PDT 24 |
2719513526 ps |
| T887 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1900177179 |
|
|
Mar 26 04:10:40 PM PDT 24 |
Mar 26 04:22:45 PM PDT 24 |
6163410020 ps |
| T888 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4286448662 |
|
|
Mar 26 03:46:32 PM PDT 24 |
Mar 26 04:03:55 PM PDT 24 |
7997981480 ps |
| T889 |
/workspace/coverage/default/2.chip_tap_straps_prod.3707720411 |
|
|
Mar 26 04:04:34 PM PDT 24 |
Mar 26 04:07:36 PM PDT 24 |
2469390280 ps |
| T890 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1439683781 |
|
|
Mar 26 03:49:07 PM PDT 24 |
Mar 26 03:54:01 PM PDT 24 |
3011439432 ps |
| T891 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2261086485 |
|
|
Mar 26 03:59:13 PM PDT 24 |
Mar 26 04:48:15 PM PDT 24 |
38145452082 ps |
| T315 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3070841583 |
|
|
Mar 26 03:57:41 PM PDT 24 |
Mar 26 04:13:02 PM PDT 24 |
4733979192 ps |
| T165 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1222309511 |
|
|
Mar 26 03:58:38 PM PDT 24 |
Mar 26 04:08:20 PM PDT 24 |
3831222555 ps |
| T169 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1888820 |
|
|
Mar 26 03:47:56 PM PDT 24 |
Mar 26 04:20:14 PM PDT 24 |
24836434551 ps |
| T351 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.4102035869 |
|
|
Mar 26 04:10:12 PM PDT 24 |
Mar 26 04:20:16 PM PDT 24 |
5166846418 ps |
| T19 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1867161564 |
|
|
Mar 26 03:48:35 PM PDT 24 |
Mar 26 04:46:36 PM PDT 24 |
19972270862 ps |
| T892 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3311017003 |
|
|
Mar 26 03:48:02 PM PDT 24 |
Mar 26 04:11:05 PM PDT 24 |
10879851108 ps |
| T893 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3880574689 |
|
|
Mar 26 03:48:18 PM PDT 24 |
Mar 26 04:09:34 PM PDT 24 |
7580518438 ps |
| T894 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3552053692 |
|
|
Mar 26 03:49:15 PM PDT 24 |
Mar 26 04:07:14 PM PDT 24 |
5622950272 ps |
| T170 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1355308511 |
|
|
Mar 26 03:47:36 PM PDT 24 |
Mar 26 03:49:59 PM PDT 24 |
3087389707 ps |
| T895 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.971111409 |
|
|
Mar 26 04:07:38 PM PDT 24 |
Mar 26 04:20:55 PM PDT 24 |
8896802071 ps |
| T688 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.596099548 |
|
|
Mar 26 04:08:06 PM PDT 24 |
Mar 26 04:21:11 PM PDT 24 |
6414169802 ps |
| T896 |
/workspace/coverage/default/0.chip_sw_example_concurrency.2677016262 |
|
|
Mar 26 03:46:46 PM PDT 24 |
Mar 26 03:50:45 PM PDT 24 |
2934163160 ps |
| T727 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.652724582 |
|
|
Mar 26 04:07:15 PM PDT 24 |
Mar 26 04:16:51 PM PDT 24 |
5702740174 ps |
| T897 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.415407140 |
|
|
Mar 26 03:53:12 PM PDT 24 |
Mar 26 04:04:22 PM PDT 24 |
4398498788 ps |
| T898 |
/workspace/coverage/default/0.rom_e2e_smoke.3963563860 |
|
|
Mar 26 03:50:21 PM PDT 24 |
Mar 26 04:27:39 PM PDT 24 |
8945953488 ps |
| T12 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2612632536 |
|
|
Mar 26 03:47:21 PM PDT 24 |
Mar 26 03:55:13 PM PDT 24 |
4498986844 ps |
| T138 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.71052024 |
|
|
Mar 26 03:49:29 PM PDT 24 |
Mar 26 03:58:26 PM PDT 24 |
7681671592 ps |
| T45 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.856775506 |
|
|
Mar 26 03:48:35 PM PDT 24 |
Mar 26 03:55:37 PM PDT 24 |
4480035128 ps |
| T312 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.708552059 |
|
|
Mar 26 03:49:41 PM PDT 24 |
Mar 26 04:36:43 PM PDT 24 |
14045564975 ps |
| T400 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878075635 |
|
|
Mar 26 04:06:50 PM PDT 24 |
Mar 26 04:12:21 PM PDT 24 |
3364707862 ps |
| T48 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3164156670 |
|
|
Mar 26 04:04:37 PM PDT 24 |
Mar 26 04:27:43 PM PDT 24 |
17343121000 ps |
| T401 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.457963734 |
|
|
Mar 26 03:53:44 PM PDT 24 |
Mar 26 03:57:21 PM PDT 24 |
2570071936 ps |
| T144 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.144017406 |
|
|
Mar 26 03:48:07 PM PDT 24 |
Mar 26 03:53:05 PM PDT 24 |
2667190613 ps |
| T402 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.278362139 |
|
|
Mar 26 03:56:39 PM PDT 24 |
Mar 26 04:06:23 PM PDT 24 |
4175695380 ps |
| T20 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2193016640 |
|
|
Mar 26 04:00:08 PM PDT 24 |
Mar 26 04:47:08 PM PDT 24 |
20955869617 ps |
| T403 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.807917737 |
|
|
Mar 26 04:02:39 PM PDT 24 |
Mar 26 04:59:38 PM PDT 24 |
16677638424 ps |
| T404 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3169161370 |
|
|
Mar 26 03:53:15 PM PDT 24 |
Mar 26 04:24:52 PM PDT 24 |
8879836434 ps |
| T899 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1633515503 |
|
|
Mar 26 03:47:12 PM PDT 24 |
Mar 26 03:51:12 PM PDT 24 |
3460756449 ps |
| T900 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2244050229 |
|
|
Mar 26 03:52:21 PM PDT 24 |
Mar 26 03:57:29 PM PDT 24 |
3610443101 ps |
| T631 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.4034587173 |
|
|
Mar 26 03:50:30 PM PDT 24 |
Mar 26 04:24:05 PM PDT 24 |
8441860760 ps |
| T57 |
/workspace/coverage/default/2.chip_sw_alert_test.2063501945 |
|
|
Mar 26 04:02:20 PM PDT 24 |
Mar 26 04:07:27 PM PDT 24 |
2841949928 ps |
| T742 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3665428675 |
|
|
Mar 26 04:09:00 PM PDT 24 |
Mar 26 04:14:42 PM PDT 24 |
3431086030 ps |
| T901 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1866124251 |
|
|
Mar 26 03:53:54 PM PDT 24 |
Mar 26 04:03:30 PM PDT 24 |
4968300846 ps |
| T323 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2429038098 |
|
|
Mar 26 03:56:32 PM PDT 24 |
Mar 26 04:09:42 PM PDT 24 |
5293827825 ps |
| T698 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3983115869 |
|
|
Mar 26 04:10:55 PM PDT 24 |
Mar 26 04:17:39 PM PDT 24 |
3865367712 ps |
| T229 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2726386083 |
|
|
Mar 26 03:53:16 PM PDT 24 |
Mar 26 04:07:26 PM PDT 24 |
4038418400 ps |
| T410 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3332072425 |
|
|
Mar 26 04:08:01 PM PDT 24 |
Mar 26 04:18:02 PM PDT 24 |
4692034368 ps |
| T902 |
/workspace/coverage/default/1.chip_sw_example_rom.3025410229 |
|
|
Mar 26 03:45:31 PM PDT 24 |
Mar 26 03:47:28 PM PDT 24 |
2326456318 ps |
| T903 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.4170634977 |
|
|
Mar 26 03:50:06 PM PDT 24 |
Mar 26 03:58:34 PM PDT 24 |
5486144520 ps |
| T134 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4231022799 |
|
|
Mar 26 03:50:41 PM PDT 24 |
Mar 26 04:06:00 PM PDT 24 |
8708298822 ps |
| T427 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3640903693 |
|
|
Mar 26 04:02:03 PM PDT 24 |
Mar 26 04:07:53 PM PDT 24 |
5594049838 ps |
| T904 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1740354155 |
|
|
Mar 26 03:50:40 PM PDT 24 |
Mar 26 04:25:01 PM PDT 24 |
8896977310 ps |
| T628 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3171120220 |
|
|
Mar 26 04:05:33 PM PDT 24 |
Mar 26 05:20:22 PM PDT 24 |
24385526276 ps |
| T905 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2372538459 |
|
|
Mar 26 04:02:25 PM PDT 24 |
Mar 26 04:11:30 PM PDT 24 |
4033986447 ps |
| T310 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1713256930 |
|
|
Mar 26 03:48:52 PM PDT 24 |
Mar 26 04:08:23 PM PDT 24 |
5779799588 ps |
| T906 |
/workspace/coverage/default/0.chip_tap_straps_dev.1766693851 |
|
|
Mar 26 03:48:08 PM PDT 24 |
Mar 26 04:09:03 PM PDT 24 |
11285674580 ps |
| T615 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1910255580 |
|
|
Mar 26 03:46:47 PM PDT 24 |
Mar 26 03:48:47 PM PDT 24 |
2601212762 ps |
| T907 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1669879716 |
|
|
Mar 26 04:09:15 PM PDT 24 |
Mar 26 04:18:00 PM PDT 24 |
4656485448 ps |
| T324 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1702468482 |
|
|
Mar 26 04:13:06 PM PDT 24 |
Mar 26 04:24:19 PM PDT 24 |
5420438924 ps |
| T301 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.213124378 |
|
|
Mar 26 03:53:33 PM PDT 24 |
Mar 26 04:06:49 PM PDT 24 |
4419964584 ps |
| T908 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.906405083 |
|
|
Mar 26 03:48:52 PM PDT 24 |
Mar 26 04:02:03 PM PDT 24 |
6755729170 ps |
| T909 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2675454520 |
|
|
Mar 26 04:02:03 PM PDT 24 |
Mar 26 04:05:25 PM PDT 24 |
2970439104 ps |
| T334 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.85485238 |
|
|
Mar 26 03:48:44 PM PDT 24 |
Mar 26 03:59:15 PM PDT 24 |
3904138810 ps |
| T910 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1564246453 |
|
|
Mar 26 03:51:15 PM PDT 24 |
Mar 26 03:55:50 PM PDT 24 |
2676695600 ps |
| T707 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2704479189 |
|
|
Mar 26 04:12:45 PM PDT 24 |
Mar 26 04:20:30 PM PDT 24 |
3409262910 ps |
| T139 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.4195791892 |
|
|
Mar 26 03:49:57 PM PDT 24 |
Mar 26 03:56:19 PM PDT 24 |
8745568960 ps |
| T911 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.856960918 |
|
|
Mar 26 03:52:56 PM PDT 24 |
Mar 26 03:58:41 PM PDT 24 |
3668746127 ps |
| T192 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3868325345 |
|
|
Mar 26 03:58:43 PM PDT 24 |
Mar 26 04:11:43 PM PDT 24 |
6986823892 ps |
| T128 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1305005211 |
|
|
Mar 26 03:50:17 PM PDT 24 |
Mar 26 03:59:25 PM PDT 24 |
5533658668 ps |
| T912 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4012272487 |
|
|
Mar 26 03:51:46 PM PDT 24 |
Mar 26 04:02:29 PM PDT 24 |
4703050216 ps |
| T913 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2003363456 |
|
|
Mar 26 03:53:24 PM PDT 24 |
Mar 26 04:22:19 PM PDT 24 |
10989745599 ps |
| T914 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.381081370 |
|
|
Mar 26 03:48:33 PM PDT 24 |
Mar 26 04:00:30 PM PDT 24 |
5610053000 ps |
| T915 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1265815921 |
|
|
Mar 26 04:02:22 PM PDT 24 |
Mar 26 04:33:40 PM PDT 24 |
23991729714 ps |
| T916 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2930893981 |
|
|
Mar 26 03:57:04 PM PDT 24 |
Mar 26 04:23:10 PM PDT 24 |
14196546393 ps |
| T917 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.4031271005 |
|
|
Mar 26 03:47:40 PM PDT 24 |
Mar 26 03:53:24 PM PDT 24 |
3618777176 ps |
| T757 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3930100319 |
|
|
Mar 26 04:11:26 PM PDT 24 |
Mar 26 04:18:55 PM PDT 24 |
3627335460 ps |
| T83 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4031984810 |
|
|
Mar 26 03:48:55 PM PDT 24 |
Mar 26 07:30:19 PM PDT 24 |
255225862024 ps |
| T918 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2260023652 |
|
|
Mar 26 04:14:32 PM PDT 24 |
Mar 26 04:48:03 PM PDT 24 |
12638073333 ps |
| T919 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1910719492 |
|
|
Mar 26 04:03:43 PM PDT 24 |
Mar 26 04:09:17 PM PDT 24 |
3346980670 ps |
| T744 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.3864676027 |
|
|
Mar 26 04:11:48 PM PDT 24 |
Mar 26 04:22:48 PM PDT 24 |
4781443424 ps |
| T920 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.3134634747 |
|
|
Mar 26 03:48:49 PM PDT 24 |
Mar 26 04:07:51 PM PDT 24 |
5988830146 ps |
| T687 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1124735676 |
|
|
Mar 26 04:07:25 PM PDT 24 |
Mar 26 04:16:18 PM PDT 24 |
4017638740 ps |
| T921 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1282494834 |
|
|
Mar 26 03:51:03 PM PDT 24 |
Mar 26 03:57:57 PM PDT 24 |
5130150812 ps |
| T745 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2237124931 |
|
|
Mar 26 04:13:46 PM PDT 24 |
Mar 26 04:22:01 PM PDT 24 |
5407031290 ps |
| T922 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2043843977 |
|
|
Mar 26 03:49:43 PM PDT 24 |
Mar 26 03:58:24 PM PDT 24 |
4052693880 ps |
| T923 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3447978486 |
|
|
Mar 26 03:49:57 PM PDT 24 |
Mar 26 03:53:21 PM PDT 24 |
2957735980 ps |
| T230 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1266589351 |
|
|
Mar 26 03:48:04 PM PDT 24 |
Mar 26 04:08:00 PM PDT 24 |
5919484288 ps |
| T182 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1833512836 |
|
|
Mar 26 03:49:35 PM PDT 24 |
Mar 26 03:52:51 PM PDT 24 |
3324521127 ps |
| T195 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1229663059 |
|
|
Mar 26 03:46:29 PM PDT 24 |
Mar 26 03:57:43 PM PDT 24 |
4458960161 ps |
| T409 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.519015541 |
|
|
Mar 26 04:08:07 PM PDT 24 |
Mar 26 04:16:12 PM PDT 24 |
3299839638 ps |
| T924 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.451906222 |
|
|
Mar 26 04:05:06 PM PDT 24 |
Mar 26 04:21:46 PM PDT 24 |
6795179900 ps |
| T925 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1979817625 |
|
|
Mar 26 03:53:33 PM PDT 24 |
Mar 26 03:58:27 PM PDT 24 |
2414975655 ps |
| T636 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1545564681 |
|
|
Mar 26 04:06:23 PM PDT 24 |
Mar 26 04:19:25 PM PDT 24 |
5670919800 ps |
| T926 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2544968666 |
|
|
Mar 26 04:00:00 PM PDT 24 |
Mar 26 04:09:19 PM PDT 24 |
6766714290 ps |
| T304 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1543847767 |
|
|
Mar 26 03:57:56 PM PDT 24 |
Mar 26 04:08:19 PM PDT 24 |
3954358544 ps |
| T160 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2626088820 |
|
|
Mar 26 03:44:46 PM PDT 24 |
Mar 26 03:55:04 PM PDT 24 |
5691923368 ps |
| T927 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.40431009 |
|
|
Mar 26 03:56:16 PM PDT 24 |
Mar 26 04:01:37 PM PDT 24 |
2800513544 ps |
| T26 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.1916040166 |
|
|
Mar 26 03:53:33 PM PDT 24 |
Mar 26 03:58:17 PM PDT 24 |
2455337088 ps |
| T221 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.301282272 |
|
|
Mar 26 03:53:53 PM PDT 24 |
Mar 26 05:18:07 PM PDT 24 |
47324410861 ps |
| T928 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.4176412941 |
|
|
Mar 26 03:48:30 PM PDT 24 |
Mar 26 04:04:38 PM PDT 24 |
5655255718 ps |
| T929 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.1233452551 |
|
|
Mar 26 03:55:08 PM PDT 24 |
Mar 26 04:00:43 PM PDT 24 |
3570484712 ps |
| T84 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.18594384 |
|
|
Mar 26 03:46:28 PM PDT 24 |
Mar 26 04:10:00 PM PDT 24 |
12548362366 ps |
| T196 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1682641696 |
|
|
Mar 26 03:56:53 PM PDT 24 |
Mar 26 04:11:38 PM PDT 24 |
5504036436 ps |
| T930 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.3814906847 |
|
|
Mar 26 03:48:22 PM PDT 24 |
Mar 26 03:52:38 PM PDT 24 |
3439286324 ps |
| T931 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1325043727 |
|
|
Mar 26 03:59:44 PM PDT 24 |
Mar 26 04:19:06 PM PDT 24 |
13099832187 ps |
| T78 |
/workspace/coverage/default/0.chip_jtag_mem_access.3426584948 |
|
|
Mar 26 03:36:47 PM PDT 24 |
Mar 26 03:57:59 PM PDT 24 |
12927116130 ps |
| T333 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.209343752 |
|
|
Mar 26 03:57:30 PM PDT 24 |
Mar 26 04:10:19 PM PDT 24 |
4328298503 ps |
| T932 |
/workspace/coverage/default/3.chip_tap_straps_prod.1262248465 |
|
|
Mar 26 04:05:46 PM PDT 24 |
Mar 26 04:18:42 PM PDT 24 |
8494086406 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2326584692 |
|
|
Mar 26 03:51:17 PM PDT 24 |
Mar 26 03:56:29 PM PDT 24 |
2673676120 ps |
| T378 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1282837301 |
|
|
Mar 26 04:06:05 PM PDT 24 |
Mar 26 04:13:50 PM PDT 24 |
5458718248 ps |
| T379 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1115996951 |
|
|
Mar 26 04:06:03 PM PDT 24 |
Mar 26 04:19:35 PM PDT 24 |
11910019210 ps |
| T380 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1076815138 |
|
|
Mar 26 03:47:47 PM PDT 24 |
Mar 26 03:57:46 PM PDT 24 |
4959002080 ps |
| T34 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2379728319 |
|
|
Mar 26 03:51:53 PM PDT 24 |
Mar 26 03:55:57 PM PDT 24 |
2109180100 ps |
| T375 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1541171563 |
|
|
Mar 26 03:50:52 PM PDT 24 |
Mar 26 03:58:50 PM PDT 24 |
3815827920 ps |
| T381 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2161496362 |
|
|
Mar 26 03:46:50 PM PDT 24 |
Mar 26 03:54:07 PM PDT 24 |
3495520087 ps |
| T355 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.3537908507 |
|
|
Mar 26 04:01:03 PM PDT 24 |
Mar 26 04:07:37 PM PDT 24 |
3297422880 ps |
| T187 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.325560480 |
|
|
Mar 26 04:03:02 PM PDT 24 |
Mar 26 04:18:26 PM PDT 24 |
9020281456 ps |
| T382 |
/workspace/coverage/default/0.chip_sw_aes_idle.1301013929 |
|
|
Mar 26 03:46:59 PM PDT 24 |
Mar 26 03:51:35 PM PDT 24 |
2812195064 ps |
| T719 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1224777237 |
|
|
Mar 26 04:08:49 PM PDT 24 |
Mar 26 04:14:37 PM PDT 24 |
3058100540 ps |
| T933 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2046409220 |
|
|
Mar 26 03:47:14 PM PDT 24 |
Mar 26 04:04:19 PM PDT 24 |
6086302184 ps |
| T934 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2781958133 |
|
|
Mar 26 03:47:01 PM PDT 24 |
Mar 26 04:48:52 PM PDT 24 |
24862920038 ps |
| T197 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1532255260 |
|
|
Mar 26 04:06:00 PM PDT 24 |
Mar 26 04:43:09 PM PDT 24 |
14539208099 ps |
| T935 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3269660746 |
|
|
Mar 26 03:56:43 PM PDT 24 |
Mar 26 04:37:12 PM PDT 24 |
8038645547 ps |
| T936 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.343784083 |
|
|
Mar 26 03:47:11 PM PDT 24 |
Mar 26 03:50:32 PM PDT 24 |
3134937512 ps |
| T21 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1164525544 |
|
|
Mar 26 03:50:26 PM PDT 24 |
Mar 26 04:17:38 PM PDT 24 |
22685511280 ps |
| T937 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3653584832 |
|
|
Mar 26 04:03:16 PM PDT 24 |
Mar 26 04:13:53 PM PDT 24 |
4139343208 ps |
| T938 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2843858176 |
|
|
Mar 26 03:46:31 PM PDT 24 |
Mar 26 04:10:49 PM PDT 24 |
10285982167 ps |
| T939 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.477817030 |
|
|
Mar 26 03:50:48 PM PDT 24 |
Mar 26 03:53:18 PM PDT 24 |
2883768100 ps |
| T940 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1102616495 |
|
|
Mar 26 04:03:36 PM PDT 24 |
Mar 26 04:12:17 PM PDT 24 |
5287128476 ps |
| T62 |
/workspace/coverage/default/0.chip_tap_straps_rma.1894387493 |
|
|
Mar 26 03:45:13 PM PDT 24 |
Mar 26 03:53:53 PM PDT 24 |
5417600436 ps |
| T941 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2247953877 |
|
|
Mar 26 03:47:31 PM PDT 24 |
Mar 26 04:00:48 PM PDT 24 |
10544120228 ps |
| T942 |
/workspace/coverage/default/1.chip_tap_straps_rma.3082440032 |
|
|
Mar 26 03:52:01 PM PDT 24 |
Mar 26 04:00:16 PM PDT 24 |
6071091098 ps |
| T340 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2020548230 |
|
|
Mar 26 04:00:43 PM PDT 24 |
Mar 26 04:10:38 PM PDT 24 |
18718116504 ps |
| T749 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2799764950 |
|
|
Mar 26 04:10:08 PM PDT 24 |
Mar 26 04:20:21 PM PDT 24 |
4932921938 ps |
| T943 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.2309429405 |
|
|
Mar 26 04:04:08 PM PDT 24 |
Mar 26 04:14:12 PM PDT 24 |
4489709370 ps |
| T944 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2215924623 |
|
|
Mar 26 04:00:18 PM PDT 24 |
Mar 26 04:04:14 PM PDT 24 |
3636022840 ps |
| T945 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1198235844 |
|
|
Mar 26 03:47:45 PM PDT 24 |
Mar 26 03:55:42 PM PDT 24 |
4296019252 ps |
| T665 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.2886087660 |
|
|
Mar 26 03:52:10 PM PDT 24 |
Mar 26 04:00:50 PM PDT 24 |
5427148288 ps |
| T946 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.674684577 |
|
|
Mar 26 04:05:52 PM PDT 24 |
Mar 26 04:24:19 PM PDT 24 |
5861860462 ps |
| T947 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1726236895 |
|
|
Mar 26 04:06:16 PM PDT 24 |
Mar 26 04:12:19 PM PDT 24 |
2527141480 ps |
| T948 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.2833569960 |
|
|
Mar 26 03:53:59 PM PDT 24 |
Mar 26 03:59:02 PM PDT 24 |
2586376676 ps |
| T739 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1372298533 |
|
|
Mar 26 04:08:36 PM PDT 24 |
Mar 26 04:23:48 PM PDT 24 |
5770954876 ps |
| T949 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.93861469 |
|
|
Mar 26 03:56:06 PM PDT 24 |
Mar 26 04:28:07 PM PDT 24 |
8938876680 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_example_rom.2674885341 |
|
|
Mar 26 03:45:13 PM PDT 24 |
Mar 26 03:47:45 PM PDT 24 |
2416654016 ps |
| T71 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1877668633 |
|
|
Mar 26 03:45:23 PM PDT 24 |
Mar 26 03:52:59 PM PDT 24 |
3360111762 ps |
| T228 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3563405075 |
|
|
Mar 26 03:48:02 PM PDT 24 |
Mar 26 05:16:15 PM PDT 24 |
48935619725 ps |
| T674 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1689272897 |
|
|
Mar 26 04:12:46 PM PDT 24 |
Mar 26 04:22:29 PM PDT 24 |
5824086152 ps |
| T951 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3407515732 |
|
|
Mar 26 03:49:41 PM PDT 24 |
Mar 26 04:00:27 PM PDT 24 |
6543391578 ps |
| T723 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3094421724 |
|
|
Mar 26 04:10:00 PM PDT 24 |
Mar 26 04:17:16 PM PDT 24 |
3717565192 ps |
| T46 |
/workspace/coverage/default/2.chip_jtag_csr_rw.844094730 |
|
|
Mar 26 03:55:15 PM PDT 24 |
Mar 26 04:25:26 PM PDT 24 |
11804160491 ps |
| T383 |
/workspace/coverage/default/1.chip_sw_edn_kat.3365694984 |
|
|
Mar 26 03:47:55 PM PDT 24 |
Mar 26 03:59:01 PM PDT 24 |
3797698768 ps |
| T384 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2445779539 |
|
|
Mar 26 03:47:19 PM PDT 24 |
Mar 26 03:50:57 PM PDT 24 |
2732339772 ps |
| T146 |
/workspace/coverage/default/2.rom_raw_unlock.2536498715 |
|
|
Mar 26 04:06:37 PM PDT 24 |
Mar 26 04:43:24 PM PDT 24 |
16278445260 ps |
| T385 |
/workspace/coverage/default/2.rom_e2e_static_critical.1755640987 |
|
|
Mar 26 04:11:04 PM PDT 24 |
Mar 26 04:46:33 PM PDT 24 |
10583275400 ps |
| T308 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3586440718 |
|
|
Mar 26 03:56:59 PM PDT 24 |
Mar 26 04:10:37 PM PDT 24 |
5739591176 ps |
| T386 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.34778268 |
|
|
Mar 26 03:47:57 PM PDT 24 |
Mar 26 03:52:49 PM PDT 24 |
3267394256 ps |
| T387 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2438490013 |
|
|
Mar 26 04:06:38 PM PDT 24 |
Mar 26 04:12:42 PM PDT 24 |
4554307302 ps |
| T388 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1741381663 |
|
|
Mar 26 03:42:49 PM PDT 24 |
Mar 26 04:03:51 PM PDT 24 |
11280924136 ps |
| T7 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1195167991 |
|
|
Mar 26 03:48:24 PM PDT 24 |
Mar 26 03:55:27 PM PDT 24 |
2859996001 ps |
| T952 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.146025317 |
|
|
Mar 26 04:01:20 PM PDT 24 |
Mar 26 04:11:44 PM PDT 24 |
4501688455 ps |
| T953 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.2484087298 |
|
|
Mar 26 03:52:44 PM PDT 24 |
Mar 26 03:57:47 PM PDT 24 |
3285723050 ps |
| T954 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.731286533 |
|
|
Mar 26 03:57:43 PM PDT 24 |
Mar 26 04:27:50 PM PDT 24 |
6796734868 ps |
| T955 |
/workspace/coverage/default/3.chip_tap_straps_rma.878404795 |
|
|
Mar 26 04:06:00 PM PDT 24 |
Mar 26 04:17:56 PM PDT 24 |
6920543287 ps |
| T956 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1430591787 |
|
|
Mar 26 04:07:03 PM PDT 24 |
Mar 26 04:55:34 PM PDT 24 |
17670040105 ps |
| T223 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3506315463 |
|
|
Mar 26 03:48:00 PM PDT 24 |
Mar 26 03:55:55 PM PDT 24 |
4063076395 ps |
| T957 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.160096328 |
|
|
Mar 26 03:59:00 PM PDT 24 |
Mar 26 04:51:07 PM PDT 24 |
12084533600 ps |
| T53 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3411480680 |
|
|
Mar 26 03:56:08 PM PDT 24 |
Mar 26 04:04:58 PM PDT 24 |
6296362536 ps |
| T201 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.1852756 |
|
|
Mar 26 03:58:21 PM PDT 24 |
Mar 26 04:50:42 PM PDT 24 |
23291239836 ps |
| T225 |
/workspace/coverage/default/2.chip_sw_flash_init.1834381295 |
|
|
Mar 26 03:57:07 PM PDT 24 |
Mar 26 04:31:08 PM PDT 24 |
24960305472 ps |
| T958 |
/workspace/coverage/default/0.chip_sw_aes_entropy.2464075315 |
|
|
Mar 26 03:47:54 PM PDT 24 |
Mar 26 03:52:28 PM PDT 24 |
2869501856 ps |
| T352 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.440111504 |
|
|
Mar 26 04:07:56 PM PDT 24 |
Mar 26 04:17:39 PM PDT 24 |
4951163416 ps |
| T959 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1196372840 |
|
|
Mar 26 03:47:08 PM PDT 24 |
Mar 26 03:57:44 PM PDT 24 |
4919844220 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.65393635 |
|
|
Mar 26 03:49:44 PM PDT 24 |
Mar 26 03:54:07 PM PDT 24 |
3225459979 ps |
| T699 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2758209430 |
|
|
Mar 26 04:15:10 PM PDT 24 |
Mar 26 04:23:32 PM PDT 24 |
3745346250 ps |
| T961 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3278130858 |
|
|
Mar 26 03:49:37 PM PDT 24 |
Mar 26 03:59:26 PM PDT 24 |
4281739418 ps |
| T268 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1626004445 |
|
|
Mar 26 03:55:23 PM PDT 24 |
Mar 26 04:07:09 PM PDT 24 |
5580557816 ps |
| T962 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3150910610 |
|
|
Mar 26 03:54:01 PM PDT 24 |
Mar 26 04:04:24 PM PDT 24 |
3481010600 ps |
| T129 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2947313657 |
|
|
Mar 26 03:47:44 PM PDT 24 |
Mar 26 03:55:37 PM PDT 24 |
5623032280 ps |
| T963 |
/workspace/coverage/default/2.chip_sw_aes_entropy.3148491141 |
|
|
Mar 26 04:01:50 PM PDT 24 |
Mar 26 04:05:40 PM PDT 24 |
2102431080 ps |
| T964 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3002862511 |
|
|
Mar 26 03:46:58 PM PDT 24 |
Mar 26 03:54:15 PM PDT 24 |
4475485330 ps |
| T204 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.2031497518 |
|
|
Mar 26 03:50:37 PM PDT 24 |
Mar 26 04:06:50 PM PDT 24 |
5754494444 ps |
| T704 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4209114368 |
|
|
Mar 26 04:12:19 PM PDT 24 |
Mar 26 04:17:57 PM PDT 24 |
3594608558 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3138717369 |
|
|
Mar 26 03:50:46 PM PDT 24 |
Mar 26 04:03:20 PM PDT 24 |
3901398540 ps |
| T966 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1226891955 |
|
|
Mar 26 04:06:41 PM PDT 24 |
Mar 26 04:15:07 PM PDT 24 |
6264193185 ps |
| T8 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2979600236 |
|
|
Mar 26 03:51:52 PM PDT 24 |
Mar 26 03:55:53 PM PDT 24 |
2630544706 ps |
| T217 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3106769585 |
|
|
Mar 26 04:01:49 PM PDT 24 |
Mar 26 05:11:49 PM PDT 24 |
17326978600 ps |
| T967 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2093012953 |
|
|
Mar 26 03:54:08 PM PDT 24 |
Mar 26 03:59:59 PM PDT 24 |
3175904948 ps |
| T151 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1958406536 |
|
|
Mar 26 03:48:20 PM PDT 24 |
Mar 26 03:53:35 PM PDT 24 |
3118213451 ps |
| T968 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3761013061 |
|
|
Mar 26 03:52:42 PM PDT 24 |
Mar 26 04:07:41 PM PDT 24 |
5512910712 ps |
| T325 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2141501681 |
|
|
Mar 26 03:48:06 PM PDT 24 |
Mar 26 03:55:50 PM PDT 24 |
4392703788 ps |