| T1125 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1740897345 |
|
|
Mar 26 03:56:06 PM PDT 24 |
Mar 26 04:21:49 PM PDT 24 |
7659894396 ps |
| T618 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4115197506 |
|
|
Mar 26 03:58:38 PM PDT 24 |
Mar 26 04:00:23 PM PDT 24 |
1720580159 ps |
| T1126 |
/workspace/coverage/default/1.chip_sw_flash_init.598977451 |
|
|
Mar 26 03:52:25 PM PDT 24 |
Mar 26 04:20:38 PM PDT 24 |
17596073363 ps |
| T1127 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.53609386 |
|
|
Mar 26 04:01:22 PM PDT 24 |
Mar 26 04:13:25 PM PDT 24 |
6349985462 ps |
| T1128 |
/workspace/coverage/default/2.chip_sw_example_flash.2886429838 |
|
|
Mar 26 03:54:56 PM PDT 24 |
Mar 26 03:58:22 PM PDT 24 |
3257071920 ps |
| T313 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.174396873 |
|
|
Mar 26 03:57:32 PM PDT 24 |
Mar 26 04:14:34 PM PDT 24 |
5756693600 ps |
| T1129 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.559248007 |
|
|
Mar 26 03:59:07 PM PDT 24 |
Mar 26 04:05:46 PM PDT 24 |
3852355848 ps |
| T1130 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1934525350 |
|
|
Mar 26 03:46:45 PM PDT 24 |
Mar 26 03:52:58 PM PDT 24 |
3379307170 ps |
| T690 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.873128708 |
|
|
Mar 26 04:07:49 PM PDT 24 |
Mar 26 04:17:23 PM PDT 24 |
4215360584 ps |
| T657 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4211673670 |
|
|
Mar 26 03:46:52 PM PDT 24 |
Mar 26 04:01:17 PM PDT 24 |
4872835514 ps |
| T1131 |
/workspace/coverage/default/2.chip_sw_power_idle_load.2298236213 |
|
|
Mar 26 04:03:57 PM PDT 24 |
Mar 26 04:12:42 PM PDT 24 |
4822734950 ps |
| T679 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1402991880 |
|
|
Mar 26 04:13:18 PM PDT 24 |
Mar 26 04:26:49 PM PDT 24 |
5875633750 ps |
| T1132 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1816266094 |
|
|
Mar 26 03:53:26 PM PDT 24 |
Mar 26 04:02:49 PM PDT 24 |
4236637997 ps |
| T1133 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3687280994 |
|
|
Mar 26 04:07:51 PM PDT 24 |
Mar 26 04:43:16 PM PDT 24 |
13985531833 ps |
| T1134 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1005971787 |
|
|
Mar 26 04:01:58 PM PDT 24 |
Mar 26 04:17:18 PM PDT 24 |
9192603432 ps |
| T1135 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.121560810 |
|
|
Mar 26 03:45:16 PM PDT 24 |
Mar 26 03:52:32 PM PDT 24 |
4804852912 ps |
| T1136 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.1777825671 |
|
|
Mar 26 03:48:44 PM PDT 24 |
Mar 26 04:15:01 PM PDT 24 |
8600618646 ps |
| T619 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.3756416445 |
|
|
Mar 26 04:06:32 PM PDT 24 |
Mar 26 04:08:17 PM PDT 24 |
2250104799 ps |
| T1137 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3888958426 |
|
|
Mar 26 03:47:23 PM PDT 24 |
Mar 26 03:52:27 PM PDT 24 |
2968057460 ps |
| T1138 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1025266428 |
|
|
Mar 26 04:00:18 PM PDT 24 |
Mar 26 04:06:17 PM PDT 24 |
3259773648 ps |
| T1139 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4235928131 |
|
|
Mar 26 03:46:27 PM PDT 24 |
Mar 26 04:19:41 PM PDT 24 |
24876755784 ps |
| T289 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2778868730 |
|
|
Mar 26 04:03:23 PM PDT 24 |
Mar 26 04:07:22 PM PDT 24 |
2875591450 ps |
| T620 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.3963973219 |
|
|
Mar 26 03:53:53 PM PDT 24 |
Mar 26 03:55:33 PM PDT 24 |
2136278159 ps |
| T1140 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3546195707 |
|
|
Mar 26 04:01:23 PM PDT 24 |
Mar 26 04:09:55 PM PDT 24 |
3485316744 ps |
| T38 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.2855257564 |
|
|
Mar 26 03:45:50 PM PDT 24 |
Mar 26 03:51:51 PM PDT 24 |
3330428882 ps |
| T172 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1115725996 |
|
|
Mar 26 03:50:33 PM PDT 24 |
Mar 26 03:52:47 PM PDT 24 |
3750795691 ps |
| T718 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.110836542 |
|
|
Mar 26 04:11:58 PM PDT 24 |
Mar 26 04:25:14 PM PDT 24 |
5755547092 ps |
| T1141 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2646985403 |
|
|
Mar 26 04:11:28 PM PDT 24 |
Mar 26 04:25:04 PM PDT 24 |
4996284280 ps |
| T752 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.4294303394 |
|
|
Mar 26 04:10:31 PM PDT 24 |
Mar 26 04:22:33 PM PDT 24 |
6458922122 ps |
| T1142 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.115691060 |
|
|
Mar 26 04:10:41 PM PDT 24 |
Mar 26 04:16:46 PM PDT 24 |
3589032456 ps |
| T1143 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.740517112 |
|
|
Mar 26 04:05:01 PM PDT 24 |
Mar 26 04:10:06 PM PDT 24 |
2127580864 ps |
| T1144 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3762127329 |
|
|
Mar 26 03:51:05 PM PDT 24 |
Mar 26 04:25:00 PM PDT 24 |
8151476306 ps |
| T1145 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.1243056230 |
|
|
Mar 26 03:51:33 PM PDT 24 |
Mar 26 04:43:54 PM PDT 24 |
23905632608 ps |
| T1146 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3923033820 |
|
|
Mar 26 03:45:41 PM PDT 24 |
Mar 26 03:55:24 PM PDT 24 |
4368249528 ps |
| T1147 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.4279989541 |
|
|
Mar 26 03:47:58 PM PDT 24 |
Mar 26 03:52:54 PM PDT 24 |
2386180224 ps |
| T1148 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.3508603541 |
|
|
Mar 26 04:08:07 PM PDT 24 |
Mar 26 04:18:40 PM PDT 24 |
5782237960 ps |
| T1149 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.161608452 |
|
|
Mar 26 03:44:58 PM PDT 24 |
Mar 26 04:08:32 PM PDT 24 |
7205204360 ps |
| T1150 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.656853418 |
|
|
Mar 26 03:47:28 PM PDT 24 |
Mar 26 05:26:54 PM PDT 24 |
49408588976 ps |
| T737 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.292619369 |
|
|
Mar 26 04:07:02 PM PDT 24 |
Mar 26 04:19:37 PM PDT 24 |
5745605490 ps |
| T753 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2837339947 |
|
|
Mar 26 04:11:49 PM PDT 24 |
Mar 26 04:17:34 PM PDT 24 |
3430239920 ps |
| T738 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1438545645 |
|
|
Mar 26 04:09:09 PM PDT 24 |
Mar 26 04:16:31 PM PDT 24 |
3771647118 ps |
| T1151 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.921173292 |
|
|
Mar 26 03:46:26 PM PDT 24 |
Mar 26 03:53:25 PM PDT 24 |
6326497675 ps |
| T1152 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.3218816111 |
|
|
Mar 26 04:01:04 PM PDT 24 |
Mar 26 04:04:36 PM PDT 24 |
2617786440 ps |
| T1153 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.196701182 |
|
|
Mar 26 04:01:57 PM PDT 24 |
Mar 26 04:05:41 PM PDT 24 |
2844105624 ps |
| T1154 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1557815001 |
|
|
Mar 26 04:15:53 PM PDT 24 |
Mar 26 04:25:05 PM PDT 24 |
3770119952 ps |
| T1155 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.29350423 |
|
|
Mar 26 03:48:39 PM PDT 24 |
Mar 26 03:57:55 PM PDT 24 |
3517689078 ps |
| T219 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.828530367 |
|
|
Mar 26 03:50:06 PM PDT 24 |
Mar 26 04:46:12 PM PDT 24 |
11647977924 ps |
| T700 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3101903985 |
|
|
Mar 26 04:13:16 PM PDT 24 |
Mar 26 04:21:51 PM PDT 24 |
4345203596 ps |
| T1156 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1581821150 |
|
|
Mar 26 03:47:10 PM PDT 24 |
Mar 26 03:57:42 PM PDT 24 |
5214078776 ps |
| T1157 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2772379205 |
|
|
Mar 26 04:06:17 PM PDT 24 |
Mar 26 04:10:34 PM PDT 24 |
2862269104 ps |
| T1158 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.966314221 |
|
|
Mar 26 03:47:15 PM PDT 24 |
Mar 26 03:51:31 PM PDT 24 |
3264690360 ps |
| T697 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2154791193 |
|
|
Mar 26 04:13:12 PM PDT 24 |
Mar 26 04:24:22 PM PDT 24 |
4345696276 ps |
| T1159 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.828917100 |
|
|
Mar 26 03:48:33 PM PDT 24 |
Mar 26 03:57:58 PM PDT 24 |
4785930800 ps |
| T1160 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.786922503 |
|
|
Mar 26 04:00:16 PM PDT 24 |
Mar 26 04:04:12 PM PDT 24 |
2921716416 ps |
| T216 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1130670866 |
|
|
Mar 26 03:48:27 PM PDT 24 |
Mar 26 03:55:53 PM PDT 24 |
3873008792 ps |
| T695 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2420079669 |
|
|
Mar 26 04:10:19 PM PDT 24 |
Mar 26 04:15:44 PM PDT 24 |
3350457464 ps |
| T1161 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1519015147 |
|
|
Mar 26 04:07:03 PM PDT 24 |
Mar 26 04:55:11 PM PDT 24 |
23406223063 ps |
| T1162 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.806534700 |
|
|
Mar 26 04:14:29 PM PDT 24 |
Mar 26 04:23:58 PM PDT 24 |
3581137468 ps |
| T1163 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2616364472 |
|
|
Mar 26 03:52:17 PM PDT 24 |
Mar 26 04:04:31 PM PDT 24 |
8300640552 ps |
| T1164 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2096171239 |
|
|
Mar 26 03:51:04 PM PDT 24 |
Mar 26 04:33:48 PM PDT 24 |
28143724021 ps |
| T629 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.3432556353 |
|
|
Mar 26 04:04:41 PM PDT 24 |
Mar 26 04:29:27 PM PDT 24 |
4658770520 ps |
| T1165 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3619271750 |
|
|
Mar 26 03:48:25 PM PDT 24 |
Mar 26 07:01:59 PM PDT 24 |
58454746336 ps |
| T1166 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.430970416 |
|
|
Mar 26 04:00:18 PM PDT 24 |
Mar 26 04:05:02 PM PDT 24 |
3073079385 ps |
| T1167 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.3574488138 |
|
|
Mar 26 03:53:34 PM PDT 24 |
Mar 26 04:31:17 PM PDT 24 |
8364846159 ps |
| T238 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2818895485 |
|
|
Mar 26 04:10:05 PM PDT 24 |
Mar 26 04:17:46 PM PDT 24 |
3876071784 ps |
| T1168 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1806780166 |
|
|
Mar 26 03:47:47 PM PDT 24 |
Mar 26 04:20:33 PM PDT 24 |
7782072912 ps |
| T1169 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3922804838 |
|
|
Mar 26 03:48:26 PM PDT 24 |
Mar 26 03:59:26 PM PDT 24 |
6361180062 ps |
| T1170 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3449645125 |
|
|
Mar 26 03:59:55 PM PDT 24 |
Mar 26 05:06:48 PM PDT 24 |
23170518024 ps |
| T1171 |
/workspace/coverage/default/0.chip_sival_flash_info_access.620237028 |
|
|
Mar 26 03:45:25 PM PDT 24 |
Mar 26 03:50:42 PM PDT 24 |
2770619400 ps |
| T664 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3763117323 |
|
|
Mar 26 04:02:08 PM PDT 24 |
Mar 26 04:29:09 PM PDT 24 |
23350042616 ps |
| T1172 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1248144708 |
|
|
Mar 26 03:55:38 PM PDT 24 |
Mar 26 04:46:56 PM PDT 24 |
11937693080 ps |
| T1173 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1212840002 |
|
|
Mar 26 04:00:01 PM PDT 24 |
Mar 26 04:16:28 PM PDT 24 |
5768791482 ps |
| T254 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1983328931 |
|
|
Mar 26 03:46:36 PM PDT 24 |
Mar 26 03:54:02 PM PDT 24 |
4777290310 ps |
| T1174 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2176756232 |
|
|
Mar 26 03:48:09 PM PDT 24 |
Mar 26 04:09:53 PM PDT 24 |
6575199274 ps |
| T1175 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.1612535199 |
|
|
Mar 26 04:09:56 PM PDT 24 |
Mar 26 04:17:52 PM PDT 24 |
3329079524 ps |
| T1176 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.988535539 |
|
|
Mar 26 04:00:28 PM PDT 24 |
Mar 26 04:19:36 PM PDT 24 |
8139207728 ps |
| T630 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.2309714022 |
|
|
Mar 26 03:48:13 PM PDT 24 |
Mar 26 04:09:21 PM PDT 24 |
4913410184 ps |
| T130 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.735564683 |
|
|
Mar 26 04:01:41 PM PDT 24 |
Mar 26 04:09:40 PM PDT 24 |
4684782456 ps |
| T1177 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1726703474 |
|
|
Mar 26 04:11:40 PM PDT 24 |
Mar 26 04:21:27 PM PDT 24 |
5858931832 ps |
| T701 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1146540197 |
|
|
Mar 26 04:12:28 PM PDT 24 |
Mar 26 04:23:40 PM PDT 24 |
5067133580 ps |
| T1178 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3490171192 |
|
|
Mar 26 04:04:34 PM PDT 24 |
Mar 26 04:11:19 PM PDT 24 |
3487203160 ps |
| T1179 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.3704931612 |
|
|
Mar 26 03:45:03 PM PDT 24 |
Mar 26 03:49:11 PM PDT 24 |
2498629589 ps |
| T1180 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1468549092 |
|
|
Mar 26 04:06:42 PM PDT 24 |
Mar 26 04:18:36 PM PDT 24 |
4874329654 ps |
| T1181 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.175752921 |
|
|
Mar 26 04:09:57 PM PDT 24 |
Mar 26 04:48:35 PM PDT 24 |
11826231320 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1583526633 |
|
|
Mar 26 03:46:04 PM PDT 24 |
Mar 26 03:50:28 PM PDT 24 |
3183659776 ps |
| T681 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.4151250681 |
|
|
Mar 26 04:14:08 PM PDT 24 |
Mar 26 04:28:25 PM PDT 24 |
5433491726 ps |
| T1182 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.2438011158 |
|
|
Mar 26 03:56:45 PM PDT 24 |
Mar 26 04:34:33 PM PDT 24 |
8488588288 ps |
| T1183 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3064494551 |
|
|
Mar 26 03:46:31 PM PDT 24 |
Mar 26 04:10:04 PM PDT 24 |
15312007556 ps |
| T1184 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.603051887 |
|
|
Mar 26 03:52:30 PM PDT 24 |
Mar 26 04:15:21 PM PDT 24 |
7169507466 ps |
| T694 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1852523926 |
|
|
Mar 26 04:13:09 PM PDT 24 |
Mar 26 04:27:32 PM PDT 24 |
6651667432 ps |
| T1185 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.622919936 |
|
|
Mar 26 04:03:53 PM PDT 24 |
Mar 26 04:13:08 PM PDT 24 |
5366487200 ps |
| T1186 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2264830738 |
|
|
Mar 26 03:52:42 PM PDT 24 |
Mar 26 04:14:51 PM PDT 24 |
8244995600 ps |
| T1187 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.691119174 |
|
|
Mar 26 03:50:04 PM PDT 24 |
Mar 26 04:00:20 PM PDT 24 |
3699268996 ps |
| T720 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1452839034 |
|
|
Mar 26 04:11:13 PM PDT 24 |
Mar 26 04:24:02 PM PDT 24 |
5380826880 ps |
| T290 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.764367096 |
|
|
Mar 26 04:06:57 PM PDT 24 |
Mar 26 04:10:11 PM PDT 24 |
2585644000 ps |
| T1188 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.703023942 |
|
|
Mar 26 03:47:22 PM PDT 24 |
Mar 26 03:51:00 PM PDT 24 |
2414400610 ps |
| T1189 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.624469805 |
|
|
Mar 26 04:04:56 PM PDT 24 |
Mar 26 04:09:27 PM PDT 24 |
3367256991 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2969627676 |
|
|
Mar 26 04:01:20 PM PDT 24 |
Mar 26 04:16:31 PM PDT 24 |
7832441408 ps |
| T1191 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2430490693 |
|
|
Mar 26 03:55:33 PM PDT 24 |
Mar 26 04:33:30 PM PDT 24 |
8971272450 ps |
| T1192 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3579000610 |
|
|
Mar 26 03:52:15 PM PDT 24 |
Mar 26 03:55:34 PM PDT 24 |
2781874588 ps |
| T1193 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.3948525414 |
|
|
Mar 26 04:09:29 PM PDT 24 |
Mar 26 05:01:26 PM PDT 24 |
26684472688 ps |
| T1194 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2261889662 |
|
|
Mar 26 04:01:14 PM PDT 24 |
Mar 26 04:10:56 PM PDT 24 |
4744603436 ps |
| T255 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3045151680 |
|
|
Mar 26 04:11:02 PM PDT 24 |
Mar 26 04:17:44 PM PDT 24 |
5282160968 ps |
| T1195 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2417861409 |
|
|
Mar 26 03:47:20 PM PDT 24 |
Mar 26 03:52:35 PM PDT 24 |
2683591130 ps |
| T710 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3976200881 |
|
|
Mar 26 04:12:33 PM PDT 24 |
Mar 26 04:18:45 PM PDT 24 |
3567258824 ps |
| T209 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3497079172 |
|
|
Mar 26 03:56:53 PM PDT 24 |
Mar 26 04:07:21 PM PDT 24 |
4800413970 ps |
| T1196 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1272877734 |
|
|
Mar 26 03:46:31 PM PDT 24 |
Mar 26 03:57:12 PM PDT 24 |
8200120294 ps |
| T1197 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3145756426 |
|
|
Mar 26 04:09:06 PM PDT 24 |
Mar 26 05:02:23 PM PDT 24 |
22446326974 ps |
| T297 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2152681793 |
|
|
Mar 26 03:47:38 PM PDT 24 |
Mar 26 04:00:30 PM PDT 24 |
6270090400 ps |
| T676 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.2247666029 |
|
|
Mar 26 04:09:25 PM PDT 24 |
Mar 26 04:17:29 PM PDT 24 |
4896390150 ps |
| T1198 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1088249324 |
|
|
Mar 26 03:48:38 PM PDT 24 |
Mar 26 03:59:57 PM PDT 24 |
4327890120 ps |
| T1199 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2480376300 |
|
|
Mar 26 04:11:40 PM PDT 24 |
Mar 26 04:24:30 PM PDT 24 |
5829904940 ps |
| T703 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1676728012 |
|
|
Mar 26 04:15:53 PM PDT 24 |
Mar 26 04:22:20 PM PDT 24 |
3620063566 ps |
| T1200 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2898553269 |
|
|
Mar 26 03:47:48 PM PDT 24 |
Mar 26 04:08:21 PM PDT 24 |
5372404056 ps |
| T1201 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2423413092 |
|
|
Mar 26 03:51:44 PM PDT 24 |
Mar 26 03:57:19 PM PDT 24 |
4253595850 ps |
| T702 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1231863531 |
|
|
Mar 26 04:09:14 PM PDT 24 |
Mar 26 04:14:18 PM PDT 24 |
3324920970 ps |
| T1202 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.120926217 |
|
|
Mar 26 03:48:02 PM PDT 24 |
Mar 26 03:57:30 PM PDT 24 |
5976025955 ps |
| T1203 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.2842599428 |
|
|
Mar 26 03:55:09 PM PDT 24 |
Mar 26 04:29:48 PM PDT 24 |
8870225312 ps |
| T1204 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.211481821 |
|
|
Mar 26 03:56:53 PM PDT 24 |
Mar 26 04:12:29 PM PDT 24 |
4701545286 ps |
| T1205 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3888679715 |
|
|
Mar 26 03:49:17 PM PDT 24 |
Mar 26 03:52:51 PM PDT 24 |
1942857940 ps |
| T1206 |
/workspace/coverage/default/1.chip_sw_example_flash.2958730233 |
|
|
Mar 26 03:50:45 PM PDT 24 |
Mar 26 03:53:16 PM PDT 24 |
2950005432 ps |
| T1207 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1444617673 |
|
|
Mar 26 04:06:11 PM PDT 24 |
Mar 26 04:11:54 PM PDT 24 |
3134262118 ps |
| T337 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2934831079 |
|
|
Mar 26 03:47:26 PM PDT 24 |
Mar 26 03:59:45 PM PDT 24 |
4710007254 ps |
| T1208 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1088798469 |
|
|
Mar 26 03:51:16 PM PDT 24 |
Mar 26 03:59:04 PM PDT 24 |
3351327552 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.873968725 |
|
|
Mar 26 03:45:38 PM PDT 24 |
Mar 26 04:12:40 PM PDT 24 |
8267147290 ps |
| T716 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3317376275 |
|
|
Mar 26 04:10:27 PM PDT 24 |
Mar 26 04:16:48 PM PDT 24 |
3316548792 ps |
| T1210 |
/workspace/coverage/default/1.chip_sw_kmac_idle.1690295476 |
|
|
Mar 26 03:52:53 PM PDT 24 |
Mar 26 03:56:49 PM PDT 24 |
3351131602 ps |
| T1211 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1101803049 |
|
|
Mar 26 03:51:42 PM PDT 24 |
Mar 26 03:58:17 PM PDT 24 |
3839670040 ps |
| T291 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.237007794 |
|
|
Mar 26 03:45:45 PM PDT 24 |
Mar 26 03:49:54 PM PDT 24 |
3235393358 ps |
| T1212 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3964942252 |
|
|
Mar 26 03:48:17 PM PDT 24 |
Mar 26 07:35:10 PM PDT 24 |
79300737363 ps |
| T706 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4189935118 |
|
|
Mar 26 04:11:13 PM PDT 24 |
Mar 26 04:16:17 PM PDT 24 |
3312937984 ps |
| T1213 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.725809740 |
|
|
Mar 26 03:49:50 PM PDT 24 |
Mar 26 03:56:23 PM PDT 24 |
3209539190 ps |
| T1214 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.322515026 |
|
|
Mar 26 04:01:14 PM PDT 24 |
Mar 26 04:10:29 PM PDT 24 |
4756897352 ps |
| T1215 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2896477928 |
|
|
Mar 26 03:47:58 PM PDT 24 |
Mar 26 03:51:27 PM PDT 24 |
3323694849 ps |
| T740 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.2087989908 |
|
|
Mar 26 04:07:30 PM PDT 24 |
Mar 26 04:19:16 PM PDT 24 |
4616871804 ps |
| T1216 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2834914213 |
|
|
Mar 26 03:51:37 PM PDT 24 |
Mar 26 04:00:00 PM PDT 24 |
3993210088 ps |
| T1217 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.721819642 |
|
|
Mar 26 04:05:28 PM PDT 24 |
Mar 26 04:08:42 PM PDT 24 |
2808340886 ps |
| T1218 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2521557499 |
|
|
Mar 26 03:53:24 PM PDT 24 |
Mar 26 03:59:12 PM PDT 24 |
3596399723 ps |
| T1219 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2707134496 |
|
|
Mar 26 04:02:24 PM PDT 24 |
Mar 26 04:11:49 PM PDT 24 |
4843482428 ps |
| T1220 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.809039657 |
|
|
Mar 26 03:46:50 PM PDT 24 |
Mar 26 03:59:41 PM PDT 24 |
5822657632 ps |
| T90 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3314246925 |
|
|
Mar 26 04:09:18 PM PDT 24 |
Mar 26 04:14:36 PM PDT 24 |
2917200204 ps |
| T1221 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1705765269 |
|
|
Mar 26 04:13:26 PM PDT 24 |
Mar 26 04:22:29 PM PDT 24 |
5502356380 ps |
| T1222 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.4108816312 |
|
|
Mar 26 03:55:33 PM PDT 24 |
Mar 26 04:44:36 PM PDT 24 |
11593200873 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3964225848 |
|
|
Mar 26 03:45:53 PM PDT 24 |
Mar 26 04:00:27 PM PDT 24 |
5442464037 ps |
| T1224 |
/workspace/coverage/default/0.chip_sw_power_idle_load.1499529169 |
|
|
Mar 26 03:50:08 PM PDT 24 |
Mar 26 03:59:59 PM PDT 24 |
4195039480 ps |
| T1225 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1823663959 |
|
|
Mar 26 04:03:15 PM PDT 24 |
Mar 26 04:09:43 PM PDT 24 |
3262218063 ps |
| T1226 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3128216808 |
|
|
Mar 26 03:58:43 PM PDT 24 |
Mar 26 04:19:16 PM PDT 24 |
5919986163 ps |
| T63 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.3960813654 |
|
|
Mar 26 03:48:52 PM PDT 24 |
Mar 26 03:53:51 PM PDT 24 |
3414848232 ps |
| T1227 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2014906671 |
|
|
Mar 26 04:13:20 PM PDT 24 |
Mar 26 04:21:44 PM PDT 24 |
4843744142 ps |
| T1228 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3059065534 |
|
|
Mar 26 04:07:24 PM PDT 24 |
Mar 26 04:39:57 PM PDT 24 |
12864291276 ps |
| T1229 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1806301586 |
|
|
Mar 26 03:47:19 PM PDT 24 |
Mar 26 03:49:12 PM PDT 24 |
2183173070 ps |
| T1230 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4062694225 |
|
|
Mar 26 04:13:06 PM PDT 24 |
Mar 26 04:46:51 PM PDT 24 |
13211047407 ps |
| T173 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.490434171 |
|
|
Mar 26 04:00:33 PM PDT 24 |
Mar 26 04:05:23 PM PDT 24 |
3542996696 ps |
| T743 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.3380876616 |
|
|
Mar 26 03:48:37 PM PDT 24 |
Mar 26 04:00:23 PM PDT 24 |
6096471176 ps |
| T721 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2586850219 |
|
|
Mar 26 04:06:42 PM PDT 24 |
Mar 26 04:12:40 PM PDT 24 |
3601663244 ps |
| T1231 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1666995744 |
|
|
Mar 26 03:54:54 PM PDT 24 |
Mar 26 04:34:01 PM PDT 24 |
9405224687 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2899771805 |
|
|
Mar 26 04:03:23 PM PDT 24 |
Mar 26 04:14:36 PM PDT 24 |
4148452530 ps |
| T1233 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.2868495881 |
|
|
Mar 26 03:46:19 PM PDT 24 |
Mar 26 04:00:15 PM PDT 24 |
5694102621 ps |
| T1234 |
/workspace/coverage/default/4.chip_tap_straps_dev.2630000303 |
|
|
Mar 26 04:06:37 PM PDT 24 |
Mar 26 04:15:23 PM PDT 24 |
6022907634 ps |
| T1235 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.3657713934 |
|
|
Mar 26 03:54:44 PM PDT 24 |
Mar 26 03:59:01 PM PDT 24 |
2618944902 ps |
| T755 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1475558918 |
|
|
Mar 26 03:49:51 PM PDT 24 |
Mar 26 03:57:59 PM PDT 24 |
4034481046 ps |
| T1236 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3119785242 |
|
|
Mar 26 04:10:00 PM PDT 24 |
Mar 26 04:19:56 PM PDT 24 |
4963605200 ps |
| T666 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2091848363 |
|
|
Mar 26 04:07:21 PM PDT 24 |
Mar 26 04:17:36 PM PDT 24 |
5834460572 ps |
| T1237 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2455745527 |
|
|
Mar 26 03:57:58 PM PDT 24 |
Mar 26 04:10:26 PM PDT 24 |
4397809096 ps |
| T91 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2555901422 |
|
|
Mar 26 04:11:40 PM PDT 24 |
Mar 26 04:23:52 PM PDT 24 |
5907565416 ps |
| T1238 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3872290192 |
|
|
Mar 26 04:07:01 PM PDT 24 |
Mar 26 04:19:26 PM PDT 24 |
5334681421 ps |
| T1239 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.62718178 |
|
|
Mar 26 03:50:42 PM PDT 24 |
Mar 26 03:57:37 PM PDT 24 |
4091485956 ps |
| T1240 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3047860113 |
|
|
Mar 26 03:49:34 PM PDT 24 |
Mar 26 03:55:35 PM PDT 24 |
4267918872 ps |
| T1241 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2429796305 |
|
|
Mar 26 03:47:34 PM PDT 24 |
Mar 26 04:00:35 PM PDT 24 |
7367106914 ps |
| T711 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.441872312 |
|
|
Mar 26 04:08:37 PM PDT 24 |
Mar 26 04:14:39 PM PDT 24 |
3395889026 ps |
| T1242 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.1622206434 |
|
|
Mar 26 04:02:23 PM PDT 24 |
Mar 26 04:35:21 PM PDT 24 |
8624597164 ps |
| T1243 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3792093877 |
|
|
Mar 26 03:50:51 PM PDT 24 |
Mar 26 03:53:29 PM PDT 24 |
2572660129 ps |
| T1244 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.1346751021 |
|
|
Mar 26 04:03:01 PM PDT 24 |
Mar 26 04:08:42 PM PDT 24 |
2793590672 ps |
| T1245 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3086381191 |
|
|
Mar 26 03:46:34 PM PDT 24 |
Mar 26 03:59:39 PM PDT 24 |
5145043116 ps |
| T1246 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2007559240 |
|
|
Mar 26 03:50:30 PM PDT 24 |
Mar 26 04:01:44 PM PDT 24 |
5241551488 ps |
| T1247 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1103151621 |
|
|
Mar 26 03:58:58 PM PDT 24 |
Mar 26 05:31:17 PM PDT 24 |
50233104673 ps |
| T1248 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2088926099 |
|
|
Mar 26 03:47:31 PM PDT 24 |
Mar 26 03:56:34 PM PDT 24 |
4047389350 ps |
| T1249 |
/workspace/coverage/default/1.chip_sw_aes_idle.1044641455 |
|
|
Mar 26 03:51:02 PM PDT 24 |
Mar 26 03:54:23 PM PDT 24 |
2079821250 ps |
| T413 |
/workspace/coverage/default/2.chip_jtag_mem_access.2302373569 |
|
|
Mar 26 03:55:27 PM PDT 24 |
Mar 26 04:19:52 PM PDT 24 |
13674924375 ps |
| T256 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3036882455 |
|
|
Mar 26 03:53:49 PM PDT 24 |
Mar 26 04:02:27 PM PDT 24 |
4920751880 ps |
| T1250 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.561137728 |
|
|
Mar 26 03:57:53 PM PDT 24 |
Mar 26 04:55:11 PM PDT 24 |
11416722426 ps |
| T1251 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.697594246 |
|
|
Mar 26 03:46:35 PM PDT 24 |
Mar 26 03:51:17 PM PDT 24 |
3189057340 ps |
| T1252 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.662106727 |
|
|
Mar 26 03:48:02 PM PDT 24 |
Mar 26 04:06:54 PM PDT 24 |
9901104440 ps |
| T1253 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3997836727 |
|
|
Mar 26 03:50:39 PM PDT 24 |
Mar 26 03:54:08 PM PDT 24 |
1907033680 ps |
| T1254 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2584060775 |
|
|
Mar 26 03:53:05 PM PDT 24 |
Mar 26 04:00:09 PM PDT 24 |
4297930424 ps |
| T92 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3453242157 |
|
|
Mar 26 04:12:32 PM PDT 24 |
Mar 26 04:20:41 PM PDT 24 |
3392004248 ps |
| T1255 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3598843417 |
|
|
Mar 26 03:47:57 PM PDT 24 |
Mar 26 03:50:16 PM PDT 24 |
2528196892 ps |
| T72 |
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3466602610 |
|
|
Mar 26 04:14:54 PM PDT 24 |
Mar 26 04:31:43 PM PDT 24 |
53878358197 ps |
| T73 |
/workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.3311433973 |
|
|
Mar 26 04:20:05 PM PDT 24 |
Mar 26 04:30:30 PM PDT 24 |
35241887487 ps |
| T74 |
/workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.4056889281 |
|
|
Mar 26 04:17:34 PM PDT 24 |
Mar 26 04:19:19 PM PDT 24 |
9253887043 ps |
| T126 |
/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1875459746 |
|
|
Mar 26 04:26:43 PM PDT 24 |
Mar 26 04:28:24 PM PDT 24 |
425173647 ps |
| T239 |
/workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.2247501574 |
|
|
Mar 26 04:26:56 PM PDT 24 |
Mar 26 04:27:13 PM PDT 24 |
178217315 ps |
| T506 |
/workspace/coverage/cover_reg_top/8.chip_tl_errors.713292099 |
|
|
Mar 26 04:12:42 PM PDT 24 |
Mar 26 04:15:30 PM PDT 24 |
2826109830 ps |
| T141 |
/workspace/coverage/cover_reg_top/4.chip_csr_rw.3655373997 |
|
|
Mar 26 04:11:06 PM PDT 24 |
Mar 26 04:22:07 PM PDT 24 |
5700267576 ps |
| T510 |
/workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.1461083705 |
|
|
Mar 26 04:30:11 PM PDT 24 |
Mar 26 04:34:32 PM PDT 24 |
14220324376 ps |
| T442 |
/workspace/coverage/cover_reg_top/17.xbar_same_source.3465653387 |
|
|
Mar 26 04:16:18 PM PDT 24 |
Mar 26 04:17:47 PM PDT 24 |
2473689864 ps |
| T507 |
/workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2806532672 |
|
|
Mar 26 04:26:53 PM PDT 24 |
Mar 26 05:15:15 PM PDT 24 |
164101843809 ps |
| T686 |
/workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.2131325751 |
|
|
Mar 26 04:25:04 PM PDT 24 |
Mar 26 04:42:48 PM PDT 24 |
56718391828 ps |
| T421 |
/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.295664299 |
|
|
Mar 26 04:28:07 PM PDT 24 |
Mar 26 04:32:25 PM PDT 24 |
3902129801 ps |
| T508 |
/workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.82779907 |
|
|
Mar 26 04:28:52 PM PDT 24 |
Mar 26 04:42:18 PM PDT 24 |
42843745628 ps |
| T509 |
/workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.3208792551 |
|
|
Mar 26 04:27:44 PM PDT 24 |
Mar 26 04:27:58 PM PDT 24 |
128097226 ps |
| T476 |
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2449385861 |
|
|
Mar 26 04:15:44 PM PDT 24 |
Mar 26 04:22:24 PM PDT 24 |
1584796540 ps |
| T390 |
/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.2427595155 |
|
|
Mar 26 04:26:42 PM PDT 24 |
Mar 26 04:32:44 PM PDT 24 |
3545882225 ps |
| T398 |
/workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.1365467282 |
|
|
Mar 26 04:09:09 PM PDT 24 |
Mar 26 04:18:49 PM PDT 24 |
33585515350 ps |
| T426 |
/workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.1721176358 |
|
|
Mar 26 04:19:06 PM PDT 24 |
Mar 26 04:29:36 PM PDT 24 |
36573785875 ps |
| T422 |
/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3584448158 |
|
|
Mar 26 04:12:06 PM PDT 24 |
Mar 26 04:20:56 PM PDT 24 |
9379255018 ps |
| T461 |
/workspace/coverage/cover_reg_top/41.xbar_random.3593968077 |
|
|
Mar 26 04:21:28 PM PDT 24 |
Mar 26 04:22:33 PM PDT 24 |
1806281613 ps |
| T433 |
/workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2637019534 |
|
|
Mar 26 04:22:50 PM PDT 24 |
Mar 26 04:35:15 PM PDT 24 |
41191639680 ps |
| T389 |
/workspace/coverage/cover_reg_top/86.xbar_stress_all.1230721587 |
|
|
Mar 26 04:28:41 PM PDT 24 |
Mar 26 04:32:04 PM PDT 24 |
2153373940 ps |
| T423 |
/workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.485351094 |
|
|
Mar 26 04:30:31 PM PDT 24 |
Mar 26 04:30:56 PM PDT 24 |
567717539 ps |
| T531 |
/workspace/coverage/cover_reg_top/57.xbar_same_source.2918887515 |
|
|
Mar 26 04:24:03 PM PDT 24 |
Mar 26 04:24:42 PM PDT 24 |
472831955 ps |
| T397 |
/workspace/coverage/cover_reg_top/65.xbar_same_source.1831094799 |
|
|
Mar 26 04:25:01 PM PDT 24 |
Mar 26 04:25:38 PM PDT 24 |
1030544201 ps |
| T668 |
/workspace/coverage/cover_reg_top/49.xbar_error_random.2930711121 |
|
|
Mar 26 04:22:49 PM PDT 24 |
Mar 26 04:23:29 PM PDT 24 |
943028943 ps |
| T1256 |
/workspace/coverage/cover_reg_top/62.xbar_error_random.2039584237 |
|
|
Mar 26 04:24:42 PM PDT 24 |
Mar 26 04:25:15 PM PDT 24 |
781868853 ps |
| T464 |
/workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.2023383025 |
|
|
Mar 26 04:20:31 PM PDT 24 |
Mar 26 04:29:39 PM PDT 24 |
29915638016 ps |
| T511 |
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.840251781 |
|
|
Mar 26 04:16:27 PM PDT 24 |
Mar 26 04:22:25 PM PDT 24 |
4505877511 ps |
| T535 |
/workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.1324356579 |
|
|
Mar 26 04:27:39 PM PDT 24 |
Mar 26 04:37:07 PM PDT 24 |
32479794607 ps |
| T1257 |
/workspace/coverage/cover_reg_top/2.xbar_error_random.3388236263 |
|
|
Mar 26 04:09:30 PM PDT 24 |
Mar 26 04:10:18 PM PDT 24 |
511041884 ps |
| T592 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2898692573 |
|
|
Mar 26 04:15:05 PM PDT 24 |
Mar 26 04:27:17 PM PDT 24 |
7248490851 ps |
| T623 |
/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1931349944 |
|
|
Mar 26 04:17:23 PM PDT 24 |
Mar 26 04:21:00 PM PDT 24 |
3365850707 ps |
| T667 |
/workspace/coverage/cover_reg_top/35.xbar_error_random.2643724724 |
|
|
Mar 26 04:20:29 PM PDT 24 |
Mar 26 04:22:08 PM PDT 24 |
2222141972 ps |
| T781 |
/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3122738379 |
|
|
Mar 26 04:21:58 PM PDT 24 |
Mar 26 04:44:17 PM PDT 24 |
76242815865 ps |
| T1258 |
/workspace/coverage/cover_reg_top/76.xbar_smoke.86774655 |
|
|
Mar 26 04:26:51 PM PDT 24 |
Mar 26 04:26:58 PM PDT 24 |
53447070 ps |
| T824 |
/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.363158280 |
|
|
Mar 26 04:22:28 PM PDT 24 |
Mar 26 04:22:41 PM PDT 24 |
19820614 ps |
| T1259 |
/workspace/coverage/cover_reg_top/97.xbar_error_random.2962816812 |
|
|
Mar 26 04:30:12 PM PDT 24 |
Mar 26 04:31:14 PM PDT 24 |
1786984394 ps |
| T1260 |
/workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2797758639 |
|
|
Mar 26 04:20:32 PM PDT 24 |
Mar 26 04:20:58 PM PDT 24 |
192481021 ps |
| T580 |
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3881818335 |
|
|
Mar 26 04:14:22 PM PDT 24 |
Mar 26 04:14:50 PM PDT 24 |
233067509 ps |
| T773 |
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3635858208 |
|
|
Mar 26 04:14:30 PM PDT 24 |
Mar 26 04:16:01 PM PDT 24 |
1647785371 ps |
| T469 |
/workspace/coverage/cover_reg_top/29.xbar_random_large_delays.2543761060 |
|
|
Mar 26 04:19:13 PM PDT 24 |
Mar 26 04:34:16 PM PDT 24 |
84584366110 ps |
| T434 |
/workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.2307910175 |
|
|
Mar 26 04:23:40 PM PDT 24 |
Mar 26 04:23:48 PM PDT 24 |
64270964 ps |
| T483 |
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3156659510 |
|
|
Mar 26 04:14:30 PM PDT 24 |
Mar 26 04:25:57 PM PDT 24 |
34721518408 ps |
| T637 |
/workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2102547438 |
|
|
Mar 26 04:09:27 PM PDT 24 |
Mar 26 04:21:05 PM PDT 24 |
38851523989 ps |
| T405 |
/workspace/coverage/cover_reg_top/41.xbar_stress_all.1622065103 |
|
|
Mar 26 04:21:30 PM PDT 24 |
Mar 26 04:24:26 PM PDT 24 |
1879248208 ps |
| T487 |
/workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1940791705 |
|
|
Mar 26 04:23:11 PM PDT 24 |
Mar 26 04:23:36 PM PDT 24 |
516197259 ps |
| T581 |
/workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.2045755552 |
|
|
Mar 26 04:17:17 PM PDT 24 |
Mar 26 04:18:35 PM PDT 24 |
7414121187 ps |
| T1261 |
/workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3756737564 |
|
|
Mar 26 04:23:38 PM PDT 24 |
Mar 26 04:23:46 PM PDT 24 |
56156838 ps |
| T1262 |
/workspace/coverage/cover_reg_top/51.xbar_smoke.1363180639 |
|
|
Mar 26 04:23:08 PM PDT 24 |
Mar 26 04:23:14 PM PDT 24 |
42048362 ps |
| T576 |
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2987231170 |
|
|
Mar 26 04:14:56 PM PDT 24 |
Mar 26 04:15:28 PM PDT 24 |
286648174 ps |
| T1263 |
/workspace/coverage/cover_reg_top/26.xbar_smoke.2325475001 |
|
|
Mar 26 04:18:33 PM PDT 24 |
Mar 26 04:18:43 PM PDT 24 |
228537924 ps |
| T396 |
/workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2016694001 |
|
|
Mar 26 04:17:55 PM PDT 24 |
Mar 26 04:21:36 PM PDT 24 |
20110210050 ps |
| T797 |
/workspace/coverage/cover_reg_top/40.xbar_access_same_device.1137328303 |
|
|
Mar 26 04:21:17 PM PDT 24 |
Mar 26 04:21:46 PM PDT 24 |
186172779 ps |
| T525 |
/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1057053605 |
|
|
Mar 26 04:26:26 PM PDT 24 |
Mar 26 04:27:35 PM PDT 24 |
1070171382 ps |
| T458 |
/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2192236991 |
|
|
Mar 26 04:24:52 PM PDT 24 |
Mar 26 04:49:38 PM PDT 24 |
90423856702 ps |
| T624 |
/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.123931279 |
|
|
Mar 26 04:27:45 PM PDT 24 |
Mar 26 04:30:09 PM PDT 24 |
3944286382 ps |
| T1264 |
/workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.900370541 |
|
|
Mar 26 04:21:01 PM PDT 24 |
Mar 26 04:22:16 PM PDT 24 |
6955914183 ps |
| T774 |
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2367555550 |
|
|
Mar 26 04:08:16 PM PDT 24 |
Mar 26 04:38:04 PM PDT 24 |
101748528251 ps |
| T607 |
/workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.4279981093 |
|
|
Mar 26 04:18:34 PM PDT 24 |
Mar 26 04:19:04 PM PDT 24 |
633204060 ps |
| T625 |
/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1539282586 |
|
|
Mar 26 04:20:13 PM PDT 24 |
Mar 26 04:27:39 PM PDT 24 |
8468783096 ps |
| T1265 |
/workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1039032059 |
|
|
Mar 26 04:20:02 PM PDT 24 |
Mar 26 04:21:04 PM PDT 24 |
3517610852 ps |
| T550 |
/workspace/coverage/cover_reg_top/71.xbar_random.4070216303 |
|
|
Mar 26 04:26:26 PM PDT 24 |
Mar 26 04:28:23 PM PDT 24 |
2667194542 ps |