| T150 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3817660430 |
|
|
Mar 26 03:47:55 PM PDT 24 |
Mar 26 03:55:58 PM PDT 24 |
4265261006 ps |
| T969 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1277289738 |
|
|
Mar 26 03:59:59 PM PDT 24 |
Mar 26 04:13:28 PM PDT 24 |
5490622600 ps |
| T691 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1409806815 |
|
|
Mar 26 04:11:33 PM PDT 24 |
Mar 26 04:22:56 PM PDT 24 |
5508782760 ps |
| T970 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3040528903 |
|
|
Mar 26 03:54:45 PM PDT 24 |
Mar 26 04:01:05 PM PDT 24 |
4232721700 ps |
| T971 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.4264690775 |
|
|
Mar 26 03:48:00 PM PDT 24 |
Mar 26 03:55:38 PM PDT 24 |
5408608436 ps |
| T972 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1583588118 |
|
|
Mar 26 03:54:14 PM PDT 24 |
Mar 26 04:26:27 PM PDT 24 |
8355571584 ps |
| T642 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2543158836 |
|
|
Mar 26 03:48:37 PM PDT 24 |
Mar 26 03:53:20 PM PDT 24 |
2315583000 ps |
| T973 |
/workspace/coverage/default/1.chip_sw_aes_entropy.4062331483 |
|
|
Mar 26 03:47:54 PM PDT 24 |
Mar 26 03:52:15 PM PDT 24 |
2487865080 ps |
| T722 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.523301506 |
|
|
Mar 26 04:08:25 PM PDT 24 |
Mar 26 04:14:35 PM PDT 24 |
3275760202 ps |
| T734 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3586487505 |
|
|
Mar 26 04:09:47 PM PDT 24 |
Mar 26 04:17:10 PM PDT 24 |
3320271648 ps |
| T974 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.263227205 |
|
|
Mar 26 04:00:56 PM PDT 24 |
Mar 26 04:19:29 PM PDT 24 |
6187524172 ps |
| T975 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2133956792 |
|
|
Mar 26 03:59:30 PM PDT 24 |
Mar 26 04:18:52 PM PDT 24 |
7544109902 ps |
| T643 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4019594793 |
|
|
Mar 26 03:54:02 PM PDT 24 |
Mar 26 03:57:45 PM PDT 24 |
2836165560 ps |
| T361 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3823856879 |
|
|
Mar 26 03:48:04 PM PDT 24 |
Mar 26 03:50:12 PM PDT 24 |
2437574592 ps |
| T976 |
/workspace/coverage/default/2.rom_e2e_smoke.2770024759 |
|
|
Mar 26 04:06:02 PM PDT 24 |
Mar 26 04:39:40 PM PDT 24 |
8521227268 ps |
| T51 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1662430275 |
|
|
Mar 26 03:52:37 PM PDT 24 |
Mar 26 03:58:17 PM PDT 24 |
3624024456 ps |
| T746 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4256198935 |
|
|
Mar 26 04:09:50 PM PDT 24 |
Mar 26 04:16:10 PM PDT 24 |
3450125800 ps |
| T731 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871610735 |
|
|
Mar 26 04:10:50 PM PDT 24 |
Mar 26 04:18:19 PM PDT 24 |
3566946204 ps |
| T977 |
/workspace/coverage/default/2.chip_sw_kmac_idle.1687468061 |
|
|
Mar 26 04:04:23 PM PDT 24 |
Mar 26 04:09:36 PM PDT 24 |
2776959190 ps |
| T978 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2100437099 |
|
|
Mar 26 04:01:42 PM PDT 24 |
Mar 26 04:11:35 PM PDT 24 |
3941895336 ps |
| T979 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1786057269 |
|
|
Mar 26 03:51:12 PM PDT 24 |
Mar 26 04:03:27 PM PDT 24 |
4922468152 ps |
| T980 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.1400442321 |
|
|
Mar 26 03:55:12 PM PDT 24 |
Mar 26 04:33:37 PM PDT 24 |
8781286924 ps |
| T981 |
/workspace/coverage/default/4.chip_tap_straps_prod.1370933037 |
|
|
Mar 26 04:06:29 PM PDT 24 |
Mar 26 04:27:29 PM PDT 24 |
11964285413 ps |
| T982 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.2689794506 |
|
|
Mar 26 03:49:35 PM PDT 24 |
Mar 26 04:06:50 PM PDT 24 |
5878814840 ps |
| T153 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.4059231164 |
|
|
Mar 26 03:47:01 PM PDT 24 |
Mar 26 03:52:08 PM PDT 24 |
3341063289 ps |
| T983 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.4066773478 |
|
|
Mar 26 04:00:19 PM PDT 24 |
Mar 26 04:10:14 PM PDT 24 |
5950352580 ps |
| T984 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.4261260639 |
|
|
Mar 26 03:50:13 PM PDT 24 |
Mar 26 03:54:45 PM PDT 24 |
3483058274 ps |
| T985 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1249871259 |
|
|
Mar 26 03:47:03 PM PDT 24 |
Mar 26 03:57:06 PM PDT 24 |
3353339560 ps |
| T724 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2206158227 |
|
|
Mar 26 04:08:02 PM PDT 24 |
Mar 26 04:15:48 PM PDT 24 |
3370559980 ps |
| T671 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4031096167 |
|
|
Mar 26 03:48:04 PM PDT 24 |
Mar 26 04:45:01 PM PDT 24 |
20399873809 ps |
| T759 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.190608469 |
|
|
Mar 26 04:11:41 PM PDT 24 |
Mar 26 04:18:18 PM PDT 24 |
3794239164 ps |
| T986 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1442723154 |
|
|
Mar 26 03:54:07 PM PDT 24 |
Mar 26 03:57:09 PM PDT 24 |
2874048612 ps |
| T244 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1565345132 |
|
|
Mar 26 04:04:34 PM PDT 24 |
Mar 26 04:13:34 PM PDT 24 |
4199111520 ps |
| T322 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.2910344446 |
|
|
Mar 26 03:55:46 PM PDT 24 |
Mar 26 04:11:17 PM PDT 24 |
5582964102 ps |
| T987 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.907131949 |
|
|
Mar 26 03:48:30 PM PDT 24 |
Mar 26 04:05:49 PM PDT 24 |
5020257046 ps |
| T27 |
/workspace/coverage/default/2.chip_sw_gpio.1938861346 |
|
|
Mar 26 03:56:40 PM PDT 24 |
Mar 26 04:03:59 PM PDT 24 |
3828580330 ps |
| T140 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.4256364400 |
|
|
Mar 26 04:02:22 PM PDT 24 |
Mar 26 04:11:05 PM PDT 24 |
8541601334 ps |
| T988 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1874049029 |
|
|
Mar 26 03:56:07 PM PDT 24 |
Mar 26 04:32:25 PM PDT 24 |
8767480936 ps |
| T226 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.705822572 |
|
|
Mar 26 04:03:16 PM PDT 24 |
Mar 26 04:37:18 PM PDT 24 |
27511241081 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1943454158 |
|
|
Mar 26 03:56:45 PM PDT 24 |
Mar 26 04:07:30 PM PDT 24 |
5153263432 ps |
| T990 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3725460073 |
|
|
Mar 26 03:50:35 PM PDT 24 |
Mar 26 03:56:36 PM PDT 24 |
3184187792 ps |
| T991 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2910637014 |
|
|
Mar 26 04:08:30 PM PDT 24 |
Mar 26 04:46:36 PM PDT 24 |
13810340818 ps |
| T992 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.139082878 |
|
|
Mar 26 03:47:07 PM PDT 24 |
Mar 26 04:01:43 PM PDT 24 |
5678673950 ps |
| T736 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2802950279 |
|
|
Mar 26 04:10:33 PM PDT 24 |
Mar 26 04:18:01 PM PDT 24 |
3577079860 ps |
| T993 |
/workspace/coverage/default/1.chip_sival_flash_info_access.2382650362 |
|
|
Mar 26 03:52:38 PM PDT 24 |
Mar 26 03:56:36 PM PDT 24 |
3145364190 ps |
| T725 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.1958290360 |
|
|
Mar 26 04:15:40 PM PDT 24 |
Mar 26 04:25:11 PM PDT 24 |
4789078058 ps |
| T994 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3855721533 |
|
|
Mar 26 03:45:55 PM PDT 24 |
Mar 26 03:54:19 PM PDT 24 |
4339748044 ps |
| T995 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1201230546 |
|
|
Mar 26 03:49:27 PM PDT 24 |
Mar 26 04:03:11 PM PDT 24 |
6096645616 ps |
| T732 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.1046725928 |
|
|
Mar 26 04:10:50 PM PDT 24 |
Mar 26 04:23:48 PM PDT 24 |
5758616132 ps |
| T996 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1197895894 |
|
|
Mar 26 03:47:17 PM PDT 24 |
Mar 26 03:56:48 PM PDT 24 |
18964199416 ps |
| T411 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2437341646 |
|
|
Mar 26 04:11:52 PM PDT 24 |
Mar 26 04:20:59 PM PDT 24 |
5698769120 ps |
| T997 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3212665690 |
|
|
Mar 26 03:52:49 PM PDT 24 |
Mar 26 04:07:06 PM PDT 24 |
5174393876 ps |
| T998 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2464371617 |
|
|
Mar 26 03:51:17 PM PDT 24 |
Mar 26 04:01:02 PM PDT 24 |
4420444264 ps |
| T999 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2188224569 |
|
|
Mar 26 04:03:07 PM PDT 24 |
Mar 26 04:15:10 PM PDT 24 |
4173330032 ps |
| T1000 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.2009699917 |
|
|
Mar 26 03:47:12 PM PDT 24 |
Mar 26 03:51:21 PM PDT 24 |
3246716430 ps |
| T614 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1481547694 |
|
|
Mar 26 03:51:49 PM PDT 24 |
Mar 26 04:02:39 PM PDT 24 |
5766420599 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3121782254 |
|
|
Mar 26 03:49:50 PM PDT 24 |
Mar 26 04:02:23 PM PDT 24 |
4361527668 ps |
| T1002 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.3509321999 |
|
|
Mar 26 04:05:24 PM PDT 24 |
Mar 26 04:20:55 PM PDT 24 |
4988834953 ps |
| T1003 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2217397831 |
|
|
Mar 26 03:46:49 PM PDT 24 |
Mar 26 03:49:54 PM PDT 24 |
2607474465 ps |
| T1004 |
/workspace/coverage/default/3.chip_tap_straps_dev.2138069046 |
|
|
Mar 26 04:05:24 PM PDT 24 |
Mar 26 04:07:41 PM PDT 24 |
2529326278 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2035813529 |
|
|
Mar 26 04:04:42 PM PDT 24 |
Mar 26 04:10:04 PM PDT 24 |
3573900998 ps |
| T751 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.555600586 |
|
|
Mar 26 04:09:09 PM PDT 24 |
Mar 26 04:15:41 PM PDT 24 |
4181629644 ps |
| T353 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.449887988 |
|
|
Mar 26 04:10:38 PM PDT 24 |
Mar 26 04:17:22 PM PDT 24 |
3650954892 ps |
| T1006 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3784556765 |
|
|
Mar 26 03:47:59 PM PDT 24 |
Mar 26 03:54:55 PM PDT 24 |
3742953640 ps |
| T1007 |
/workspace/coverage/default/4.chip_tap_straps_rma.4146905277 |
|
|
Mar 26 04:06:00 PM PDT 24 |
Mar 26 04:09:35 PM PDT 24 |
2857502888 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.632700687 |
|
|
Mar 26 04:04:59 PM PDT 24 |
Mar 26 04:08:58 PM PDT 24 |
2958158432 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3380201630 |
|
|
Mar 26 04:04:15 PM PDT 24 |
Mar 26 04:14:54 PM PDT 24 |
4837650517 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1984200939 |
|
|
Mar 26 04:06:03 PM PDT 24 |
Mar 26 04:10:00 PM PDT 24 |
2492798782 ps |
| T202 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.1871643699 |
|
|
Mar 26 03:44:46 PM PDT 24 |
Mar 26 06:51:05 PM PDT 24 |
65463242415 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3860531671 |
|
|
Mar 26 04:01:59 PM PDT 24 |
Mar 26 04:18:11 PM PDT 24 |
5163945404 ps |
| T54 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1231260477 |
|
|
Mar 26 03:44:44 PM PDT 24 |
Mar 26 03:49:04 PM PDT 24 |
4209293888 ps |
| T1012 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.2024554008 |
|
|
Mar 26 03:53:03 PM PDT 24 |
Mar 26 04:02:09 PM PDT 24 |
5382755788 ps |
| T344 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.3857997498 |
|
|
Mar 26 03:53:29 PM PDT 24 |
Mar 26 04:00:09 PM PDT 24 |
3410321088 ps |
| T1013 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4086707426 |
|
|
Mar 26 03:47:08 PM PDT 24 |
Mar 26 04:48:12 PM PDT 24 |
18831553067 ps |
| T728 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1939349934 |
|
|
Mar 26 04:14:24 PM PDT 24 |
Mar 26 04:21:45 PM PDT 24 |
4275997312 ps |
| T88 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2087873245 |
|
|
Mar 26 04:10:58 PM PDT 24 |
Mar 26 04:20:46 PM PDT 24 |
5078973728 ps |
| T1014 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.1934251322 |
|
|
Mar 26 03:49:30 PM PDT 24 |
Mar 26 04:13:54 PM PDT 24 |
6211331254 ps |
| T1015 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2227552722 |
|
|
Mar 26 04:00:44 PM PDT 24 |
Mar 26 04:04:27 PM PDT 24 |
2880548360 ps |
| T171 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.653773961 |
|
|
Mar 26 03:59:08 PM PDT 24 |
Mar 26 04:32:19 PM PDT 24 |
34253410088 ps |
| T1016 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2470965162 |
|
|
Mar 26 03:50:38 PM PDT 24 |
Mar 26 04:20:08 PM PDT 24 |
9992473728 ps |
| T616 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.464414234 |
|
|
Mar 26 03:51:48 PM PDT 24 |
Mar 26 03:53:44 PM PDT 24 |
2576832772 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3923463642 |
|
|
Mar 26 03:59:53 PM PDT 24 |
Mar 26 04:10:08 PM PDT 24 |
3982814966 ps |
| T407 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.654743010 |
|
|
Mar 26 03:46:31 PM PDT 24 |
Mar 26 03:50:56 PM PDT 24 |
2980518040 ps |
| T89 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3800208937 |
|
|
Mar 26 04:11:22 PM PDT 24 |
Mar 26 04:22:29 PM PDT 24 |
6314258084 ps |
| T733 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1311206571 |
|
|
Mar 26 04:10:38 PM PDT 24 |
Mar 26 04:23:44 PM PDT 24 |
5333819128 ps |
| T1018 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.499114823 |
|
|
Mar 26 04:06:28 PM PDT 24 |
Mar 26 04:45:02 PM PDT 24 |
14244548990 ps |
| T326 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.4108946768 |
|
|
Mar 26 03:56:55 PM PDT 24 |
Mar 26 04:06:30 PM PDT 24 |
3517755048 ps |
| T1019 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3463168849 |
|
|
Mar 26 03:47:21 PM PDT 24 |
Mar 26 04:25:13 PM PDT 24 |
25869756477 ps |
| T1020 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3032726072 |
|
|
Mar 26 03:46:37 PM PDT 24 |
Mar 26 04:02:58 PM PDT 24 |
6071186288 ps |
| T1021 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3227988541 |
|
|
Mar 26 03:53:12 PM PDT 24 |
Mar 26 04:03:19 PM PDT 24 |
5306489800 ps |
| T317 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.186224397 |
|
|
Mar 26 04:02:18 PM PDT 24 |
Mar 26 04:16:12 PM PDT 24 |
4473570822 ps |
| T1022 |
/workspace/coverage/default/0.rom_keymgr_functest.1281272530 |
|
|
Mar 26 03:48:47 PM PDT 24 |
Mar 26 03:58:55 PM PDT 24 |
5441678420 ps |
| T1023 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.2291085823 |
|
|
Mar 26 03:52:23 PM PDT 24 |
Mar 26 03:58:05 PM PDT 24 |
3087065728 ps |
| T1024 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.836191252 |
|
|
Mar 26 03:48:39 PM PDT 24 |
Mar 26 04:15:44 PM PDT 24 |
8342839356 ps |
| T1025 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.480290769 |
|
|
Mar 26 03:48:03 PM PDT 24 |
Mar 26 03:56:41 PM PDT 24 |
5273229672 ps |
| T1026 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1493734553 |
|
|
Mar 26 03:52:45 PM PDT 24 |
Mar 26 03:58:25 PM PDT 24 |
2929514918 ps |
| T1027 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2124482733 |
|
|
Mar 26 03:56:52 PM PDT 24 |
Mar 26 04:02:24 PM PDT 24 |
3107530552 ps |
| T1028 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.1797212682 |
|
|
Mar 26 04:00:12 PM PDT 24 |
Mar 26 04:06:51 PM PDT 24 |
3585030988 ps |
| T1029 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.3224225375 |
|
|
Mar 26 04:09:03 PM PDT 24 |
Mar 26 04:13:17 PM PDT 24 |
2740977394 ps |
| T147 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1547468160 |
|
|
Mar 26 03:56:21 PM PDT 24 |
Mar 26 07:00:24 PM PDT 24 |
57422466845 ps |
| T1030 |
/workspace/coverage/default/1.rom_raw_unlock.2952586428 |
|
|
Mar 26 03:54:08 PM PDT 24 |
Mar 26 04:27:55 PM PDT 24 |
16323502318 ps |
| T1031 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1147903805 |
|
|
Mar 26 03:52:59 PM PDT 24 |
Mar 26 04:04:14 PM PDT 24 |
5109292677 ps |
| T1032 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1880286995 |
|
|
Mar 26 03:52:56 PM PDT 24 |
Mar 26 04:01:40 PM PDT 24 |
3445134754 ps |
| T617 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.4012835820 |
|
|
Mar 26 03:50:21 PM PDT 24 |
Mar 26 03:52:27 PM PDT 24 |
2366909252 ps |
| T1033 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.55986096 |
|
|
Mar 26 03:48:32 PM PDT 24 |
Mar 26 03:57:07 PM PDT 24 |
3753043178 ps |
| T1034 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3282154071 |
|
|
Mar 26 04:00:24 PM PDT 24 |
Mar 26 04:09:09 PM PDT 24 |
7619127716 ps |
| T1035 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3385605091 |
|
|
Mar 26 03:59:20 PM PDT 24 |
Mar 26 04:05:27 PM PDT 24 |
4751779488 ps |
| T1036 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2722416596 |
|
|
Mar 26 04:02:05 PM PDT 24 |
Mar 26 04:07:02 PM PDT 24 |
3305496460 ps |
| T1037 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1694195069 |
|
|
Mar 26 03:48:31 PM PDT 24 |
Mar 26 07:20:51 PM PDT 24 |
64242553932 ps |
| T1038 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3967765752 |
|
|
Mar 26 04:07:50 PM PDT 24 |
Mar 26 04:16:03 PM PDT 24 |
7591127014 ps |
| T345 |
/workspace/coverage/default/1.chip_sw_hmac_enc.3830208085 |
|
|
Mar 26 03:47:54 PM PDT 24 |
Mar 26 03:51:42 PM PDT 24 |
2532651990 ps |
| T696 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.153888602 |
|
|
Mar 26 04:07:19 PM PDT 24 |
Mar 26 04:19:41 PM PDT 24 |
6046523282 ps |
| T714 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.281871420 |
|
|
Mar 26 04:10:21 PM PDT 24 |
Mar 26 04:19:31 PM PDT 24 |
4466124300 ps |
| T735 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2418769060 |
|
|
Mar 26 04:11:31 PM PDT 24 |
Mar 26 04:18:25 PM PDT 24 |
3194606114 ps |
| T1039 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4090659491 |
|
|
Mar 26 03:54:24 PM PDT 24 |
Mar 26 07:26:17 PM PDT 24 |
255612407956 ps |
| T1040 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.280658836 |
|
|
Mar 26 03:44:38 PM PDT 24 |
Mar 26 03:54:49 PM PDT 24 |
4136666538 ps |
| T9 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2744840218 |
|
|
Mar 26 03:54:27 PM PDT 24 |
Mar 26 03:59:20 PM PDT 24 |
3359303261 ps |
| T1041 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1724894850 |
|
|
Mar 26 03:59:04 PM PDT 24 |
Mar 26 04:12:07 PM PDT 24 |
8879547846 ps |
| T634 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.1632988869 |
|
|
Mar 26 03:49:29 PM PDT 24 |
Mar 26 03:59:03 PM PDT 24 |
3277096336 ps |
| T188 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2130749197 |
|
|
Mar 26 03:52:09 PM PDT 24 |
Mar 26 04:04:08 PM PDT 24 |
7847048820 ps |
| T101 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3639012346 |
|
|
Mar 26 03:53:01 PM PDT 24 |
Mar 26 04:20:04 PM PDT 24 |
20532301632 ps |
| T316 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.170180480 |
|
|
Mar 26 03:49:38 PM PDT 24 |
Mar 26 04:03:22 PM PDT 24 |
5290103896 ps |
| T412 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2501159619 |
|
|
Mar 26 04:13:08 PM PDT 24 |
Mar 26 04:24:49 PM PDT 24 |
5207964662 ps |
| T758 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3750434503 |
|
|
Mar 26 04:16:04 PM PDT 24 |
Mar 26 04:21:50 PM PDT 24 |
3467185176 ps |
| T680 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.951616186 |
|
|
Mar 26 04:08:14 PM PDT 24 |
Mar 26 04:19:34 PM PDT 24 |
4652331098 ps |
| T1042 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.22788456 |
|
|
Mar 26 04:13:45 PM PDT 24 |
Mar 26 04:22:05 PM PDT 24 |
4446031550 ps |
| T1043 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3427765347 |
|
|
Mar 26 03:48:30 PM PDT 24 |
Mar 26 04:30:43 PM PDT 24 |
22797472509 ps |
| T682 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.2470965679 |
|
|
Mar 26 04:14:35 PM PDT 24 |
Mar 26 04:25:34 PM PDT 24 |
4614916800 ps |
| T49 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2231017530 |
|
|
Mar 26 03:52:56 PM PDT 24 |
Mar 26 04:25:17 PM PDT 24 |
21448628136 ps |
| T1044 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1888021052 |
|
|
Mar 26 04:02:06 PM PDT 24 |
Mar 26 04:14:12 PM PDT 24 |
4447120410 ps |
| T1045 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3776453845 |
|
|
Mar 26 03:56:37 PM PDT 24 |
Mar 26 04:13:22 PM PDT 24 |
6231770618 ps |
| T224 |
/workspace/coverage/default/0.chip_sw_flash_init.3628233397 |
|
|
Mar 26 03:48:12 PM PDT 24 |
Mar 26 04:22:28 PM PDT 24 |
24615006344 ps |
| T708 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.144594893 |
|
|
Mar 26 04:08:38 PM PDT 24 |
Mar 26 04:22:05 PM PDT 24 |
5096771952 ps |
| T183 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3442805555 |
|
|
Mar 26 03:48:38 PM PDT 24 |
Mar 26 05:17:46 PM PDT 24 |
43075652216 ps |
| T1046 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2798793090 |
|
|
Mar 26 04:05:34 PM PDT 24 |
Mar 26 04:09:52 PM PDT 24 |
3280632624 ps |
| T319 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3125412849 |
|
|
Mar 26 03:48:32 PM PDT 24 |
Mar 26 04:31:44 PM PDT 24 |
22768189998 ps |
| T1047 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2828610131 |
|
|
Mar 26 03:50:08 PM PDT 24 |
Mar 26 04:04:06 PM PDT 24 |
7706855270 ps |
| T1048 |
/workspace/coverage/default/1.chip_sw_aes_enc.8320013 |
|
|
Mar 26 03:50:04 PM PDT 24 |
Mar 26 03:55:15 PM PDT 24 |
2534579038 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.2963935031 |
|
|
Mar 26 03:47:38 PM PDT 24 |
Mar 26 04:38:10 PM PDT 24 |
11997421520 ps |
| T1049 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3761312727 |
|
|
Mar 26 03:54:17 PM PDT 24 |
Mar 26 04:03:32 PM PDT 24 |
3555785180 ps |
| T1050 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2006100839 |
|
|
Mar 26 03:55:17 PM PDT 24 |
Mar 26 03:58:37 PM PDT 24 |
3242393648 ps |
| T218 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2644072570 |
|
|
Mar 26 03:46:07 PM PDT 24 |
Mar 26 04:50:51 PM PDT 24 |
14799851120 ps |
| T135 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1808117991 |
|
|
Mar 26 04:05:46 PM PDT 24 |
Mar 26 04:21:41 PM PDT 24 |
8083669040 ps |
| T1051 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2619160021 |
|
|
Mar 26 03:52:55 PM PDT 24 |
Mar 26 04:26:43 PM PDT 24 |
8477097025 ps |
| T1052 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.58154268 |
|
|
Mar 26 03:49:34 PM PDT 24 |
Mar 26 04:00:13 PM PDT 24 |
5291409962 ps |
| T1053 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2437882854 |
|
|
Mar 26 04:02:24 PM PDT 24 |
Mar 26 04:10:19 PM PDT 24 |
3855443586 ps |
| T1054 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.3795644064 |
|
|
Mar 26 03:47:14 PM PDT 24 |
Mar 26 05:01:24 PM PDT 24 |
19188037840 ps |
| T1055 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3082863489 |
|
|
Mar 26 03:59:19 PM PDT 24 |
Mar 26 04:19:12 PM PDT 24 |
7321463520 ps |
| T1056 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1863818616 |
|
|
Mar 26 04:04:42 PM PDT 24 |
Mar 26 04:31:21 PM PDT 24 |
10687855272 ps |
| T227 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2965675748 |
|
|
Mar 26 03:44:42 PM PDT 24 |
Mar 26 04:18:34 PM PDT 24 |
19755344879 ps |
| T675 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.349143126 |
|
|
Mar 26 04:11:34 PM PDT 24 |
Mar 26 04:18:21 PM PDT 24 |
3422510832 ps |
| T327 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1982527996 |
|
|
Mar 26 03:46:01 PM PDT 24 |
Mar 26 03:57:54 PM PDT 24 |
4536718248 ps |
| T1057 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.826252417 |
|
|
Mar 26 03:46:32 PM PDT 24 |
Mar 26 03:59:26 PM PDT 24 |
8437778680 ps |
| T1058 |
/workspace/coverage/default/2.chip_sw_edn_kat.1120734971 |
|
|
Mar 26 04:02:14 PM PDT 24 |
Mar 26 04:12:34 PM PDT 24 |
3195211804 ps |
| T52 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2057663039 |
|
|
Mar 26 03:55:13 PM PDT 24 |
Mar 26 04:01:53 PM PDT 24 |
4512092396 ps |
| T1059 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2352365684 |
|
|
Mar 26 03:46:00 PM PDT 24 |
Mar 26 03:52:06 PM PDT 24 |
2867940609 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.2758981977 |
|
|
Mar 26 03:47:01 PM PDT 24 |
Mar 26 03:55:54 PM PDT 24 |
4786405082 ps |
| T1061 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1410205988 |
|
|
Mar 26 03:51:50 PM PDT 24 |
Mar 26 04:02:27 PM PDT 24 |
7140491143 ps |
| T1062 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1120834704 |
|
|
Mar 26 03:58:56 PM PDT 24 |
Mar 26 04:04:00 PM PDT 24 |
3063128848 ps |
| T1063 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.566456103 |
|
|
Mar 26 03:48:01 PM PDT 24 |
Mar 26 03:55:02 PM PDT 24 |
4228810088 ps |
| T1064 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2303841555 |
|
|
Mar 26 03:49:57 PM PDT 24 |
Mar 26 04:06:15 PM PDT 24 |
6466927604 ps |
| T1065 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.3057134029 |
|
|
Mar 26 04:02:54 PM PDT 24 |
Mar 26 04:07:47 PM PDT 24 |
3766333007 ps |
| T1066 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2839064631 |
|
|
Mar 26 04:00:12 PM PDT 24 |
Mar 26 04:04:51 PM PDT 24 |
3450615813 ps |
| T1067 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3956989117 |
|
|
Mar 26 03:50:28 PM PDT 24 |
Mar 26 04:15:55 PM PDT 24 |
13152388288 ps |
| T715 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4017222737 |
|
|
Mar 26 04:09:11 PM PDT 24 |
Mar 26 04:17:13 PM PDT 24 |
3649398652 ps |
| T750 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.747046080 |
|
|
Mar 26 04:10:32 PM PDT 24 |
Mar 26 04:17:51 PM PDT 24 |
3135632100 ps |
| T1068 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.308815246 |
|
|
Mar 26 03:46:53 PM PDT 24 |
Mar 26 04:11:25 PM PDT 24 |
9467244168 ps |
| T1069 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2043999897 |
|
|
Mar 26 03:50:53 PM PDT 24 |
Mar 26 04:23:20 PM PDT 24 |
17791884932 ps |
| T713 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.4229332460 |
|
|
Mar 26 04:08:08 PM PDT 24 |
Mar 26 04:16:08 PM PDT 24 |
3792139150 ps |
| T1070 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.806962282 |
|
|
Mar 26 04:11:55 PM PDT 24 |
Mar 26 04:23:37 PM PDT 24 |
5059088200 ps |
| T253 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2489418142 |
|
|
Mar 26 04:12:19 PM PDT 24 |
Mar 26 04:21:50 PM PDT 24 |
4749297240 ps |
| T1071 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3210949433 |
|
|
Mar 26 03:47:58 PM PDT 24 |
Mar 26 03:51:19 PM PDT 24 |
2698056060 ps |
| T1072 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3716268402 |
|
|
Mar 26 04:02:10 PM PDT 24 |
Mar 26 07:31:13 PM PDT 24 |
255853176012 ps |
| T331 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2436298266 |
|
|
Mar 26 03:51:53 PM PDT 24 |
Mar 26 03:55:33 PM PDT 24 |
2555365277 ps |
| T1073 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3098969517 |
|
|
Mar 26 03:48:49 PM PDT 24 |
Mar 26 03:58:10 PM PDT 24 |
5282070776 ps |
| T1074 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.4036484090 |
|
|
Mar 26 03:54:18 PM PDT 24 |
Mar 26 04:21:43 PM PDT 24 |
7261563560 ps |
| T184 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2479876412 |
|
|
Mar 26 03:58:40 PM PDT 24 |
Mar 26 05:15:52 PM PDT 24 |
44212255200 ps |
| T37 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.3427339892 |
|
|
Mar 26 03:56:46 PM PDT 24 |
Mar 26 04:02:18 PM PDT 24 |
3817128477 ps |
| T598 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3766589850 |
|
|
Mar 26 04:04:12 PM PDT 24 |
Mar 26 04:18:31 PM PDT 24 |
5961387528 ps |
| T1075 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.21428315 |
|
|
Mar 26 04:08:56 PM PDT 24 |
Mar 26 04:15:41 PM PDT 24 |
3985375816 ps |
| T1076 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.1508610699 |
|
|
Mar 26 03:51:50 PM PDT 24 |
Mar 26 03:55:26 PM PDT 24 |
2366723430 ps |
| T237 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.966245728 |
|
|
Mar 26 04:10:00 PM PDT 24 |
Mar 26 04:20:56 PM PDT 24 |
5741675608 ps |
| T1077 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1119609553 |
|
|
Mar 26 03:56:36 PM PDT 24 |
Mar 26 04:21:18 PM PDT 24 |
6757711100 ps |
| T1078 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.4293296723 |
|
|
Mar 26 03:54:08 PM PDT 24 |
Mar 26 04:03:32 PM PDT 24 |
3772136334 ps |
| T1079 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.579805010 |
|
|
Mar 26 04:08:04 PM PDT 24 |
Mar 26 04:15:55 PM PDT 24 |
6823268780 ps |
| T1080 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3541318473 |
|
|
Mar 26 03:49:05 PM PDT 24 |
Mar 26 03:54:04 PM PDT 24 |
2809360748 ps |
| T338 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.3011111019 |
|
|
Mar 26 03:42:49 PM PDT 24 |
Mar 26 03:45:25 PM PDT 24 |
2417580704 ps |
| T332 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3814706140 |
|
|
Mar 26 03:48:31 PM PDT 24 |
Mar 26 03:53:04 PM PDT 24 |
2862317309 ps |
| T709 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.2109009177 |
|
|
Mar 26 04:08:18 PM PDT 24 |
Mar 26 04:19:34 PM PDT 24 |
5291802040 ps |
| T1081 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.941416496 |
|
|
Mar 26 03:50:59 PM PDT 24 |
Mar 26 03:55:15 PM PDT 24 |
2554832892 ps |
| T154 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2947506723 |
|
|
Mar 26 03:59:26 PM PDT 24 |
Mar 26 04:02:29 PM PDT 24 |
2735322635 ps |
| T1082 |
/workspace/coverage/default/2.chip_tap_straps_dev.424884101 |
|
|
Mar 26 04:03:13 PM PDT 24 |
Mar 26 04:23:20 PM PDT 24 |
11135800269 ps |
| T1083 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.559667255 |
|
|
Mar 26 03:48:04 PM PDT 24 |
Mar 26 04:14:17 PM PDT 24 |
11033328698 ps |
| T1084 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1958288786 |
|
|
Mar 26 03:47:10 PM PDT 24 |
Mar 26 06:46:38 PM PDT 24 |
59210746540 ps |
| T1085 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3118770456 |
|
|
Mar 26 03:53:39 PM PDT 24 |
Mar 26 03:58:10 PM PDT 24 |
2765958142 ps |
| T1086 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3417595980 |
|
|
Mar 26 03:53:56 PM PDT 24 |
Mar 26 04:00:18 PM PDT 24 |
4593797350 ps |
| T1087 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3206144168 |
|
|
Mar 26 03:47:24 PM PDT 24 |
Mar 26 03:50:45 PM PDT 24 |
2483788244 ps |
| T1088 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2433155154 |
|
|
Mar 26 04:12:54 PM PDT 24 |
Mar 26 04:20:38 PM PDT 24 |
3461131440 ps |
| T705 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.897594123 |
|
|
Mar 26 04:08:59 PM PDT 24 |
Mar 26 04:16:19 PM PDT 24 |
3675005320 ps |
| T1089 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.2580638748 |
|
|
Mar 26 03:52:16 PM PDT 24 |
Mar 26 03:59:06 PM PDT 24 |
3261525208 ps |
| T663 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3778083155 |
|
|
Mar 26 03:49:26 PM PDT 24 |
Mar 26 04:12:35 PM PDT 24 |
21790004260 ps |
| T1090 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1224262200 |
|
|
Mar 26 03:48:20 PM PDT 24 |
Mar 26 03:53:38 PM PDT 24 |
3621995416 ps |
| T1091 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2566237864 |
|
|
Mar 26 03:45:13 PM PDT 24 |
Mar 26 03:52:50 PM PDT 24 |
4232417624 ps |
| T1092 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3045310915 |
|
|
Mar 26 03:46:40 PM PDT 24 |
Mar 26 04:06:48 PM PDT 24 |
6495323320 ps |
| T311 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.4095560358 |
|
|
Mar 26 03:48:16 PM PDT 24 |
Mar 26 04:06:39 PM PDT 24 |
5717541180 ps |
| T1093 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1224536 |
|
|
Mar 26 03:54:03 PM PDT 24 |
Mar 26 04:29:19 PM PDT 24 |
8615603325 ps |
| T314 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.739233048 |
|
|
Mar 26 03:46:01 PM PDT 24 |
Mar 26 03:57:03 PM PDT 24 |
4717979752 ps |
| T1094 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2941431185 |
|
|
Mar 26 04:01:11 PM PDT 24 |
Mar 26 04:09:18 PM PDT 24 |
9903815079 ps |
| T1095 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.4235267910 |
|
|
Mar 26 03:47:30 PM PDT 24 |
Mar 26 04:28:11 PM PDT 24 |
9939423364 ps |
| T1096 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4196089027 |
|
|
Mar 26 04:02:18 PM PDT 24 |
Mar 26 04:24:38 PM PDT 24 |
7556979112 ps |
| T1097 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1864685695 |
|
|
Mar 26 03:47:41 PM PDT 24 |
Mar 26 03:59:51 PM PDT 24 |
4552331999 ps |
| T161 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.651562924 |
|
|
Mar 26 04:11:18 PM PDT 24 |
Mar 26 04:20:44 PM PDT 24 |
5081224600 ps |
| T1098 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1450197239 |
|
|
Mar 26 03:59:57 PM PDT 24 |
Mar 26 04:03:11 PM PDT 24 |
2548131424 ps |
| T1099 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1217924250 |
|
|
Mar 26 03:50:29 PM PDT 24 |
Mar 26 04:06:52 PM PDT 24 |
9298889943 ps |
| T1100 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.407143335 |
|
|
Mar 26 04:00:07 PM PDT 24 |
Mar 26 04:05:41 PM PDT 24 |
3187061190 ps |
| T1101 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2705805210 |
|
|
Mar 26 03:50:04 PM PDT 24 |
Mar 26 03:54:13 PM PDT 24 |
2651937683 ps |
| T1102 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1887361421 |
|
|
Mar 26 03:50:28 PM PDT 24 |
Mar 26 04:02:27 PM PDT 24 |
19170389852 ps |
| T1103 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.293423762 |
|
|
Mar 26 04:02:24 PM PDT 24 |
Mar 26 04:08:02 PM PDT 24 |
3020846910 ps |
| T1104 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3671254678 |
|
|
Mar 26 04:03:16 PM PDT 24 |
Mar 26 04:12:00 PM PDT 24 |
4534233310 ps |
| T1105 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2567570879 |
|
|
Mar 26 04:04:42 PM PDT 24 |
Mar 26 04:10:03 PM PDT 24 |
3476364739 ps |
| T1106 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.4008180291 |
|
|
Mar 26 03:44:59 PM PDT 24 |
Mar 26 03:53:31 PM PDT 24 |
10760532300 ps |
| T1107 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3351347331 |
|
|
Mar 26 04:06:41 PM PDT 24 |
Mar 26 04:18:06 PM PDT 24 |
6752443772 ps |
| T653 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.3661725361 |
|
|
Mar 26 03:53:23 PM PDT 24 |
Mar 26 04:00:38 PM PDT 24 |
4720343648 ps |
| T717 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2742149508 |
|
|
Mar 26 04:10:41 PM PDT 24 |
Mar 26 04:23:11 PM PDT 24 |
5754346228 ps |
| T1108 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4293508147 |
|
|
Mar 26 04:10:31 PM PDT 24 |
Mar 26 04:17:52 PM PDT 24 |
3689060432 ps |
| T1109 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1770838275 |
|
|
Mar 26 03:48:04 PM PDT 24 |
Mar 26 03:52:44 PM PDT 24 |
2274754664 ps |
| T1110 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.531158521 |
|
|
Mar 26 03:47:37 PM PDT 24 |
Mar 26 04:03:43 PM PDT 24 |
6879149096 ps |
| T1111 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.518038482 |
|
|
Mar 26 03:51:27 PM PDT 24 |
Mar 26 03:58:48 PM PDT 24 |
3827450222 ps |
| T1112 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.35505695 |
|
|
Mar 26 03:53:55 PM PDT 24 |
Mar 26 04:30:23 PM PDT 24 |
8978821170 ps |
| T1113 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3933754461 |
|
|
Mar 26 04:04:11 PM PDT 24 |
Mar 26 04:17:12 PM PDT 24 |
7629258536 ps |
| T1114 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.262950522 |
|
|
Mar 26 04:05:59 PM PDT 24 |
Mar 26 04:19:32 PM PDT 24 |
6118009023 ps |
| T155 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2991098298 |
|
|
Mar 26 03:48:04 PM PDT 24 |
Mar 26 03:52:22 PM PDT 24 |
2837155258 ps |
| T307 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1832797624 |
|
|
Mar 26 03:51:41 PM PDT 24 |
Mar 26 04:11:07 PM PDT 24 |
5872448790 ps |
| T1115 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.271158812 |
|
|
Mar 26 03:57:06 PM PDT 24 |
Mar 26 04:38:41 PM PDT 24 |
9170755620 ps |
| T692 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3061023384 |
|
|
Mar 26 03:47:02 PM PDT 24 |
Mar 26 03:53:49 PM PDT 24 |
4149269304 ps |
| T1116 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.4214604260 |
|
|
Mar 26 03:48:24 PM PDT 24 |
Mar 26 03:53:58 PM PDT 24 |
2678569545 ps |
| T1117 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.4088695321 |
|
|
Mar 26 04:00:07 PM PDT 24 |
Mar 26 04:05:35 PM PDT 24 |
2382941350 ps |
| T185 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.872040083 |
|
|
Mar 26 03:45:42 PM PDT 24 |
Mar 26 05:20:06 PM PDT 24 |
44286367526 ps |
| T305 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.4070466150 |
|
|
Mar 26 03:48:09 PM PDT 24 |
Mar 26 04:00:04 PM PDT 24 |
4564844092 ps |
| T729 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3558828425 |
|
|
Mar 26 04:11:36 PM PDT 24 |
Mar 26 04:18:38 PM PDT 24 |
4230701000 ps |
| T1118 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2289558940 |
|
|
Mar 26 03:53:01 PM PDT 24 |
Mar 26 03:57:14 PM PDT 24 |
3178860652 ps |
| T1119 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3732197816 |
|
|
Mar 26 03:55:38 PM PDT 24 |
Mar 26 04:43:28 PM PDT 24 |
11525174496 ps |
| T1120 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.100462671 |
|
|
Mar 26 03:47:24 PM PDT 24 |
Mar 26 03:52:38 PM PDT 24 |
3423470515 ps |
| T1121 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.82989038 |
|
|
Mar 26 04:00:21 PM PDT 24 |
Mar 26 04:08:30 PM PDT 24 |
4410516900 ps |
| T1122 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2325695124 |
|
|
Mar 26 03:52:37 PM PDT 24 |
Mar 26 03:59:40 PM PDT 24 |
3907235704 ps |
| T1123 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2639987822 |
|
|
Mar 26 03:50:47 PM PDT 24 |
Mar 26 04:07:43 PM PDT 24 |
5690445810 ps |
| T309 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.3416590971 |
|
|
Mar 26 04:04:09 PM PDT 24 |
Mar 26 04:25:30 PM PDT 24 |
6306860872 ps |
| T399 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1559207178 |
|
|
Mar 26 04:05:43 PM PDT 24 |
Mar 26 04:10:53 PM PDT 24 |
4743925412 ps |
| T747 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.4146995803 |
|
|
Mar 26 04:05:59 PM PDT 24 |
Mar 26 04:16:18 PM PDT 24 |
5558450566 ps |
| T1124 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1571359993 |
|
|
Mar 26 03:49:41 PM PDT 24 |
Mar 26 03:56:19 PM PDT 24 |
2945624660 ps |