b938dde05c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.267m | 2.466ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.271m | 2.441ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.778m | 2.580ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.141m | 2.925ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 45.366m | 10.010ms | 0 | 3 | 0.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | chip_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V1 | xbar_smoke | xbar_smoke | 0 | 100 | 0.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 7.935m | 3.707ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 7.935m | 3.707ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 7.935m | 3.707ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 11.989m | 4.497ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 11.989m | 4.497ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 11.229m | 4.124ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 11.755m | 4.656ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 12.555m | 4.255ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 53.893m | 12.428ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 49.862m | 13.072ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 25.241m | 12.834ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 65 | 223 | 29.15 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.999m | 4.287ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.999m | 4.287ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 4.412m | 2.826ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 7.626m | 4.840ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 6.834m | 3.579ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 31.516m | 17.043ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 6.852m | 5.290ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 12.583m | 7.358ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 33.516m | 15.333ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.008m | 3.541ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 22.997m | 9.263ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 15.021m | 5.701ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 15.021m | 5.701ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 16.559m | 7.344ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 45.517m | 18.345ms | 1 | 3 | 33.33 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.266m | 4.329ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.770m | 5.202ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.236h | 19.075ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.792m | 3.154ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 20.907m | 5.952ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.032m | 2.587ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 10.885m | 5.615ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.351m | 3.705ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.585m | 4.860ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.996m | 2.925ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 4.743m | 2.396ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 13.619m | 5.860ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.760m | 5.346ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.774m | 2.795ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.760m | 5.346ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.696m | 2.169ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 4.543m | 3.123ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.956m | 2.770ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 5.417m | 2.623ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.060m | 3.122ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 8.432m | 3.860ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.579m | 3.614ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 5.888m | 2.446ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 4.377m | 2.925ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 43.466m | 10.779ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 5.333m | 2.654ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.136m | 5.853ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 8.281m | 4.303ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.476m | 2.888ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.991m | 2.651ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.173m | 3.158ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 5.196m | 2.639ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.153m | 3.165ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 10.381m | 5.035ms | 3 | 3 | 100.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 45.366m | 10.010ms | 0 | 3 | 0.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.754h | 77.734ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 0 | 3 | 0.00 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 11.953m | 4.728ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 9.531m | 11.095ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.060h | 58.319ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.537h | 63.710ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_illegal_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | xbar_base_random_sequence | xbar_random | 0 | 100 | 0.00 | ||
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 0 | 100 | 0.00 | ||
| xbar_smoke_large_delays | 0 | 100 | 0.00 | ||||
| xbar_smoke_slow_rsp | 0 | 100 | 0.00 | ||||
| xbar_random_zero_delays | 0 | 100 | 0.00 | ||||
| xbar_random_large_delays | 0 | 100 | 0.00 | ||||
| xbar_random_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_error_cases | xbar_error_random | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 0 | 100 | 0.00 | ||
| xbar_access_same_device_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 0 | 100 | 0.00 | ||
| V2 | xbar_stress_all | xbar_stress_all | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_error | 0 | 100 | 0.00 | ||||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_reset_error | 0 | 100 | 0.00 | ||||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 44.150s | 10.300us | 0 | 3 | 0.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 0 | 1 | 0.00 | ||||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 8.922h | 152.937ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 4.563h | 79.772ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 4.398h | 80.828ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 0 | 1 | 0.00 | ||||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_dev | 0 | 3 | 0.00 | ||||
| rom_e2e_asm_init_prod | 0 | 3 | 0.00 | ||||
| rom_e2e_asm_init_prod_end | 0 | 3 | 0.00 | ||||
| rom_e2e_asm_init_rma | 0 | 3 | 0.00 | ||||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 0 | 3 | 0.00 | ||
| rom_e2e_keymgr_init_rom_ext_no_meas | 0 | 3 | 0.00 | ||||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 0 | 3 | 0.00 | ||||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 40.140s | 10.200us | 0 | 3 | 0.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.923m | 3.626ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 4.792m | 3.154ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 3.814m | 2.837ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 5.916m | 2.929ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 11.320m | 5.938ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.055m | 18.487ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.055m | 18.487ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 8.688m | 3.494ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 9.136m | 5.853ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 8.688m | 3.494ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.744m | 8.033ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.744m | 8.033ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 9.701m | 6.424ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 12.603m | 5.530ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 17.872m | 5.379ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 5.916m | 2.929ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.066m | 2.256ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 5.409m | 3.068ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 9.835m | 4.122ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 11.290m | 4.131ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 9.336m | 4.395ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 8.027m | 4.250ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 27.334m | 11.020ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.231m | 4.494ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.689m | 4.764ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.391m | 4.204ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.312m | 5.140ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.383m | 3.662ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.600m | 4.507ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 16.559m | 7.344ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 15.224m | 11.462ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.391m | 4.204ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.312m | 5.140ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.266m | 4.329ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.770m | 5.202ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.236h | 19.075ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.792m | 3.154ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 20.907m | 5.952ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.032m | 2.587ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 10.885m | 5.615ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.351m | 3.705ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.585m | 4.860ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.996m | 2.925ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.630m | 2.523ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 11.419m | 4.378ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 22.041m | 7.059ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.304h | 24.022ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.374m | 2.895ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.506m | 3.457ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 9.730m | 5.360ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.414m | 2.833ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 11.056m | 5.734ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 37.958m | 19.397ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 1.433h | 28.978ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 16.559m | 7.344ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.583m | 4.827ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.505m | 3.637ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 17.027m | 6.077ms | 97 | 100 | 97.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 36.667m | 8.074ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 31.055m | 7.089ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 8.216m | 4.964ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 13.432m | 7.256ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.302m | 2.866ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 19.758m | 7.170ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 30.429m | 20.894ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 4.832m | 3.636ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 41.640s | 10.220us | 0 | 3 | 0.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 11.301m | 4.459ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 30.429m | 20.894ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 30.429m | 20.894ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.150h | 20.291ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.150h | 20.291ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.562m | 5.541ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.055m | 18.487ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.082h | 14.335ms | 3 | 3 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 4.897m | 2.420ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 18.692m | 4.960ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.897m | 2.420ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 31.055m | 7.089ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 3.885m | 3.064ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 44.606m | 25.846ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 18.473m | 5.132ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.770m | 5.202ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 12.144m | 4.187ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 12.266m | 4.329ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.611h | 43.056ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 44.606m | 25.846ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.119m | 3.005ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 10.142m | 4.695ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 8.422m | 5.118ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.611h | 43.056ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 8.422m | 5.118ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 8.422m | 5.118ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 8.422m | 5.118ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 8.422m | 5.118ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 17.027m | 6.077ms | 97 | 100 | 97.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 19.925m | 5.038ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 13.857m | 5.875ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 13.857m | 5.875ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 4.275m | 2.696ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 4.032m | 2.587ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.066m | 2.256ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 15.418m | 5.066ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 14.628m | 5.333ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 13.401m | 4.946ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 9.815m | 4.454ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 10.142m | 4.695ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 10.885m | 5.615ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 9.652m | 4.079ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 11.320m | 5.938ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.124h | 12.414ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 5.119m | 2.701ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.380m | 2.599ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.351m | 3.705ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 10.142m | 4.695ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 22.645m | 12.121ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 3.819m | 2.530ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 5.672m | 2.779ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.409m | 3.068ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 8.887m | 5.833ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 31.516m | 17.043ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 12.583m | 7.358ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 33.516m | 15.333ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.293m | 2.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 22.645m | 12.121ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 22.645m | 12.121ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 22.645m | 12.121ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 9.122m | 5.450ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 8.422m | 5.118ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.611h | 43.056ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.661m | 4.630ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 22.680m | 7.168ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 22.461m | 7.984ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 29.761m | 7.366ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 22.645m | 12.121ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 10.142m | 4.695ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 11.367m | 8.748ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 13.359m | 9.013ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_lc | 15.224m | 11.462ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.231m | 4.494ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.689m | 4.764ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.391m | 4.204ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.312m | 5.140ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.383m | 3.662ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.600m | 4.507ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 31.516m | 17.043ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 12.583m | 7.358ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 33.516m | 15.333ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 2.223m | 2.177ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.403m | 3.672ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.065m | 3.212ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 2.363m | 3.463ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 41.331m | 29.253ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.746h | 46.945ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.652h | 46.585ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 17.251m | 10.078ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.598h | 46.025ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 41.331m | 29.253ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 1.819m | 2.269ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 1.890m | 1.988ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 0 | 3 | 0.00 | ||||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 22.645m | 12.121ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 44.606m | 25.846ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 7.767m | 3.457ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 10.142m | 4.695ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.378m | 5.194ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.125m | 3.430ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 44.606m | 25.846ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 7.767m | 3.457ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 10.142m | 4.695ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.378m | 5.194ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.125m | 3.430ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 22.645m | 12.121ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 15.827m | 14.223ms | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.293m | 2.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.661m | 4.630ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 22.680m | 7.168ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 22.461m | 7.984ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 29.761m | 7.366ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 22.645m | 12.121ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 10.758m | 6.204ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 26.782m | 20.904ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 6.123m | 6.842ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 13.284m | 10.462ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 13.686m | 7.554ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 30.651m | 20.843ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 29.082m | 14.826ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 15.744m | 8.033ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 27.723m | 12.808ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 9.920m | 5.443ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 10.758m | 6.204ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 8.755m | 4.798ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1.278h | 42.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 6.900m | 4.695ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 7.892m | 5.219ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 36.450m | 19.361ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 19.758m | 7.170ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 31.659m | 12.363ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 41.239m | 21.964ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.476m | 3.081ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 17.027m | 6.077ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 11.367m | 8.748ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 11.367m | 8.748ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 31.659m | 12.363ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 36.450m | 19.361ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 9.920m | 5.443ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.136m | 5.853ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 7.937m | 3.879ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 11.421m | 7.625ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 7.264m | 4.159ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 45.984m | 12.096ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 3.820m | 2.596ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 17.027m | 6.077ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 30.720m | 7.325ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 23.672m | 6.667ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.200m | 3.757ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 12.086m | 4.545ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.908m | 3.332ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.021m | 3.124ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 0 | 3 | 0.00 | ||
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 16.897m | 7.433ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.217m | 4.206ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 7.810m | 3.211ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.417m | 3.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 12.378m | 5.194ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.585m | 4.860ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 11.313m | 5.998ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 11.964m | 7.097ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 13.359m | 9.013ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 17.027m | 6.077ms | 97 | 100 | 97.00 |
| chip_sw_data_integrity_escalation | 15.021m | 5.701ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 5.073m | 2.542ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 4.214m | 3.044ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 9.390m | 3.423ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 8.541m | 4.452ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 33.146m | 7.963ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.247h | 31.486ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 56.142m | 12.407ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 7.150m | 3.107ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 8.887m | 5.833ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 17.027m | 6.077ms | 97 | 100 | 97.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.510m | 3.761ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 45.984m | 12.096ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 9.954m | 4.755ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.906m | 3.723ms | 89 | 90 | 98.89 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 28.703m | 12.257ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 36.667m | 8.074ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 30.720m | 7.325ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.866h | 255.850ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 39.950m | 18.828ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 26.676m | 13.824ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 7.937m | 3.879ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 9.476m | 5.107ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 9.508m | 3.826ms | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 12.583m | 7.358ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 787 | 2627 | 29.96 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.056m | 2.531ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 3 | 0.00 | ||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 1.575m | 2.346ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 1.792m | 1.685ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 2.007m | 2.239ms | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 1.182h | 51.649ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_inject_dev | 1.022h | 50.315ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_inject_rma | 1.387h | 50.696ms | 0 | 1 | 0.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 0 | 0 | -- | ||
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 8.875m | 3.178ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 8.402m | 3.145ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 20.592m | 4.746ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 30.886m | 8.914ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 9.990m | 3.094ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 18.569m | 5.553ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | //sw/device/tests:i2c_host_override_test | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | //sw/device/tests:i2c_target_test | 0 | 0 | -- | ||
| //sw/device/tests/pmod:i2c_host_clock_stretching_test | 0 | 0 | -- | ||||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.872m | 2.566ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 7.886m | 4.865ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 9.650m | 23.662ms | 0 | 3 | 0.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 10.095m | 4.288ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 31.659m | 12.363ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 17.027m | 6.077ms | 97 | 100 | 97.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_pass_through | chip_sw_spi_host_pass_through | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | chip_sw_spi_host_configuration | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 11.989m | 4.497ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.276h | 18.444ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 1.575m | 2.346ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 1.792m | 1.685ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 2.007m | 2.239ms | 0 | 1 | 0.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 9.083m | 4.351ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 29 | 45 | 64.44 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.000m | 3.448ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 14.372m | 4.620ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.164h | 17.221ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 18.361m | 5.352ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 18.054m | 4.621ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 11.607m | 5.326ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 6.026m | 3.173ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 4.274m | 2.700ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_write_clear | 0 | 3 | 0.00 | ||||
| TOTAL | 908 | 2925 | 31.04 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 9 | 9 | 8 | 88.89 |
| V1 | 19 | 19 | 12 | 63.16 |
| V2 | 280 | 266 | 198 | 70.71 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 92 | 21 | 11 | 11.96 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.22 | 92.38 | 82.42 | 90.36 | -- | 94.36 | 97.38 | 84.43 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:
Test chip_csr_bit_bash has 3 failures.
0.chip_csr_bit_bash.2758187051021911218576507579736367011160696484675387970354491602137745629618
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
2.chip_csr_bit_bash.2642720884587997311302836950752013813781463139184928557604413423876566270335
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log
... and 1 more failures.
Test chip_same_csr_outstanding has 3 failures.
0.chip_same_csr_outstanding.34845403826462224273198986467376573453206417214070398048164921474909852392228
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
2.chip_same_csr_outstanding.115177400855633014213394970924778607160465159835354441793143364545276329548464
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log
... and 1 more failures.
Test chip_prim_tl_access has 2 failures.
0.chip_prim_tl_access.53354051993023058146211795248936567490732886882268360991296117516825992093289
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
2.chip_prim_tl_access.4715350069481666576432994516136111625989386907782848954449352173189184335478
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log
Test xbar_smoke has 8 failures.
0.xbar_smoke.84333779128874185245076976855919399601362166885162758459952715352450676395779
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log
2.xbar_smoke.86688852678697326027286954297742596913814810264597886674080031770195687255266
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log
... and 6 more failures.
Test xbar_smoke_large_delays has 8 failures.
0.xbar_smoke_large_delays.101816804060091567956534312836463716540699498608874979278530868880896427339809
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log
2.xbar_smoke_large_delays.69609776863650370600479734698802150192579063507455637241326785229681540585359
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log
... and 6 more failures.
... and 22 more tests.
Job killed most likely because its dependent job failed. has 955 failures:
Test chip_csr_aliasing has 3 failures.
0.chip_csr_aliasing.13454866902828051192287398234281516116114245925569228443298977357210346681502
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
2.chip_csr_aliasing.45866803028078809550872073968771739102365761769143177207247217748127136442982
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
... and 1 more failures.
Test chip_tl_errors has 8 failures.
0.chip_tl_errors.60229452606301927205980508035509965394676272647960345683479906845793274285800
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
2.chip_tl_errors.108930015307215137944879297889319982223606522797771529132654154500673028971964
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log
... and 6 more failures.
Test chip_rv_dm_lc_disabled has 2 failures.
0.chip_rv_dm_lc_disabled.28943665525274052894927469914667807513351857641539126004212751225049785911672
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
2.chip_rv_dm_lc_disabled.81078177423395105809382292349797005923901881506476276893602765675660200178429
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
Test xbar_smoke_zero_delays has 8 failures.
0.xbar_smoke_zero_delays.91207413945499173566076987648794943160232503288144063299015973010785810683620
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
2.xbar_smoke_zero_delays.109758887642673656563416002435554226485921029171622929086352372838344652649822
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log
... and 6 more failures.
Test xbar_smoke_slow_rsp has 8 failures.
0.xbar_smoke_slow_rsp.78078467567216054687516822958739611853736880847405577384784889342541404984621
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log
2.xbar_smoke_slow_rsp.110072150556530919176199410727783296223823251838017614757457802963378442768292
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log
... and 6 more failures.
... and 22 more tests.
Exit reason: Error: User command failed Job returned non-zero exit code has 54 failures:
Test chip_sw_flash_ctrl_write_clear has 3 failures.
0.chip_sw_flash_ctrl_write_clear.57722952452923261619717643950576113986094586845074483426990394271961656105398
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log
(15:17:53) Loading:
(15:17:54) Loading:
(15:17:54) Loading: 4 packages loaded
(15:17:54) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
(15:17:54) WARNING: Target pattern parsing failed.
(15:17:54) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
(15:17:54) INFO: Elapsed time: 17.777s
(15:17:54) INFO: 0 processes.
(15:17:54) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_flash_ctrl_write_clear.17160502569887269632560057079131370540376361199049526563194373192772386703659
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log
(15:30:34) Loading:
(15:30:35) Loading:
(15:30:35) Loading: 4 packages loaded
(15:30:35) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
(15:30:35) WARNING: Target pattern parsing failed.
(15:30:35) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
(15:30:35) INFO: Elapsed time: 23.474s
(15:30:35) INFO: 0 processes.
(15:30:35) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
Test rom_e2e_smoke has 3 failures.
0.rom_e2e_smoke.12260323639003544921033410301964138785102823371858268286508259938526165411391
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log
(15:18:32) Loading:
(15:18:33) Loading:
(15:18:33) Loading: 4 packages loaded
(15:18:33) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:18:33) WARNING: Target pattern parsing failed.
(15:18:33) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:18:33) INFO: Elapsed time: 26.303s
(15:18:33) INFO: 0 processes.
(15:18:33) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.rom_e2e_smoke.82302596849441763509044070146053432279181641682067420958984709752909061060687
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log
(15:31:17) Loading:
(15:31:17) Loading:
(15:31:17) Loading: 4 packages loaded
(15:31:18) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:31:18) WARNING: Target pattern parsing failed.
(15:31:18) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:31:18) INFO: Elapsed time: 19.640s
(15:31:18) INFO: 0 processes.
(15:31:18) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
Test rom_e2e_shutdown_output has 3 failures.
0.rom_e2e_shutdown_output.42111225749412909144110691159214243586798293021781808271818284324513390546250
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
(15:18:38) Loading:
(15:18:38) Loading:
(15:18:38) Loading: 4 packages loaded
(15:18:39) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:18:39) WARNING: Target pattern parsing failed.
(15:18:39) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:18:39) INFO: Elapsed time: 26.166s
(15:18:39) INFO: 0 processes.
(15:18:39) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.rom_e2e_shutdown_output.70145432962930974461449454243317577557854928289816525581941936606882911566544
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
(15:31:27) Loading:
(15:31:28) Loading:
(15:31:28) Loading: 4 packages loaded
(15:31:28) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:31:28) WARNING: Target pattern parsing failed.
(15:31:28) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:31:28) INFO: Elapsed time: 19.410s
(15:31:28) INFO: 0 processes.
(15:31:28) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.
0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.38790371835925654447532787874738731186562246468630368105101105806527843204616
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log
(15:18:59) Loading:
(15:18:59) Loading:
(15:18:59) Loading: 4 packages loaded
(15:19:00) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:19:00) WARNING: Target pattern parsing failed.
(15:19:00) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:19:00) INFO: Elapsed time: 35.802s
(15:19:00) INFO: 0 processes.
(15:19:00) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.
0.rom_e2e_boot_policy_valid_a_good_b_good_dev.71653088879022362173166979674641706305224807373260304845705617478892961825782
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log
(15:18:52) Loading:
(15:18:53) Loading:
(15:18:53) Loading: 4 packages loaded
(15:18:54) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:18:54) WARNING: Target pattern parsing failed.
(15:18:54) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(15:18:54) INFO: Elapsed time: 40.689s
(15:18:54) INFO: 0 processes.
(15:18:54) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 23 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.45758802091092769027982502338601835264998958451563979325965923822010683748696
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:1c1d9607-9a42-42a6-abff-671ab3f68f20
1.chip_sw_rv_timer_systick_test.48697416779241827059532973913973589027450064887287961938389662358700106452125
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:cd985605-4c0b-423a-955b-cdaece61ebd4
... and 1 more failures.
Test chip_sw_coremark has 1 failures.
0.chip_sw_coremark.9888434237264666633343394676129063308899573296751621566816173154077325202438
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
Job ID: smart:0f4e2dc8-2282-46aa-a0e2-da852425c456
Test chip_sw_ast_clk_rst_inputs has 2 failures.
0.chip_sw_ast_clk_rst_inputs.81178189243949419700751401013522262899260225127823185617576096191964416639109
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
Job ID: smart:50e862fd-633f-4e78-a315-80f8aad51eb5
2.chip_sw_ast_clk_rst_inputs.29273690814026129363191774332524628965421177921784485999354040901648884231242
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
Job ID: smart:1369d574-9229-4e95-84e5-38b410b75739
Test chip_sw_power_virus has 3 failures.
0.chip_sw_power_virus.26945544947026190231693689654930060404995953054121972374754026668439054104169
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
Job ID: smart:2910b96d-403a-4286-b9c5-4a394af0d382
1.chip_sw_power_virus.95073380516978977185845689490827467119719531976477162491064043657618684462490
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
Job ID: smart:8137335c-c7b1-4fd1-a215-668e3acab2c8
... and 1 more failures.
Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_bad_dev.20666160504200142215341569385112944002740651860292511304809584715681346230593
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
Job ID: smart:64b5e05e-6ff6-4124-87fc-7ae6d3f88b79
... and 11 more tests.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
0.chip_sw_sysrst_ctrl_outputs.63573203960597869495695080531145316028826042076211651692571334932094595787675
Line 793, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_sysrst_ctrl_outputs.3058075020408140340042685225151168202471527536944531918140080350914327788793
Line 752, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
0.chip_sw_lc_ctrl_program_error.41561981650562432840179054690484437903704070184084707822872207547830296017886
Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
UVM_ERROR @ 14832.366252 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
UVM_INFO @ 14832.366252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_lc_ctrl_program_error.113595768111755324902911846499368913770746310295926247374979073681403051838075
Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
UVM_ERROR @ 14517.712464 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
UVM_INFO @ 14517.712464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.106931586149614067689578392835081209604219525699354015733928779584878666579265
Line 846, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
UVM_FATAL @ 22737.478156 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
UVM_INFO @ 22737.478156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.81655370244237529554098370720888557788718099338990949059697833166685447634440
Line 815, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
UVM_FATAL @ 22733.417144 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
UVM_INFO @ 22733.417144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
0.chip_sw_rv_dm_access_after_wakeup.49619746168884740458240890483361978152933619852833747404033813902048186096070
Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_FATAL @ 3826.010564 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
UVM_INFO @ 3826.010564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_dm_access_after_wakeup.66894182125221492637723557781216917276064186731798269617191548039984327029637
Line 735, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_FATAL @ 4444.666535 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
UVM_INFO @ 4444.666535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
0.rom_e2e_shutdown_exception_c.83641525535519178128997302206002474297209006415728296436838284925768657872945
Line 1006, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_shutdown_exception_c.87195243620578988448860286713608840107088451717908930119674352377896831550853
Line 974, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
0.rom_e2e_jtag_debug_test_unlocked0.45108653669342269690474633276220508183604934071255170531264924705817052732222
Line 739, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
UVM_FATAL @ 2345.918500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
UVM_INFO @ 2345.918500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_debug_dev has 1 failures.
0.rom_e2e_jtag_debug_dev.11478624505706843296228251940376920291226398297926291282334113225982367496390
Line 843, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
UVM_FATAL @ 1685.390000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
UVM_INFO @ 1685.390000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_debug_rma has 1 failures.
0.rom_e2e_jtag_debug_rma.24000169621516135721716942392304250882240565021135955008856166670195061676431
Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
UVM_FATAL @ 2238.771000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
UVM_INFO @ 2238.771000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
0.rom_e2e_jtag_inject_test_unlocked0.4795826752608340171847023026975639426308213794490150556275963012991019784164
Line 747, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
UVM_FATAL @ 51648.786519 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 51648.786519 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_inject_dev has 1 failures.
0.rom_e2e_jtag_inject_dev.77104196303267083254523906825021755604912915873903607524184373872370171409811
Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
UVM_FATAL @ 50315.058440 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 50315.058440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_inject_rma has 1 failures.
0.rom_e2e_jtag_inject_rma.11068026519278225304223414421819783806898150100507177872289211018289221318852
Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
UVM_FATAL @ 50695.941426 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 50695.941426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
0.rom_e2e_static_critical.111031149579673246313490922396376873253297450053108133669978289381813263297117
Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_static_critical.42087883725467904365444498745262081893382606123898584691622825970707103029862
Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_uart_smoke_vseq.sv:24) [chip_sw_uart_smoke_vseq] wait timeout occurred! has 3 failures:
0.chip_sw_uart_smoketest_signed.45807970741553347264586054688371463907593669998744460885115509852605706973904
Line 1053, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_smoketest_signed/latest/run.log
UVM_FATAL @ 10010.340001 us: (chip_sw_uart_smoke_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.chip_sw_uart_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_uart_smoketest_signed.92225394270352948687706593568277104632255525421487073635307731282558538773930
Line 943, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_smoketest_signed/latest/run.log
UVM_FATAL @ 10010.260001 us: (chip_sw_uart_smoke_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.chip_sw_uart_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
2.chip_sw_all_escalation_resets.13007303178203025081746907147525317730901830487756379175933207867524578393289
Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3570.340856 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3570.340856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
50.chip_sw_all_escalation_resets.95645377235746217458499054588127281988827781006185295328032868374443659755195
Line 805, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2746.113000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2746.113000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
36.chip_sw_alert_handler_lpg_sleep_mode_alerts.31010881826543007075755491338023316825959462290685263891602434277271018575965
Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3161.031100 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
UVM_INFO @ 3161.031100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---