CHIP Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.107m	2.771ms	3	3	100.00
		chip_sw_example_rom	2.462m	2.942ms	3	3	100.00
		chip_sw_example_manufacturer	5.113m	3.375ms	3	3	100.00
		chip_sw_example_concurrency	4.603m	2.446ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.627m	5.485ms	5	5	100.00
V1	csr_rw	chip_csr_rw	12.624m	6.109ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.541h	59.844ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.805h	58.068ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.579m	2.380ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.805h	58.068ms	4	5	80.00
		chip_csr_rw	12.624m	6.109ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.690s	267.120us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.457m	4.711ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.457m	4.711ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.457m	4.711ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.602m	4.109ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.602m	4.109ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	13.224m	4.123ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	11.072m	4.007ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.707m	4.416ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	44.624m	12.966ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	29.916m	8.115ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	23.305m	8.395ms	5	5	100.00
V1		TOTAL			199	220	90.45
V2	chip_pin_mux	chip_padctrl_attributes	6.873m	6.291ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	6.873m	6.291ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.901m	2.842ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	6.005m	5.273ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.830m	4.102ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	19.599m	12.571ms	5	5	100.00
		chip_tap_straps_testunlock0	9.248m	6.344ms	5	5	100.00
		chip_tap_straps_rma	8.103m	5.386ms	5	5	100.00
		chip_tap_straps_prod	9.101m	5.547ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.988m	3.223ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	29.978m	8.302ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.947m	5.836ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.947m	5.836ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	21.118m	7.583ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	38.164m	16.880ms	2	3	66.67
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.059m	4.061ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.519m	6.093ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.175h	18.240ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.781m	2.696ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.100m	6.193ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.367m	3.549ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.859m	4.719ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.869m	3.453ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.558m	4.868ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.276m	3.278ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.652m	3.064ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	17.499m	5.530ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.393m	5.379ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.702m	2.693ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.393m	5.379ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.232m	3.055ms	3	3	100.00
		chip_sw_aes_smoketest	5.658m	2.803ms	3	3	100.00
		chip_sw_aon_timer_smoketest	4.877m	3.360ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.325m	3.412ms	3	3	100.00
		chip_sw_csrng_smoketest	5.001m	2.532ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.373m	3.581ms	3	3	100.00
		chip_sw_gpio_smoketest	4.431m	3.423ms	3	3	100.00
		chip_sw_hmac_smoketest	7.169m	3.500ms	3	3	100.00
		chip_sw_kmac_smoketest	6.475m	2.765ms	3	3	100.00
		chip_sw_otbn_smoketest	41.331m	10.645ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.312m	3.230ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.388m	5.813ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	7.674m	4.354ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.093m	2.727ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.460m	3.121ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.601m	3.097ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.468m	2.877ms	3	3	100.00
		chip_sw_uart_smoketest	5.651m	3.073ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	10.657m	5.412ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.737h	76.494ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke			0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock			0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.702m	3.574ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	10.139m	9.295ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.245h	59.379ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.453h	63.034ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	7.418m	5.029ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	7.418m	5.029ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.805h	58.068ms	4	5	80.00
		chip_same_csr_outstanding	58.704m	27.998ms	20	20	100.00
		chip_csr_hw_reset	6.627m	5.485ms	5	5	100.00
		chip_csr_rw	12.624m	6.109ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.805h	58.068ms	4	5	80.00
		chip_same_csr_outstanding	58.704m	27.998ms	20	20	100.00
		chip_csr_hw_reset	6.627m	5.485ms	5	5	100.00
		chip_csr_rw	12.624m	6.109ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.724m	2.660ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.960s	61.654us	100	100	100.00
		xbar_smoke_large_delays	2.036m	10.465ms	100	100	100.00
		xbar_smoke_slow_rsp	2.206m	7.339ms	100	100	100.00
		xbar_random_zero_delays	1.124m	622.502us	100	100	100.00
		xbar_random_large_delays	22.523m	107.920ms	100	100	100.00
		xbar_random_slow_rsp	22.089m	70.441ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.181m	1.527ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.165m	1.513ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.872m	2.666ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.165m	1.513ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.718m	3.362ms	100	100	100.00
		xbar_access_same_device_slow_rsp	47.798m	160.184ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.432m	2.703ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.911m	20.056ms	100	100	100.00
		xbar_stress_all_with_error	13.688m	21.682ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	19.459m	19.483ms	100	100	100.00
		xbar_stress_all_with_reset_error	24.506m	15.297ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke			0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output			0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.230s	10.160us	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma			0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	8.628h	152.851ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	4.187h	79.109ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	4.473h	79.651ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma			0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0			0	3	0.00
		rom_e2e_asm_init_dev			0	3	0.00
		rom_e2e_asm_init_prod			0	3	0.00
		rom_e2e_asm_init_prod_end			0	3	0.00
		rom_e2e_asm_init_rma			0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.710s	10.240us	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.572m	2.798ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.781m	2.696ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.577m	2.779ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.955m	2.945ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	7.624m	4.175ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.885m	18.368ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.885m	18.368ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	6.104m	3.398ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.388m	5.813ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	6.104m	3.398ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.559m	8.821ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.559m	8.821ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.789m	7.231ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.499m	5.194ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	19.613m	5.768ms	3	3	100.00
		chip_sw_aes_idle	4.955m	2.945ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.803m	3.256ms	3	3	100.00
		chip_sw_kmac_idle	4.378m	2.511ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	8.979m	5.691ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.770m	4.510ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	6.978m	3.649ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.562m	5.088ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	28.446m	9.567ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.588m	4.544ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.566m	4.549ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.994m	4.083ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.551m	4.580ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.341m	3.382ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.399m	4.868ms	3	3	100.00
		chip_sw_ast_clk_outputs	21.118m	7.583ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	20.128m	13.370ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.994m	4.083ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.551m	4.580ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.059m	4.061ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.519m	6.093ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.175h	18.240ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.781m	2.696ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.100m	6.193ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.367m	3.549ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.859m	4.719ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.869m	3.453ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.558m	4.868ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.276m	3.278ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.658m	2.678ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	14.993m	5.103ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	23.375m	6.567ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.408h	24.007ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.257m	2.906ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.280m	2.714ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	7.497m	4.485ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	4.845m	3.205ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.215m	5.400ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	41.582m	23.830ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.152h	36.019ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	21.118m	7.583ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.917m	4.874ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.657m	3.661ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.785m	5.178ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	30.923m	7.651ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	32.203m	7.235ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	10.758m	4.474ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	12.721m	7.503ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.094m	2.741ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.862m	7.454ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	33.236m	24.224ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.403m	3.420ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	40.830s	10.100us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.930m	4.683ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	33.236m	24.224ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	33.236m	24.224ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.195h	20.428ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.195h	20.428ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	7.514m	4.246ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.885m	18.368ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.016h	15.491ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.546m	2.780ms	3	3	100.00
		chip_sw_edn_entropy_reqs	20.170m	5.601ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.546m	2.780ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	32.203m	7.235ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.274m	2.895ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	43.138m	20.761ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	17.816m	5.914ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.519m	6.093ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.920m	3.715ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.059m	4.061ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.551h	43.210ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	43.138m	20.761ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.118m	3.868ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	9.766m	3.880ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.116m	4.022ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.551h	43.210ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.116m	4.022ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.116m	4.022ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	8.116m	4.022ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.116m	4.022ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.785m	5.178ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.635m	7.901ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.724m	5.425ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	11.735m	4.955ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	11.735m	4.955ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.447m	3.005ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.367m	3.549ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.803m	3.256ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	17.152m	5.711ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	15.835m	6.052ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	18.833m	6.060ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.940m	4.020ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	9.766m	3.880ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.859m	4.719ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	10.852m	4.567ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	7.624m	4.175ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.462h	15.570ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.602m	3.243ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.748m	2.816ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.869m	3.453ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	9.766m	3.880ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	23.267m	13.150ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.151m	2.997ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.409m	2.903ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.378m	2.511ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.456m	5.888ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	19.599m	12.571ms	5	5	100.00
		chip_tap_straps_rma	8.103m	5.386ms	5	5	100.00
		chip_tap_straps_prod	9.101m	5.547ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.244m	3.254ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	23.267m	13.150ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	23.267m	13.150ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	23.267m	13.150ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.897m	5.180ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	8.116m	4.022ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.551h	43.210ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.042m	4.129ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.699m	7.686ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.119m	7.994ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.245m	9.563ms	3	3	100.00
		chip_sw_lc_ctrl_transition	23.267m	13.150ms	15	15	100.00
		chip_sw_keymgr_key_derivation	9.766m	3.880ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	11.675m	8.747ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	10.723m	8.876ms	3	3	100.00
		chip_prim_tl_access	4.635m	7.901ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	20.128m	13.370ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.588m	4.544ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.566m	4.549ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.994m	4.083ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.551m	4.580ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.341m	3.382ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.399m	4.868ms	3	3	100.00
		chip_tap_straps_dev	19.599m	12.571ms	5	5	100.00
		chip_tap_straps_rma	8.103m	5.386ms	5	5	100.00
		chip_tap_straps_prod	9.101m	5.547ms	5	5	100.00
		chip_rv_dm_lc_disabled	10.822m	12.533ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.923m	3.485ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.875m	3.020ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.160m	3.058ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.613m	3.141ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	38.915m	27.764ms	3	3	100.00
		chip_rv_dm_lc_disabled	10.822m	12.533ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.738h	49.699ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.688h	49.772ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	14.876m	9.323ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.682h	48.277ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	38.915m	27.764ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.109m	2.656ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.730m	1.793ms	3	3	100.00
		rom_volatile_raw_unlock			0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	23.267m	13.150ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	43.138m	20.761ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.910m	3.603ms	3	3	100.00
		chip_sw_keymgr_key_derivation	9.766m	3.880ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.298m	4.171ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.462m	3.040ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	43.138m	20.761ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.910m	3.603ms	3	3	100.00
		chip_sw_keymgr_key_derivation	9.766m	3.880ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.298m	4.171ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.462m	3.040ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	23.267m	13.150ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.727m	14.075ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.244m	3.254ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.042m	4.129ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.699m	7.686ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.119m	7.994ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.245m	9.563ms	3	3	100.00
		chip_sw_lc_ctrl_transition	23.267m	13.150ms	15	15	100.00
		chip_prim_tl_access	4.635m	7.901ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.635m	7.901ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.424m	8.742ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	34.389m	21.914ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	8.935m	7.826ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	16.339m	7.869ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	13.662m	7.119ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	28.778m	21.635ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	27.238m	15.632ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.559m	8.821ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	24.077m	12.513ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.284m	4.410ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.424m	8.742ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.652m	4.994ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.084h	35.115ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	6.400m	6.274ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.394m	5.004ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	49.916m	25.529ms	2	3	66.67
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.862m	7.454ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	35.379m	10.596ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	48.474m	24.508ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.631m	2.707ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.785m	5.178ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.675m	8.747ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.675m	8.747ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	35.379m	10.596ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	49.916m	25.529ms	2	3	66.67
		chip_sw_pwrmgr_wdog_reset	12.284m	4.410ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.388m	5.813ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.631m	3.642ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	9.483m	4.749ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.137m	3.647ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	38.814m	10.915ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.530m	2.843ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.785m	5.178ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	31.928m	7.665ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	19.908m	6.901ms	3	3	100.00
		chip_plic_all_irqs_10	11.338m	4.399ms	3	3	100.00
		chip_plic_all_irqs_20	13.827m	4.690ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.551m	3.465ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.792m	3.460ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke			0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.670m	7.606ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.890m	4.222ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.694m	3.474ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.835m	3.245ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.298m	4.171ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.558m	4.868ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.277m	7.116ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.906m	8.674ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.723m	8.876ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.785m	5.178ms	97	100	97.00
		chip_sw_data_integrity_escalation	14.947m	5.836ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.400m	2.779ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.672m	3.030ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	9.250m	3.751ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.086m	3.223ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	30.631m	7.749ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.224h	31.062ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	50.995m	11.786ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	4.810m	3.359ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.456m	5.888ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.785m	5.178ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	4.652m	2.846ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	38.814m	10.915ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.885m	4.942ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.412m	3.620ms	86	90	95.56
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	20.589m	11.950ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	30.923m	7.651ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	31.928m	7.665ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.584h	254.425ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	37.931m	18.324ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	28.332m	13.242ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.631m	3.642ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.740m	4.287ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.206m	3.745ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	8.103m	5.386ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.822m	12.533ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2538	2627	96.61
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.650m	3.001ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.061m	5.425ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.837m	2.591ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.780m	2.249ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.295m	2.352ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.206h	51.232ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.619h	50.652ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.407h	51.496ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.428m	3.381ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.875m	2.981ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	1.271h	18.017ms	2	3	66.67
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	39.723m	9.904ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.415m	3.058ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	23.479m	5.691ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	//sw/device/tests:i2c_target_test			0	0	--
		//sw/device/tests/pmod:i2c_host_clock_stretching_test			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	5.315m	2.694ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	11.788m	4.916ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.735m	23.617ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.170m	4.555ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	35.379m	10.596ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.785m	5.178ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.602m	4.109ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.315h	18.614ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.837m	2.591ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.780m	2.249ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.295m	2.352ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.390m	5.586ms	3	3	100.00
V3		TOTAL			28	45	62.22
	Unmapped tests	chip_sival_flash_info_access	6.382m	2.915ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	11.232m	4.411ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.259h	16.993ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	18.950m	5.863ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.803m	4.654ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.989m	5.659ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.228m	2.733ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.467m	2.598ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2792	2922	95.55

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	18	18	16	88.89
V2	280	266	217	77.50
V2S	1	1	1	100.00
V3	92	21	10	10.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.34	95.50	94.59	95.66	--	95.37	97.38	99.57

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 54 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.9147372083201279669523564952538142952360974809832357331654706657101106427941
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:46:38) Loading:
  (15:46:38) Loading:
  (15:46:38) Loading: 4 packages loaded
  (15:46:38) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:46:38) WARNING: Target pattern parsing failed.
  (15:46:38) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:46:38) INFO: Elapsed time: 38.876s
  (15:46:38) INFO: 0 processes.
  (15:46:38) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.111116395471225597166195725387666241146316051142083319381461321843774175550597
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:55:27) Loading:
  (15:55:28) Loading:
  (15:55:28) Loading: 4 packages loaded
  (15:55:28) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:55:28) WARNING: Target pattern parsing failed.
  (15:55:28) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:55:28) INFO: Elapsed time: 16.106s
  (15:55:28) INFO: 0 processes.
  (15:55:28) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_smoke has 3 failures.

0.rom_e2e_smoke.87026798197357524725254576386609368975088970155475838511343453227796330614980
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log

  (15:47:12) Loading:
  (15:47:12) Loading:
  (15:47:12) Loading: 4 packages loaded
  (15:47:13) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:47:13) WARNING: Target pattern parsing failed.
  (15:47:13) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:47:13) INFO: Elapsed time: 46.005s
  (15:47:13) INFO: 0 processes.
  (15:47:13) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_smoke.17479510716182528913957922207764397548032014078560985774508949001203155821173
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log

  (15:56:56) Loading:
  (15:56:57) Loading:
  (15:56:57) Loading: 4 packages loaded
  (15:56:57) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:56:57) WARNING: Target pattern parsing failed.
  (15:56:57) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:56:57) INFO: Elapsed time: 21.675s
  (15:56:57) INFO: 0 processes.
  (15:56:57) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_shutdown_output has 3 failures.

0.rom_e2e_shutdown_output.86723042815263219790594099157214366618636161977011807809008207539457519194236
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

  (15:46:24) Loading:
  (15:46:25) Loading:
  (15:46:25) Loading: 4 packages loaded
  (15:46:25) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:46:25) WARNING: Target pattern parsing failed.
  (15:46:25) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:46:25) INFO: Elapsed time: 23.407s
  (15:46:25) INFO: 0 processes.
  (15:46:25) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_shutdown_output.43989882912834256651805075170028366065959359440653298283591260299794680521238
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log

  (15:57:07) Loading:
  (15:57:08) Loading:
  (15:57:08) Loading: 4 packages loaded
  (15:57:08) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:08) WARNING: Target pattern parsing failed.
  (15:57:08) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:08) INFO: Elapsed time: 21.972s
  (15:57:08) INFO: 0 processes.
  (15:57:08) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.41335829054523230105085738812604310360912141435833667857685125348536607808459
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

  (15:46:38) Loading:
  (15:46:39) Loading:
  (15:46:39) Loading: 4 packages loaded
  (15:46:39) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:46:39) WARNING: Target pattern parsing failed.
  (15:46:39) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:46:39) INFO: Elapsed time: 33.305s
  (15:46:39) INFO: 0 processes.
  (15:46:39) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.86457696066095660331230785505358854078594484167733646905279725622847002831986
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

  (15:46:20) Loading:
  (15:46:21) Loading:
  (15:46:21) Loading: 4 packages loaded
  (15:46:21) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:46:21) WARNING: Target pattern parsing failed.
  (15:46:21) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:46:21) INFO: Elapsed time: 25.584s
  (15:46:21) INFO: 0 processes.
  (15:46:21) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 23 more tests.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test chip_sw_uart_tx_rx_bootstrap has 2 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.52228059669147545545681711295905589029012939354004916056848419939181668241742
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:7872923a-2d3f-46b5-8ece-8648ac3e7b43
```
  - 1.chip_sw_uart_tx_rx_bootstrap.7189351621440829196341012211119807357355509128569618363116672086098887175023
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:9af508df-0265-4f29-bd7a-a7fb44120f41
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.11251971859608054866508221756410250122638114835707136484704582104330329927930
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:9a400a24-4af9-42b4-802e-27030d441b1e
```
  - 1.chip_sw_rv_timer_systick_test.89812830561441232467597598096737638503960145318679648616620799704752549026436
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:eff1872b-7ebe-4d00-9bfc-b20ff0f30a84
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.33455183418592082132067165152652980255127233755733692468568774789085214881016
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:fcea8061-ca35-43a3-b5c5-4a08cd6b7e2c
```
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.101916574817752365493242750690486563723449019916270632059658167663557572427421
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:2f7d4d6d-e4f6-4d61-8fcf-4abe389f41e1
```
  - 2.chip_sw_power_virus.109717069113761885980055370043288798192015041665354519156304988275353895179786
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:65726910-d2f5-4c0b-989b-a9518ab0a954
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.96660459746621166844647095999167134960461240197273338488026573331719410266917
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  Job ID: smart:85fef7cd-b3ac-4df3-ad80-a283cfbdddb7
```
- ... and 12 more tests.
UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.47112899839451693141045740176216173614737033888358093386496371289359936217346
    Line 400, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2116.849216 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2116.849216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.43943000523843364675974531452761447560520560302773896617835490186903994535586
    Line 378, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1980.687008 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1980.687008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 4 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 4 failures.
  - 20.chip_sw_alert_handler_lpg_sleep_mode_alerts.109057494282477140791058672345899515222957843047823226451530041023365791695987
    Line 831, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3851.580090 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3851.580090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.chip_sw_alert_handler_lpg_sleep_mode_alerts.70940200065961978568268046932487879761314958803651920362804992297014950237686
    Line 824, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3151.683892 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3151.683892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.61011041347922443658626509545825095492245366499768651455097357619559490565225
    Line 825, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.8559663764602133831127089622547163081641204427307597564858488475366363414384
    Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.86176893887905535402261021055147281383528355713642291624924628253902086243549
    Line 815, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14736.569062 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14736.569062 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.94617265035180793011303206962670789490668268675010753916923246490839067557533
    Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14472.524160 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14472.524160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.19773664685195194584040522081804000325563060703828676507937243991882082533331
    Line 823, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23100.062060 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23100.062060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.38976742948600718815624899045046087503870573836172120215471162335216354233032
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23616.613130 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23616.613130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.64060972105089770468688274373516317135497888557091431036433322632280571225399
    Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3663.294166 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3663.294166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.105009508094642171508709322867515890299873746589669593986680794057051034529270
    Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3373.477055 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3373.477055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_shutdown_exception_c has 3 failures.
  - 0.rom_e2e_shutdown_exception_c.85397293336453444508768443156237719870202948200112934449079480394782707966538
    Line 989, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_shutdown_exception_c.68253886770669977508273151693274769854132225244496375500936227093656827551707
    Line 990, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.87702711040535595488516299481932585403654082503232899825045591064298443989017
    Line 760, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2591.403000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2591.403000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.3282783087990203657932678450879155543388246455745586875267624635453018050797
    Line 737, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2249.103000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2249.103000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.78158294529490906594022155616083580016117336480427037965990541438440840879701
    Line 859, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2352.228500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2352.228500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.74561350120946942035510471894213862550027854805965896896170536979288990128451
    Line 797, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 51232.441547 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 51232.441547 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.92168674471573202264423431219685664777174331859043151889713629330429149510546
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 50652.124147 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 50652.124147 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.49517746510321221300876174140003900567031804049799656993531356956763721709000
    Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 51495.684166 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 51495.684166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.32291483041359834912498709627148970255854978609722934129852257016487276403308
    Line 814, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_static_critical.101070974132235083026383903747586335825494356780555725003071120806407814185967
    Line 746, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 12.chip_sw_all_escalation_resets.73203615303101902888705181699742629383749947856139980982832336260719692973086
    Line 825, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3125.847348 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3125.847348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.chip_sw_all_escalation_resets.11941980921979428909731749450800295598739269135501186495791105365693459300490
    Line 808, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2938.576056 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2938.576056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.26054295533499989998177378092721352336655607315393792752096205448487637276629
    Line 864, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 17742.979754 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 17742.979754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 1.chip_sw_power_virus.94118076056552284016977624624233148404209683007343223653973967932905764771193
    Line 1022, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5425.467510 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5425.467510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 2.chip_csr_aliasing.16048927361743124283691966653003502956564471198548666501698929021865320973491
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:643c42d7-2722-42ea-b9ef-280eb72a6cc2
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_edn_auto_mode has 1 failures.
  - 2.chip_sw_edn_auto_mode.23744325475165741626161631603973218262672994810076047641958610000979638620729
    Line 1490, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_auto_mode/latest/run.log
```
  UVM_ERROR @ 18016.961801 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
  
  UVM_INFO @ 18016.961801 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```