CHIP Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.164m	2.317ms	3	3	100.00
		chip_sw_example_rom	2.051m	2.427ms	3	3	100.00
		chip_sw_example_manufacturer	4.241m	2.634ms	3	3	100.00
		chip_sw_example_concurrency	5.418m	2.694ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	5.625m	5.757ms	5	5	100.00
V1	csr_rw	chip_csr_rw	10.264m	5.876ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.087h	39.182ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.806h	63.292ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.832m	2.374ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.806h	63.292ms	5	5	100.00
		chip_csr_rw	10.264m	5.876ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.190s	256.752us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.287m	4.059ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.287m	4.059ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.287m	4.059ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	11.584m	4.410ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	11.584m	4.410ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	11.233m	4.512ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	11.484m	4.419ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	12.596m	4.716ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	36.664m	12.896ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	32.002m	7.852ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	23.759m	12.884ms	5	5	100.00
V1		TOTAL			200	220	90.91
V2	chip_pin_mux	chip_padctrl_attributes	4.556m	5.254ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.556m	5.254ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.331m	3.149ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.738m	2.806ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	7.226m	3.647ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	33.437m	16.609ms	5	5	100.00
		chip_tap_straps_testunlock0	19.670m	10.201ms	5	5	100.00
		chip_tap_straps_rma	8.729m	5.364ms	5	5	100.00
		chip_tap_straps_prod	31.824m	16.806ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.236m	2.792ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	22.660m	8.337ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	13.770m	5.613ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	13.770m	5.613ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.841m	7.462ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	47.289m	21.249ms	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.017m	4.158ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.599m	5.784ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.224m	18.573ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.708m	3.636ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	16.410m	5.619ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.488m	3.354ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	29.194m	9.816ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.629m	2.887ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.669m	5.485ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.987m	2.534ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.289m	2.415ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	18.962m	7.036ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.177m	5.032ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.166m	3.090ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.177m	5.032ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.706m	3.123ms	3	3	100.00
		chip_sw_aes_smoketest	4.513m	2.827ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.325m	2.967ms	3	3	100.00
		chip_sw_clkmgr_smoketest	3.570m	3.115ms	3	3	100.00
		chip_sw_csrng_smoketest	5.810m	2.968ms	3	3	100.00
		chip_sw_entropy_src_smoketest	9.454m	3.458ms	3	3	100.00
		chip_sw_gpio_smoketest	4.658m	3.096ms	3	3	100.00
		chip_sw_hmac_smoketest	7.553m	2.581ms	3	3	100.00
		chip_sw_kmac_smoketest	4.424m	2.700ms	3	3	100.00
		chip_sw_otbn_smoketest	30.153m	9.997ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	4.622m	3.376ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.097m	4.922ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.329m	6.072ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.497m	3.322ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.394m	2.750ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.759m	2.453ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.025m	2.511ms	3	3	100.00
		chip_sw_uart_smoketest	5.580m	3.078ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.601m	4.620ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.700h	77.024ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke			0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock			0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	11.305m	4.525ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	7.054m	4.573ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.974h	59.300ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.283h	64.853ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	9.412m	5.592ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	9.412m	5.592ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.806h	63.292ms	5	5	100.00
		chip_same_csr_outstanding	1.280h	28.985ms	19	20	95.00
		chip_csr_hw_reset	5.625m	5.757ms	5	5	100.00
		chip_csr_rw	10.264m	5.876ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.806h	63.292ms	5	5	100.00
		chip_same_csr_outstanding	1.280h	28.985ms	19	20	95.00
		chip_csr_hw_reset	5.625m	5.757ms	5	5	100.00
		chip_csr_rw	10.264m	5.876ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.634m	2.816ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.100s	57.527us	100	100	100.00
		xbar_smoke_large_delays	2.017m	10.828ms	100	100	100.00
		xbar_smoke_slow_rsp	2.118m	7.117ms	100	100	100.00
		xbar_random_zero_delays	52.870s	592.791us	100	100	100.00
		xbar_random_large_delays	20.832m	116.627ms	100	100	100.00
		xbar_random_slow_rsp	21.598m	66.674ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.003m	1.476ms	100	100	100.00
		xbar_error_and_unmapped_addr	58.820s	1.335ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.643m	2.709ms	100	100	100.00
		xbar_error_and_unmapped_addr	58.820s	1.335ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.530m	3.051ms	100	100	100.00
		xbar_access_same_device_slow_rsp	47.469m	153.569ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.337m	2.517ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.542m	20.559ms	100	100	100.00
		xbar_stress_all_with_error	12.556m	20.360ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	18.245m	24.671ms	100	100	100.00
		xbar_stress_all_with_reset_error	14.629m	21.841ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke			0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output			0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.560s	10.320us	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma			0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	39.040s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	40.080s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	38.320s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	39.720s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	40.050s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	39.980s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	42.590s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	39.460s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	39.750s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	41.310s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	38.580s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	42.050s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	39.780s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	40.720s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	37.980s	10.200us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0			0	3	0.00
		rom_e2e_asm_init_dev			0	3	0.00
		rom_e2e_asm_init_prod			0	3	0.00
		rom_e2e_asm_init_prod_end			0	3	0.00
		rom_e2e_asm_init_rma			0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	40.870s	10.300us	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.969m	3.167ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.708m	3.636ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.685m	2.804ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.275m	3.399ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	35.997m	10.010ms	1	3	33.33
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.547m	18.196ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.547m	18.196ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	6.913m	4.061ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.097m	4.922ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	6.913m	4.061ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	19.503m	8.416ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	19.503m	8.416ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.913m	6.827ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.696m	5.042ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.012m	5.448ms	3	3	100.00
		chip_sw_aes_idle	5.275m	3.399ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.356m	3.380ms	3	3	100.00
		chip_sw_kmac_idle	4.801m	3.708ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	8.703m	4.197ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.701m	4.480ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.652m	5.145ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.023m	5.264ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	21.010m	9.078ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.429m	3.498ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.932m	4.512ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.743m	4.339ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.742m	4.617ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.675m	4.753ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.635m	4.839ms	3	3	100.00
		chip_sw_ast_clk_outputs	16.841m	7.462ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.155m	9.738ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.743m	4.339ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.742m	4.617ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.017m	4.158ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.599m	5.784ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.224m	18.573ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.708m	3.636ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	16.410m	5.619ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.488m	3.354ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	29.194m	9.816ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.629m	2.887ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.669m	5.485ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.987m	2.534ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.954m	3.067ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	11.940m	3.975ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	19.745m	7.349ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	56.677m	24.206ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.173m	3.074ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.410m	3.183ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	25.914m	10.010ms	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	4.931m	3.244ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	9.469m	4.985ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	31.676m	27.118ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.252h	29.103ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.841m	7.462ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.257m	5.041ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.540m	3.105ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.815m	5.052ms	98	100	98.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	31.445m	8.640ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	29.300m	7.462ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.348m	3.627ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	13.119m	5.840ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.333m	2.923ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	24.749m	8.603ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	31.568m	24.472ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.109m	3.322ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	41.400s	10.300us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.126m	4.870ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	31.568m	24.472ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	31.568m	24.472ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	53.233m	20.580ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	53.233m	20.580ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.622m	5.576ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.547m	18.196ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	55.408m	13.795ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.616m	2.637ms	3	3	100.00
		chip_sw_edn_entropy_reqs	14.126m	4.150ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.616m	2.637ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	29.300m	7.462ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	5.631m	2.943ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	34.793m	18.484ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.554m	5.925ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.599m	5.784ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.743m	4.094ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.017m	4.158ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.386h	43.184ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	34.793m	18.484ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.582m	3.085ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	29.992m	10.010ms	2	3	66.67
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.317m	4.769ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.386h	43.184ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.317m	4.769ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.317m	4.769ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	8.317m	4.769ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.317m	4.769ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.815m	5.052ms	98	100	98.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.816m	8.070ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.072m	5.883ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.557m	5.559ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.557m	5.559ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.930m	3.539ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.488m	3.354ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.356m	3.380ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	13.761m	4.912ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	18.326m	4.979ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	14.399m	4.797ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.983m	4.318ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	29.992m	10.010ms	2	3	66.67
		chip_sw_keymgr_key_derivation_jitter_en	29.194m	9.816ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	30.199m	9.609ms	2	3	66.67
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	35.997m	10.010ms	1	3	33.33
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.226h	18.043ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.359m	2.571ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.209m	3.104ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.629m	2.887ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	29.992m	10.010ms	2	3	66.67
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	16.162m	12.127ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.589m	3.308ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.041m	2.414ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.801m	3.708ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.911m	6.038ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	33.437m	16.609ms	5	5	100.00
		chip_tap_straps_rma	8.729m	5.364ms	5	5	100.00
		chip_tap_straps_prod	31.824m	16.806ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.863m	3.240ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	16.162m	12.127ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	16.162m	12.127ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	16.162m	12.127ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	30.845m	8.609ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	8.317m	4.769ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.386h	43.184ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.861m	3.989ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	20.545m	7.886ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.417m	8.938ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.963m	9.455ms	3	3	100.00
		chip_sw_lc_ctrl_transition	16.162m	12.127ms	15	15	100.00
		chip_sw_keymgr_key_derivation	29.992m	10.010ms	2	3	66.67
		chip_sw_rom_ctrl_integrity_check	8.338m	8.863ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	15.907m	8.628ms	3	3	100.00
		chip_prim_tl_access	5.816m	8.070ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.155m	9.738ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.429m	3.498ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.932m	4.512ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.743m	4.339ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.742m	4.617ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.675m	4.753ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.635m	4.839ms	3	3	100.00
		chip_tap_straps_dev	33.437m	16.609ms	5	5	100.00
		chip_tap_straps_rma	8.729m	5.364ms	5	5	100.00
		chip_tap_straps_prod	31.824m	16.806ms	5	5	100.00
		chip_rv_dm_lc_disabled	7.910m	17.249ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.044m	2.598ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.968m	3.139ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.973m	3.735ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.853m	3.341ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	34.256m	26.852ms	3	3	100.00
		chip_rv_dm_lc_disabled	7.910m	17.249ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.551h	49.882ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.460h	50.697ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	15.115m	9.330ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.439h	46.861ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	34.256m	26.852ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.933m	3.009ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.058m	2.666ms	3	3	100.00
		rom_volatile_raw_unlock			0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	16.162m	12.127ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	34.793m	18.484ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.106m	3.771ms	3	3	100.00
		chip_sw_keymgr_key_derivation	29.992m	10.010ms	2	3	66.67
		chip_sw_sram_ctrl_scrambled_access	11.646m	5.043ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.906m	2.862ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	34.793m	18.484ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.106m	3.771ms	3	3	100.00
		chip_sw_keymgr_key_derivation	29.992m	10.010ms	2	3	66.67
		chip_sw_sram_ctrl_scrambled_access	11.646m	5.043ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.906m	2.862ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	16.162m	12.127ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	21.157m	14.785ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.863m	3.240ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.861m	3.989ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	20.545m	7.886ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.417m	8.938ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.963m	9.455ms	3	3	100.00
		chip_sw_lc_ctrl_transition	16.162m	12.127ms	15	15	100.00
		chip_prim_tl_access	5.816m	8.070ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.816m	8.070ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.130m	9.013ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	27.049m	19.628ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.716m	7.828ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.320m	8.445ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	11.443m	5.648ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	27.916m	22.061ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	24.226m	12.291ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	19.503m	8.416ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	23.330m	9.804ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	9.826m	4.545ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.130m	9.013ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	7.213m	5.105ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.011h	36.386ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.773m	7.309ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.668m	6.909ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	43.042m	26.193ms	2	3	66.67
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	24.749m	8.603ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	30.494m	13.527ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	35.311m	20.754ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.770m	2.555ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.815m	5.052ms	98	100	98.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.338m	8.863ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.338m	8.863ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	30.494m	13.527ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	43.042m	26.193ms	2	3	66.67
		chip_sw_pwrmgr_wdog_reset	9.826m	4.545ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.097m	4.922ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.100m	4.991ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	12.467m	6.689ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.478m	5.060ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	35.370m	11.822ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.494m	2.883ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.815m	5.052ms	98	100	98.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	29.624m	8.322ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	19.690m	5.991ms	3	3	100.00
		chip_plic_all_irqs_10	10.482m	3.781ms	3	3	100.00
		chip_plic_all_irqs_20	15.371m	4.629ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.401m	2.766ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.526m	3.278ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke			0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.613m	6.976ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.886m	4.648ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.442m	3.438ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.803m	2.542ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.646m	5.043ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.669m	5.485ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	14.131m	8.497ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.658m	6.327ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	15.907m	8.628ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.815m	5.052ms	98	100	98.00
		chip_sw_data_integrity_escalation	13.770m	5.613ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.424m	2.432ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.361m	3.147ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.325m	3.095ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.904m	4.041ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	29.488m	8.009ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.731h	31.228ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	46.285m	12.816ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.699m	3.475ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.911m	6.038ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.815m	5.052ms	98	100	98.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.912m	3.251ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	35.370m	11.822ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.503m	5.609ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.915m	4.003ms	87	90	96.67
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	25.505m	12.464ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	31.445m	8.640ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	29.624m	8.322ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.519h	256.201ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	47.111m	22.236ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	28.320m	14.056ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.100m	4.991ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.694m	3.963ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.692m	4.419ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	8.729m	5.364ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	7.910m	17.249ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2529	2627	96.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.507m	3.415ms	0	3	0.00
V2S		TOTAL			0	3	0.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.618h	49.923ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.210m	5.604ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.662m	2.486ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.711m	1.721ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.944m	2.403ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.084h	50.669ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.063h	60.000ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.221h	49.882ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.827m	3.643ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.321m	3.213ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	29.527m	6.365ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	26.036m	7.254ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	10.920m	3.357ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	20.311m	5.513ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	//sw/device/tests:i2c_target_test			0	0	--
		//sw/device/tests/pmod:i2c_host_clock_stretching_test			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.609m	2.432ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	8.866m	4.381ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.778m	23.349ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.042m	5.511ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	30.494m	13.527ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.815m	5.052ms	98	100	98.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	11.584m	4.410ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.292h	18.213ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.662m	2.486ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.711m	1.721ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.944m	2.403ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.135m	5.972ms	3	3	100.00
V3		TOTAL			30	45	66.67
	Unmapped tests	chip_sival_flash_info_access	5.385m	2.733ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	14.093m	5.958ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.107h	17.752ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	17.605m	5.600ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.811m	4.723ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.805m	5.989ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.786m	3.009ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.001m	2.557ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2783	2922	95.24

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	18	18	17	94.44
V2	280	266	209	74.64
V2S	1	1	0	0.00
V3	92	21	12	13.04

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.23	95.49	94.26	95.69	--	94.98	97.38	99.55

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 54 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.40862753016156369881968405345232231734962283368611074064904297438062926630227
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (16:19:52) Loading:
  (16:19:53) Loading:
  (16:19:53) Loading: 4 packages loaded
  (16:19:53) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:19:53) WARNING: Target pattern parsing failed.
  (16:19:53) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:19:53) INFO: Elapsed time: 31.809s
  (16:19:53) INFO: 0 processes.
  (16:19:53) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.93013290982874853845215745840957462627564702881937807398783610675253474944644
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (16:24:38) Loading:
  (16:24:39) Loading:
  (16:24:39) Loading: 4 packages loaded
  (16:24:39) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:24:39) WARNING: Target pattern parsing failed.
  (16:24:39) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:24:39) INFO: Elapsed time: 24.646s
  (16:24:39) INFO: 0 processes.
  (16:24:39) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_smoke has 3 failures.

0.rom_e2e_smoke.82326924121353661682095711326951990451299854114563105342174744791274391731443
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log

  (16:20:34) Loading:
  (16:20:35) Loading:
  (16:20:35) Loading: 4 packages loaded
  (16:20:35) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:20:35) WARNING: Target pattern parsing failed.
  (16:20:35) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:20:35) INFO: Elapsed time: 21.425s
  (16:20:35) INFO: 0 processes.
  (16:20:35) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_smoke.8828439653059795075297513271237313476580939218842597011338042107709073308155
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log

  (16:26:14) Loading:
  (16:26:15) Loading:
  (16:26:15) Loading: 4 packages loaded
  (16:26:15) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:26:15) WARNING: Target pattern parsing failed.
  (16:26:15) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:26:15) INFO: Elapsed time: 21.173s
  (16:26:15) INFO: 0 processes.
  (16:26:15) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_shutdown_output has 3 failures.

0.rom_e2e_shutdown_output.59121211216152630205029956153104269584290146385762804063684661775565801499951
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

  (16:20:24) Loading:
  (16:20:25) Loading:
  (16:20:25) Loading: 4 packages loaded
  (16:20:25) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:20:25) WARNING: Target pattern parsing failed.
  (16:20:25) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:20:25) INFO: Elapsed time: 19.818s
  (16:20:25) INFO: 0 processes.
  (16:20:25) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_shutdown_output.94410811165812264730576471804997893444657514437773522029210726382181312406548
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log

  (16:25:48) Loading:
  (16:25:48) Loading:
  (16:25:48) Loading: 4 packages loaded
  (16:25:48) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:25:48) WARNING: Target pattern parsing failed.
  (16:25:48) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:25:48) INFO: Elapsed time: 31.711s
  (16:25:48) INFO: 0 processes.
  (16:25:48) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.39750269477050668220130513805058507392405097165856492763744834423137776808486
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

  (16:21:41) Loading:
  (16:21:42) Loading:
  (16:21:42) Loading: 4 packages loaded
  (16:21:42) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:21:42) WARNING: Target pattern parsing failed.
  (16:21:42) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:21:42) INFO: Elapsed time: 74.867s
  (16:21:42) INFO: 0 processes.
  (16:21:42) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.58579151706102708916735320523548378406126844543450749400007108363177919373446
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

  (16:20:47) Loading:
  (16:20:48) Loading:
  (16:20:48) Loading: 4 packages loaded
  (16:20:48) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:20:48) WARNING: Target pattern parsing failed.
  (16:20:48) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:20:48) INFO: Elapsed time: 27.701s
  (16:20:48) INFO: 0 processes.
  (16:20:48) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 23 more tests.

UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.535143450632291404331750594572952347533335452515911386334282816107613873429
    Line 383, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2652.764384 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2652.764384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.66896222367285529044399654925293841236843340823919074718779796856416741986853
    Line 377, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2393.605220 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2393.605220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 6 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.82750693852461087229681644298016805817670942067566111818667794237626533762048
    Line 1039, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.12953710901471668968064903281302073303033371337387286085478291180546570320262
    Line 1030, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.6360360470635942229263065897430705837658268229836067028205544061539473904910
    Line 1077, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.38862103736490794366384479005658330154488987730123941681599851195292580166610
    Line 989, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.8247695090937894332212102612310727444752454244858797994121264132389639802784
    Line 980, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.10843425127365693552196066279358664556797276667589365025444235288567353916455
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:4fe66cb2-3d7a-4f5d-b0d5-ad0b8525796f
```
  - 1.chip_sw_rv_timer_systick_test.79970207258959724838118593337464425846459822263063076976172394568181438755780
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:4bff01f4-3df2-4ed1-8de4-597750513f95
```
  - ... and 1 more failures.
- Test chip_sw_ast_clk_rst_inputs has 2 failures.
  - 0.chip_sw_ast_clk_rst_inputs.23829546684624998999042049282223524340666318320929651995463104949133376021513
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:590b283a-bee6-49aa-805e-1aaee3d912c0
```
  - 1.chip_sw_ast_clk_rst_inputs.61432989247677635080089081830971870149992496258781996448981492197012925896402
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:52e5dd0a-8992-4705-ba98-2ad2d2d68520
```
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_key_derivation_vseq] wait timeout occurred! has 4 failures:
- Test chip_sw_keymgr_key_derivation_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.47152398624399208637908721615478010964821033056391782843504044351336789518052
    Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @ 10010.300001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.90653484395701354081926575169090586960513187159272994137436776798005801543379
    Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @ 10010.400001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_key_derivation has 1 failures.
  - 2.chip_sw_keymgr_key_derivation.87232945480681194236923389696599086930515784244325238818526963943205692831810
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation/latest/run.log
```
  UVM_FATAL @ 10010.240001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.94037347218419802230892573882992415693230001665667115442733903639878758295170
    Line 746, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.6277065892201520409242454699393641150198557721794726926880462529955275171134
    Line 862, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_aes_masking_off_vseq.sv:162) [chip_sw_aes_masking_off_vseq] Check failed state_init_share* == '* (* [*] vs * [*]) Share * of the input not equal zero. has 3 failures:

Test chip_sw_aes_masking_off has 3 failures.

0.chip_sw_aes_masking_off.50872679030684457411525866978198029813162651732304102301881216380340976679238
Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_masking_off/latest/run.log

  UVM_FATAL @ 3321.421894 us: (chip_sw_aes_masking_off_vseq.sv:162) [uvm_test_top.env.virtual_sequencer.chip_sw_aes_masking_off_vseq] Check failed state_init_share1 == '0 (261008556511606517935595337728332530022 [0xc45c6b6290143840c51c1bbea8020166] vs 0 [0x0]) Share 1 of the input not equal zero.
  UVM_INFO @ 3321.421894 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aes_masking_off.62014364074305549766088787075294037528818904623409476815904894661659903874324
Line 918, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_masking_off/latest/run.log

  UVM_FATAL @ 3414.944890 us: (chip_sw_aes_masking_off_vseq.sv:162) [uvm_test_top.env.virtual_sequencer.chip_sw_aes_masking_off_vseq] Check failed state_init_share1 == '0 (258020827431365450105344558941365215953 [0xc21d00f7e4e3eb55b5669806fa8622d1] vs 0 [0x0]) Share 1 of the input not equal zero.
  UVM_INFO @ 3414.944890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.102841661005946481450200304798145510571736259324833952850580848522979190746169
    Line 938, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14784.838980 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14784.838980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.49766202853738897683454037243007736773885160473909065379666770329005639255277
    Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14778.092440 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14778.092440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.7036777322173862109375248679377161412239578650673451432459905471308994610270
    Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23349.227158 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23349.227158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.18404070654127733114531757992438767388445056463725642951741655434399757291446
    Line 827, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23250.791560 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23250.791560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.51328793612728637661911398092219773894484720334074009106692961393313728283250
    Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3629.943799 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3629.943799 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.113136490155389670188299959995719206461156004831801819429974379755819234440056
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 4418.719231 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 4418.719231 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 3 failures:
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.100846748680572648740736134723432276337259428303656681063058465249117529117045
    Line 1048, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5220.418512 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5220.418512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_power_virus.14051390760265511950892607530009660416886370059893322948239498507086522415679
    Line 1034, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5604.410807 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5604.410807 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_shutdown_exception_c has 3 failures.
  - 0.rom_e2e_shutdown_exception_c.65300008407476637567432054457098743057559776263042568367596473216296210615783
    Line 1062, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_shutdown_exception_c.25076937301523304972460531581995117707850020192091519258363484441924093258356
    Line 983, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.82402961447043464048660952364917596210183162771071162768380877149099713318114
    Line 1003, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.35623013989341761455878482777909357444828303275145565297571344526163592362061
    Line 1021, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.27147971759146522000216617592516233717549041996804222139807007037569487603296
    Line 984, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.4168643093229915810534223336482066527463712785014805818270185443505482562926
    Line 847, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2485.639500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2485.639500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.110135494271709687143663662499253385422686211884355046276461636969120427135479
    Line 740, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 1721.227000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1721.227000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.74410943126293457262525679181913583177147463005202989707418514794496984502434
    Line 844, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2403.437000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2403.437000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.107320899494546645472432911124678272028772044077624264771974516388259113858843
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_static_critical.42453745365040664155845910379241168983898090215754424101043002894845481755460
    Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 3 failures.
  - 14.chip_sw_alert_handler_lpg_sleep_mode_alerts.74634935433994298010694729416389094973915555091546138356617674325358483092028
    Line 793, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3872.301490 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3872.301490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.chip_sw_alert_handler_lpg_sleep_mode_alerts.62159322624214020031077067466889464988764313809455464965979563181169697564464
    Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4196.943362 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 4196.943362 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred! has 2 failures:
- Test chip_sw_keymgr_sideload_aes has 2 failures.
  - 0.chip_sw_keymgr_sideload_aes.24085572007690272102992517842729165880250862095157425362862141771645260619903
    Line 799, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest/run.log
```
  UVM_FATAL @ 10010.140001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred!
  UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_keymgr_sideload_aes.64300661346824258830247567423127224643689074732793482453451729001496003424950
    Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_aes/latest/run.log
```
  UVM_FATAL @ 10010.340001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred!
  UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.61534949809771093701869951322766817277969171123662393953684718118155861378047
    Line 1055, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3164275472340747788794005886428883175986403776920112235887286051304525338167
    Line 1036, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.83132834097052772956454270883836001564614246328489443467433626464706525869165
    Line 1056, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.103779254762838639781705150871208891965354980902321670292725581157744718172003
    Line 1069, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 2 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.94912644052488231284393971759766544796478818155305999566915643871092859781669
    Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 50668.663175 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 50668.663175 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.63445188818479803017133892489284355144307899678795996785564211120852543550380
    Line 882, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 49881.762529 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 49881.762529 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 10.chip_sw_all_escalation_resets.47307958292265421120445775882192511044861802522120552982527767171777673059781
    Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3213.757400 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3213.757400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 68.chip_sw_all_escalation_resets.54978965755495396634394661854729244557613225252843305109364704601873566928534
    Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3093.334376 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3093.334376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.67621070031006687929358233948459650158161326587591999362495733402960995924950
    Line 1030, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.91122576623353341776445564343742434179062113439562379823325438778317461486977
    Line 1070, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.47296012500223157143650627281643759645554722286028671895605595615322079626660
    Line 879, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.49636698291624620570829552155616237148724899163184190474573077670628117784301
    Line 871, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 14291.837532 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 14291.837532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred! has 1 failures:
- Test chip_sw_keymgr_sideload_kmac has 1 failures.
  - 1.chip_sw_keymgr_sideload_kmac.79992499284584561405268423064754084708006489022364802003957812451325227469157
    Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_kmac/latest/run.log
```
  UVM_FATAL @ 10010.320001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred!
  UVM_INFO @ 10010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.
  - 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.95130221583020020740892995289157009844264668312241096680042071409888806151734
    Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6347.370056 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6347.370056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'scl_o' has 1 failures:
- Test chip_same_csr_outstanding has 1 failures.
  - 10.chip_same_csr_outstanding.106745990217023790351117174732334335443883943448001236342526425561093161511893
    Line 3147, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/10.chip_same_csr_outstanding/latest/run.log
```
      Offending 'scl_o'
  UVM_ERROR @ 18709.166082 us: (i2c_controller_fsm.sv:925) [ASSERT FAILED] SclOutputGlitch_A
  UVM_INFO @ 18709.166082 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```