CHIP Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.187m	3.366ms	3	3	100.00
		chip_sw_example_rom	2.374m	2.690ms	3	3	100.00
		chip_sw_example_manufacturer	5.163m	2.708ms	3	3	100.00
		chip_sw_example_concurrency	3.959m	2.618ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.521m	6.476ms	5	5	100.00
V1	csr_rw	chip_csr_rw	10.306m	5.697ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	31.413m	16.255ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	1.679h	34.970ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.993m	2.675ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.679h	34.970ms	4	5	80.00
		chip_csr_rw	10.306m	5.697ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.910s	245.253us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.720m	4.800ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.720m	4.800ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.720m	4.800ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	13.222m	4.117ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	13.222m	4.117ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	11.132m	4.650ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	11.389m	4.814ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	11.607m	4.152ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	42.060m	12.922ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	24.199m	7.814ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	31.129m	13.222ms	5	5	100.00
V1		TOTAL			199	220	90.45
V2	chip_pin_mux	chip_padctrl_attributes	5.377m	5.500ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.377m	5.500ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.278m	3.097ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	9.799m	5.527ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.386m	4.139ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	35.602m	19.267ms	5	5	100.00
		chip_tap_straps_testunlock0	6.004m	4.884ms	5	5	100.00
		chip_tap_straps_rma	9.980m	6.844ms	5	5	100.00
		chip_tap_straps_prod	20.037m	10.386ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.874m	2.857ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	25.521m	8.701ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	13.544m	5.159ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	13.544m	5.159ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	17.922m	8.090ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	51.180m	20.874ms	3	3	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.338m	3.843ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.137m	5.416ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.076h	18.849ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.016m	3.366ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	15.537m	6.284ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.656m	3.125ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	29.746m	9.245ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en	5.820m	3.671ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.008m	5.489ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.499m	2.300ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.990m	2.401ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	18.341m	7.975ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.123m	5.471ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.657m	2.416ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.123m	5.471ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.384m	2.751ms	3	3	100.00
		chip_sw_aes_smoketest	4.155m	2.456ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.288m	2.750ms	3	3	100.00
		chip_sw_clkmgr_smoketest	3.708m	2.722ms	3	3	100.00
		chip_sw_csrng_smoketest	4.062m	2.325ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.094m	3.388ms	3	3	100.00
		chip_sw_gpio_smoketest	4.091m	2.902ms	3	3	100.00
		chip_sw_hmac_smoketest	6.484m	2.788ms	3	3	100.00
		chip_sw_kmac_smoketest	6.612m	3.056ms	3	3	100.00
		chip_sw_otbn_smoketest	46.292m	11.250ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.032m	3.578ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	6.814m	5.588ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.633m	5.899ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.452m	3.013ms	3	3	100.00
		chip_sw_rv_timer_smoketest	6.817m	2.768ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.574m	2.477ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.265m	3.178ms	3	3	100.00
		chip_sw_uart_smoketest	5.818m	2.848ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	8.258m	5.262ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.811h	77.262ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke			0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock			0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	10.059m	4.162ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	12.719m	10.515ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.008h	58.331ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.134h	64.033ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.900m	4.941ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.900m	4.941ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.679h	34.970ms	4	5	80.00
		chip_same_csr_outstanding	1.151h	31.345ms	20	20	100.00
		chip_csr_hw_reset	6.521m	6.476ms	5	5	100.00
		chip_csr_rw	10.306m	5.697ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.679h	34.970ms	4	5	80.00
		chip_same_csr_outstanding	1.151h	31.345ms	20	20	100.00
		chip_csr_hw_reset	6.521m	6.476ms	5	5	100.00
		chip_csr_rw	10.306m	5.697ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.758m	2.818ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.540s	53.341us	100	100	100.00
		xbar_smoke_large_delays	2.091m	10.958ms	100	100	100.00
		xbar_smoke_slow_rsp	2.075m	7.108ms	100	100	100.00
		xbar_random_zero_delays	54.880s	640.413us	100	100	100.00
		xbar_random_large_delays	21.850m	115.199ms	100	100	100.00
		xbar_random_slow_rsp	23.106m	68.426ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.008m	1.329ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.009m	1.413ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.649m	2.513ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.009m	1.413ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.532m	3.479ms	100	100	100.00
		xbar_access_same_device_slow_rsp	52.081m	154.943ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.491m	2.569ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	13.950m	22.530ms	100	100	100.00
		xbar_stress_all_with_error	10.744m	13.800ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	15.379m	17.529ms	100	100	100.00
		xbar_stress_all_with_reset_error	15.435m	19.492ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke			0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output			0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	42.370s	10.320us	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma			0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	38.420s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	39.110s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	39.800s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	39.960s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	39.070s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	38.770s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	39.460s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	42.850s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	38.260s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	40.460s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	41.020s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	40.820s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	38.790s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	41.700s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	40.420s	10.120us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0			0	3	0.00
		rom_e2e_asm_init_dev			0	3	0.00
		rom_e2e_asm_init_prod			0	3	0.00
		rom_e2e_asm_init_prod_end			0	3	0.00
		rom_e2e_asm_init_rma			0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	40.610s	10.280us	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.408m	2.639ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.016m	3.366ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.003m	3.167ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.674m	2.960ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	35.580m	10.010ms	1	3	33.33
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.934m	19.431ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.934m	19.431ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.509m	3.745ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	6.814m	5.588ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.509m	3.745ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.528m	8.171ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.528m	8.171ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.942m	7.612ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.637m	5.307ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.089m	5.444ms	3	3	100.00
		chip_sw_aes_idle	4.674m	2.960ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.585m	2.541ms	3	3	100.00
		chip_sw_kmac_idle	4.885m	2.742ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.210m	5.217ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.759m	4.432ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	12.443m	5.280ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.963m	5.085ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	27.001m	12.254ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.635m	4.284ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.349m	4.708ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.428m	3.650ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.929m	4.218ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.901m	3.620ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.304m	4.488ms	3	3	100.00
		chip_sw_ast_clk_outputs	17.922m	8.090ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	17.263m	9.756ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.428m	3.650ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.929m	4.218ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.338m	3.843ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.137m	5.416ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.076h	18.849ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.016m	3.366ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	15.537m	6.284ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.656m	3.125ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	29.746m	9.245ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en	5.820m	3.671ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.008m	5.489ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.499m	2.300ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.753m	3.467ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	13.698m	4.887ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	18.428m	7.740ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	58.873m	24.918ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.280m	2.894ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	6.124m	3.545ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	22.121m	7.527ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	4.951m	2.929ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.041m	5.529ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	35.078m	16.865ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.044h	23.530ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	17.922m	8.090ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.581m	5.306ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.268m	3.410ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.744m	5.736ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	32.879m	10.477ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	26.595m	7.436ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.625m	4.939ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	11.780m	5.604ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.891m	2.803ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	24.616m	8.568ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	28.711m	24.659ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.777m	2.897ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	43.020s	10.220us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.961m	5.251ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	28.711m	24.659ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	28.711m	24.659ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	54.383m	20.493ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	54.383m	20.493ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.931m	5.883ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.934m	19.431ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	51.554m	14.616ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	3.781m	2.407ms	3	3	100.00
		chip_sw_edn_entropy_reqs	21.061m	5.179ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.781m	2.407ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	26.595m	7.436ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.966m	2.558ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	34.218m	18.504ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	17.662m	5.773ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.137m	5.416ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.505m	4.808ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.338m	3.843ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.293h	42.716ms	2	3	66.67
V2	chip_sw_flash_scramble	chip_sw_flash_init	34.218m	18.504ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.715m	3.450ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	29.049m	10.010ms	1	3	33.33
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.062m	3.927ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.293h	42.716ms	2	3	66.67
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.062m	3.927ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.062m	3.927ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	11.062m	3.927ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.062m	3.927ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.744m	5.736ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	6.348m	10.201ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.176m	5.580ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.296m	5.033ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.296m	5.033ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.459m	2.862ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.656m	3.125ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.585m	2.541ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	16.239m	5.263ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	14.161m	4.950ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	13.548m	5.591ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.495m	4.213ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	29.049m	10.010ms	1	3	33.33
		chip_sw_keymgr_key_derivation_jitter_en	29.746m	9.245ms	2	3	66.67
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	35.381m	10.010ms	2	3	66.67
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	35.580m	10.010ms	1	3	33.33
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.125h	14.510ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.099m	2.298ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.830m	3.000ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.820m	3.671ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	29.049m	10.010ms	1	3	33.33
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	21.315m	12.903ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	3.924m	3.322ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.385m	2.974ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.885m	2.742ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.478m	5.733ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	35.602m	19.267ms	5	5	100.00
		chip_tap_straps_rma	9.980m	6.844ms	5	5	100.00
		chip_tap_straps_prod	20.037m	10.386ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.193m	3.198ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	21.315m	12.903ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	21.315m	12.903ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	21.315m	12.903ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	33.888m	10.038ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	11.062m	3.927ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.293h	42.716ms	2	3	66.67
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.367m	4.583ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.526m	8.582ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	20.220m	8.664ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.531m	8.737ms	3	3	100.00
		chip_sw_lc_ctrl_transition	21.315m	12.903ms	15	15	100.00
		chip_sw_keymgr_key_derivation	29.049m	10.010ms	1	3	33.33
		chip_sw_rom_ctrl_integrity_check	10.090m	8.951ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	17.049m	9.541ms	3	3	100.00
		chip_prim_tl_access	6.348m	10.201ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	17.263m	9.756ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.635m	4.284ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.349m	4.708ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.428m	3.650ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.929m	4.218ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.901m	3.620ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.304m	4.488ms	3	3	100.00
		chip_tap_straps_dev	35.602m	19.267ms	5	5	100.00
		chip_tap_straps_rma	9.980m	6.844ms	5	5	100.00
		chip_tap_straps_prod	20.037m	10.386ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.273m	8.654ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.755m	2.874ms	0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	2.625m	3.116ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.712m	3.295ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.139m	3.331ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	48.127m	27.421ms	3	3	100.00
		chip_rv_dm_lc_disabled	6.273m	8.654ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.555h	50.412ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.486h	48.586ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	19.049m	11.089ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.497h	45.176ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	48.127m	27.421ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.276m	2.234ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.023m	1.963ms	3	3	100.00
		rom_volatile_raw_unlock			0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	21.315m	12.903ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	34.218m	18.504ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.119m	3.188ms	3	3	100.00
		chip_sw_keymgr_key_derivation	29.049m	10.010ms	1	3	33.33
		chip_sw_sram_ctrl_scrambled_access	12.401m	5.025ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.717m	3.176ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	34.218m	18.504ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.119m	3.188ms	3	3	100.00
		chip_sw_keymgr_key_derivation	29.049m	10.010ms	1	3	33.33
		chip_sw_sram_ctrl_scrambled_access	12.401m	5.025ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.717m	3.176ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	21.315m	12.903ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	18.767m	13.916ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.193m	3.198ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.367m	4.583ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.526m	8.582ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	20.220m	8.664ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.531m	8.737ms	3	3	100.00
		chip_sw_lc_ctrl_transition	21.315m	12.903ms	15	15	100.00
		chip_prim_tl_access	6.348m	10.201ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.348m	10.201ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.633m	9.443ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	27.082m	18.150ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	8.635m	7.366ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.936m	9.577ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.191m	6.085ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	25.402m	22.191ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	25.251m	16.274ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.528m	8.171ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	28.384m	11.694ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.451m	5.574ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.633m	9.443ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.465m	3.971ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.072h	43.869ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.649m	7.311ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.025m	6.336ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	36.167m	27.784ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	24.616m	8.568ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	28.558m	11.364ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	33.726m	26.106ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.810m	2.895ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.744m	5.736ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.090m	8.951ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.090m	8.951ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	28.558m	11.364ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	36.167m	27.784ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	11.451m	5.574ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	6.814m	5.588ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.894m	4.589ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	11.252m	6.064ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.663m	4.039ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	28.307m	13.288ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.207m	3.155ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.744m	5.736ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	32.881m	8.330ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.101m	6.456ms	3	3	100.00
		chip_plic_all_irqs_10	10.809m	4.414ms	3	3	100.00
		chip_plic_all_irqs_20	16.253m	4.002ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.411m	3.002ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.001m	3.431ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke			0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.016m	8.053ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.532m	4.732ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.587m	3.584ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.196m	3.158ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.401m	5.025ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.008m	5.489ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	14.219m	8.911ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.620m	7.910ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	17.049m	9.541ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.744m	5.736ms	97	100	97.00
		chip_sw_data_integrity_escalation	13.544m	5.159ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.156m	2.851ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.445m	3.017ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.529m	4.219ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.732m	4.655ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	33.018m	8.651ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.197h	31.342ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	46.966m	11.897ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.860m	3.176ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.478m	5.733ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.744m	5.736ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.705m	3.811ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	28.307m	13.288ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.699m	5.280ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.761m	4.227ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	24.396m	12.377ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	32.879m	10.477ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	32.881m	8.330ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.602h	253.908ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	34.272m	17.134ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	26.379m	13.086ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.894m	4.589ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.697m	4.747ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.248m	4.353ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	9.980m	6.844ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.273m	8.654ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2533	2627	96.42
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.023m	2.638ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.899m	2.356ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.102m	2.206ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.120m	1.895ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.248h	50.446ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.328h	45.428ms	0	1	0.00
		rom_e2e_jtag_inject_rma	48.580m	51.069ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.565m	3.296ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.509m	2.683ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	24.647m	4.664ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	25.543m	8.268ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.570m	3.088ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	19.690m	5.284ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.699m	3.184ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.298m	5.872ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.915m	23.572ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	7.637m	5.190ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	28.558m	11.364ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.744m	5.736ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	13.222m	4.117ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.345h	18.891ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.899m	2.356ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.102m	2.206ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.120m	1.895ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.968m	4.178ms	3	3	100.00
V3		TOTAL			29	45	64.44
	Unmapped tests	chip_sival_flash_info_access	5.446m	3.176ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	13.633m	5.267ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	57.460m	17.547ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	19.200m	5.366ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.586m	4.834ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.542m	5.939ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.542m	2.874ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.537m	2.262ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2788	2922	95.41

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	18	18	16	88.89
V2	280	266	210	75.00
V2S	1	1	1	100.00
V3	91	21	11	12.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.98	95.29	93.71	95.58	--	94.38	97.38	99.53

Failure Buckets

• Exit reason: Error: User command failed Job returned non-zero exit code has 54 failures:

  • Test chip_sw_flash_ctrl_write_clear has 3 failures.

    • 0.chip_sw_flash_ctrl_write_clear.87312969755998436667384498984732342950350734921325286328764986553881543231933
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

        (16:34:05) Loading:
        (16:34:05) Loading:
        (16:34:05) Loading: 4 packages loaded
        (16:34:05) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (16:34:05) WARNING: Target pattern parsing failed.
        (16:34:05) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (16:34:05) INFO: Elapsed time: 20.036s
        (16:34:05) INFO: 0 processes.
        (16:34:05) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_flash_ctrl_write_clear.48057368440310397731372198000949493861223110991878223500593963904902317524209
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

        (16:41:59) Loading:
        (16:42:00) Loading:
        (16:42:00) Loading: 4 packages loaded
        (16:42:00) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (16:42:00) WARNING: Target pattern parsing failed.
        (16:42:00) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (16:42:00) INFO: Elapsed time: 25.730s
        (16:42:00) INFO: 0 processes.
        (16:42:00) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_smoke has 3 failures.

    • 0.rom_e2e_smoke.89953035837714323235629449916645138127875230210260853321083183552695061499965
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log

        (16:34:41) Loading:
        (16:34:41) Loading:
        (16:34:41) Loading: 4 packages loaded
        (16:34:41) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:34:41) WARNING: Target pattern parsing failed.
        (16:34:41) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:34:42) INFO: Elapsed time: 33.935s
        (16:34:42) INFO: 0 processes.
        (16:34:42) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_smoke.31885031470374288961209528710381142759090667029318781895236371014631537389108
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log

        (16:43:14) Loading:
        (16:43:15) Loading:
        (16:43:15) Loading: 4 packages loaded
        (16:43:15) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:43:15) WARNING: Target pattern parsing failed.
        (16:43:15) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:43:15) INFO: Elapsed time: 32.883s
        (16:43:15) INFO: 0 processes.
        (16:43:15) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_shutdown_output has 3 failures.

    • 0.rom_e2e_shutdown_output.89889895355799216173209451455428494538170448648796531515359759882835743123554
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

        (16:36:46) Loading:
        (16:36:47) Loading:
        (16:36:47) Loading: 4 packages loaded
        (16:36:47) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:36:47) WARNING: Target pattern parsing failed.
        (16:36:47) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:36:47) INFO: Elapsed time: 112.203s
        (16:36:47) INFO: 0 processes.
        (16:36:47) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_shutdown_output.110443307053033849147895696555418081147185774583120587220392644158731028564990
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log

        (16:43:17) Loading:
        (16:43:17) Loading:
        (16:43:17) Loading: 4 packages loaded
        (16:43:18) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:43:18) WARNING: Target pattern parsing failed.
        (16:43:18) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:43:18) INFO: Elapsed time: 35.024s
        (16:43:18) INFO: 0 processes.
        (16:43:18) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.69378876598103294587012607649459660532328878335802830481600840252834050193366
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

        (16:34:42) Loading:
        (16:34:43) Loading:
        (16:34:43) Loading: 4 packages loaded
        (16:34:44) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:34:44) WARNING: Target pattern parsing failed.
        (16:34:44) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:34:44) INFO: Elapsed time: 38.852s
        (16:34:44) INFO: 0 processes.
        (16:34:44) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.43274377805294950551644117664202385180599269394033935914269715206297140195456
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

        (16:34:50) Loading:
        (16:34:51) Loading:
        (16:34:51) Loading: 4 packages loaded
        (16:34:52) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:34:52) WARNING: Target pattern parsing failed.
        (16:34:52) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
        (16:34:52) INFO: Elapsed time: 38.769s
        (16:34:52) INFO: 0 processes.
        (16:34:52) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • ... and 23 more tests.

• UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test chip_csr_mem_rw_with_rand_reset has 20 failures.

    • 0.chip_csr_mem_rw_with_rand_reset.81513405996979005739207765089576021862372178547183788698930678606758808838068
      Line 391, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2731.685250 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2731.685250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_csr_mem_rw_with_rand_reset.684303657498312023334291670618016329461554389028257548592667695150476397586
      Line 366, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2341.935431 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2341.935431 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:

  • Test chip_sw_rv_timer_systick_test has 3 failures.

    • 0.chip_sw_rv_timer_systick_test.41341303688757111195975660579278154824125392165378194797426535214089227934252
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:db69457c-f6cd-4f71-b798-d297232d9a6a
      

    • 1.chip_sw_rv_timer_systick_test.90831136832105131350013667650200107764528862053156371397332682351218608682887
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:f464b044-146e-443c-9954-5debe28855be
      

    • ... and 1 more failures.

  • Test chip_sw_coremark has 1 failures.

    • 0.chip_sw_coremark.17994306772278623840202694923006518822516814536885117229001578867825382696698
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log

        Job ID: smart:de8e85ec-f7d9-4aa2-9ef7-c4389a3b8d7c
      

  • Test chip_sw_power_virus has 3 failures.

    • 0.chip_sw_power_virus.2271585637166871476340078336948204813746744984498306157627281826944154177811
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log

        Job ID: smart:8b44de12-9e5e-46ff-a477-874ddfab1bf9
      

    • 1.chip_sw_power_virus.72329331577616518686001031920979432978955150102891844660051021308236101167912
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log

        Job ID: smart:9f84b15d-dee2-407f-8747-2459307f61e2
      

    • ... and 1 more failures.

  • Test chip_sw_flash_rma_unlocked has 1 failures.

    • 1.chip_sw_flash_rma_unlocked.66632472295277468903892855303263735926194350040928683255773665162040298453470
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log

        Job ID: smart:dd53dcfb-baba-4832-9491-c0b7fe964793
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 6 failures:

  • Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.107006446384275592827958027731783408515478208713003564281170916857892404481655
      Line 1043, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log

        UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.12556172992836142118691422059510066820630187537020961465764183688151182591169
      Line 1086, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log

        UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.47139793559988876496476653752636126321690146576939155481590839942088707835637
      Line 1061, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log

        UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_bad_b_nothing_prod has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.106387063702376272047033139516701740357381968241739158523443729490878791382548
      Line 992, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log

        UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_bad_b_nothing_prod_end has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.61103318921927989048948516225885104221943272809047712486098048375422431180474
      Line 994, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log

        UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 1 more tests.

• UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_key_derivation_vseq] wait timeout occurred! has 4 failures:

  • Test chip_sw_keymgr_key_derivation has 2 failures.

    • 0.chip_sw_keymgr_key_derivation.96268544841747081932028464529082540773539436760844717456186166515686104775833
      Line 831, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest/run.log

        UVM_FATAL @ 10010.280001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
        UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_keymgr_key_derivation.17777554320681382775759919298484126268303003158732681806301756658654178167832
      Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest/run.log

        UVM_FATAL @ 10010.240001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
        UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_keymgr_key_derivation_jitter_en has 1 failures.

    • 1.chip_sw_keymgr_key_derivation_jitter_en.84826847117254531062097152071544168541626166584171261648646955196839971658181
      Line 833, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @ 10010.160001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
        UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_keymgr_key_derivation_jitter_en_reduced_freq has 1 failures.

    • 2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.105865923990106315531210627750547916908358904027555191776252445801315510453852
      Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log

        UVM_FATAL @ 10010.160001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
        UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:

  • Test chip_sw_sysrst_ctrl_outputs has 3 failures.

    • 0.chip_sw_sysrst_ctrl_outputs.59853757297832957799411523943094916968880581122528726820961491066387684391463
      Line 829, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_sysrst_ctrl_outputs.60684592338941317477268351005302319879157642121482208143095789758580653785465
      Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

  • Test chip_sw_lc_ctrl_program_error has 3 failures.

    • 0.chip_sw_lc_ctrl_program_error.28560403168245721432773022953133804226747652879860699290507174983507032066785
      Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 15332.138376 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 15332.138376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.chip_sw_lc_ctrl_program_error.33144586409937386735336662980245511723131047908077878267996677970923850325936
      Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 13916.427900 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 13916.427900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:

  • Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.

    • 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.27313803173464399736539992305710904133116829064781827659795151159659396047294
      Line 809, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log

        UVM_FATAL @ 23571.820900 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
        UVM_INFO @ 23571.820900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.39695011041566920478568755335340750351506487902526032530558143666475100233880
      Line 810, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log

        UVM_FATAL @ 23623.660956 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
        UVM_INFO @ 23623.660956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:

  • Test chip_sw_rv_dm_access_after_wakeup has 3 failures.

    • 0.chip_sw_rv_dm_access_after_wakeup.87124834595330006447629336031080288206162130133890975247070758325643165182754
      Line 894, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log

        UVM_FATAL @ 3690.297807 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
        UVM_INFO @ 3690.297807 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_rv_dm_access_after_wakeup.55304526336166730264689853949995074530672950333219471057244431436456194356974
      Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log

        UVM_FATAL @ 4352.957345 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
        UVM_INFO @ 4352.957345 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:

  • Test rom_e2e_shutdown_exception_c has 3 failures.

    • 0.rom_e2e_shutdown_exception_c.1338355914713605997404406874049733591298020572586506589635623700275027521027
      Line 968, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log

        UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_e2e_shutdown_exception_c.43349472497754564713181028233880940623317126680713592945684364658592307731625
      Line 1019, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log

        UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.63673353968276430026314264924875439321718939550490680862407496509880156718320
      Line 1010, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log

        UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.28750703466734051424676184114114951742109720348588110156713740959241034349030
      Line 991, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log

        UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.41078947111942294752783303988159066084110207268982486707993729657882915531078
      Line 1003, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log

        UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:

  • Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_debug_test_unlocked0.51487193819138369117368541197616014536719454305960955210770762885532573299937
      Line 842, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log

        UVM_FATAL @ 2356.287500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2356.287500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_dev has 1 failures.

    • 0.rom_e2e_jtag_debug_dev.49198402186751369144174587758952123534838061178542053283948491959853706571143
      Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log

        UVM_FATAL @ 2205.740500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2205.740500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_rma has 1 failures.

    • 0.rom_e2e_jtag_debug_rma.43420587596410203627463785790803415480002680628545149475255209623107556836057
      Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log

        UVM_FATAL @ 1895.196000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 1895.196000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:

  • Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_inject_test_unlocked0.64170899997199539234444850345360442530646469827159370307659260726463878684171
      Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log

        UVM_FATAL @ 50445.563365 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 50445.563365 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_dev has 1 failures.

    • 0.rom_e2e_jtag_inject_dev.49822417716948929466299908939429158411066106666205177627187822445214635518806
      Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log

        UVM_FATAL @ 45428.026201 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 45428.026201 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_rma has 1 failures.

    • 0.rom_e2e_jtag_inject_rma.96741805571400209546731209628410875921246332592138371783097730108336821637353
      Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log

        UVM_FATAL @ 51068.655890 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 51068.655890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:

  • Test rom_e2e_static_critical has 3 failures.

    • 0.rom_e2e_static_critical.57561800668176081215146821926195764483484359281705298864610945937214602734436
      Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log

        UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_e2e_static_critical.9548046392773657692989710611675173540867688374663217698563467068682264195240
      Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log

        UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:

  • Test chip_sw_all_escalation_resets has 3 failures.

    • 18.chip_sw_all_escalation_resets.46918862605670152590696944768664196753107374886597191862644183771011339286554
      Line 782, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 2493.981004 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 2493.981004 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.chip_sw_all_escalation_resets.63944086112695909082891100112967736676424540757424070072593209377717014002239
      Line 815, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 3345.963946 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 3345.963946 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred! has 2 failures:

  • Test chip_sw_keymgr_sideload_aes has 2 failures.

    • 0.chip_sw_keymgr_sideload_aes.86962995914594190631085453210108258826106007297587157477724426805143409807695
      Line 815, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest/run.log

        UVM_FATAL @ 10010.200001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred!
        UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_keymgr_sideload_aes.28219163314509283680958149797008194617037038521597836645116941102177469071526
      Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_aes/latest/run.log

        UVM_FATAL @ 10010.160001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred!
        UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:

  • Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.115726422044627034902238146483093237321528711373098286148991282013482800651786
      Line 1052, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log

        UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.68150427533797938655647027928571833038171417987402082273035662522259950649087
      Line 992, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log

        UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:

  • Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.33822638613345820935483696892765228423085751951537931718692799464643075807864
      Line 1062, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log

        UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.84487739389095092370981560010396687235104907886604479522902258609377428359628
      Line 1050, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log

        UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:770) [chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error *c* has 1 failures:

  • Test chip_sw_lc_ctrl_rma_to_scrap has 1 failures.

    • 0.chip_sw_lc_ctrl_rma_to_scrap.76330856294524163685711952422459750785499940999804025761801481247434007489402
      Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log

        UVM_ERROR @ 2873.518058 us: (chip_sw_base_vseq.sv:770) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == 0 (507904 [0x7c000] vs 0 [0x0]) Unexpected status error 7c000000
        UVM_INFO @ 2873.518058 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred! has 1 failures:

  • Test chip_sw_keymgr_sideload_kmac has 1 failures.

    • 0.chip_sw_keymgr_sideload_kmac.66934018434379688127856469205326438437896192389084234669036036970374985801732
      Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_kmac/latest/run.log

        UVM_FATAL @ 10010.120001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred!
        UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.80648216263184940813819254524242167512525629021227684842297354515065884661920
      Line 1000, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log

        UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.21507596866745556793653199624513568523439421594470450816950534530780744722184
      Line 1032, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log

        UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.

    • 1.chip_sw_alert_handler_lpg_sleep_mode_alerts.11128536368313525783152014130135877700525942055447524238009281421577969089062
      Line 821, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3558.996760 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
        UVM_INFO @ 3558.996760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test chip_csr_aliasing has 1 failures.

    • 4.chip_csr_aliasing.85923999901799127465931608328653911667363204827443243456959916737895859594386
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest/run.log

        Job ID: smart:72a34213-3ab2-41c1-a8b4-8e5458bb0407
      

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