CHIP Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.187m	3.568ms	3	3	100.00
		chip_sw_example_rom	2.509m	2.428ms	3	3	100.00
		chip_sw_example_manufacturer	3.431m	2.897ms	3	3	100.00
		chip_sw_example_concurrency	5.092m	3.362ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	8.880m	7.289ms	5	5	100.00
V1	csr_rw	chip_csr_rw	13.095m	5.534ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.600h	59.032ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.920h	56.146ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.426m	2.323ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.920h	56.146ms	5	5	100.00
		chip_csr_rw	13.095m	5.534ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.900s	224.490us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.105m	3.744ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.105m	3.744ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.105m	3.744ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	11.359m	3.921ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	11.359m	3.921ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	13.026m	4.743ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	11.515m	3.851ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	11.360m	4.937ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	47.083m	12.943ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	12.187m	4.239ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	26.986m	13.285ms	5	5	100.00
V1		TOTAL			200	220	90.91
V2	chip_pin_mux	chip_padctrl_attributes	5.042m	4.564ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.042m	4.564ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.976m	3.358ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.995m	3.078ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.780m	3.080ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	31.593m	17.994ms	5	5	100.00
		chip_tap_straps_testunlock0	25.971m	15.786ms	4	5	80.00
		chip_tap_straps_rma	31.506m	17.163ms	4	5	80.00
		chip_tap_straps_prod	35.818m	19.159ms	4	5	80.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.913m	2.679ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	25.492m	8.132ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	17.486m	5.346ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	17.486m	5.346ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.705m	7.993ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	51.352m	19.111ms	2	3	66.67
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.226m	4.243ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.037m	6.540ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.122h	18.921ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.003m	2.901ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	21.182m	7.205ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.633m	3.066ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	36.713m	12.793ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.723m	2.913ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.063m	5.561ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.350m	2.867ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	6.071m	3.253ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	20.423m	9.065ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.401m	5.579ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	6.015m	3.351ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.401m	5.579ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.925m	3.208ms	3	3	100.00
		chip_sw_aes_smoketest	6.763m	3.429ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.436m	2.957ms	3	3	100.00
		chip_sw_clkmgr_smoketest	6.269m	2.593ms	3	3	100.00
		chip_sw_csrng_smoketest	5.369m	3.015ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.550m	3.876ms	3	3	100.00
		chip_sw_gpio_smoketest	6.456m	2.810ms	3	3	100.00
		chip_sw_hmac_smoketest	6.420m	3.472ms	3	3	100.00
		chip_sw_kmac_smoketest	5.162m	2.545ms	3	3	100.00
		chip_sw_otbn_smoketest	26.169m	6.784ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.061m	5.668ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	7.591m	5.850ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.576m	3.196ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.540m	3.115ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.548m	2.580ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.790m	3.472ms	3	3	100.00
		chip_sw_uart_smoketest	4.753m	2.985ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	6.054m	3.516ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.357m	5.508ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	4.157h	78.897ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.290h	14.520ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	5.007h	204.465ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	14.662m	5.035ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.104m	4.133ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.131h	58.160ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.654h	64.636ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	11.352m	4.787ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	11.352m	4.787ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.920h	56.146ms	5	5	100.00
		chip_same_csr_outstanding	1.296h	28.574ms	20	20	100.00
		chip_csr_hw_reset	8.880m	7.289ms	5	5	100.00
		chip_csr_rw	13.095m	5.534ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.920h	56.146ms	5	5	100.00
		chip_same_csr_outstanding	1.296h	28.574ms	20	20	100.00
		chip_csr_hw_reset	8.880m	7.289ms	5	5	100.00
		chip_csr_rw	13.095m	5.534ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.913m	2.517ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.270s	58.893us	100	100	100.00
		xbar_smoke_large_delays	2.071m	11.017ms	100	100	100.00
		xbar_smoke_slow_rsp	2.180m	6.688ms	100	100	100.00
		xbar_random_zero_delays	1.082m	635.563us	100	100	100.00
		xbar_random_large_delays	20.536m	110.232ms	100	100	100.00
		xbar_random_slow_rsp	20.476m	74.168ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.008m	1.183ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.023m	1.403ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.585m	2.242ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.023m	1.403ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.650m	3.477ms	100	100	100.00
		xbar_access_same_device_slow_rsp	46.462m	153.578ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.554m	2.495ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	12.550m	19.221ms	100	100	100.00
		xbar_stress_all_with_error	12.143m	16.414ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	24.829m	12.666ms	100	100	100.00
		xbar_stress_all_with_reset_error	14.828m	21.242ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.290h	14.520ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	1.187h	30.422ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.048h	15.078ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	57.915m	11.179ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.442h	15.407ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.097h	14.989ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.138h	15.498ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.114h	14.498ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	1.071h	11.070ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.295h	15.171ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.097h	16.026ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.173h	15.713ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.108h	14.715ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.466h	17.870ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.994h	24.082ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.785h	24.418ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.910h	24.249ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	2.005h	23.342ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.710h	18.132ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.810h	23.351ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.999h	22.991ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.652h	22.647ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.757h	21.959ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	58.600m	10.758ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	1.217h	14.185ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.071h	15.018ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.204h	14.690ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	1.127h	13.540ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	1.016h	10.212ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.101h	14.342ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	1.294h	14.138ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	1.399h	14.724ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	1.005h	13.718ms	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	1.013h	11.608ms	3	3	100.00
		rom_e2e_asm_init_dev	1.365h	15.017ms	3	3	100.00
		rom_e2e_asm_init_prod	1.247h	15.808ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.192h	15.552ms	3	3	100.00
		rom_e2e_asm_init_rma	1.124h	14.912ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.241h	14.974ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.105h	14.425ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.276h	14.866ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.239h	16.894ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.212m	3.212ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.003m	2.901ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.093m	2.733ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.634m	2.803ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	46.014m	11.715ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.740m	19.961ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.740m	19.961ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	6.932m	3.846ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.061m	5.668ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	6.932m	3.846ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.077m	8.142ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.077m	8.142ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.273m	7.183ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.031m	5.696ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	16.947m	5.953ms	3	3	100.00
		chip_sw_aes_idle	4.634m	2.803ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.692m	2.882ms	3	3	100.00
		chip_sw_kmac_idle	4.735m	2.671ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.241m	4.235ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.512m	5.468ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	10.152m	5.886ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.929m	4.623ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	30.389m	12.615ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.246m	4.781ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.700m	4.801ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.617m	4.075ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.085m	4.878ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.781m	4.478ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.135m	4.996ms	3	3	100.00
		chip_sw_ast_clk_outputs	16.705m	7.993ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.535m	12.340ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.617m	4.075ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.085m	4.878ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.226m	4.243ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.037m	6.540ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.122h	18.921ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.003m	2.901ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	21.182m	7.205ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.633m	3.066ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	36.713m	12.793ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.723m	2.913ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.063m	5.561ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.350m	2.867ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.263m	2.866ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	13.681m	5.378ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.554m	7.026ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.225h	25.117ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.229m	2.432ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.510m	3.511ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	36.768m	11.786ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	4.847m	3.080ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	14.125m	5.599ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	39.893m	26.973ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.677h	32.501ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.705m	7.993ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.287m	4.729ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	9.759m	3.778ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.842m	5.089ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	31.608m	8.183ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	27.030m	6.583ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	9.223m	5.228ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	13.754m	6.547ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.909m	2.942ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.505m	8.160ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	38.157m	24.141ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.194m	3.210ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	7.176m	3.852ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.490m	3.950ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	38.157m	24.141ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	38.157m	24.141ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.070h	20.986ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.070h	20.986ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	11.298m	5.804ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.740m	19.961ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.564h	25.706ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	3.787m	2.311ms	3	3	100.00
		chip_sw_edn_entropy_reqs	18.649m	6.210ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.787m	2.311ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	27.030m	6.583ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.623m	2.427ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	42.390m	21.960ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	21.390m	6.187ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.037m	6.540ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.177m	3.400ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.226m	4.243ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.572h	43.696ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	42.390m	21.960ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.131m	3.384ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	41.864m	12.753ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.024m	5.080ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.572h	43.696ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.024m	5.080ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.024m	5.080ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	11.024m	5.080ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.024m	5.080ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.842m	5.089ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	9.273m	11.273ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	23.923m	5.494ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.460m	5.732ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.460m	5.732ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.164m	3.759ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.633m	3.066ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.692m	2.882ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	6.159m	2.774ms	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	37.271m	8.521ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.387m	4.457ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	18.758m	5.138ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.928m	5.392ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.239m	3.662ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	41.864m	12.753ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	36.713m	12.793ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	40.137m	9.857ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	46.014m	11.715ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.441h	15.739ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.560m	2.403ms	3	3	100.00
		chip_sw_kmac_mode_kmac	4.386m	2.941ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.723m	2.913ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	41.864m	12.753ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.942m	11.246ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.617m	2.880ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.578m	2.471ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.735m	2.671ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.002m	6.076ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	31.593m	17.994ms	5	5	100.00
		chip_tap_straps_rma	31.506m	17.163ms	4	5	80.00
		chip_tap_straps_prod	35.818m	19.159ms	4	5	80.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.409m	2.767ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.942m	11.246ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.942m	11.246ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.942m	11.246ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	39.340m	12.306ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	11.024m	5.080ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.572h	43.696ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.321m	4.315ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.930m	8.822ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.934m	6.967ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.036m	8.019ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.942m	11.246ms	15	15	100.00
		chip_sw_keymgr_key_derivation	41.864m	12.753ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	12.294m	8.095ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	16.932m	7.611ms	3	3	100.00
		chip_prim_tl_access	9.273m	11.273ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.535m	12.340ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.246m	4.781ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.700m	4.801ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.617m	4.075ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.085m	4.878ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.781m	4.478ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.135m	4.996ms	3	3	100.00
		chip_tap_straps_dev	31.593m	17.994ms	5	5	100.00
		chip_tap_straps_rma	31.506m	17.163ms	4	5	80.00
		chip_tap_straps_prod	35.818m	19.159ms	4	5	80.00
		chip_rv_dm_lc_disabled	9.620m	15.938ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.014m	3.163ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.462m	3.508ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.299m	2.721ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.958m	3.362ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	44.769m	31.209ms	3	3	100.00
		chip_rv_dm_lc_disabled	9.620m	15.938ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.630h	50.109ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.623h	49.100ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	21.074m	9.405ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.528h	48.846ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	44.769m	31.209ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.321m	2.831ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.013m	2.812ms	3	3	100.00
		rom_volatile_raw_unlock	2.036m	2.331ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.942m	11.246ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	42.390m	21.960ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.864m	3.760ms	3	3	100.00
		chip_sw_keymgr_key_derivation	41.864m	12.753ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.933m	5.975ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.116m	2.762ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	42.390m	21.960ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.864m	3.760ms	3	3	100.00
		chip_sw_keymgr_key_derivation	41.864m	12.753ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.933m	5.975ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.116m	2.762ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.942m	11.246ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	9.697m	6.004ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.409m	2.767ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.321m	4.315ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.930m	8.822ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.934m	6.967ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.036m	8.019ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.942m	11.246ms	15	15	100.00
		chip_prim_tl_access	9.273m	11.273ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.273m	11.273ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.716h	27.352ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.685m	8.560ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	31.784m	23.746ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	8.223m	7.270ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.708m	7.145ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	13.140m	7.655ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	37.306m	22.387ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	29.964m	13.641ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	13.077m	8.142ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	30.128m	13.091ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.237m	4.994ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.685m	8.560ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	6.787m	4.797ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	58.051m	39.576ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.747m	7.823ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.490m	6.103ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.874m	24.233ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.505m	8.160ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	25.096m	9.156ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	42.018m	27.034ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.673m	2.845ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.842m	5.089ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	12.294m	8.095ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	12.294m	8.095ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	25.096m	9.156ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.874m	24.233ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	12.237m	4.994ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.061m	5.668ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.439m	4.777ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	14.463m	6.165ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.894m	3.713ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	39.581m	13.443ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.744m	2.242ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.842m	5.089ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	30.972m	7.668ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	21.054m	5.626ms	3	3	100.00
		chip_plic_all_irqs_10	11.551m	3.530ms	3	3	100.00
		chip_plic_all_irqs_20	13.299m	4.223ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.995m	3.196ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.491m	3.408ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.290h	14.520ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	16.445m	7.619ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.250m	4.882ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.870m	3.250ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.552m	3.347ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.933m	5.975ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.063m	5.561ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	10.920m	7.314ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.729m	7.723ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.932m	7.611ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.842m	5.089ms	97	100	97.00
		chip_sw_data_integrity_escalation	17.486m	5.346ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	5.192m	3.262ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.031m	3.490ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.257m	4.308ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.406m	3.955ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	37.784m	8.233ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.138h	31.821ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	51.530m	12.377ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.393m	3.801ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.002m	6.076ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.842m	5.089ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.495m	3.446ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	39.581m	13.443ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	7.549m	4.626ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.849m	4.298ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	29.207m	13.004ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	31.608m	8.183ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	30.972m	7.668ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	28.806m	7.357ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.759h	254.517ms	2	3	66.67
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	40.304m	20.570ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	32.517m	14.009ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.439m	4.777ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.027m	3.935ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	8.375m	3.204ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	31.506m	17.163ms	4	5	80.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.620m	15.938ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2613	2644	98.83
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.970m	3.047ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	3.600h	71.447ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	20.691m	7.181ms	0	1	0.00
		rom_e2e_jtag_debug_dev	22.829m	7.593ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.554m	7.700ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	42.102m	27.777ms	1	1	100.00
		rom_e2e_jtag_inject_dev	47.485m	32.094ms	1	1	100.00
		rom_e2e_jtag_inject_rma	55.848m	25.742ms	1	1	100.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.335m	3.348ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	11.019m	3.277ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	17.173m	4.735ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	30.954m	7.787ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.527m	3.064ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.018m	5.225ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.084m	2.060ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	9.730m	5.080ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.338m	5.820ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.314m	4.071ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	25.096m	9.156ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.842m	5.089ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	11.359m	3.921ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.191h	18.302ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	20.691m	7.181ms	0	1	0.00
		rom_e2e_jtag_debug_dev	22.829m	7.593ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.554m	7.700ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.663m	5.742ms	3	3	100.00
V3		TOTAL			36	45	80.00
	Unmapped tests	chip_sival_flash_info_access	5.985m	3.074ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.056m	6.535ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	4.459m	2.833ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.064h	17.180ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	17.247m	5.873ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.460m	4.681ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	7.296m	4.485ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.160m	5.438ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.277m	3.172ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	5.347m	2.505ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	7.187m	3.179ms	3	3	100.00
		TOTAL			2885	2945	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	11	11	11	100.00
V1	18	18	17	94.44
V2	285	270	246	86.32
V2S	1	1	1	100.00
V3	90	21	16	17.78

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.15	95.47	94.09	95.20	--	94.91	97.71	99.54

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.38312771080174207401373111898103368534394582441055982195862284996047196116307
    Line 379, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2988.902473 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2988.902473 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.42128386809953015047741512312207245926941357401178415045544840723507987052560
    Line 398, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2322.592770 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2322.592770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:*-*-* has 15 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.15760710379016885120022203096942812511613090235330995682906322354917492160506
    Line 1205, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 18132.436487 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:02108421
  "
  UVM_INFO @ 18132.436487 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.60485035153054564379791163365885130414173152741269584908694891650190873563336
    Line 1151, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_ERROR @ 23351.449929 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:21084210
  "
  UVM_INFO @ 23351.449929 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.90215417291047508368500388464404564099838851990637224620935714356341041477026
    Line 1234, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_ERROR @ 22991.340129 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:2318c631
  "
  UVM_INFO @ 22991.340129 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.111060617055093202452568049349153009362301910213582181324999872359754598959552
    Line 1103, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_ERROR @ 22647.106217 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:25294a52
  "
  UVM_INFO @ 22647.106217 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.101336523359398072611577041432239649813979155361720735008667851159931311100243
    Line 1281, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_ERROR @ 21958.587145 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:2739ce73
  "
  UVM_INFO @ 21958.587145 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- ... and 10 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.72847775923134838398349014027182825270358186058360958420526772436096330952411
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:7795e83d-f5e2-4a7c-870d-f7cb0afb0a7c
```
  - 1.chip_sw_rv_timer_systick_test.63003180966553087832005908181025478403365408685333154819059556285989851028042
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:bd1b8f07-e02a-4de8-bafb-ec84c0a0fcc6
```
  - ... and 1 more failures.
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.3190987896073509698030188345390759171576514463813219816785623872521378548774
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:b95cd803-817e-4739-9406-d3a70006d6af
```
  - 1.chip_sw_power_virus.69432813947133192844008159791155126945010950195347372664065776761109872854627
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:889c4b34-5a77-4390-a66c-61f936b10ef4
```
  - ... and 1 more failures.
- Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 1 failures.
  - 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.69124171056413201788002109102678970590177520830921142472958616028238347737056
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
```
  Job ID: smart:36074f0b-b1d2-4af4-be69-8596a52df85d
```
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 2.chip_sw_ast_clk_rst_inputs.95726563316437507518040277640739059023233414219550353171445457145246103963747
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:9b5f9abf-62bf-4a12-816c-c88cd22baa04
```
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.83124399141309370253645365739496466490901535266696152138805004804716698960523
    Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3203.927381 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3203.927381 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.71773093317627196016308303041183663270479307365056996442300146624147935268766
    Line 753, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3926.386108 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3926.386108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.53908057655376553138536919330569460037296912484371479415944547296700994422436
    Line 899, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 7180.634000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7180.634000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.33350572117620480246091698887112500781861580096018606896439454436192111827121
    Line 936, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 7592.963500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7592.963500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.30536424826939134949955671332251316560777660973906502102325211687583637974496
    Line 923, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 7699.693000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7699.693000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.13358350378082086380724626278096625754373684231166062952381954850961933527408
Line 878, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 206145.582726 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 206145.582726 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.68089979722904456329403443976096603467156997194984937371288576480201167898595
Line 794, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 204465.078889 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 204465.078889 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (jtag_driver.sv:124) [driver] wait timeout occurred! has 3 failures:
- Test chip_tap_straps_testunlock0 has 1 failures.
  - 2.chip_tap_straps_testunlock0.28792718635264970385520743149933648050980502287054288260872812020424473780798
    Line 5992, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_testunlock0/latest/run.log
```
  UVM_FATAL @ 15785.959569 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 15785.959569 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_tap_straps_rma has 1 failures.
  - 2.chip_tap_straps_rma.108475057317337316863797185442632362998587393090504999712377679521380767684709
    Line 6034, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest/run.log
```
  UVM_FATAL @ 17163.105953 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 17163.105953 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_tap_straps_prod has 1 failures.
  - 4.chip_tap_straps_prod.43275643229643589055999723464650063618338330865269563574292845826769673399608
    Line 6060, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_prod/latest/run.log
```
  UVM_FATAL @ 19158.850355 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 19158.850355 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 61.chip_sw_all_escalation_resets.58112331414178296301431160502882413703080690329025481589583476361839434825728
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3751.651374 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3751.651374 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 62.chip_sw_all_escalation_resets.73077724053226007800321211539048478236584894818167453971704798369471553256177
    Line 820, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3267.836268 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3267.836268 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 14.chip_sw_alert_handler_lpg_sleep_mode_alerts.40404212110816044277444537522684029229949375526535691282646546611246658455816
    Line 953, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3626.099716 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3626.099716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 53.chip_sw_alert_handler_lpg_sleep_mode_alerts.61381862411696980531895252108924032389736116986990209367266842339209747948571
    Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3597.871448 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3597.871448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```