CHIP Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.859m	2.822ms	3	3	100.00
		chip_sw_example_rom	2.743m	2.675ms	3	3	100.00
		chip_sw_example_manufacturer	5.466m	2.545ms	3	3	100.00
		chip_sw_example_concurrency	5.285m	3.283ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	7.844m	6.450ms	5	5	100.00
V1	csr_rw	chip_csr_rw	12.325m	6.525ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.195h	41.644ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.513h	52.615ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.391m	2.947ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.513h	52.615ms	5	5	100.00
		chip_csr_rw	12.325m	6.525ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	12.150s	268.974us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.988m	4.016ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.988m	4.016ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.988m	4.016ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	13.462m	5.083ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	13.462m	5.083ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	13.892m	4.677ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	12.431m	4.015ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	12.338m	4.734ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	54.669m	13.142ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.006h	13.128ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	32.078m	13.249ms	5	5	100.00
V1		TOTAL			200	220	90.91
V2	chip_pin_mux	chip_padctrl_attributes	4.618m	5.684ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.618m	5.684ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.691m	2.544ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	9.316m	6.399ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	7.736m	4.005ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	32.337m	17.119ms	5	5	100.00
		chip_tap_straps_testunlock0	23.096m	14.487ms	5	5	100.00
		chip_tap_straps_rma	25.577m	13.879ms	4	5	80.00
		chip_tap_straps_prod	33.030m	16.669ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.738m	3.152ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	25.126m	8.541ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	16.087m	6.319ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	16.087m	6.319ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	23.264m	8.778ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	40.537m	14.938ms	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.541m	4.430ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.413m	6.528ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.379h	18.955ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.483m	2.620ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	24.924m	8.224ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.575m	2.680ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	34.544m	11.269ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.510m	3.200ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.246m	5.627ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.437m	2.147ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.690m	2.652ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	21.087m	8.896ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.370m	5.888ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.454m	3.229ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.370m	5.888ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.664m	2.480ms	3	3	100.00
		chip_sw_aes_smoketest	5.162m	2.736ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.192m	2.902ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.395m	3.109ms	3	3	100.00
		chip_sw_csrng_smoketest	4.868m	2.757ms	3	3	100.00
		chip_sw_entropy_src_smoketest	12.488m	4.438ms	3	3	100.00
		chip_sw_gpio_smoketest	5.574m	2.426ms	3	3	100.00
		chip_sw_hmac_smoketest	6.321m	3.185ms	3	3	100.00
		chip_sw_kmac_smoketest	4.705m	3.060ms	3	3	100.00
		chip_sw_otbn_smoketest	46.381m	10.543ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.902m	6.549ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.188m	5.398ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.652m	2.952ms	3	3	100.00
		chip_sw_rv_timer_smoketest	6.052m	3.125ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.619m	3.374ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.257m	3.013ms	3	3	100.00
		chip_sw_uart_smoketest	6.196m	3.329ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	5.412m	3.088ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.021m	4.451ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	4.025h	77.272ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.153h	15.177ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	3.757h	205.525ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	14.124m	4.151ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	11.129m	11.150ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.249h	59.813ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.363h	62.955ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.842m	5.404ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.842m	5.404ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.513h	52.615ms	5	5	100.00
		chip_same_csr_outstanding	1.055h	29.244ms	20	20	100.00
		chip_csr_hw_reset	7.844m	6.450ms	5	5	100.00
		chip_csr_rw	12.325m	6.525ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.513h	52.615ms	5	5	100.00
		chip_same_csr_outstanding	1.055h	29.244ms	20	20	100.00
		chip_csr_hw_reset	7.844m	6.450ms	5	5	100.00
		chip_csr_rw	12.325m	6.525ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.789m	2.579ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.090s	51.220us	100	100	100.00
		xbar_smoke_large_delays	2.128m	11.230ms	100	100	100.00
		xbar_smoke_slow_rsp	1.908m	6.826ms	100	100	100.00
		xbar_random_zero_delays	59.360s	561.970us	100	100	100.00
		xbar_random_large_delays	19.832m	105.764ms	100	100	100.00
		xbar_random_slow_rsp	20.672m	71.119ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.113m	1.450ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.095m	1.392ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.963m	2.924ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.095m	1.392ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.760m	3.803ms	100	100	100.00
		xbar_access_same_device_slow_rsp	43.594m	144.651ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.570m	2.674ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.312m	23.334ms	100	100	100.00
		xbar_stress_all_with_error	10.654m	18.228ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	19.709m	20.986ms	100	100	100.00
		xbar_stress_all_with_reset_error	14.965m	8.148ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.153h	15.177ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	1.158h	28.108ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.098h	14.952ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	52.117m	11.336ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.113h	14.867ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.283h	15.142ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.347h	15.216ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.121h	15.009ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	58.745m	11.560ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.098h	15.506ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.124h	15.742ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.227h	15.470ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.145h	14.697ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.362h	18.252ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.845h	24.803ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.801h	24.088ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.674h	24.457ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.694h	23.354ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.293h	17.300ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.681h	22.792ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.732h	22.608ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.575h	22.647ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.751h	22.694ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	1.011h	9.965ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	1.032h	13.972ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.224h	14.848ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.192h	14.120ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	1.310h	13.782ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	57.496m	10.432ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.147h	14.014ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	1.254h	13.947ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	1.089h	14.526ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	58.293m	13.350ms	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	56.095m	11.087ms	3	3	100.00
		rom_e2e_asm_init_dev	1.356h	15.640ms	3	3	100.00
		rom_e2e_asm_init_prod	1.202h	16.061ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.172h	15.574ms	3	3	100.00
		rom_e2e_asm_init_rma	1.302h	14.515ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.310h	14.660ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.229h	15.063ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.175h	14.605ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.269h	16.706ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.785m	2.754ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.483m	2.620ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.080m	2.918ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.436m	2.393ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	38.539m	13.017ms	2	3	66.67
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.340m	19.946ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.340m	19.946ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.963m	4.640ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.902m	6.549ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.963m	4.640ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.353m	10.326ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.353m	10.326ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.193m	7.038ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	14.306m	6.062ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.771m	6.255ms	3	3	100.00
		chip_sw_aes_idle	5.436m	2.393ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.135m	2.924ms	3	3	100.00
		chip_sw_kmac_idle	5.551m	2.716ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	7.613m	4.773ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.531m	5.597ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	9.235m	4.039ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.435m	5.673ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	21.568m	10.793ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.081m	4.116ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.794m	4.322ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.521m	4.110ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.027m	4.759ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	15.068m	4.645ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.363m	4.718ms	3	3	100.00
		chip_sw_ast_clk_outputs	23.264m	8.778ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	16.113m	10.901ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.521m	4.110ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.027m	4.759ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.541m	4.430ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.413m	6.528ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.379h	18.955ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.483m	2.620ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	24.924m	8.224ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.575m	2.680ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	34.544m	11.269ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.510m	3.200ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.246m	5.627ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.437m	2.147ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.711m	2.535ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.862m	5.061ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	23.256m	7.201ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.198h	25.234ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.926m	3.605ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.597m	3.361ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	39.022m	12.007ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.790m	3.132ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.665m	5.588ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	39.457m	17.797ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.666h	55.624ms	1	3	33.33
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	23.264m	8.778ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.072m	4.614ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	6.878m	3.489ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	16.140m	6.266ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	34.301m	8.228ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	26.621m	6.683ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	10.302m	5.204ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	13.276m	6.549ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.424m	3.518ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	22.479m	6.802ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	35.316m	23.236ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.064m	3.897ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	6.184m	3.409ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.941m	4.618ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	35.316m	23.236ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	35.316m	23.236ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.183h	20.634ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.183h	20.634ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.549m	5.342ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.340m	19.946ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.487h	34.819ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	5.608m	2.790ms	3	3	100.00
		chip_sw_edn_entropy_reqs	25.210m	6.331ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.608m	2.790ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	26.621m	6.683ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	3.972m	2.510ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	42.438m	24.063ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	20.884m	5.106ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.413m	6.528ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.610m	4.579ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.541m	4.430ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.610h	44.432ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	42.438m	24.063ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	8.842m	3.678ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	43.052m	12.759ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.760m	5.325ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.610h	44.432ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.760m	5.325ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.760m	5.325ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	10.760m	5.325ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.760m	5.325ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	16.140m	6.266ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	7.996m	9.290ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.009m	5.125ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.652m	5.622ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.652m	5.622ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.794m	3.434ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.575m	2.680ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.135m	2.924ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	7.061m	3.751ms	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	29.858m	7.766ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	13.999m	4.917ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	15.740m	5.083ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.177m	4.979ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.502m	4.278ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	43.052m	12.759ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	34.544m	11.269ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	47.337m	13.112ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	38.539m	13.017ms	2	3	66.67
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.272h	16.194ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.368m	2.846ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.832m	3.024ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.510m	3.200ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	43.052m	12.759ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	21.379m	13.478ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.789m	2.597ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.005m	3.060ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.551m	2.716ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.581m	5.761ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	32.337m	17.119ms	5	5	100.00
		chip_tap_straps_rma	25.577m	13.879ms	4	5	80.00
		chip_tap_straps_prod	33.030m	16.669ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.257m	2.973ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	21.379m	13.478ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	21.379m	13.478ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	21.379m	13.478ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	42.463m	12.808ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	10.760m	5.325ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.610h	44.432ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.694m	4.391ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.160m	6.569ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	20.136m	8.592ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.812m	6.956ms	3	3	100.00
		chip_sw_lc_ctrl_transition	21.379m	13.478ms	15	15	100.00
		chip_sw_keymgr_key_derivation	43.052m	12.759ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	12.254m	8.684ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	17.832m	8.194ms	3	3	100.00
		chip_prim_tl_access	7.996m	9.290ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	16.113m	10.901ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.081m	4.116ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.794m	4.322ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.521m	4.110ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.027m	4.759ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	15.068m	4.645ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.363m	4.718ms	3	3	100.00
		chip_tap_straps_dev	32.337m	17.119ms	5	5	100.00
		chip_tap_straps_rma	25.577m	13.879ms	4	5	80.00
		chip_tap_straps_prod	33.030m	16.669ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.885m	8.284ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.520m	2.809ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.167m	3.255ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.717m	3.467ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.583m	3.761ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	46.749m	27.434ms	3	3	100.00
		chip_rv_dm_lc_disabled	6.885m	8.284ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.591h	46.960ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.738h	47.993ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	17.070m	8.884ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.659h	46.644ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	46.749m	27.434ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.083m	3.073ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.954m	2.803ms	3	3	100.00
		rom_volatile_raw_unlock	2.120m	2.286ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	21.379m	13.478ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	42.438m	24.063ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.603m	4.074ms	3	3	100.00
		chip_sw_keymgr_key_derivation	43.052m	12.759ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.719m	5.212ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.996m	3.503ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	42.438m	24.063ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.603m	4.074ms	3	3	100.00
		chip_sw_keymgr_key_derivation	43.052m	12.759ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.719m	5.212ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.996m	3.503ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	21.379m	13.478ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	8.704m	4.824ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.257m	2.973ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.694m	4.391ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.160m	6.569ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	20.136m	8.592ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.812m	6.956ms	3	3	100.00
		chip_sw_lc_ctrl_transition	21.379m	13.478ms	15	15	100.00
		chip_prim_tl_access	7.996m	9.290ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.996m	9.290ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.503h	27.931ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	12.964m	9.294ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	35.582m	23.766ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.785m	7.041ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.877m	8.640ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.106m	6.584ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	26.952m	26.580ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	29.333m	16.139ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	17.353m	10.326ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	30.268m	13.367ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.359m	4.665ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	12.964m	9.294ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.543m	4.481ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.143h	40.932ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	7.592m	6.851ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.480m	5.798ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	40.437m	21.400ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	22.479m	6.802ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	40.064m	10.362ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	54.188m	27.692ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.282m	3.496ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	16.140m	6.266ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	12.254m	8.684ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	12.254m	8.684ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	40.064m	10.362ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	40.437m	21.400ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	13.359m	4.665ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.902m	6.549ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	9.586m	3.908ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	13.798m	7.158ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.536m	5.109ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	39.907m	10.588ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.088m	3.035ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	16.140m	6.266ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	29.807m	7.317ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	23.649m	6.775ms	3	3	100.00
		chip_plic_all_irqs_10	10.946m	4.162ms	3	3	100.00
		chip_plic_all_irqs_20	12.613m	4.488ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	6.584m	2.930ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.425m	2.913ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.153h	15.177ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.690m	7.261ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.026m	4.465ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.836m	3.586ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.304m	2.674ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.719m	5.212ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.246m	5.627ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	17.793m	7.196ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	14.210m	7.045ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	17.832m	8.194ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	16.140m	6.266ms	97	100	97.00
		chip_sw_data_integrity_escalation	16.087m	6.319ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	5.184m	2.520ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.979m	2.815ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	6.389m	3.900ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	8.089m	3.525ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	36.427m	7.852ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.080h	32.168ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	53.410m	12.358ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	8.052m	2.863ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.581m	5.761ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	16.140m	6.266ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.295m	3.541ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	39.907m	10.588ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.102m	5.848ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.234m	3.724ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	28.625m	13.528ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	34.301m	8.228ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	29.807m	7.317ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	26.134m	8.131ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.848h	255.073ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	21.905m	12.471ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.751m	13.952ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	9.586m	3.908ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	8.772m	3.645ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.983m	4.289ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	25.577m	13.879ms	4	5	80.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.885m	8.284ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2613	2644	98.83
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.453m	2.831ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	26.161m	7.933ms	0	1	0.00
		rom_e2e_jtag_debug_dev	23.388m	7.935ms	0	1	0.00
		rom_e2e_jtag_debug_rma	21.786m	7.367ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	50.276m	24.651ms	1	1	100.00
		rom_e2e_jtag_inject_dev	48.038m	36.392ms	1	1	100.00
		rom_e2e_jtag_inject_rma	49.365m	31.423ms	1	1	100.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.355m	3.796ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	11.477m	3.314ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	26.011m	5.886ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	36.802m	9.648ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.005m	3.454ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	24.293m	5.914ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.133m	2.719ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	11.134m	5.644ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	10.503m	6.976ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.167m	5.092ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	40.064m	10.362ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	16.140m	6.266ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	13.462m	5.083ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.410h	19.367ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	26.161m	7.933ms	0	1	0.00
		rom_e2e_jtag_debug_dev	23.388m	7.935ms	0	1	0.00
		rom_e2e_jtag_debug_rma	21.786m	7.367ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.828m	4.829ms	3	3	100.00
V3		TOTAL			35	45	77.78
	Unmapped tests	chip_sival_flash_info_access	6.055m	3.589ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.990m	5.410ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	6.621m	2.616ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.192h	17.226ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	19.166m	5.549ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	17.106m	5.254ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	9.856m	3.779ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.438m	6.069ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.378m	2.819ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.508m	2.366ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	7.500m	3.082ms	3	3	100.00
		TOTAL			2884	2945	97.93

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	11	11	11	100.00
V1	18	18	17	94.44
V2	285	270	247	86.67
V2S	1	1	1	100.00
V3	90	21	15	16.67

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.02	95.45	93.64	95.54	--	94.43	97.53	99.54

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.10037988816282982651633821545478573295726282880110388311207725433032667431379
    Line 368, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1875.190285 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1875.190285 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.57640924234273687740646608661266413775097474679127445043815044827929502791068
    Line 375, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2946.854082 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2946.854082 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:*-*-* has 15 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.64278529567169523315628008779956250809239751213510110583828987502281637017822
    Line 1041, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 17299.660937 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:02108421
  "
  UVM_INFO @ 17299.660937 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.10745826649319125920356883729823387536601722903862757833315477528384973856403
    Line 1090, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_ERROR @ 22791.876945 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:21084210
  "
  UVM_INFO @ 22791.876945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.67951887032260056025062234910621292216545711254690185008894744962647779302993
    Line 1214, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_ERROR @ 22607.751481 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:2318c631
  "
  UVM_INFO @ 22607.751481 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.113844067825658046481724527492633537620231641863006795992825841056973135038574
    Line 1036, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_ERROR @ 22647.190281 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:25294a52
  "
  UVM_INFO @ 22647.190281 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.9642542898002913427969221362209063170462656646006687679197998194298006358365
    Line 1121, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_ERROR @ 22694.426193 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:2739ce73
  "
  UVM_INFO @ 22694.426193 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- ... and 10 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.33282082430013812250167173775894673710970428465549880634561745267539082326945
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:10c5dc6e-ee24-44d6-86ef-362ea796f117
```
  - 1.chip_sw_rv_timer_systick_test.50149046165720008173576819902788908230761734261160960006913100111171318893723
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:935ba1f6-c53d-4f8b-a4f7-10a68486bf48
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_sideload_aes has 1 failures.
  - 0.chip_sw_keymgr_sideload_aes.114522349252225464137182492895459652255011980197504586450949376296570691050878
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest/run.log
```
  Job ID: smart:73b84516-30d8-4104-bfaf-d6640560e35b
```
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.43973586329450994609786956509634761087044505437966625345476258807338587300502
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:dc5aec8d-eb5d-4146-8312-97bbda595f9a
```
- Test chip_sw_ast_clk_rst_inputs has 2 failures.
  - 0.chip_sw_ast_clk_rst_inputs.98442337495837397900682452995347277720780299869882522766313881244175175198616
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:10896d59-16ce-45a7-9071-c0f16527e195
```
  - 2.chip_sw_ast_clk_rst_inputs.51596585872412461153425265597542142087948502413571858482981388942939967578052
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:f8488b5b-3728-412d-965e-82acc2517ec6
```
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.373347692502166933460339266739620403909636147342590421519215956856005212816
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:70f276d7-bcc5-4f70-8d25-65b190feabca
```
  - 1.chip_sw_power_virus.106033042515108194972221007551987402731682136752937029011355736768183705420094
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:cda2a146-e9e7-4f8d-a5d8-5710f869f29b
```
  - ... and 1 more failures.
- ... and 1 more tests.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.14397308913603155195662137658541323103589047697890870904029910433025183173990
    Line 866, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3984.236387 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3984.236387 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.53857713566155923408771765443587911428700687364404015954002639198206618556016
    Line 725, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 4288.880476 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 4288.880476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.109975057247515206637037156934292742513040103360740237244153435984595284175257
    Line 885, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 7932.750000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7932.750000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.35326339858950701769367180878468258105562755982132495747625191774919906267773
    Line 868, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 7935.035500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7935.035500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.80348581048264597756134158738687610357770270147334059582925142655302390358085
    Line 839, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 7367.414000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7367.414000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.55654037299568297880102677265909073094815895617443362191161191256683059453539
Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 206308.886138 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 206308.886138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.46207024351582264637299869191869933082702709347185811750072578734875205849241
Line 957, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205525.432331 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205525.432331 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 5.chip_sw_all_escalation_resets.58858110321312354945378214662025707014255539095599829932340276645364916833133
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2995.840340 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2995.840340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.chip_sw_all_escalation_resets.85525446950467225516038994381340337359512311164088406911776406029677395270410
    Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3306.492464 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3306.492464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (jtag_driver.sv:124) [driver] wait timeout occurred! has 1 failures:
- Test chip_tap_straps_rma has 1 failures.
  - 0.chip_tap_straps_rma.6844475308476365053177933908904742508197146086210287602238618159298828559700
    Line 6027, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_rma/latest/run.log
```
  UVM_FATAL @ 13878.652827 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 13878.652827 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 70.chip_sw_alert_handler_lpg_sleep_mode_alerts.110267681187769318484545489170029898840456809858915845073369529633733656302649
    Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3546.174896 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3546.174896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```