CHIP Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.933m	3.162ms	3	3	100.00
		chip_sw_example_rom	2.611m	2.613ms	3	3	100.00
		chip_sw_example_manufacturer	5.534m	2.750ms	3	3	100.00
		chip_sw_example_concurrency	5.099m	3.575ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	7.753m	6.084ms	5	5	100.00
V1	csr_rw	chip_csr_rw	13.040m	5.926ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	58.527m	31.419ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	1.651h	40.954ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.356m	3.040ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.651h	40.954ms	4	5	80.00
		chip_csr_rw	13.040m	5.926ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.840s	256.829us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.741m	4.217ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.741m	4.217ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.741m	4.217ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	11.571m	4.413ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	11.571m	4.413ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	12.836m	4.302ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	12.921m	4.619ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	11.603m	4.980ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	53.303m	13.577ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	44.045m	13.060ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	23.750m	8.758ms	5	5	100.00
V1		TOTAL			199	220	90.45
V2	chip_pin_mux	chip_padctrl_attributes	4.772m	4.898ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.772m	4.898ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.095m	3.459ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.423m	5.643ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.105m	4.411ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	29.000m	15.114ms	4	5	80.00
		chip_tap_straps_testunlock0	30.201m	14.752ms	4	5	80.00
		chip_tap_straps_rma	30.118m	15.010ms	3	5	60.00
		chip_tap_straps_prod	28.791m	12.980ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.405m	3.388ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	25.269m	8.250ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	15.252m	6.364ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	15.252m	6.364ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.426m	7.536ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.712m	4.729ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.451m	5.375ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.155h	18.525ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.882m	2.667ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	24.765m	7.030ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.496m	3.082ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	44.218m	11.882ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.852m	2.980ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.579m	3.705ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.569m	2.933ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	6.807m	2.949ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	18.630m	7.438ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.331m	5.474ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.384m	3.262ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.331m	5.474ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	5.279m	2.654ms	3	3	100.00
		chip_sw_aes_smoketest	5.323m	3.228ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.669m	3.331ms	3	3	100.00
		chip_sw_clkmgr_smoketest	3.377m	2.899ms	3	3	100.00
		chip_sw_csrng_smoketest	4.881m	3.279ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.924m	3.441ms	3	3	100.00
		chip_sw_gpio_smoketest	6.535m	3.327ms	3	3	100.00
		chip_sw_hmac_smoketest	6.681m	3.065ms	3	3	100.00
		chip_sw_kmac_smoketest	5.137m	3.315ms	3	3	100.00
		chip_sw_otbn_smoketest	36.825m	8.323ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.374m	5.018ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.350m	5.710ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.469m	2.679ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.846m	3.160ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.409m	2.697ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.301m	3.388ms	3	3	100.00
		chip_sw_uart_smoketest	5.076m	3.113ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	6.312m	3.507ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.197m	5.798ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	4.177h	78.393ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.202h	15.665ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	4.844h	204.866ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.803m	4.798ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	13.875m	10.688ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.227h	59.940ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.350h	65.283ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	9.102m	5.347ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	9.102m	5.347ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.651h	40.954ms	4	5	80.00
		chip_same_csr_outstanding	1.069h	30.943ms	20	20	100.00
		chip_csr_hw_reset	7.753m	6.084ms	5	5	100.00
		chip_csr_rw	13.040m	5.926ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.651h	40.954ms	4	5	80.00
		chip_same_csr_outstanding	1.069h	30.943ms	20	20	100.00
		chip_csr_hw_reset	7.753m	6.084ms	5	5	100.00
		chip_csr_rw	13.040m	5.926ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.829m	2.613ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.960s	49.338us	100	100	100.00
		xbar_smoke_large_delays	2.013m	10.461ms	100	100	100.00
		xbar_smoke_slow_rsp	2.070m	6.949ms	100	100	100.00
		xbar_random_zero_delays	58.850s	586.607us	100	100	100.00
		xbar_random_large_delays	20.559m	118.028ms	100	100	100.00
		xbar_random_slow_rsp	20.203m	72.730ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.180m	1.542ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.090m	1.373ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.747m	2.641ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.090m	1.373ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.446m	3.262ms	100	100	100.00
		xbar_access_same_device_slow_rsp	48.718m	170.766ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.689m	2.732ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	12.807m	18.232ms	100	100	100.00
		xbar_stress_all_with_error	13.468m	21.124ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	21.355m	20.972ms	100	100	100.00
		xbar_stress_all_with_reset_error	16.264m	9.566ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.202h	15.665ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	1.281h	29.624ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.297h	14.512ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	48.139m	11.572ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.107h	16.263ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.345h	15.698ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.272h	15.126ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.246h	15.060ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	58.448m	11.689ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.225h	15.768ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.269h	15.335ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.274h	15.431ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.071h	15.432ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.444h	18.197ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.624h	24.575ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.821h	23.779ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.670h	24.401ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.674h	23.252ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.379h	17.907ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.715h	22.482ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.763h	22.476ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.612h	23.052ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.838h	21.568ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	54.105m	10.199ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	1.123h	14.439ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.171h	14.145ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.108h	14.013ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	1.186h	13.679ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	44.660m	11.106ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.165h	14.487ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	1.163h	14.416ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	1.253h	13.960ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	1.194h	12.989ms	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	1.070h	11.659ms	3	3	100.00
		rom_e2e_asm_init_dev	1.166h	15.018ms	3	3	100.00
		rom_e2e_asm_init_prod	1.251h	15.478ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.300h	16.055ms	3	3	100.00
		rom_e2e_asm_init_rma	1.127h	15.448ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.179h	14.798ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.456h	14.636ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.170h	14.681ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.368h	17.362ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.066m	3.406ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.882m	2.667ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.414m	3.224ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.894m	2.597ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	39.831m	11.134ms	2	3	66.67
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.136m	18.689ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.136m	18.689ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.797m	4.130ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.374m	5.018ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.797m	4.130ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.996m	9.773ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.996m	9.773ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.273m	7.774ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.675m	5.095ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	16.424m	6.112ms	3	3	100.00
		chip_sw_aes_idle	4.894m	2.597ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.568m	2.875ms	3	3	100.00
		chip_sw_kmac_idle	4.122m	2.887ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.357m	5.127ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	12.169m	5.045ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.553m	5.076ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.058m	4.685ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	23.885m	11.073ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.999m	3.902ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.596m	5.075ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.594m	4.331ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.905m	5.536ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.622m	4.086ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.963m	4.605ms	3	3	100.00
		chip_sw_ast_clk_outputs	19.426m	7.536ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	16.096m	11.195ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.594m	4.331ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.905m	5.536ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.712m	4.729ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.451m	5.375ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.155h	18.525ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.882m	2.667ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	24.765m	7.030ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.496m	3.082ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	44.218m	11.882ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.852m	2.980ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.579m	3.705ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.569m	2.933ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.612m	3.355ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	11.944m	4.618ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	24.185m	7.551ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.431h	24.062ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.122m	2.934ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.495m	4.014ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	36.584m	9.960ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.097m	3.720ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.680m	4.768ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	43.924m	24.995ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.980h	63.372ms	2	3	66.67
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.426m	7.536ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.197m	4.795ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.976m	3.861ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.987m	5.846ms	99	100	99.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	39.366m	8.475ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	39.020m	8.007ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	10.566m	4.537ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	12.479m	6.453ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.957m	3.270ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.685m	8.882ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	35.496m	25.712ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.531m	2.895ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	8.098m	3.614ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	13.030m	5.212ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	35.496m	25.712ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	35.496m	25.712ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.111h	20.772ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.111h	20.772ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	12.395m	5.876ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.136m	18.689ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.178h	32.257ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	3.790m	2.885ms	3	3	100.00
		chip_sw_edn_entropy_reqs	23.247m	6.211ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.790m	2.885ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	39.020m	8.007ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.523m	2.830ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	35.685m	21.560ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	21.980m	5.751ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.451m	5.375ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.222m	3.799ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	11.712m	4.729ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.655h	42.887ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	35.685m	21.560ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.098m	3.490ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	35.080m	8.241ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.948m	5.752ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.655h	42.887ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.948m	5.752ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.948m	5.752ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	9.948m	5.752ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.948m	5.752ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.987m	5.846ms	99	100	99.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	7.784m	12.590ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.687m	5.592ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.029m	5.893ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.029m	5.893ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.750m	3.142ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.496m	3.082ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.568m	2.875ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	7.713m	3.035ms	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	32.991m	7.754ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	16.070m	5.418ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	14.074m	5.167ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	20.064m	5.544ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.341m	3.907ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	35.080m	8.241ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	44.218m	11.882ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	43.891m	13.056ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	39.831m	11.134ms	2	3	66.67
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.290h	15.304ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.929m	2.721ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.184m	2.857ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.852m	2.980ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	35.080m	8.241ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	21.051m	12.590ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.088m	3.522ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.859m	3.634ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.122m	2.887ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.092m	5.370ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	29.000m	15.114ms	4	5	80.00
		chip_tap_straps_rma	30.118m	15.010ms	3	5	60.00
		chip_tap_straps_prod	28.791m	12.980ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.376m	3.180ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	21.051m	12.590ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	21.051m	12.590ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	21.051m	12.590ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	43.603m	11.088ms	2	3	66.67
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	9.948m	5.752ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.655h	42.887ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.939m	4.275ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.780m	8.035ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.560m	8.297ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.343m	7.745ms	3	3	100.00
		chip_sw_lc_ctrl_transition	21.051m	12.590ms	15	15	100.00
		chip_sw_keymgr_key_derivation	35.080m	8.241ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	11.641m	8.955ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	18.492m	7.224ms	3	3	100.00
		chip_prim_tl_access	7.784m	12.590ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	16.096m	11.195ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.999m	3.902ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.596m	5.075ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.594m	4.331ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.905m	5.536ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.622m	4.086ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.963m	4.605ms	3	3	100.00
		chip_tap_straps_dev	29.000m	15.114ms	4	5	80.00
		chip_tap_straps_rma	30.118m	15.010ms	3	5	60.00
		chip_tap_straps_prod	28.791m	12.980ms	5	5	100.00
		chip_rv_dm_lc_disabled	12.747m	17.195ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.704m	3.257ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.840m	2.868ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.663m	3.869ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.622m	3.354ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	43.951m	32.233ms	2	3	66.67
		chip_rv_dm_lc_disabled	12.747m	17.195ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.617h	49.540ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.663h	50.700ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	20.663m	10.572ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.681h	47.313ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	43.951m	32.233ms	2	3	66.67
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.985m	2.380ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.060m	2.100ms	3	3	100.00
		rom_volatile_raw_unlock	1.884m	2.181ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	21.051m	12.590ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	35.685m	21.560ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.734m	3.592ms	3	3	100.00
		chip_sw_keymgr_key_derivation	35.080m	8.241ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.796m	5.020ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.245m	3.186ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	35.685m	21.560ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.734m	3.592ms	3	3	100.00
		chip_sw_keymgr_key_derivation	35.080m	8.241ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.796m	5.020ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.245m	3.186ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	21.051m	12.590ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.389m	4.461ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.376m	3.180ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.939m	4.275ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.780m	8.035ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.560m	8.297ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.343m	7.745ms	3	3	100.00
		chip_sw_lc_ctrl_transition	21.051m	12.590ms	15	15	100.00
		chip_prim_tl_access	7.784m	12.590ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.784m	12.590ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.778h	28.278ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.330m	7.483ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	31.213m	21.901ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	8.318m	7.672ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	17.191m	9.404ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	10.756m	7.116ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	41.987m	25.831ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	30.428m	18.844ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	13.996m	9.773ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	24.849m	12.278ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.544m	5.650ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.330m	7.483ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.938m	4.074ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.131h	34.246ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.792m	6.759ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.110m	4.308ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.999m	28.089ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.685m	8.882ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	28.300m	10.516ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	57.407m	29.286ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.874m	2.963ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.987m	5.846ms	99	100	99.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.641m	8.955ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.641m	8.955ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	28.300m	10.516ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.999m	28.089ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	12.544m	5.650ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.374m	5.018ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	9.582m	4.725ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	10.470m	4.560ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.703m	4.386ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	35.891m	16.613ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.965m	2.733ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.987m	5.846ms	99	100	99.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	34.171m	7.627ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	24.017m	6.304ms	3	3	100.00
		chip_plic_all_irqs_10	10.703m	4.760ms	3	3	100.00
		chip_plic_all_irqs_20	17.794m	4.803ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.349m	2.966ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.452m	3.338ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.202h	15.665ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	19.399m	7.546ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	13.351m	4.816ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.432m	3.939ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.790m	3.268ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.796m	5.020ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.579m	3.705ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	16.956m	9.332ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	16.241m	8.379ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.492m	7.224ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.987m	5.846ms	99	100	99.00
		chip_sw_data_integrity_escalation	15.252m	6.364ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.600m	3.345ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.195m	3.358ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.355m	3.298ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.780m	4.168ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	39.034m	8.535ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.113h	31.672ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	57.710m	12.017ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.885m	3.141ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.092m	5.370ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.987m	5.846ms	99	100	99.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.484m	2.973ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	35.891m	16.613ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.009m	5.696ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.173m	4.329ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	32.441m	13.243ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	39.366m	8.475ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	34.171m	7.627ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	27.083m	8.651ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.611h	255.233ms	2	3	66.67
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	44.834m	20.144ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	30.985m	14.028ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	9.582m	4.725ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.760m	4.539ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.111m	3.385ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	30.118m	15.010ms	3	5	60.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.747m	17.195ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2608	2644	98.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.703m	3.786ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	25.783m	8.596ms	0	1	0.00
		rom_e2e_jtag_debug_dev	18.257m	8.666ms	0	1	0.00
		rom_e2e_jtag_debug_rma	21.811m	6.959ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	53.565m	34.160ms	1	1	100.00
		rom_e2e_jtag_inject_dev	55.608m	21.987ms	1	1	100.00
		rom_e2e_jtag_inject_rma	48.687m	27.191ms	1	1	100.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.531m	3.114ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.937m	3.491ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	22.040m	4.805ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	42.760m	10.308ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	13.498m	3.214ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	27.899m	6.268ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	5.108m	2.422ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	8.868m	4.289ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	10.017m	7.381ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.921m	5.128ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	28.300m	10.516ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.987m	5.846ms	99	100	99.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	11.571m	4.413ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.379h	19.366ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	25.783m	8.596ms	0	1	0.00
		rom_e2e_jtag_debug_dev	18.257m	8.666ms	0	1	0.00
		rom_e2e_jtag_debug_rma	21.811m	6.959ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.500m	5.731ms	3	3	100.00
V3		TOTAL			35	45	77.78
	Unmapped tests	chip_sival_flash_info_access	6.477m	3.360ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	11.370m	5.115ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	4.654m	2.201ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.120h	16.815ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	17.943m	5.800ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.678m	4.759ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	8.668m	4.270ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	7.480m	6.960ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	6.756m	3.258ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.907m	2.695ms	2	3	66.67
		chip_sw_flash_ctrl_write_clear	8.357m	3.823ms	3	3	100.00
		TOTAL			2877	2945	97.69

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	11	11	10	90.91
V1	18	18	16	88.89
V2	285	270	241	84.56
V2S	1	1	1	100.00
V3	90	21	15	16.67

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	95.46	93.77	95.25	--	94.47	97.53	99.58

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.105458702504016457972404246831897491811201973562216463153495365156473162330283
    Line 373, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2663.808013 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2663.808013 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.93448913987022260322283840016271335391710795396963755557985102562185181269853
    Line 361, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2821.932615 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2821.932615 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test chip_sw_lc_walkthrough_testunlocks has 1 failures.
  - 0.chip_sw_lc_walkthrough_testunlocks.49321934879776955708248483175452292263855892122064598864326006795489258239161
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  Job ID: smart:1641cb70-8a4c-4777-90e6-434a96f6e58f
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.31912716390272756245633572386100022114348178162681344733407860651111069308003
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:9f937a4e-7f39-46e8-96bf-d2fd4dfaadb3
```
  - 1.chip_sw_rv_timer_systick_test.44838220262408546279692745781303510510853164721522294708184441266497307515980
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:038fb41b-1559-4ce5-a2d8-fc49667cc634
```
  - ... and 1 more failures.
- Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 1 failures.
  - 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.40511106794618958210266580744231897367466538070772540140464926230036272066875
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
```
  Job ID: smart:a59bf4d1-c1c7-4ad1-a787-917645f618e4
```
- Test chip_sw_keymgr_key_derivation_prod has 1 failures.
  - 0.chip_sw_keymgr_key_derivation_prod.17493173996988577791348989800205718129875586588243353560409278386997798266511
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
  Job ID: smart:a4998485-0994-496a-8d30-e6192fad0abc
```
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.39692573639144915506993563425618240781548211301522168091758413291920126684168
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:febb430a-02f6-462b-b9e5-298ec2915c32
```
- ... and 5 more tests.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:*-*-* has 15 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.17797138597896682305167467845518482597049748051145526084663374454728981307833
    Line 1004, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 17906.999413 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:02108421
  "
  UVM_INFO @ 17906.999413 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.57284564787480205353297948156749978983998153195595687317410505093905791579944
    Line 1018, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_ERROR @ 22482.390693 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:21084210
  "
  UVM_INFO @ 22482.390693 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.79949221764900537590069024179504856544663841269354948335968125380048453393075
    Line 997, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_ERROR @ 22476.061785 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:2318c631
  "
  UVM_INFO @ 22476.061785 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.106922663221489487352920880833055908774099932457008955273268318829394425464015
    Line 987, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_ERROR @ 23051.508673 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:25294a52
  "
  UVM_INFO @ 23051.508673 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.54323730719060991603855173289586596330989076186253825574029316587457365753158
    Line 1075, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_ERROR @ 21568.309377 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  BFV:" == "BFV:07535603
  LCV:2739ce73
  "
  UVM_INFO @ 21568.309377 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- ... and 10 more tests.
UVM_FATAL @ * us: (jtag_driver.sv:124) [driver] wait timeout occurred! has 4 failures:
- Test chip_tap_straps_testunlock0 has 1 failures.
  - 0.chip_tap_straps_testunlock0.107106261568417477856102480392167281732943591120344958166346056455406511440845
    Line 5968, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_testunlock0/latest/run.log
```
  UVM_FATAL @ 14751.519988 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 14751.519988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_tap_straps_rma has 2 failures.
  - 1.chip_tap_straps_rma.69309869889131440606213190329287976609511145880212112384949178157260371825705
    Line 5972, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_rma/latest/run.log
```
  UVM_FATAL @ 15010.356709 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 15010.356709 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.chip_tap_straps_rma.61838875048814176660207662047183068048262016846091498915233593809285000670033
    Line 5997, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_rma/latest/run.log
```
  UVM_FATAL @ 16545.841435 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 16545.841435 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_tap_straps_dev has 1 failures.
  - 3.chip_tap_straps_dev.44803428379663806161967671792106340233789874832749072814833295252494561174306
    Line 5966, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_dev/latest/run.log
```
  UVM_FATAL @ 15114.488782 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 15114.488782 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.113759234658628089189451689883223120872120607646763709348331611601756852324938
    Line 731, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3367.523304 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3367.523304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.88005095143450653157878257587453184660895063658142346542116238401401412282405
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3384.696789 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3384.696789 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.31486153649427271981783482989215765282359434038437707725750598576818507540454
    Line 831, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 8595.513500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 8595.513500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.84660943989981748763616168184655089434583690784033927069667927419388151282705
    Line 811, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 8665.567500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 8665.567500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.24712171667168652193261742779213487225953130604674522635026019183478644882711
    Line 799, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 6959.265000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 6959.265000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:

Test rom_raw_unlock has 2 failures.

1.rom_raw_unlock.37313721050081185730760670539332126978147318627700034718703437251538728882859
Line 760, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 204866.081076 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 204866.081076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_raw_unlock.72566612107493220417306220569081829793305733171186382158045993805839014224979
Line 758, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 207191.929487 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 207191.929487 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:689) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert unexpectedly fired in cycle *. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 1.chip_sw_rv_core_ibex_lockstep_glitch.17531078787754983385042491755123186307911178252969300328817740197567598795866
    Line 746, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2694.965788 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:689) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (1 [0x1] vs 0 [0x0]) Major alert unexpectedly fired in cycle 5.
  UVM_INFO @ 2694.965788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 2.chip_csr_aliasing.13795491556988156786950044799019491666458324737401546683096106384624772342302
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:042a8569-1756-45c8-8943-1ac31a1d248d
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 2.chip_sw_all_escalation_resets.33439881587912885190980491665907174523023741438334156752700896935812706947928
    Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2695.726280 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2695.726280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.
  - 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.97423363907109011524654151133811469556067602662746690587310221385008737574309
    Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6550.274008 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6550.274008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 20.chip_sw_alert_handler_lpg_sleep_mode_alerts.76846649835919240981084959722395436166881904134306161203863756434105056166410
    Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3844.858032 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3844.858032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```