| T1001 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2764875613 |
|
|
Jul 24 08:09:46 PM PDT 24 |
Jul 24 08:21:33 PM PDT 24 |
4700329824 ps |
| T1002 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.488095758 |
|
|
Jul 24 08:07:04 PM PDT 24 |
Jul 24 08:16:48 PM PDT 24 |
4089862486 ps |
| T1003 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3493430324 |
|
|
Jul 24 08:01:06 PM PDT 24 |
Jul 24 08:21:09 PM PDT 24 |
12312396541 ps |
| T382 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1292674110 |
|
|
Jul 24 08:25:37 PM PDT 24 |
Jul 24 08:34:26 PM PDT 24 |
4189395880 ps |
| T290 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1093762669 |
|
|
Jul 24 08:05:41 PM PDT 24 |
Jul 24 08:15:35 PM PDT 24 |
5022389405 ps |
| T158 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3878235844 |
|
|
Jul 24 08:27:23 PM PDT 24 |
Jul 24 08:35:24 PM PDT 24 |
5219072696 ps |
| T801 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.840679432 |
|
|
Jul 24 08:13:58 PM PDT 24 |
Jul 24 08:26:26 PM PDT 24 |
8857217232 ps |
| T1004 |
/workspace/coverage/default/1.rom_e2e_static_critical.3019588383 |
|
|
Jul 24 08:13:31 PM PDT 24 |
Jul 24 09:22:38 PM PDT 24 |
16889050768 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3090207692 |
|
|
Jul 24 08:15:28 PM PDT 24 |
Jul 24 09:10:59 PM PDT 24 |
18506701721 ps |
| T1006 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.1351912679 |
|
|
Jul 24 08:26:23 PM PDT 24 |
Jul 24 09:17:16 PM PDT 24 |
15094407886 ps |
| T273 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.799542469 |
|
|
Jul 24 08:04:37 PM PDT 24 |
Jul 24 09:46:10 PM PDT 24 |
23542255295 ps |
| T1007 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.1849218501 |
|
|
Jul 24 08:15:09 PM PDT 24 |
Jul 24 08:19:31 PM PDT 24 |
2804285616 ps |
| T340 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3534648770 |
|
|
Jul 24 08:11:35 PM PDT 24 |
Jul 24 08:26:36 PM PDT 24 |
4657166890 ps |
| T1008 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.893849143 |
|
|
Jul 24 08:01:15 PM PDT 24 |
Jul 24 08:13:22 PM PDT 24 |
9173111140 ps |
| T369 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.679854545 |
|
|
Jul 24 08:21:13 PM PDT 24 |
Jul 24 08:55:46 PM PDT 24 |
12629015560 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2830544606 |
|
|
Jul 24 08:13:53 PM PDT 24 |
Jul 24 08:32:26 PM PDT 24 |
6051956746 ps |
| T367 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3294142063 |
|
|
Jul 24 08:06:45 PM PDT 24 |
Jul 24 08:26:24 PM PDT 24 |
5380709248 ps |
| T759 |
/workspace/coverage/default/1.chip_sw_power_idle_load.2174968698 |
|
|
Jul 24 08:08:45 PM PDT 24 |
Jul 24 08:18:51 PM PDT 24 |
3942368514 ps |
| T200 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.728200033 |
|
|
Jul 24 07:56:44 PM PDT 24 |
Jul 24 11:41:15 PM PDT 24 |
78790698558 ps |
| T328 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2745379914 |
|
|
Jul 24 07:58:31 PM PDT 24 |
Jul 24 08:12:46 PM PDT 24 |
4530403490 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2741080787 |
|
|
Jul 24 08:12:21 PM PDT 24 |
Jul 24 08:17:59 PM PDT 24 |
2870351832 ps |
| T265 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1660820305 |
|
|
Jul 24 08:29:17 PM PDT 24 |
Jul 24 08:38:47 PM PDT 24 |
4985132600 ps |
| T1011 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2087253525 |
|
|
Jul 24 07:56:46 PM PDT 24 |
Jul 24 08:07:48 PM PDT 24 |
4497466914 ps |
| T1012 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1715434869 |
|
|
Jul 24 08:00:55 PM PDT 24 |
Jul 24 08:09:25 PM PDT 24 |
4745941950 ps |
| T782 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2435308154 |
|
|
Jul 24 08:26:40 PM PDT 24 |
Jul 24 08:35:43 PM PDT 24 |
5964359670 ps |
| T365 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2739298790 |
|
|
Jul 24 08:06:22 PM PDT 24 |
Jul 24 08:11:56 PM PDT 24 |
2944950508 ps |
| T40 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3960051340 |
|
|
Jul 24 07:56:43 PM PDT 24 |
Jul 24 08:06:46 PM PDT 24 |
6555174740 ps |
| T361 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1518260833 |
|
|
Jul 24 08:05:00 PM PDT 24 |
Jul 24 08:15:17 PM PDT 24 |
18647622928 ps |
| T348 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3492775638 |
|
|
Jul 24 08:02:14 PM PDT 24 |
Jul 24 08:09:18 PM PDT 24 |
3994212612 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.61895065 |
|
|
Jul 24 08:14:52 PM PDT 24 |
Jul 24 09:26:38 PM PDT 24 |
18043924948 ps |
| T332 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.4018301916 |
|
|
Jul 24 08:12:01 PM PDT 24 |
Jul 24 08:26:00 PM PDT 24 |
5345047752 ps |
| T366 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.4191379355 |
|
|
Jul 24 08:14:24 PM PDT 24 |
Jul 24 08:17:56 PM PDT 24 |
2501710048 ps |
| T1014 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3583638397 |
|
|
Jul 24 08:13:04 PM PDT 24 |
Jul 24 09:14:59 PM PDT 24 |
15798539883 ps |
| T1015 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.486369875 |
|
|
Jul 24 08:06:13 PM PDT 24 |
Jul 24 08:15:53 PM PDT 24 |
4285521034 ps |
| T1016 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1749253729 |
|
|
Jul 24 08:00:41 PM PDT 24 |
Jul 24 08:10:35 PM PDT 24 |
4325759672 ps |
| T785 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2178348686 |
|
|
Jul 24 08:03:57 PM PDT 24 |
Jul 24 08:07:47 PM PDT 24 |
2464878856 ps |
| T374 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.1998676454 |
|
|
Jul 24 08:01:26 PM PDT 24 |
Jul 24 08:09:20 PM PDT 24 |
4426965200 ps |
| T1017 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.328704763 |
|
|
Jul 24 08:24:20 PM PDT 24 |
Jul 24 08:42:04 PM PDT 24 |
8701684132 ps |
| T894 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2761687868 |
|
|
Jul 24 08:28:48 PM PDT 24 |
Jul 24 08:36:30 PM PDT 24 |
4393454956 ps |
| T54 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.791288748 |
|
|
Jul 24 08:03:05 PM PDT 24 |
Jul 24 08:06:40 PM PDT 24 |
3796653658 ps |
| T1018 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1446551221 |
|
|
Jul 24 08:15:35 PM PDT 24 |
Jul 24 08:27:44 PM PDT 24 |
7903750920 ps |
| T164 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.2396529720 |
|
|
Jul 24 08:30:40 PM PDT 24 |
Jul 24 08:39:06 PM PDT 24 |
5036207480 ps |
| T142 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3895835147 |
|
|
Jul 24 08:15:30 PM PDT 24 |
Jul 24 08:21:29 PM PDT 24 |
3193922531 ps |
| T1019 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.2525669382 |
|
|
Jul 24 08:09:25 PM PDT 24 |
Jul 24 08:15:02 PM PDT 24 |
2800802166 ps |
| T205 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.734499635 |
|
|
Jul 24 08:03:43 PM PDT 24 |
Jul 24 08:14:11 PM PDT 24 |
4642342713 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.644481609 |
|
|
Jul 24 07:55:41 PM PDT 24 |
Jul 24 08:28:56 PM PDT 24 |
7963478830 ps |
| T71 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.4209103772 |
|
|
Jul 24 08:00:13 PM PDT 24 |
Jul 24 08:08:01 PM PDT 24 |
5204036526 ps |
| T1020 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1276755930 |
|
|
Jul 24 07:59:25 PM PDT 24 |
Jul 24 08:18:31 PM PDT 24 |
8050744990 ps |
| T1021 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1201436459 |
|
|
Jul 24 08:08:19 PM PDT 24 |
Jul 24 08:41:49 PM PDT 24 |
13772357623 ps |
| T849 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2340555778 |
|
|
Jul 24 08:26:57 PM PDT 24 |
Jul 24 08:32:48 PM PDT 24 |
3374472596 ps |
| T827 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.494698903 |
|
|
Jul 24 08:26:24 PM PDT 24 |
Jul 24 08:38:05 PM PDT 24 |
5757851400 ps |
| T1022 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1218002959 |
|
|
Jul 24 08:08:33 PM PDT 24 |
Jul 24 08:14:19 PM PDT 24 |
2861041528 ps |
| T1023 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2253127073 |
|
|
Jul 24 08:01:57 PM PDT 24 |
Jul 24 08:10:21 PM PDT 24 |
3079876524 ps |
| T842 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2654546553 |
|
|
Jul 24 08:31:05 PM PDT 24 |
Jul 24 08:37:49 PM PDT 24 |
4349741564 ps |
| T355 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3357884988 |
|
|
Jul 24 08:01:25 PM PDT 24 |
Jul 24 08:12:24 PM PDT 24 |
5250617788 ps |
| T404 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.107336865 |
|
|
Jul 24 08:28:45 PM PDT 24 |
Jul 24 08:37:10 PM PDT 24 |
4655970016 ps |
| T341 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3218158742 |
|
|
Jul 24 08:02:24 PM PDT 24 |
Jul 24 08:16:10 PM PDT 24 |
5210154720 ps |
| T331 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.1313540074 |
|
|
Jul 24 08:08:10 PM PDT 24 |
Jul 24 08:22:37 PM PDT 24 |
5554560754 ps |
| T1024 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.77369142 |
|
|
Jul 24 08:13:54 PM PDT 24 |
Jul 24 09:01:40 PM PDT 24 |
39095227725 ps |
| T825 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3955020781 |
|
|
Jul 24 08:24:09 PM PDT 24 |
Jul 24 08:29:47 PM PDT 24 |
3918551468 ps |
| T1025 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3938880784 |
|
|
Jul 24 07:58:57 PM PDT 24 |
Jul 24 08:16:02 PM PDT 24 |
6136540844 ps |
| T1026 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.125253357 |
|
|
Jul 24 08:07:32 PM PDT 24 |
Jul 24 08:12:05 PM PDT 24 |
2341557973 ps |
| T1027 |
/workspace/coverage/default/3.chip_tap_straps_dev.3802798902 |
|
|
Jul 24 08:19:37 PM PDT 24 |
Jul 24 08:22:57 PM PDT 24 |
2647008235 ps |
| T325 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.881836526 |
|
|
Jul 24 08:06:43 PM PDT 24 |
Jul 24 08:24:06 PM PDT 24 |
5372819988 ps |
| T1028 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.306509445 |
|
|
Jul 24 08:12:57 PM PDT 24 |
Jul 24 08:20:30 PM PDT 24 |
3110999200 ps |
| T89 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1814408969 |
|
|
Jul 24 08:30:58 PM PDT 24 |
Jul 24 08:38:53 PM PDT 24 |
4089008432 ps |
| T818 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3611970481 |
|
|
Jul 24 08:28:11 PM PDT 24 |
Jul 24 08:33:50 PM PDT 24 |
3713365094 ps |
| T1029 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.860749599 |
|
|
Jul 24 08:05:27 PM PDT 24 |
Jul 24 09:10:44 PM PDT 24 |
15105247320 ps |
| T451 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.4116092871 |
|
|
Jul 24 08:06:53 PM PDT 24 |
Jul 24 08:35:03 PM PDT 24 |
7134401430 ps |
| T1030 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.327606566 |
|
|
Jul 24 08:07:15 PM PDT 24 |
Jul 24 08:15:02 PM PDT 24 |
6325629932 ps |
| T1031 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3348187434 |
|
|
Jul 24 08:11:37 PM PDT 24 |
Jul 24 08:18:35 PM PDT 24 |
2995609376 ps |
| T1032 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2117970331 |
|
|
Jul 24 08:06:06 PM PDT 24 |
Jul 24 08:40:17 PM PDT 24 |
9766979796 ps |
| T870 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2320378902 |
|
|
Jul 24 08:21:30 PM PDT 24 |
Jul 24 08:28:19 PM PDT 24 |
3510229932 ps |
| T1033 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3321648797 |
|
|
Jul 24 08:17:05 PM PDT 24 |
Jul 24 08:36:46 PM PDT 24 |
8300608802 ps |
| T1034 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.771344683 |
|
|
Jul 24 08:06:56 PM PDT 24 |
Jul 24 08:50:06 PM PDT 24 |
27151214720 ps |
| T274 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.2457315503 |
|
|
Jul 24 08:03:32 PM PDT 24 |
Jul 24 09:05:10 PM PDT 24 |
26541111800 ps |
| T1035 |
/workspace/coverage/default/4.chip_tap_straps_rma.4261112678 |
|
|
Jul 24 08:20:20 PM PDT 24 |
Jul 24 08:23:39 PM PDT 24 |
3039060877 ps |
| T153 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2427809037 |
|
|
Jul 24 08:08:24 PM PDT 24 |
Jul 24 08:17:50 PM PDT 24 |
3810220644 ps |
| T1036 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1292699941 |
|
|
Jul 24 08:04:17 PM PDT 24 |
Jul 24 09:08:58 PM PDT 24 |
15941879048 ps |
| T1037 |
/workspace/coverage/default/0.chip_sw_example_flash.254765162 |
|
|
Jul 24 07:55:00 PM PDT 24 |
Jul 24 07:58:08 PM PDT 24 |
2968614604 ps |
| T771 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1077321018 |
|
|
Jul 24 08:20:49 PM PDT 24 |
Jul 24 08:28:13 PM PDT 24 |
4357144680 ps |
| T1038 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.849406841 |
|
|
Jul 24 08:14:17 PM PDT 24 |
Jul 24 08:47:00 PM PDT 24 |
8340949322 ps |
| T59 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.520567871 |
|
|
Jul 24 07:56:43 PM PDT 24 |
Jul 24 08:04:42 PM PDT 24 |
3719626152 ps |
| T212 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.583913815 |
|
|
Jul 24 08:19:10 PM PDT 24 |
Jul 24 08:24:23 PM PDT 24 |
3074325893 ps |
| T783 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3848420231 |
|
|
Jul 24 08:33:41 PM PDT 24 |
Jul 24 08:43:49 PM PDT 24 |
4674620840 ps |
| T291 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2247359412 |
|
|
Jul 24 07:56:43 PM PDT 24 |
Jul 24 08:05:23 PM PDT 24 |
3350093300 ps |
| T275 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.4025140563 |
|
|
Jul 24 08:04:45 PM PDT 24 |
Jul 24 09:09:43 PM PDT 24 |
13958112210 ps |
| T1039 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3688000059 |
|
|
Jul 24 08:16:47 PM PDT 24 |
Jul 24 08:22:26 PM PDT 24 |
3114293336 ps |
| T1040 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.301973838 |
|
|
Jul 24 08:21:01 PM PDT 24 |
Jul 24 08:28:49 PM PDT 24 |
4760994664 ps |
| T311 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.956956873 |
|
|
Jul 24 08:07:56 PM PDT 24 |
Jul 24 08:16:01 PM PDT 24 |
4802707400 ps |
| T780 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.481751544 |
|
|
Jul 24 08:28:25 PM PDT 24 |
Jul 24 08:34:12 PM PDT 24 |
3301550422 ps |
| T351 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2644444017 |
|
|
Jul 24 08:00:12 PM PDT 24 |
Jul 24 08:10:01 PM PDT 24 |
3396997766 ps |
| T740 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3760759714 |
|
|
Jul 24 08:08:50 PM PDT 24 |
Jul 24 09:07:27 PM PDT 24 |
24535627604 ps |
| T837 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3318532004 |
|
|
Jul 24 08:25:53 PM PDT 24 |
Jul 24 08:31:42 PM PDT 24 |
3040001024 ps |
| T1041 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2913720329 |
|
|
Jul 24 07:56:31 PM PDT 24 |
Jul 24 08:01:01 PM PDT 24 |
3104697513 ps |
| T251 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1904558237 |
|
|
Jul 24 08:31:38 PM PDT 24 |
Jul 24 08:37:15 PM PDT 24 |
3917274644 ps |
| T1042 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4270781197 |
|
|
Jul 24 08:17:42 PM PDT 24 |
Jul 24 08:28:19 PM PDT 24 |
6482132278 ps |
| T1043 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3048790159 |
|
|
Jul 24 08:06:04 PM PDT 24 |
Jul 24 08:18:29 PM PDT 24 |
4874271810 ps |
| T276 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.3675753094 |
|
|
Jul 24 08:25:35 PM PDT 24 |
Jul 24 09:10:55 PM PDT 24 |
23744887740 ps |
| T775 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2559465095 |
|
|
Jul 24 08:27:50 PM PDT 24 |
Jul 24 08:33:48 PM PDT 24 |
3749060902 ps |
| T277 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3737485695 |
|
|
Jul 24 08:08:37 PM PDT 24 |
Jul 24 09:11:11 PM PDT 24 |
13844465100 ps |
| T542 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.367750875 |
|
|
Jul 24 08:12:15 PM PDT 24 |
Jul 24 08:33:40 PM PDT 24 |
10863037869 ps |
| T1044 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.4068793791 |
|
|
Jul 24 08:00:03 PM PDT 24 |
Jul 24 08:10:12 PM PDT 24 |
4914241996 ps |
| T826 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1202168244 |
|
|
Jul 24 08:24:44 PM PDT 24 |
Jul 24 08:37:15 PM PDT 24 |
4628198750 ps |
| T130 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.548154033 |
|
|
Jul 24 08:15:43 PM PDT 24 |
Jul 24 08:23:33 PM PDT 24 |
5351540400 ps |
| T1045 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.3448411337 |
|
|
Jul 24 07:59:14 PM PDT 24 |
Jul 24 08:31:36 PM PDT 24 |
8022496810 ps |
| T743 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.3666295139 |
|
|
Jul 24 07:57:44 PM PDT 24 |
Jul 24 08:04:57 PM PDT 24 |
3040744720 ps |
| T1046 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2963040584 |
|
|
Jul 24 08:23:21 PM PDT 24 |
Jul 24 08:33:40 PM PDT 24 |
6837785710 ps |
| T1047 |
/workspace/coverage/default/1.chip_sw_kmac_idle.1084694688 |
|
|
Jul 24 08:06:37 PM PDT 24 |
Jul 24 08:11:20 PM PDT 24 |
2682909320 ps |
| T746 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2152967716 |
|
|
Jul 24 08:32:09 PM PDT 24 |
Jul 24 08:42:56 PM PDT 24 |
5610170824 ps |
| T1048 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.203711977 |
|
|
Jul 24 07:58:44 PM PDT 24 |
Jul 24 08:05:22 PM PDT 24 |
4255928800 ps |
| T1049 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1916997919 |
|
|
Jul 24 07:58:54 PM PDT 24 |
Jul 24 08:13:20 PM PDT 24 |
7440465328 ps |
| T201 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1280058038 |
|
|
Jul 24 08:12:55 PM PDT 24 |
Jul 24 11:29:27 PM PDT 24 |
65709922527 ps |
| T1050 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2014533715 |
|
|
Jul 24 08:08:11 PM PDT 24 |
Jul 24 08:20:26 PM PDT 24 |
5050106538 ps |
| T1051 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.4073011994 |
|
|
Jul 24 08:21:39 PM PDT 24 |
Jul 24 08:29:39 PM PDT 24 |
4032579702 ps |
| T868 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1103908478 |
|
|
Jul 24 08:24:04 PM PDT 24 |
Jul 24 08:34:06 PM PDT 24 |
5292958212 ps |
| T741 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3568734349 |
|
|
Jul 24 08:17:29 PM PDT 24 |
Jul 24 09:16:28 PM PDT 24 |
24838595441 ps |
| T1052 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3920043320 |
|
|
Jul 24 08:15:52 PM PDT 24 |
Jul 24 08:19:54 PM PDT 24 |
2779368881 ps |
| T258 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.9229719 |
|
|
Jul 24 08:01:14 PM PDT 24 |
Jul 24 08:06:16 PM PDT 24 |
2753993320 ps |
| T806 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.214106000 |
|
|
Jul 24 08:26:53 PM PDT 24 |
Jul 24 08:36:34 PM PDT 24 |
5739660540 ps |
| T1053 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.371231284 |
|
|
Jul 24 08:17:01 PM PDT 24 |
Jul 24 08:23:07 PM PDT 24 |
3862936208 ps |
| T830 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3305708998 |
|
|
Jul 24 08:28:56 PM PDT 24 |
Jul 24 08:40:04 PM PDT 24 |
5100226632 ps |
| T873 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2070441336 |
|
|
Jul 24 08:28:29 PM PDT 24 |
Jul 24 08:35:22 PM PDT 24 |
3279775068 ps |
| T1054 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.543557713 |
|
|
Jul 24 08:06:04 PM PDT 24 |
Jul 24 08:34:26 PM PDT 24 |
7780916094 ps |
| T822 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1985951161 |
|
|
Jul 24 08:33:35 PM PDT 24 |
Jul 24 08:42:47 PM PDT 24 |
3882771760 ps |
| T174 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3820703418 |
|
|
Jul 24 07:55:29 PM PDT 24 |
Jul 24 08:00:28 PM PDT 24 |
3782024761 ps |
| T814 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3037953400 |
|
|
Jul 24 08:26:25 PM PDT 24 |
Jul 24 08:32:37 PM PDT 24 |
3492904138 ps |
| T229 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3248095588 |
|
|
Jul 24 08:02:16 PM PDT 24 |
Jul 24 09:10:43 PM PDT 24 |
16518429054 ps |
| T819 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2928896820 |
|
|
Jul 24 08:28:18 PM PDT 24 |
Jul 24 08:39:00 PM PDT 24 |
5757469036 ps |
| T113 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3439279756 |
|
|
Jul 24 08:02:51 PM PDT 24 |
Jul 24 08:09:59 PM PDT 24 |
4446353820 ps |
| T1055 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2103270943 |
|
|
Jul 24 08:15:33 PM PDT 24 |
Jul 24 08:39:30 PM PDT 24 |
7117797244 ps |
| T1056 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2186972786 |
|
|
Jul 24 08:18:03 PM PDT 24 |
Jul 24 08:22:09 PM PDT 24 |
2741977820 ps |
| T1057 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2781168984 |
|
|
Jul 24 08:04:46 PM PDT 24 |
Jul 24 09:00:31 PM PDT 24 |
18639719533 ps |
| T1058 |
/workspace/coverage/default/0.chip_tap_straps_prod.2807893527 |
|
|
Jul 24 08:07:50 PM PDT 24 |
Jul 24 08:10:13 PM PDT 24 |
2923534668 ps |
| T1059 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4247782156 |
|
|
Jul 24 08:07:16 PM PDT 24 |
Jul 24 08:21:21 PM PDT 24 |
8049456438 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.124561256 |
|
|
Jul 24 08:01:42 PM PDT 24 |
Jul 24 08:06:34 PM PDT 24 |
2727319238 ps |
| T42 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.3625130703 |
|
|
Jul 24 08:03:33 PM PDT 24 |
Jul 24 08:10:50 PM PDT 24 |
3366585058 ps |
| T312 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.378993695 |
|
|
Jul 24 08:16:50 PM PDT 24 |
Jul 24 08:26:24 PM PDT 24 |
4874522660 ps |
| T1061 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.4159878811 |
|
|
Jul 24 08:02:38 PM PDT 24 |
Jul 24 08:07:47 PM PDT 24 |
3091538850 ps |
| T248 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1937718752 |
|
|
Jul 24 07:58:08 PM PDT 24 |
Jul 24 08:08:22 PM PDT 24 |
5685975036 ps |
| T764 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.4119840906 |
|
|
Jul 24 08:11:29 PM PDT 24 |
Jul 24 08:13:26 PM PDT 24 |
2953988933 ps |
| T765 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.3224583436 |
|
|
Jul 24 08:18:36 PM PDT 24 |
Jul 24 08:20:46 PM PDT 24 |
2458105998 ps |
| T356 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.2548170457 |
|
|
Jul 24 08:05:58 PM PDT 24 |
Jul 24 08:17:47 PM PDT 24 |
4791529566 ps |
| T236 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1728411855 |
|
|
Jul 24 08:12:28 PM PDT 24 |
Jul 24 09:44:04 PM PDT 24 |
47718989100 ps |
| T766 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.3262096337 |
|
|
Jul 24 08:08:26 PM PDT 24 |
Jul 24 08:10:10 PM PDT 24 |
2439726864 ps |
| T1062 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3064130405 |
|
|
Jul 24 08:14:22 PM PDT 24 |
Jul 24 08:18:46 PM PDT 24 |
2553887148 ps |
| T456 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1110138827 |
|
|
Jul 24 08:24:34 PM PDT 24 |
Jul 24 08:32:39 PM PDT 24 |
3400383834 ps |
| T359 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.2615971312 |
|
|
Jul 24 08:02:51 PM PDT 24 |
Jul 24 08:07:35 PM PDT 24 |
3013557046 ps |
| T823 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072111187 |
|
|
Jul 24 08:28:45 PM PDT 24 |
Jul 24 08:36:10 PM PDT 24 |
3370070216 ps |
| T1063 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.2548018824 |
|
|
Jul 24 08:05:52 PM PDT 24 |
Jul 24 09:07:35 PM PDT 24 |
14622583877 ps |
| T540 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.169356282 |
|
|
Jul 24 08:01:23 PM PDT 24 |
Jul 24 08:17:01 PM PDT 24 |
4623102348 ps |
| T1064 |
/workspace/coverage/default/0.chip_sw_kmac_idle.1687078444 |
|
|
Jul 24 07:59:00 PM PDT 24 |
Jul 24 08:03:12 PM PDT 24 |
2484990076 ps |
| T241 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1421683978 |
|
|
Jul 24 08:23:42 PM PDT 24 |
Jul 24 08:33:25 PM PDT 24 |
4382625800 ps |
| T1065 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2422865468 |
|
|
Jul 24 08:22:30 PM PDT 24 |
Jul 24 08:31:50 PM PDT 24 |
3919114864 ps |
| T151 |
/workspace/coverage/default/0.rom_raw_unlock.978430445 |
|
|
Jul 24 08:01:49 PM PDT 24 |
Jul 24 08:06:08 PM PDT 24 |
4963500837 ps |
| T72 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.3656320864 |
|
|
Jul 24 07:57:12 PM PDT 24 |
Jul 24 08:03:31 PM PDT 24 |
3132298620 ps |
| T1066 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1054531356 |
|
|
Jul 24 07:58:28 PM PDT 24 |
Jul 24 08:20:49 PM PDT 24 |
9260020904 ps |
| T1067 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.3572376090 |
|
|
Jul 24 08:19:26 PM PDT 24 |
Jul 24 08:23:05 PM PDT 24 |
3269369448 ps |
| T1068 |
/workspace/coverage/default/2.rom_e2e_static_critical.1320523049 |
|
|
Jul 24 08:22:32 PM PDT 24 |
Jul 24 09:19:50 PM PDT 24 |
16470156004 ps |
| T1069 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.39891793 |
|
|
Jul 24 08:10:13 PM PDT 24 |
Jul 24 08:22:54 PM PDT 24 |
4996366040 ps |
| T1070 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1533494542 |
|
|
Jul 24 08:21:09 PM PDT 24 |
Jul 24 08:31:05 PM PDT 24 |
4129289500 ps |
| T239 |
/workspace/coverage/default/1.chip_sw_flash_init.3345041894 |
|
|
Jul 24 08:02:09 PM PDT 24 |
Jul 24 08:38:03 PM PDT 24 |
17491019636 ps |
| T1071 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.998505603 |
|
|
Jul 24 08:04:16 PM PDT 24 |
Jul 24 08:22:30 PM PDT 24 |
5600333308 ps |
| T1072 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3523662503 |
|
|
Jul 24 08:23:15 PM PDT 24 |
Jul 24 09:01:28 PM PDT 24 |
11434867315 ps |
| T828 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.3265007635 |
|
|
Jul 24 08:28:31 PM PDT 24 |
Jul 24 08:39:09 PM PDT 24 |
6663386090 ps |
| T1073 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2413509144 |
|
|
Jul 24 08:11:59 PM PDT 24 |
Jul 24 08:32:12 PM PDT 24 |
12541628652 ps |
| T1074 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1385459076 |
|
|
Jul 24 08:05:17 PM PDT 24 |
Jul 24 09:04:29 PM PDT 24 |
14628702454 ps |
| T1075 |
/workspace/coverage/default/2.chip_sw_example_flash.3652392010 |
|
|
Jul 24 08:10:30 PM PDT 24 |
Jul 24 08:13:18 PM PDT 24 |
2760893336 ps |
| T1076 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3245628521 |
|
|
Jul 24 08:23:02 PM PDT 24 |
Jul 24 08:33:03 PM PDT 24 |
4577335976 ps |
| T1077 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.3586398719 |
|
|
Jul 24 08:06:44 PM PDT 24 |
Jul 24 08:48:04 PM PDT 24 |
9801370790 ps |
| T1078 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1550087254 |
|
|
Jul 24 07:58:55 PM PDT 24 |
Jul 24 09:09:03 PM PDT 24 |
16075187668 ps |
| T357 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2678722415 |
|
|
Jul 24 08:23:45 PM PDT 24 |
Jul 24 08:43:56 PM PDT 24 |
7966851052 ps |
| T1079 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4208457238 |
|
|
Jul 24 08:22:32 PM PDT 24 |
Jul 24 09:38:56 PM PDT 24 |
22403584630 ps |
| T227 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1450874047 |
|
|
Jul 24 08:14:37 PM PDT 24 |
Jul 24 08:51:47 PM PDT 24 |
11763580060 ps |
| T73 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3365878452 |
|
|
Jul 24 08:07:34 PM PDT 24 |
Jul 24 08:16:15 PM PDT 24 |
7945920784 ps |
| T1080 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2598588780 |
|
|
Jul 24 08:09:19 PM PDT 24 |
Jul 24 08:31:09 PM PDT 24 |
5482912764 ps |
| T292 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1405485654 |
|
|
Jul 24 08:20:13 PM PDT 24 |
Jul 24 08:32:54 PM PDT 24 |
6756335304 ps |
| T84 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.746869739 |
|
|
Jul 24 08:05:57 PM PDT 24 |
Jul 24 08:29:21 PM PDT 24 |
11290032828 ps |
| T541 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1383482812 |
|
|
Jul 24 08:06:42 PM PDT 24 |
Jul 24 08:21:13 PM PDT 24 |
4642872690 ps |
| T1081 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1334111084 |
|
|
Jul 24 08:07:01 PM PDT 24 |
Jul 24 09:53:04 PM PDT 24 |
22655332047 ps |
| T865 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3669324866 |
|
|
Jul 24 08:27:43 PM PDT 24 |
Jul 24 08:39:05 PM PDT 24 |
6417009634 ps |
| T1082 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1041379761 |
|
|
Jul 24 07:57:48 PM PDT 24 |
Jul 24 08:18:26 PM PDT 24 |
8273295980 ps |
| T1083 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1058080967 |
|
|
Jul 24 08:14:04 PM PDT 24 |
Jul 24 08:20:23 PM PDT 24 |
4210119749 ps |
| T1084 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.337269378 |
|
|
Jul 24 08:06:13 PM PDT 24 |
Jul 24 08:10:54 PM PDT 24 |
2412295304 ps |
| T824 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2106582466 |
|
|
Jul 24 08:21:54 PM PDT 24 |
Jul 24 08:32:05 PM PDT 24 |
5777017080 ps |
| T1085 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3446588763 |
|
|
Jul 24 08:05:13 PM PDT 24 |
Jul 24 09:02:06 PM PDT 24 |
11960299828 ps |
| T180 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.599485804 |
|
|
Jul 24 08:00:54 PM PDT 24 |
Jul 24 08:06:07 PM PDT 24 |
3803228160 ps |
| T152 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2779478548 |
|
|
Jul 24 08:10:33 PM PDT 24 |
Jul 24 11:19:35 PM PDT 24 |
57915544082 ps |
| T362 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2618643123 |
|
|
Jul 24 08:12:52 PM PDT 24 |
Jul 24 08:27:19 PM PDT 24 |
4330086846 ps |
| T1086 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3806940920 |
|
|
Jul 24 08:19:56 PM PDT 24 |
Jul 24 08:28:41 PM PDT 24 |
3279615142 ps |
| T206 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4188584692 |
|
|
Jul 24 08:06:35 PM PDT 24 |
Jul 24 08:40:14 PM PDT 24 |
24660603120 ps |
| T85 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1815305453 |
|
|
Jul 24 08:01:24 PM PDT 24 |
Jul 24 08:06:56 PM PDT 24 |
3739689848 ps |
| T1087 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2824457529 |
|
|
Jul 24 07:59:02 PM PDT 24 |
Jul 24 08:15:49 PM PDT 24 |
6303613980 ps |
| T28 |
/workspace/coverage/default/0.chip_sw_gpio.2321948170 |
|
|
Jul 24 07:56:51 PM PDT 24 |
Jul 24 08:02:33 PM PDT 24 |
3896517160 ps |
| T1088 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.137222715 |
|
|
Jul 24 08:09:17 PM PDT 24 |
Jul 24 08:13:08 PM PDT 24 |
3304828998 ps |
| T855 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2465035676 |
|
|
Jul 24 08:27:57 PM PDT 24 |
Jul 24 08:35:11 PM PDT 24 |
3469302210 ps |
| T1089 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.3157005700 |
|
|
Jul 24 07:59:11 PM PDT 24 |
Jul 24 08:04:46 PM PDT 24 |
3087971860 ps |
| T786 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.671271937 |
|
|
Jul 24 08:13:32 PM PDT 24 |
Jul 24 08:19:54 PM PDT 24 |
2851711376 ps |
| T1090 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3955900726 |
|
|
Jul 24 08:13:13 PM PDT 24 |
Jul 24 08:29:43 PM PDT 24 |
6968570273 ps |
| T186 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1797819776 |
|
|
Jul 24 07:58:13 PM PDT 24 |
Jul 24 08:08:40 PM PDT 24 |
6223581596 ps |
| T41 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.258375096 |
|
|
Jul 24 08:14:11 PM PDT 24 |
Jul 24 08:25:42 PM PDT 24 |
7152500760 ps |
| T1091 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3861883986 |
|
|
Jul 24 08:03:58 PM PDT 24 |
Jul 24 09:02:41 PM PDT 24 |
14090445058 ps |
| T1092 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.903515993 |
|
|
Jul 24 07:58:45 PM PDT 24 |
Jul 24 08:22:37 PM PDT 24 |
7712567070 ps |
| T816 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.1833593213 |
|
|
Jul 24 08:20:50 PM PDT 24 |
Jul 24 08:32:12 PM PDT 24 |
4373923950 ps |
| T1093 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2036475057 |
|
|
Jul 24 08:03:50 PM PDT 24 |
Jul 24 08:13:20 PM PDT 24 |
5494970664 ps |
| T175 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3353750568 |
|
|
Jul 24 07:57:48 PM PDT 24 |
Jul 24 08:02:29 PM PDT 24 |
3297838866 ps |
| T408 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2588516552 |
|
|
Jul 24 08:03:43 PM PDT 24 |
Jul 24 08:07:55 PM PDT 24 |
2966519264 ps |
| T207 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3361220222 |
|
|
Jul 24 08:14:17 PM PDT 24 |
Jul 24 08:24:36 PM PDT 24 |
4875560962 ps |
| T1094 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.2849232370 |
|
|
Jul 24 08:09:19 PM PDT 24 |
Jul 24 08:17:57 PM PDT 24 |
3624048736 ps |
| T1095 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3766487831 |
|
|
Jul 24 08:20:36 PM PDT 24 |
Jul 24 08:34:22 PM PDT 24 |
5377939832 ps |
| T829 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.343448000 |
|
|
Jul 24 08:25:55 PM PDT 24 |
Jul 24 08:36:27 PM PDT 24 |
5184642256 ps |
| T1096 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.4174034219 |
|
|
Jul 24 08:18:46 PM PDT 24 |
Jul 24 08:23:22 PM PDT 24 |
2497093932 ps |
| T1097 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.899922005 |
|
|
Jul 24 07:58:42 PM PDT 24 |
Jul 24 08:01:35 PM PDT 24 |
2521546250 ps |
| T1098 |
/workspace/coverage/default/4.chip_tap_straps_dev.2704019780 |
|
|
Jul 24 08:19:24 PM PDT 24 |
Jul 24 08:23:12 PM PDT 24 |
3509702736 ps |
| T1099 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3477218061 |
|
|
Jul 24 08:17:51 PM PDT 24 |
Jul 24 08:25:59 PM PDT 24 |
4426969900 ps |
| T1100 |
/workspace/coverage/default/1.chip_sw_example_rom.2006340642 |
|
|
Jul 24 08:00:32 PM PDT 24 |
Jul 24 08:02:57 PM PDT 24 |
2975436344 ps |
| T1101 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2093980391 |
|
|
Jul 24 07:58:20 PM PDT 24 |
Jul 24 08:04:20 PM PDT 24 |
5841098168 ps |
| T181 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2785247163 |
|
|
Jul 24 07:59:34 PM PDT 24 |
Jul 24 08:11:29 PM PDT 24 |
6550802518 ps |
| T117 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.440643197 |
|
|
Jul 24 08:08:20 PM PDT 24 |
Jul 24 08:54:11 PM PDT 24 |
19847128233 ps |
| T154 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.3387071068 |
|
|
Jul 24 08:07:41 PM PDT 24 |
Jul 24 08:17:59 PM PDT 24 |
3460351084 ps |
| T1102 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2127589170 |
|
|
Jul 24 08:09:35 PM PDT 24 |
Jul 24 08:20:49 PM PDT 24 |
3956666232 ps |
| T1103 |
/workspace/coverage/default/0.rom_e2e_smoke.2483005315 |
|
|
Jul 24 08:05:26 PM PDT 24 |
Jul 24 09:10:04 PM PDT 24 |
14530647160 ps |
| T1104 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.2967493139 |
|
|
Jul 24 08:08:46 PM PDT 24 |
Jul 24 08:12:48 PM PDT 24 |
3226733976 ps |
| T1105 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.3295986932 |
|
|
Jul 24 08:20:14 PM PDT 24 |
Jul 24 08:32:28 PM PDT 24 |
4802615800 ps |
| T1106 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.451873409 |
|
|
Jul 24 08:25:17 PM PDT 24 |
Jul 24 08:31:11 PM PDT 24 |
3142993942 ps |
| T1107 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2381393568 |
|
|
Jul 24 08:12:06 PM PDT 24 |
Jul 24 08:39:34 PM PDT 24 |
13193809735 ps |
| T1108 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2865586286 |
|
|
Jul 24 08:05:48 PM PDT 24 |
Jul 24 09:16:09 PM PDT 24 |
15831013317 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.781610935 |
|
|
Jul 24 08:00:17 PM PDT 24 |
Jul 24 09:04:10 PM PDT 24 |
22836292447 ps |
| T1109 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.138888737 |
|
|
Jul 24 07:59:30 PM PDT 24 |
Jul 24 08:11:39 PM PDT 24 |
4699590680 ps |
| T1110 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1748222740 |
|
|
Jul 24 07:59:43 PM PDT 24 |
Jul 24 08:04:24 PM PDT 24 |
3270875409 ps |
| T376 |
/workspace/coverage/default/1.chip_sw_hmac_enc.3369909097 |
|
|
Jul 24 08:06:39 PM PDT 24 |
Jul 24 08:11:06 PM PDT 24 |
3385732636 ps |
| T1111 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2978598920 |
|
|
Jul 24 08:04:01 PM PDT 24 |
Jul 24 08:29:41 PM PDT 24 |
11522807841 ps |
| T228 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.67069663 |
|
|
Jul 24 08:03:38 PM PDT 24 |
Jul 24 08:34:35 PM PDT 24 |
9900760520 ps |
| T1112 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1852595521 |
|
|
Jul 24 07:58:11 PM PDT 24 |
Jul 24 08:32:35 PM PDT 24 |
10844650033 ps |
| T1113 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1588226417 |
|
|
Jul 24 08:25:06 PM PDT 24 |
Jul 24 08:31:10 PM PDT 24 |
3521044250 ps |
| T163 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.678544440 |
|
|
Jul 24 08:00:06 PM PDT 24 |
Jul 24 08:03:16 PM PDT 24 |
2048423520 ps |
| T1114 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.4150412330 |
|
|
Jul 24 08:05:30 PM PDT 24 |
Jul 24 09:07:58 PM PDT 24 |
14960235744 ps |
| T29 |
/workspace/coverage/default/1.chip_sw_gpio.342357448 |
|
|
Jul 24 08:01:51 PM PDT 24 |
Jul 24 08:10:03 PM PDT 24 |
4036755348 ps |
| T1115 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4281006769 |
|
|
Jul 24 08:02:26 PM PDT 24 |
Jul 24 08:13:48 PM PDT 24 |
5557193584 ps |
| T1116 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.4033086117 |
|
|
Jul 24 08:22:15 PM PDT 24 |
Jul 24 08:39:43 PM PDT 24 |
10154005392 ps |
| T454 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3303611703 |
|
|
Jul 24 08:21:18 PM PDT 24 |
Jul 24 08:36:32 PM PDT 24 |
5382487852 ps |
| T165 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2013467495 |
|
|
Jul 24 08:28:37 PM PDT 24 |
Jul 24 08:41:40 PM PDT 24 |
6385920358 ps |
| T255 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.1510506047 |
|
|
Jul 24 07:57:22 PM PDT 24 |
Jul 24 08:02:28 PM PDT 24 |
4846791532 ps |
| T843 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3085570277 |
|
|
Jul 24 08:28:25 PM PDT 24 |
Jul 24 08:39:00 PM PDT 24 |
6527152000 ps |
| T400 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1380060420 |
|
|
Jul 24 08:04:45 PM PDT 24 |
Jul 24 10:02:10 PM PDT 24 |
24732646280 ps |
| T1117 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3237521120 |
|
|
Jul 24 08:14:46 PM PDT 24 |
Jul 24 08:19:19 PM PDT 24 |
2236104877 ps |
| T1118 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.4145268469 |
|
|
Jul 24 08:12:48 PM PDT 24 |
Jul 24 09:16:27 PM PDT 24 |
15325747226 ps |
| T1119 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1060688007 |
|
|
Jul 24 07:57:34 PM PDT 24 |
Jul 24 08:13:53 PM PDT 24 |
4675968686 ps |
| T414 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3542059706 |
|
|
Jul 24 08:05:19 PM PDT 24 |
Jul 24 08:12:39 PM PDT 24 |
9646765727 ps |
| T869 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1972180315 |
|
|
Jul 24 08:37:00 PM PDT 24 |
Jul 24 08:45:37 PM PDT 24 |
4563208100 ps |