Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.00	95.37	93.66	95.41		94.47	97.53	99.54

Total test records in report: 2932

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T2763	/workspace/coverage/cover_reg_top/43.xbar_error_random.3009178494			Jul 24 07:40:34 PM PDT 24	Jul 24 07:40:42 PM PDT 24	70664158 ps
T2764	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.966533416			Jul 24 07:34:57 PM PDT 24	Jul 24 08:07:22 PM PDT 24	110186576992 ps
T2765	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2668954974			Jul 24 07:40:31 PM PDT 24	Jul 24 07:45:09 PM PDT 24	2851740111 ps
T2766	/workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.753249782			Jul 24 07:41:43 PM PDT 24	Jul 24 07:42:45 PM PDT 24	3654735785 ps
T2767	/workspace/coverage/cover_reg_top/74.xbar_same_source.3729510098			Jul 24 07:45:16 PM PDT 24	Jul 24 07:45:42 PM PDT 24	353559657 ps
T2768	/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3210026549			Jul 24 07:37:36 PM PDT 24	Jul 24 07:56:12 PM PDT 24	62077261459 ps
T2769	/workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3498342835			Jul 24 07:43:06 PM PDT 24	Jul 24 07:44:43 PM PDT 24	5639757237 ps
T2770	/workspace/coverage/cover_reg_top/91.xbar_same_source.3946319051			Jul 24 07:47:37 PM PDT 24	Jul 24 07:48:53 PM PDT 24	2483625890 ps
T2771	/workspace/coverage/cover_reg_top/43.xbar_same_source.3160172130			Jul 24 07:40:33 PM PDT 24	Jul 24 07:41:32 PM PDT 24	2079917690 ps
T2772	/workspace/coverage/cover_reg_top/37.xbar_same_source.3919398167			Jul 24 07:39:41 PM PDT 24	Jul 24 07:40:19 PM PDT 24	1242413943 ps
T2773	/workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3466395125			Jul 24 07:45:36 PM PDT 24	Jul 24 07:51:03 PM PDT 24	32586292348 ps
T2774	/workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.2866265836			Jul 24 07:48:30 PM PDT 24	Jul 24 07:49:59 PM PDT 24	8431315925 ps
T2775	/workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.861516574			Jul 24 07:38:48 PM PDT 24	Jul 24 07:38:57 PM PDT 24	64073263 ps
T2776	/workspace/coverage/cover_reg_top/90.xbar_stress_all.174431250			Jul 24 07:47:30 PM PDT 24	Jul 24 07:50:06 PM PDT 24	1660735939 ps
T2777	/workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.3180930836			Jul 24 07:37:39 PM PDT 24	Jul 24 07:53:52 PM PDT 24	61673589254 ps
T2778	/workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.869281191			Jul 24 07:45:08 PM PDT 24	Jul 24 07:50:29 PM PDT 24	18595750673 ps
T2779	/workspace/coverage/cover_reg_top/30.xbar_smoke.3085293103			Jul 24 07:38:22 PM PDT 24	Jul 24 07:38:28 PM PDT 24	41555962 ps
T2780	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.1719989523			Jul 24 07:35:53 PM PDT 24	Jul 24 08:02:07 PM PDT 24	14564156985 ps
T2781	/workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2857788971			Jul 24 07:39:57 PM PDT 24	Jul 24 07:40:03 PM PDT 24	38548535 ps
T2782	/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3361604150			Jul 24 07:34:57 PM PDT 24	Jul 24 07:35:47 PM PDT 24	1239680757 ps
T2783	/workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2863687786			Jul 24 07:46:59 PM PDT 24	Jul 24 08:22:06 PM PDT 24	113418499235 ps
T2784	/workspace/coverage/cover_reg_top/26.xbar_same_source.4125660112			Jul 24 07:37:52 PM PDT 24	Jul 24 07:38:07 PM PDT 24	187672858 ps
T2785	/workspace/coverage/cover_reg_top/82.xbar_random_large_delays.1051477747			Jul 24 07:46:35 PM PDT 24	Jul 24 07:57:39 PM PDT 24	65640478038 ps
T2786	/workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2094091963			Jul 24 07:45:52 PM PDT 24	Jul 24 07:47:19 PM PDT 24	8102555071 ps
T2787	/workspace/coverage/cover_reg_top/79.xbar_error_random.2865057551			Jul 24 07:45:57 PM PDT 24	Jul 24 07:46:44 PM PDT 24	1469372582 ps
T2788	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1193613635			Jul 24 07:44:18 PM PDT 24	Jul 24 07:49:14 PM PDT 24	3301073831 ps
T2789	/workspace/coverage/cover_reg_top/91.xbar_stress_all.2488777478			Jul 24 07:50:01 PM PDT 24	Jul 24 07:51:55 PM PDT 24	3008992930 ps
T2790	/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1683639428			Jul 24 07:34:18 PM PDT 24	Jul 24 08:36:57 PM PDT 24	27490291198 ps
T2791	/workspace/coverage/cover_reg_top/80.xbar_same_source.2511982848			Jul 24 07:46:04 PM PDT 24	Jul 24 07:46:55 PM PDT 24	1772053796 ps
T2792	/workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.1922470855			Jul 24 07:43:09 PM PDT 24	Jul 24 07:44:27 PM PDT 24	7137175956 ps
T2793	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.4100593347			Jul 24 07:41:11 PM PDT 24	Jul 24 07:43:30 PM PDT 24	1484063693 ps
T2794	/workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.2227888273			Jul 24 07:39:58 PM PDT 24	Jul 24 07:40:12 PM PDT 24	377014380 ps
T2795	/workspace/coverage/cover_reg_top/34.xbar_access_same_device.1928133192			Jul 24 07:39:08 PM PDT 24	Jul 24 07:39:16 PM PDT 24	79253791 ps
T2796	/workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.2979428065			Jul 24 07:43:09 PM PDT 24	Jul 24 07:43:45 PM PDT 24	305838495 ps
T2797	/workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3905595937			Jul 24 07:44:50 PM PDT 24	Jul 24 07:44:57 PM PDT 24	48424559 ps
T2798	/workspace/coverage/cover_reg_top/89.xbar_stress_all.846867729			Jul 24 07:47:20 PM PDT 24	Jul 24 07:54:42 PM PDT 24	11159880185 ps
T2799	/workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.2815821478			Jul 24 07:41:14 PM PDT 24	Jul 24 07:41:21 PM PDT 24	74490628 ps
T2800	/workspace/coverage/cover_reg_top/92.xbar_random.3396562401			Jul 24 07:47:39 PM PDT 24	Jul 24 07:48:07 PM PDT 24	664728908 ps
T2801	/workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.2291567933			Jul 24 07:40:19 PM PDT 24	Jul 24 07:56:27 PM PDT 24	51916237710 ps
T2802	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.84042028			Jul 24 07:41:43 PM PDT 24	Jul 24 07:42:38 PM PDT 24	662467351 ps
T2803	/workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2511810814			Jul 24 07:38:14 PM PDT 24	Jul 24 08:07:48 PM PDT 24	96259064860 ps
T2804	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.1341805774			Jul 24 07:33:18 PM PDT 24	Jul 24 07:44:25 PM PDT 24	17962751698 ps
T2805	/workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3967948982			Jul 24 07:33:41 PM PDT 24	Jul 24 07:34:59 PM PDT 24	8001940847 ps
T2806	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3239722691			Jul 24 07:32:42 PM PDT 24	Jul 24 07:53:34 PM PDT 24	70600801215 ps
T2807	/workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.1897287937			Jul 24 07:45:36 PM PDT 24	Jul 24 07:47:13 PM PDT 24	10030606394 ps
T2808	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.269595914			Jul 24 07:46:50 PM PDT 24	Jul 24 07:56:22 PM PDT 24	15321773428 ps
T2809	/workspace/coverage/cover_reg_top/25.xbar_stress_all.1730710820			Jul 24 07:37:46 PM PDT 24	Jul 24 07:51:10 PM PDT 24	21753967577 ps
T2810	/workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1834578231			Jul 24 07:43:57 PM PDT 24	Jul 24 07:51:44 PM PDT 24	29270373878 ps
T2811	/workspace/coverage/cover_reg_top/25.xbar_error_random.1881634503			Jul 24 07:37:53 PM PDT 24	Jul 24 07:38:07 PM PDT 24	159181785 ps
T2812	/workspace/coverage/cover_reg_top/63.xbar_smoke.535285183			Jul 24 07:43:41 PM PDT 24	Jul 24 07:43:47 PM PDT 24	45493373 ps
T2813	/workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2036690284			Jul 24 07:44:42 PM PDT 24	Jul 24 07:44:53 PM PDT 24	75058229 ps
T2814	/workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.577583529			Jul 24 07:47:44 PM PDT 24	Jul 24 07:49:06 PM PDT 24	7986344630 ps
T2815	/workspace/coverage/cover_reg_top/28.xbar_smoke.1286876466			Jul 24 07:38:11 PM PDT 24	Jul 24 07:38:18 PM PDT 24	41656370 ps
T2816	/workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1756870577			Jul 24 07:44:33 PM PDT 24	Jul 24 07:46:01 PM PDT 24	4979751591 ps
T2817	/workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.326926054			Jul 24 07:47:37 PM PDT 24	Jul 24 07:48:03 PM PDT 24	307594169 ps
T2818	/workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.3911561808			Jul 24 07:45:07 PM PDT 24	Jul 24 07:46:37 PM PDT 24	8171433134 ps
T2819	/workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.2313432952			Jul 24 07:43:45 PM PDT 24	Jul 24 07:44:05 PM PDT 24	183743973 ps
T2820	/workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1210015652			Jul 24 07:38:03 PM PDT 24	Jul 24 07:49:46 PM PDT 24	41664206655 ps
T2821	/workspace/coverage/cover_reg_top/78.xbar_same_source.924547898			Jul 24 07:45:46 PM PDT 24	Jul 24 07:46:16 PM PDT 24	930849868 ps
T2822	/workspace/coverage/cover_reg_top/32.xbar_stress_all.3539241250			Jul 24 07:38:46 PM PDT 24	Jul 24 07:41:52 PM PDT 24	2337556426 ps
T2823	/workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3368987261			Jul 24 07:41:37 PM PDT 24	Jul 24 07:50:37 PM PDT 24	50409585900 ps
T2824	/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3076251604			Jul 24 07:34:50 PM PDT 24	Jul 24 07:35:47 PM PDT 24	5594890113 ps
T2825	/workspace/coverage/cover_reg_top/86.xbar_smoke.1766206567			Jul 24 07:46:52 PM PDT 24	Jul 24 07:47:03 PM PDT 24	268790995 ps
T2826	/workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.1714895563			Jul 24 07:33:18 PM PDT 24	Jul 24 07:33:25 PM PDT 24	41609717 ps
T2827	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1410406980			Jul 24 07:39:27 PM PDT 24	Jul 24 08:02:43 PM PDT 24	80746053376 ps
T2828	/workspace/coverage/cover_reg_top/70.xbar_stress_all.1446328602			Jul 24 07:44:45 PM PDT 24	Jul 24 07:48:19 PM PDT 24	6450924351 ps
T2829	/workspace/coverage/cover_reg_top/83.xbar_smoke.1080077450			Jul 24 07:46:24 PM PDT 24	Jul 24 07:46:31 PM PDT 24	48364088 ps
T2830	/workspace/coverage/cover_reg_top/2.xbar_smoke.1705115594			Jul 24 07:33:01 PM PDT 24	Jul 24 07:33:06 PM PDT 24	41384100 ps
T2831	/workspace/coverage/cover_reg_top/92.xbar_random_large_delays.524268534			Jul 24 07:47:39 PM PDT 24	Jul 24 08:07:02 PM PDT 24	94775440601 ps
T2832	/workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3478032812			Jul 24 07:44:46 PM PDT 24	Jul 24 08:15:47 PM PDT 24	100581389348 ps
T2833	/workspace/coverage/cover_reg_top/22.xbar_access_same_device.2236790538			Jul 24 07:36:32 PM PDT 24	Jul 24 07:37:39 PM PDT 24	635838160 ps
T2834	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2995905631			Jul 24 07:35:00 PM PDT 24	Jul 24 07:37:57 PM PDT 24	2249112314 ps
T2835	/workspace/coverage/cover_reg_top/36.xbar_access_same_device.3419681116			Jul 24 07:39:28 PM PDT 24	Jul 24 07:40:31 PM PDT 24	705469608 ps
T2836	/workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3988076032			Jul 24 07:39:56 PM PDT 24	Jul 24 07:40:05 PM PDT 24	140459223 ps
T2837	/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.42614168			Jul 24 07:34:42 PM PDT 24	Jul 24 07:36:05 PM PDT 24	4812390787 ps
T2838	/workspace/coverage/cover_reg_top/3.xbar_smoke.817532272			Jul 24 07:33:12 PM PDT 24	Jul 24 07:33:22 PM PDT 24	235055337 ps
T2839	/workspace/coverage/cover_reg_top/46.xbar_access_same_device.1079670263			Jul 24 07:41:18 PM PDT 24	Jul 24 07:42:32 PM PDT 24	1738541769 ps
T2840	/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.782042718			Jul 24 07:35:45 PM PDT 24	Jul 24 07:48:49 PM PDT 24	45808826198 ps
T2841	/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3637915127			Jul 24 07:35:09 PM PDT 24	Jul 24 07:41:30 PM PDT 24	23253146316 ps
T2842	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.895306171			Jul 24 07:45:35 PM PDT 24	Jul 24 07:48:52 PM PDT 24	4180808323 ps
T2843	/workspace/coverage/cover_reg_top/33.xbar_random.4265579825			Jul 24 07:38:52 PM PDT 24	Jul 24 07:39:12 PM PDT 24	520028526 ps
T2844	/workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.2090574707			Jul 24 07:39:34 PM PDT 24	Jul 24 07:50:02 PM PDT 24	39346398011 ps
T2845	/workspace/coverage/cover_reg_top/73.xbar_access_same_device.3898573337			Jul 24 07:45:06 PM PDT 24	Jul 24 07:45:52 PM PDT 24	579040349 ps
T2846	/workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1661972490			Jul 24 07:40:32 PM PDT 24	Jul 24 07:40:38 PM PDT 24	33431175 ps
T2847	/workspace/coverage/cover_reg_top/42.xbar_error_random.825669696			Jul 24 07:40:14 PM PDT 24	Jul 24 07:41:09 PM PDT 24	1767127298 ps
T2848	/workspace/coverage/cover_reg_top/8.xbar_random_large_delays.1181605027			Jul 24 07:34:16 PM PDT 24	Jul 24 07:43:54 PM PDT 24	50823064940 ps
T2849	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.1881959973			Jul 24 07:48:23 PM PDT 24	Jul 24 07:48:38 PM PDT 24	8882050 ps
T2850	/workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2884413377			Jul 24 07:36:13 PM PDT 24	Jul 24 07:37:06 PM PDT 24	2931401609 ps
T2851	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2588967254			Jul 24 07:39:08 PM PDT 24	Jul 24 07:44:23 PM PDT 24	2534020425 ps
T2852	/workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1732530442			Jul 24 07:38:39 PM PDT 24	Jul 24 08:13:36 PM PDT 24	110595799656 ps
T2853	/workspace/coverage/cover_reg_top/62.xbar_random.341812626			Jul 24 07:43:34 PM PDT 24	Jul 24 07:44:56 PM PDT 24	2350119383 ps
T2854	/workspace/coverage/cover_reg_top/61.xbar_random_large_delays.565717337			Jul 24 07:43:14 PM PDT 24	Jul 24 07:51:10 PM PDT 24	46173294555 ps
T2855	/workspace/coverage/cover_reg_top/54.xbar_same_source.2603529717			Jul 24 07:42:22 PM PDT 24	Jul 24 07:42:32 PM PDT 24	75383808 ps
T2856	/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3787455068			Jul 24 07:34:29 PM PDT 24	Jul 24 07:34:42 PM PDT 24	125044739 ps
T2857	/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.440507711			Jul 24 07:32:57 PM PDT 24	Jul 24 07:33:06 PM PDT 24	54814183 ps
T2858	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.4050997215			Jul 24 07:41:43 PM PDT 24	Jul 24 07:42:02 PM PDT 24	22477994 ps
T2859	/workspace/coverage/cover_reg_top/83.xbar_random_large_delays.2401278330			Jul 24 07:46:20 PM PDT 24	Jul 24 07:55:05 PM PDT 24	47560103661 ps
T796	/workspace/coverage/cover_reg_top/7.chip_tl_errors.1549713849			Jul 24 07:33:58 PM PDT 24	Jul 24 07:39:00 PM PDT 24	3955687296 ps
T2860	/workspace/coverage/cover_reg_top/78.xbar_error_random.2494977541			Jul 24 07:45:50 PM PDT 24	Jul 24 07:46:46 PM PDT 24	1854305099 ps
T2861	/workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.1761844896			Jul 24 07:42:24 PM PDT 24	Jul 24 07:49:57 PM PDT 24	26806668195 ps
T2862	/workspace/coverage/cover_reg_top/59.xbar_stress_all.3864401128			Jul 24 07:43:10 PM PDT 24	Jul 24 07:46:53 PM PDT 24	2547798029 ps
T2863	/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2957539317			Jul 24 07:32:25 PM PDT 24	Jul 24 07:33:50 PM PDT 24	8424938087 ps
T2864	/workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.1431362065			Jul 24 07:37:40 PM PDT 24	Jul 24 07:39:21 PM PDT 24	9038614294 ps
T2865	/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1352153801			Jul 24 07:34:09 PM PDT 24	Jul 24 07:34:34 PM PDT 24	263666241 ps
T2866	/workspace/coverage/cover_reg_top/48.xbar_random.2299419549			Jul 24 07:41:31 PM PDT 24	Jul 24 07:42:06 PM PDT 24	898346994 ps
T2867	/workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.739994692			Jul 24 07:47:38 PM PDT 24	Jul 24 07:49:31 PM PDT 24	6625369348 ps
T750	/workspace/coverage/cover_reg_top/22.chip_tl_errors.1609241057			Jul 24 07:36:41 PM PDT 24	Jul 24 07:42:45 PM PDT 24	4454906220 ps
T2868	/workspace/coverage/cover_reg_top/18.chip_csr_rw.4127314446			Jul 24 07:35:55 PM PDT 24	Jul 24 07:41:48 PM PDT 24	4372007020 ps
T2869	/workspace/coverage/cover_reg_top/9.xbar_stress_all.2481094057			Jul 24 07:34:09 PM PDT 24	Jul 24 07:34:43 PM PDT 24	881511984 ps
T2870	/workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1525323177			Jul 24 07:41:39 PM PDT 24	Jul 24 07:43:17 PM PDT 24	5765580510 ps
T2871	/workspace/coverage/cover_reg_top/90.xbar_random.2625273574			Jul 24 07:47:31 PM PDT 24	Jul 24 07:47:42 PM PDT 24	211846211 ps
T2872	/workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.399877762			Jul 24 07:48:30 PM PDT 24	Jul 24 07:49:45 PM PDT 24	7134041251 ps
T2873	/workspace/coverage/cover_reg_top/15.xbar_random.3229719895			Jul 24 07:35:10 PM PDT 24	Jul 24 07:36:10 PM PDT 24	1794038690 ps
T2874	/workspace/coverage/cover_reg_top/67.xbar_random_large_delays.1017858596			Jul 24 07:44:13 PM PDT 24	Jul 24 07:49:31 PM PDT 24	30441939860 ps
T2875	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.347444693			Jul 24 07:44:25 PM PDT 24	Jul 24 07:54:01 PM PDT 24	15325958224 ps
T2876	/workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3212813656			Jul 24 07:36:19 PM PDT 24	Jul 24 07:50:23 PM PDT 24	78167165458 ps
T2877	/workspace/coverage/cover_reg_top/19.xbar_smoke.3505709323			Jul 24 07:35:53 PM PDT 24	Jul 24 07:36:03 PM PDT 24	216825168 ps
T2878	/workspace/coverage/cover_reg_top/32.xbar_random_large_delays.3167626689			Jul 24 07:38:40 PM PDT 24	Jul 24 07:56:50 PM PDT 24	100471168563 ps
T2879	/workspace/coverage/cover_reg_top/41.xbar_error_random.2554897071			Jul 24 07:40:06 PM PDT 24	Jul 24 07:40:23 PM PDT 24	189673885 ps
T2880	/workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2575832056			Jul 24 07:39:58 PM PDT 24	Jul 24 07:41:01 PM PDT 24	6196146206 ps
T2881	/workspace/coverage/cover_reg_top/64.xbar_error_random.230298824			Jul 24 07:43:52 PM PDT 24	Jul 24 07:44:41 PM PDT 24	613975323 ps
T2882	/workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3726659116			Jul 24 07:39:38 PM PDT 24	Jul 24 08:17:28 PM PDT 24	117594089735 ps
T2883	/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.29031642			Jul 24 07:34:08 PM PDT 24	Jul 24 07:35:42 PM PDT 24	9170493824 ps
T2884	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.123070383			Jul 24 07:46:24 PM PDT 24	Jul 24 07:47:25 PM PDT 24	1596452551 ps
T2885	/workspace/coverage/cover_reg_top/18.xbar_stress_all.2582216280			Jul 24 07:35:56 PM PDT 24	Jul 24 07:38:52 PM PDT 24	2357049458 ps
T2886	/workspace/coverage/cover_reg_top/41.xbar_same_source.1632421154			Jul 24 07:40:05 PM PDT 24	Jul 24 07:40:47 PM PDT 24	1448417362 ps
T2887	/workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.299232160			Jul 24 07:48:53 PM PDT 24	Jul 24 07:49:31 PM PDT 24	415889672 ps
T2888	/workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.4292829376			Jul 24 07:37:53 PM PDT 24	Jul 24 07:38:16 PM PDT 24	280799236 ps
T2889	/workspace/coverage/cover_reg_top/26.xbar_access_same_device.4125819310			Jul 24 07:37:48 PM PDT 24	Jul 24 07:38:05 PM PDT 24	133296414 ps
T2890	/workspace/coverage/cover_reg_top/99.xbar_stress_all.838234747			Jul 24 07:48:56 PM PDT 24	Jul 24 07:49:57 PM PDT 24	1853402495 ps
T2891	/workspace/coverage/cover_reg_top/19.chip_tl_errors.1227106496			Jul 24 07:35:52 PM PDT 24	Jul 24 07:39:41 PM PDT 24	3751023064 ps
T2892	/workspace/coverage/cover_reg_top/96.xbar_random_large_delays.991470977			Jul 24 07:48:23 PM PDT 24	Jul 24 07:52:43 PM PDT 24	24430524477 ps
T2893	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2132725507			Jul 24 07:37:46 PM PDT 24	Jul 24 07:42:59 PM PDT 24	9454648628 ps
T2894	/workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.3980721080			Jul 24 07:46:49 PM PDT 24	Jul 24 07:48:23 PM PDT 24	8973273495 ps
T2895	/workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.3126749748			Jul 24 07:47:44 PM PDT 24	Jul 24 07:48:05 PM PDT 24	184904771 ps
T2896	/workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.179943168			Jul 24 07:39:40 PM PDT 24	Jul 24 07:40:27 PM PDT 24	544909710 ps
T2897	/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1758866072			Jul 24 07:34:30 PM PDT 24	Jul 24 07:34:42 PM PDT 24	235885408 ps
T2898	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.871455234			Jul 24 07:38:59 PM PDT 24	Jul 24 07:48:17 PM PDT 24	9874851026 ps
T2899	/workspace/coverage/cover_reg_top/14.xbar_error_random.2754546432			Jul 24 07:35:02 PM PDT 24	Jul 24 07:35:38 PM PDT 24	940826205 ps
T2900	/workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1721988097			Jul 24 07:41:21 PM PDT 24	Jul 24 08:00:33 PM PDT 24	61087092177 ps
T2901	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.4193781933			Jul 24 07:38:25 PM PDT 24	Jul 24 07:43:07 PM PDT 24	6691841167 ps
T2902	/workspace/coverage/cover_reg_top/61.xbar_smoke.3927348417			Jul 24 07:43:14 PM PDT 24	Jul 24 07:43:20 PM PDT 24	54714762 ps
T2903	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.122783431			Jul 24 07:32:30 PM PDT 24	Jul 24 07:38:39 PM PDT 24	6761120901 ps
T2904	/workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1575296823			Jul 24 07:41:32 PM PDT 24	Jul 24 07:42:59 PM PDT 24	8489775221 ps
T2905	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2366237095			Jul 24 07:45:45 PM PDT 24	Jul 24 07:46:12 PM PDT 24	110667841 ps
T2906	/workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.4074205683			Jul 24 07:38:11 PM PDT 24	Jul 24 07:39:40 PM PDT 24	5312799859 ps
T2907	/workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.922038795			Jul 24 07:32:51 PM PDT 24	Jul 24 08:56:19 PM PDT 24	43736842600 ps
T2908	/workspace/coverage/cover_reg_top/29.xbar_error_random.1715287729			Jul 24 07:38:15 PM PDT 24	Jul 24 07:38:32 PM PDT 24	155539829 ps
T2909	/workspace/coverage/cover_reg_top/66.xbar_same_source.1425675080			Jul 24 07:44:10 PM PDT 24	Jul 24 07:44:22 PM PDT 24	150041508 ps
T2910	/workspace/coverage/cover_reg_top/99.xbar_error_random.4056254358			Jul 24 07:48:50 PM PDT 24	Jul 24 07:49:03 PM PDT 24	281851049 ps
T2911	/workspace/coverage/cover_reg_top/18.xbar_access_same_device.2010511443			Jul 24 07:35:57 PM PDT 24	Jul 24 07:36:39 PM PDT 24	414648910 ps
T2912	/workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.748492643			Jul 24 07:40:25 PM PDT 24	Jul 24 07:40:54 PM PDT 24	652817210 ps
T2913	/workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.1627423581			Jul 24 07:43:54 PM PDT 24	Jul 24 07:45:16 PM PDT 24	8588602348 ps
T2914	/workspace/coverage/cover_reg_top/3.xbar_error_random.2317644035			Jul 24 07:32:56 PM PDT 24	Jul 24 07:33:19 PM PDT 24	246051900 ps
T2915	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.2408544246			Jul 24 07:45:54 PM PDT 24	Jul 24 07:46:46 PM PDT 24	675609052 ps
T2916	/workspace/coverage/cover_reg_top/54.xbar_random.3019488440			Jul 24 07:42:25 PM PDT 24	Jul 24 07:43:38 PM PDT 24	1804238271 ps
T2917	/workspace/coverage/cover_reg_top/70.xbar_smoke.620383462			Jul 24 07:44:34 PM PDT 24	Jul 24 07:44:41 PM PDT 24	52156392 ps
T2918	/workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.2807192010			Jul 24 07:36:12 PM PDT 24	Jul 24 07:36:42 PM PDT 24	292371317 ps
T2919	/workspace/coverage/cover_reg_top/34.xbar_random.184687624			Jul 24 07:38:58 PM PDT 24	Jul 24 07:39:39 PM PDT 24	1338433765 ps
T2920	/workspace/coverage/cover_reg_top/86.xbar_same_source.2480452938			Jul 24 07:46:59 PM PDT 24	Jul 24 07:48:03 PM PDT 24	2220095199 ps
T2921	/workspace/coverage/cover_reg_top/55.xbar_same_source.2118313397			Jul 24 07:42:32 PM PDT 24	Jul 24 07:43:11 PM PDT 24	1232391216 ps
T2922	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3137571204			Jul 24 07:38:03 PM PDT 24	Jul 24 07:38:49 PM PDT 24	174103037 ps
T2923	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1462329155			Jul 24 07:41:26 PM PDT 24	Jul 24 07:43:04 PM PDT 24	272253912 ps
T2924	/workspace/coverage/cover_reg_top/34.xbar_same_source.441973940			Jul 24 07:39:08 PM PDT 24	Jul 24 07:39:18 PM PDT 24	86565615 ps
T2925	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3812101592			Jul 24 07:47:05 PM PDT 24	Jul 24 07:52:30 PM PDT 24	2332231227 ps
T2926	/workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2981976432			Jul 24 07:33:14 PM PDT 24	Jul 24 07:34:40 PM PDT 24	5261721274 ps
T2927	/workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.672617419			Jul 24 07:33:03 PM PDT 24	Jul 24 07:33:11 PM PDT 24	57577708 ps
T2928	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2378890797			Jul 24 07:47:13 PM PDT 24	Jul 24 07:59:06 PM PDT 24	11723873998 ps
T2929	/workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.1364206342			Jul 24 07:43:00 PM PDT 24	Jul 24 07:43:09 PM PDT 24	57504348 ps
T2930	/workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.610131421			Jul 24 07:41:36 PM PDT 24	Jul 24 07:42:43 PM PDT 24	4048612710 ps
T2931	/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1115581434			Jul 24 07:34:17 PM PDT 24	Jul 24 07:35:06 PM PDT 24	519031713 ps
T2932	/workspace/coverage/cover_reg_top/62.xbar_stress_all.2333575492			Jul 24 07:43:41 PM PDT 24	Jul 24 07:43:56 PM PDT 24	197578333 ps
T30	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2193680787			Jul 24 07:32:16 PM PDT 24	Jul 24 07:36:25 PM PDT 24	5678434263 ps
T31	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1177625858			Jul 24 07:32:26 PM PDT 24	Jul 24 07:36:51 PM PDT 24	4660146344 ps
T32	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2908096363			Jul 24 07:32:22 PM PDT 24	Jul 24 07:36:21 PM PDT 24	4700034104 ps
T187	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1880958590			Jul 24 07:32:26 PM PDT 24	Jul 24 07:37:47 PM PDT 24	4849315856 ps
T188	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2407973051			Jul 24 07:32:12 PM PDT 24	Jul 24 07:36:39 PM PDT 24	6076629360 ps
T189	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2962213063			Jul 24 07:32:21 PM PDT 24	Jul 24 07:35:54 PM PDT 24	4982679632 ps
T190	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.725934641			Jul 24 07:32:22 PM PDT 24	Jul 24 07:37:13 PM PDT 24	5552620976 ps
T191	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.174428050			Jul 24 07:32:26 PM PDT 24	Jul 24 07:36:23 PM PDT 24	5261410312 ps
T192	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2640838707			Jul 24 07:32:22 PM PDT 24	Jul 24 07:37:06 PM PDT 24	4572684401 ps
T193	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3368976498			Jul 24 07:32:26 PM PDT 24	Jul 24 07:36:53 PM PDT 24	5335617624 ps

---

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.269987485
Short name	T33
Test name
Test status
Simulation time	5621903000 ps
CPU time	914.28 seconds
Started	Jul 24 07:59:40 PM PDT 24
Finished	Jul 24 08:14:55 PM PDT 24
Peak memory	611612 kb
Host	smart-854e883b-aa5a-49e3-ac9c-f6bd7248448c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269987 485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.269987485
Directory	/workspace/0.chip_sw_keymgr_sideload_aes/latest

---

Test location	/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.764169132
Short name	T395
Test name
Test status
Simulation time	8390542100 ps
CPU time	504.87 seconds
Started	Jul 24 07:34:09 PM PDT 24
Finished	Jul 24 07:42:34 PM PDT 24
Peak memory	641464 kb
Host	smart-dc243707-0251-4483-a3d3-6094c9972d7a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764169132 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.764169132
Directory	/workspace/10.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_0.1837814405
Short name	T259
Test name
Test status
Simulation time	6090649312 ps
CPU time	1231.28 seconds
Started	Jul 24 08:05:22 PM PDT 24
Finished	Jul 24 08:25:53 PM PDT 24
Peak memory	609752 kb
Host	smart-8077af87-9513-4be2-bf8c-2e683e9b8a50
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837814405 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.1837814405
Directory	/workspace/1.chip_plic_all_irqs_0/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1123710518
Short name	T438
Test name
Test status
Simulation time	104578085338 ps
CPU time	1870.35 seconds
Started	Jul 24 07:40:41 PM PDT 24
Finished	Jul 24 08:11:52 PM PDT 24
Peak memory	577288 kb
Host	smart-23838b5e-fe37-4fab-8093-cc50a77639e5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123710518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.1123710518
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3618899120
Short name	T9
Test name
Test status
Simulation time	3343789628 ps
CPU time	305.82 seconds
Started	Jul 24 08:01:43 PM PDT 24
Finished	Jul 24 08:06:49 PM PDT 24
Peak memory	610880 kb
Host	smart-5f57ef50-b34f-44bc-9811-38c5622ff4ea
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618 899120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.3618899120
Directory	/workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

---

Test location	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2193680787
Short name	T30
Test name
Test status
Simulation time	5678434263 ps
CPU time	248.98 seconds
Started	Jul 24 07:32:16 PM PDT 24
Finished	Jul 24 07:36:25 PM PDT 24
Peak memory	641300 kb
Host	smart-ac728c3c-317e-4bf4-9bd0-a903db9193c1
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193680787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.2193680787
Directory	/workspace/6.chip_padctrl_attributes/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_error_random.4240703269
Short name	T79
Test name
Test status
Simulation time	343211456 ps
CPU time	28.86 seconds
Started	Jul 24 07:46:03 PM PDT 24
Finished	Jul 24 07:46:32 PM PDT 24
Peak memory	576988 kb
Host	smart-025169f5-5923-4662-bec3-e61e79f14e20
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240703269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.4240703269
Directory	/workspace/80.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2810942248
Short name	T921
Test name
Test status
Simulation time	133339009004 ps
CPU time	2444.07 seconds
Started	Jul 24 07:46:11 PM PDT 24
Finished	Jul 24 08:26:56 PM PDT 24
Peak memory	576356 kb
Host	smart-2c9df701-f26f-4377-8bb7-4bc86aa2aa73
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810942248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.2810942248
Directory	/workspace/77.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2782897716
Short name	T897
Test name
Test status
Simulation time	58581368230 ps
CPU time	906.46 seconds
Started	Jul 24 07:41:31 PM PDT 24
Finished	Jul 24 07:56:38 PM PDT 24
Peak memory	576396 kb
Host	smart-f5525bce-0495-447a-8bde-edf900a00b54
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782897716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.2782897716
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4157935131
Short name	T48
Test name
Test status
Simulation time	15079128314 ps
CPU time	3379.87 seconds
Started	Jul 24 08:24:11 PM PDT 24
Finished	Jul 24 09:20:31 PM PDT 24
Peak memory	610760 kb
Host	smart-34290c87-c453-421f-a368-80db05bb2dcf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157935131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.4157935131
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.899700719
Short name	T895
Test name
Test status
Simulation time	96204454974 ps
CPU time	1776.95 seconds
Started	Jul 24 07:46:15 PM PDT 24
Finished	Jul 24 08:15:52 PM PDT 24
Peak memory	577288 kb
Host	smart-738c0a3f-fe99-470d-9ddd-d20ff15e28e4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899700719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_d evice_slow_rsp.899700719
Directory	/workspace/81.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.630565333
Short name	T66
Test name
Test status
Simulation time	48468033240 ps
CPU time	6165.45 seconds
Started	Jul 24 08:04:39 PM PDT 24
Finished	Jul 24 09:47:25 PM PDT 24
Peak memory	619848 kb
Host	smart-2b60bf5c-24be-46d3-b7c1-31de37b24a26
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630565333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_dev.630565333
Directory	/workspace/1.chip_sw_lc_walkthrough_dev/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.2846019804
Short name	T464
Test name
Test status
Simulation time	8899345374 ps
CPU time	592.4 seconds
Started	Jul 24 07:43:25 PM PDT 24
Finished	Jul 24 07:53:18 PM PDT 24
Peak memory	576452 kb
Host	smart-36a5532a-a946-4893-8493-0e06cf9efdfe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846019804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.2846019804
Directory	/workspace/61.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_access_same_device.2684633770
Short name	T74
Test name
Test status
Simulation time	856361600 ps
CPU time	67.8 seconds
Started	Jul 24 07:44:11 PM PDT 24
Finished	Jul 24 07:45:19 PM PDT 24
Peak memory	577036 kb
Host	smart-d228d3d5-035a-4cd1-bd8f-6feeabbbf086
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684633770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2684633770
Directory	/workspace/66.xbar_access_same_device/latest

---

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4061764057
Short name	T115
Test name
Test status
Simulation time	22553953991 ps
CPU time	2768.54 seconds
Started	Jul 24 08:26:05 PM PDT 24
Finished	Jul 24 09:12:14 PM PDT 24
Peak memory	611044 kb
Host	smart-869e6b9e-757b-4ee2-9cb0-8c137dee9a7a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061764057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.4061764057
Directory	/workspace/2.chip_sw_ast_clk_rst_inputs/latest

---

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_20.1550643016
Short name	T327
Test name
Test status
Simulation time	4793274328 ps
CPU time	808.21 seconds
Started	Jul 24 08:15:38 PM PDT 24
Finished	Jul 24 08:29:07 PM PDT 24
Peak memory	609732 kb
Host	smart-241515ff-9ded-444d-8eb7-4dbba57730dd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550643016 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.1550643016
Directory	/workspace/2.chip_plic_all_irqs_20/latest

---

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1696340109
Short name	T81
Test name
Test status
Simulation time	10419375408 ps
CPU time	1347.7 seconds
Started	Jul 24 07:59:45 PM PDT 24
Finished	Jul 24 08:22:13 PM PDT 24
Peak memory	610972 kb
Host	smart-1c3739e5-cd11-467c-a614-c0ba946ef35f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696340109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.1696340109
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.495956573
Short name	T179
Test name
Test status
Simulation time	2800540284 ps
CPU time	256.35 seconds
Started	Jul 24 08:17:38 PM PDT 24
Finished	Jul 24 08:21:55 PM PDT 24
Peak memory	610268 kb
Host	smart-885e99da-2337-4060-a3c0-2dfad29cd654
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=495956573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.495956573
Directory	/workspace/2.chip_sw_rv_core_ibex_address_translation/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.587919109
Short name	T27
Test name
Test status
Simulation time	4261673814 ps
CPU time	421.74 seconds
Started	Jul 24 08:10:48 PM PDT 24
Finished	Jul 24 08:17:50 PM PDT 24
Peak memory	610552 kb
Host	smart-6b8ea4ff-ad81-493f-b6e6-86ab03312553
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587919109 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.587919109
Directory	/workspace/2.chip_sw_sleep_pin_retention/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2673264235
Short name	T1647
Test name
Test status
Simulation time	32784037218 ps
CPU time	573.88 seconds
Started	Jul 24 07:34:08 PM PDT 24
Finished	Jul 24 07:43:42 PM PDT 24
Peak memory	577180 kb
Host	smart-57ad9f9d-f352-463b-8c6b-5bb371b4d4d8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673264235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.2673264235
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all.3441483285
Short name	T398
Test name
Test status
Simulation time	9055570687 ps
CPU time	307.69 seconds
Started	Jul 24 07:39:41 PM PDT 24
Finished	Jul 24 07:44:49 PM PDT 24
Peak memory	576440 kb
Host	smart-d99808ce-9c32-48c1-9dc0-25920b8df814
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441483285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3441483285
Directory	/workspace/38.xbar_stress_all/latest

---

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_10.2427809037
Short name	T153
Test name
Test status
Simulation time	3810220644 ps
CPU time	565.87 seconds
Started	Jul 24 08:08:24 PM PDT 24
Finished	Jul 24 08:17:50 PM PDT 24
Peak memory	609784 kb
Host	smart-c28840bf-eedd-41bc-b29d-6accba34ad35
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427809037 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.2427809037
Directory	/workspace/0.chip_plic_all_irqs_10/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.600041267
Short name	T906
Test name
Test status
Simulation time	66128685824 ps
CPU time	1176.29 seconds
Started	Jul 24 07:39:09 PM PDT 24
Finished	Jul 24 07:58:46 PM PDT 24
Peak memory	577152 kb
Host	smart-0e8be821-812c-4555-80cb-09da44341e93
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600041267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_d evice_slow_rsp.600041267
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.16061593
Short name	T418
Test name
Test status
Simulation time	30635688860 ps
CPU time	4012.53 seconds
Started	Jul 24 07:33:41 PM PDT 24
Finished	Jul 24 08:40:34 PM PDT 24
Peak memory	594180 kb
Host	smart-6199d238-af0e-4c32-8a60-b9cbce47e3d4
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16061593 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.chip_same_csr_outstanding.16061593
Directory	/workspace/6.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/default/2.chip_sw_gpio.874023866
Short name	T17
Test name
Test status
Simulation time	4476471480 ps
CPU time	571.36 seconds
Started	Jul 24 08:10:28 PM PDT 24
Finished	Jul 24 08:19:59 PM PDT 24
Peak memory	610308 kb
Host	smart-f0208714-e047-424d-8fdb-18057e1c1c2a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874023866 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_gpio.874023866
Directory	/workspace/2.chip_sw_gpio/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2044797422
Short name	T600
Test name
Test status
Simulation time	5657218569 ps
CPU time	361.42 seconds
Started	Jul 24 07:33:29 PM PDT 24
Finished	Jul 24 07:39:31 PM PDT 24
Peak memory	577284 kb
Host	smart-e63b5f0e-69ac-4411-bd3d-bebecd1f3a58
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044797422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.2044797422
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.87831467
Short name	T127
Test name
Test status
Simulation time	5406858312 ps
CPU time	440.44 seconds
Started	Jul 24 07:58:50 PM PDT 24
Finished	Jul 24 08:06:11 PM PDT 24
Peak memory	609860 kb
Host	smart-cff98fc8-61da-4227-bcb4-67721b34c238
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87831467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.87831467
Directory	/workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

---

Test location	/workspace/coverage/cover_reg_top/27.chip_tl_errors.1833172148
Short name	T563
Test name
Test status
Simulation time	3986621468 ps
CPU time	384.59 seconds
Started	Jul 24 07:37:54 PM PDT 24
Finished	Jul 24 07:44:19 PM PDT 24
Peak memory	600472 kb
Host	smart-a0ef93e5-88f5-4f8e-9830-5e9b582a49f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833172148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.1833172148
Directory	/workspace/27.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.439073142
Short name	T911
Test name
Test status
Simulation time	9971754708 ps
CPU time	430.93 seconds
Started	Jul 24 07:48:59 PM PDT 24
Finished	Jul 24 07:56:10 PM PDT 24
Peak memory	577256 kb
Host	smart-9fbabe07-ae21-4ba5-a15d-30b404a73fa2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439073142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.439073142
Directory	/workspace/99.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2972050923
Short name	T8
Test name
Test status
Simulation time	43617304992 ps
CPU time	4293.43 seconds
Started	Jul 24 08:09:34 PM PDT 24
Finished	Jul 24 09:21:08 PM PDT 24
Peak memory	621380 kb
Host	smart-d9b8927f-424a-4e6c-9f32-2ca833201f60
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2972050923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.2972050923
Directory	/workspace/2.chip_sw_flash_rma_unlocked/latest

---

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2061367279
Short name	T12
Test name
Test status
Simulation time	3914496600 ps
CPU time	487.76 seconds
Started	Jul 24 08:15:20 PM PDT 24
Finished	Jul 24 08:23:28 PM PDT 24
Peak memory	625444 kb
Host	smart-e3218750-290c-4f92-b4ad-bf6052ddf69a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061367279 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.2061367279
Directory	/workspace/2.chip_sw_spi_device_pass_through_collision/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2985044122
Short name	T22
Test name
Test status
Simulation time	22934937000 ps
CPU time	1361.12 seconds
Started	Jul 24 08:01:54 PM PDT 24
Finished	Jul 24 08:24:36 PM PDT 24
Peak memory	615228 kb
Host	smart-f63c65f5-b58e-4aaa-8328-3dc6fbf8a04a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29850441 22 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2985044122
Directory	/workspace/0.chip_sw_sysrst_ctrl_reset/latest

---

Test location	/workspace/coverage/default/1.chip_jtag_csr_rw.804082749
Short name	T68
Test name
Test status
Simulation time	11056478840 ps
CPU time	1126.03 seconds
Started	Jul 24 07:59:38 PM PDT 24
Finished	Jul 24 08:18:24 PM PDT 24
Peak memory	608336 kb
Host	smart-bc7bbc56-db70-46a1-bc2e-f33ee66e3009
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804082749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_jtag_csr_rw.804082749
Directory	/workspace/1.chip_jtag_csr_rw/latest

---

Test location	/workspace/coverage/default/2.chip_sw_alert_test.3523606118
Short name	T50
Test name
Test status
Simulation time	3268357836 ps
CPU time	339.51 seconds
Started	Jul 24 08:16:08 PM PDT 24
Finished	Jul 24 08:21:48 PM PDT 24
Peak memory	610408 kb
Host	smart-8c508bb2-7c4b-4389-ae02-1eccef558165
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523606118 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.3523606118
Directory	/workspace/2.chip_sw_alert_test/latest

---

Test location	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1419263615
Short name	T263
Test name
Test status
Simulation time	17631856508 ps
CPU time	3521.4 seconds
Started	Jul 24 08:22:08 PM PDT 24
Finished	Jul 24 09:20:50 PM PDT 24
Peak memory	610476 kb
Host	smart-94ac3d24-2f4b-4af7-8b76-3cc591debddb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419263615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.1419263615
Directory	/workspace/8.chip_sw_csrng_edn_concurrency/latest

---

Test location	/workspace/coverage/cover_reg_top/17.chip_tl_errors.100728623
Short name	T565
Test name
Test status
Simulation time	5213182475 ps
CPU time	445.38 seconds
Started	Jul 24 07:35:32 PM PDT 24
Finished	Jul 24 07:42:58 PM PDT 24
Peak memory	604580 kb
Host	smart-73d0494c-9676-4eac-aa22-e064d588d775
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100728623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.100728623
Directory	/workspace/17.chip_tl_errors/latest

---

Test location	/workspace/coverage/default/35.chip_sw_all_escalation_resets.2585361666
Short name	T4
Test name
Test status
Simulation time	5586098364 ps
CPU time	548.6 seconds
Started	Jul 24 08:25:20 PM PDT 24
Finished	Jul 24 08:34:29 PM PDT 24
Peak memory	650220 kb
Host	smart-afe7e97e-dbd3-4e7e-8c13-04e4fae0f8a7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2585361666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.2585361666
Directory	/workspace/35.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3868111001
Short name	T10
Test name
Test status
Simulation time	3496676268 ps
CPU time	339.52 seconds
Started	Jul 24 08:11:38 PM PDT 24
Finished	Jul 24 08:17:17 PM PDT 24
Peak memory	610820 kb
Host	smart-1026b318-35da-4172-90ee-bd1850b1d888
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868 111001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.3868111001
Directory	/workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3217627757
Short name	T555
Test name
Test status
Simulation time	45945256568 ps
CPU time	490.07 seconds
Started	Jul 24 07:45:57 PM PDT 24
Finished	Jul 24 07:54:08 PM PDT 24
Peak memory	577060 kb
Host	smart-92e49223-e4a4-4718-b7d6-f11f3df27082
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217627757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3217627757
Directory	/workspace/79.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_access_same_device.3472343238
Short name	T905
Test name
Test status
Simulation time	953069934 ps
CPU time	70.82 seconds
Started	Jul 24 07:48:12 PM PDT 24
Finished	Jul 24 07:49:22 PM PDT 24
Peak memory	577004 kb
Host	smart-ad5b6aec-2de8-406e-86bd-a5ad0e9a7d6c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472343238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .3472343238
Directory	/workspace/95.xbar_access_same_device/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4068742149
Short name	T119
Test name
Test status
Simulation time	3980469326 ps
CPU time	570.94 seconds
Started	Jul 24 08:07:40 PM PDT 24
Finished	Jul 24 08:17:11 PM PDT 24
Peak memory	610208 kb
Host	smart-b81602fd-b535-4ef5-9a67-ef2e8ddee905
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068742149 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4068742149
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.371479080
Short name	T156
Test name
Test status
Simulation time	4779498160 ps
CPU time	463.62 seconds
Started	Jul 24 07:58:40 PM PDT 24
Finished	Jul 24 08:06:24 PM PDT 24
Peak memory	611472 kb
Host	smart-32f8f72a-19b9-4758-968c-4aa675e0de63
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 371479080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.371479080
Directory	/workspace/0.chip_sw_otp_ctrl_escalation/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3210718330
Short name	T11
Test name
Test status
Simulation time	2372297518 ps
CPU time	262.75 seconds
Started	Jul 24 07:56:32 PM PDT 24
Finished	Jul 24 08:00:55 PM PDT 24
Peak memory	610368 kb
Host	smart-fc0ba480-385e-4b9e-8877-735b67ea7d2d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210 718330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.3210718330
Directory	/workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3010413956
Short name	T18
Test name
Test status
Simulation time	23447380788 ps
CPU time	1396.95 seconds
Started	Jul 24 08:02:52 PM PDT 24
Finished	Jul 24 08:26:09 PM PDT 24
Peak memory	611428 kb
Host	smart-f0913b72-1496-4d65-b46b-43e553b14086
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3010413956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3010413956
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1227317950
Short name	T220
Test name
Test status
Simulation time	4535577470 ps
CPU time	815.54 seconds
Started	Jul 24 08:12:31 PM PDT 24
Finished	Jul 24 08:26:07 PM PDT 24
Peak memory	609976 kb
Host	smart-416edd89-3232-4be9-8fda-65d9ef78c83b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12 27317950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1227317950
Directory	/workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all.423871247
Short name	T586
Test name
Test status
Simulation time	7626986556 ps
CPU time	289.62 seconds
Started	Jul 24 07:41:48 PM PDT 24
Finished	Jul 24 07:46:38 PM PDT 24
Peak memory	576408 kb
Host	smart-04602cd3-0ccb-42d8-acec-6dfcfb9fe1cf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423871247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.423871247
Directory	/workspace/50.xbar_stress_all/latest

---

Test location	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1321581542
Short name	T6
Test name
Test status
Simulation time	6772745638 ps
CPU time	692.42 seconds
Started	Jul 24 08:15:42 PM PDT 24
Finished	Jul 24 08:27:15 PM PDT 24
Peak memory	611256 kb
Host	smart-5acdb663-adb0-4475-8d3d-bf1c4f616f8b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321581542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.1321581542
Directory	/workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

---

Test location	/workspace/coverage/default/32.chip_sw_all_escalation_resets.287231474
Short name	T246
Test name
Test status
Simulation time	6350307952 ps
CPU time	527.35 seconds
Started	Jul 24 08:23:59 PM PDT 24
Finished	Jul 24 08:32:46 PM PDT 24
Peak memory	650772 kb
Host	smart-8917bc85-e343-46cc-afb7-25d9dd62975d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 287231474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.287231474
Directory	/workspace/32.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3226306625
Short name	T460
Test name
Test status
Simulation time	5203950751 ps
CPU time	595.64 seconds
Started	Jul 24 07:34:10 PM PDT 24
Finished	Jul 24 07:44:06 PM PDT 24
Peak memory	577276 kb
Host	smart-e29372ad-d81a-4c7d-972e-c05c234488e1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226306625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.3226306625
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1635720497
Short name	T296
Test name
Test status
Simulation time	5364809256 ps
CPU time	709.81 seconds
Started	Jul 24 08:24:43 PM PDT 24
Finished	Jul 24 08:36:33 PM PDT 24
Peak memory	651260 kb
Host	smart-6356b270-9f13-4402-88fb-eab885de21a0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1635720497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1635720497
Directory	/workspace/28.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2765493418
Short name	T5
Test name
Test status
Simulation time	12881468116 ps
CPU time	2213.38 seconds
Started	Jul 24 08:24:12 PM PDT 24
Finished	Jul 24 09:01:06 PM PDT 24
Peak memory	619300 kb
Host	smart-f33a11e2-48e1-4b3e-9228-da7ed8bcfb0e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2765493418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2765493418
Directory	/workspace/14.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.846627899
Short name	T383
Test name
Test status
Simulation time	4025849820 ps
CPU time	334 seconds
Started	Jul 24 08:22:15 PM PDT 24
Finished	Jul 24 08:27:49 PM PDT 24
Peak memory	649308 kb
Host	smart-381740c1-a63a-4a66-9a20-4d5cc2c47595
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846627899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_s w_alert_handler_lpg_sleep_mode_alerts.846627899
Directory	/workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/51.chip_sw_all_escalation_resets.999585859
Short name	T82
Test name
Test status
Simulation time	5128368600 ps
CPU time	450.09 seconds
Started	Jul 24 08:26:20 PM PDT 24
Finished	Jul 24 08:33:51 PM PDT 24
Peak memory	652164 kb
Host	smart-4e1bf43f-236d-4ab1-9f4d-1f057bd9edb7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 999585859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.999585859
Directory	/workspace/51.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3164396185
Short name	T393
Test name
Test status
Simulation time	30446980496 ps
CPU time	3715.08 seconds
Started	Jul 24 07:35:45 PM PDT 24
Finished	Jul 24 08:37:40 PM PDT 24
Peak memory	594056 kb
Host	smart-2514baf8-d3fa-465a-9884-89f4b589b35b
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164396185 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.3164396185
Directory	/workspace/18.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.2046140880
Short name	T1792
Test name
Test status
Simulation time	120446556743 ps
CPU time	2067.24 seconds
Started	Jul 24 07:47:30 PM PDT 24
Finished	Jul 24 08:21:58 PM PDT 24
Peak memory	577168 kb
Host	smart-24508d51-c34a-4317-8809-7becd53a74f7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046140880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.2046140880
Directory	/workspace/90.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/default/61.chip_sw_all_escalation_resets.2647955921
Short name	T317
Test name
Test status
Simulation time	4804824808 ps
CPU time	562.2 seconds
Started	Jul 24 08:28:48 PM PDT 24
Finished	Jul 24 08:38:11 PM PDT 24
Peak memory	650640 kb
Host	smart-5785c292-589a-401e-bc0e-5134b4323267
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2647955921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.2647955921
Directory	/workspace/61.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_0.960458433
Short name	T323
Test name
Test status
Simulation time	6298471608 ps
CPU time	1067.43 seconds
Started	Jul 24 08:16:25 PM PDT 24
Finished	Jul 24 08:34:13 PM PDT 24
Peak memory	610600 kb
Host	smart-f8ceeefc-77b8-4238-8921-7a31e11e41ff
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960458433 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_plic_all_irqs_0.960458433
Directory	/workspace/2.chip_plic_all_irqs_0/latest

---

Test location	/workspace/coverage/cover_reg_top/15.chip_tl_errors.438592314
Short name	T619
Test name
Test status
Simulation time	4100772500 ps
CPU time	379.79 seconds
Started	Jul 24 07:35:07 PM PDT 24
Finished	Jul 24 07:41:27 PM PDT 24
Peak memory	599364 kb
Host	smart-5ec4370a-f9ed-421b-aa68-b3c198b61e41
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438592314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.438592314
Directory	/workspace/15.chip_tl_errors/latest

---

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3249075885
Short name	T308
Test name
Test status
Simulation time	5692799538 ps
CPU time	805.18 seconds
Started	Jul 24 08:16:08 PM PDT 24
Finished	Jul 24 08:29:33 PM PDT 24
Peak memory	611264 kb
Host	smart-0a59eb7f-4f22-4f7d-9915-cf8337c30c3a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249075885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.3249075885
Directory	/workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

---

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3386142984
Short name	T24
Test name
Test status
Simulation time	32074123726 ps
CPU time	8337.43 seconds
Started	Jul 24 07:57:15 PM PDT 24
Finished	Jul 24 10:16:14 PM PDT 24
Peak memory	609852 kb
Host	smart-681bb8fa-f9fb-47ec-99d7-8f944e5de8d0
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3386142984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.3386142984
Directory	/workspace/0.chip_sw_usbdev_pincfg/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1193093847
Short name	T75
Test name
Test status
Simulation time	12636202588 ps
CPU time	210.38 seconds
Started	Jul 24 07:32:57 PM PDT 24
Finished	Jul 24 07:36:28 PM PDT 24
Peak memory	576276 kb
Host	smart-965df411-4380-43b7-b023-551d3b78d7da
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193093847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1193093847
Directory	/workspace/3.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1456740261
Short name	T57
Test name
Test status
Simulation time	4121920239 ps
CPU time	374.48 seconds
Started	Jul 24 08:06:28 PM PDT 24
Finished	Jul 24 08:12:43 PM PDT 24
Peak memory	619156 kb
Host	smart-45820100-b0cb-43c2-8c2e-d6e4689995bd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456740261 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.1456740261
Directory	/workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.558483994
Short name	T87
Test name
Test status
Simulation time	5518210856 ps
CPU time	858.2 seconds
Started	Jul 24 08:04:39 PM PDT 24
Finished	Jul 24 08:18:57 PM PDT 24
Peak memory	610976 kb
Host	smart-0f2b755e-6c64-4c32-8512-b4aebf4c6797
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55848399 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.558483994
Directory	/workspace/1.chip_sw_sensor_ctrl_alert/latest

---

Test location	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1953476051
Short name	T279
Test name
Test status
Simulation time	5333526282 ps
CPU time	643.64 seconds
Started	Jul 24 08:22:36 PM PDT 24
Finished	Jul 24 08:33:20 PM PDT 24
Peak memory	611388 kb
Host	smart-eb028526-6e70-4ec5-a04b-7a94152f485d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1953476051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.1953476051
Directory	/workspace/4.chip_sw_data_integrity_escalation/latest

---

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1112553760
Short name	T172
Test name
Test status
Simulation time	32723370052 ps
CPU time	2503.91 seconds
Started	Jul 24 08:01:44 PM PDT 24
Finished	Jul 24 08:43:29 PM PDT 24
Peak memory	621032 kb
Host	smart-bcb755d1-502b-41f8-a610-722874c1083d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1112553760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.1112553760
Directory	/workspace/1.chip_sw_lc_walkthrough_testunlocks/latest

---

Test location	/workspace/coverage/default/3.chip_tap_straps_rma.2587651133
Short name	T62
Test name
Test status
Simulation time	3945770610 ps
CPU time	402.64 seconds
Started	Jul 24 08:21:46 PM PDT 24
Finished	Jul 24 08:28:29 PM PDT 24
Peak memory	621444 kb
Host	smart-a57e6ca2-5181-461f-b9f4-c5dc675b0d51
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587651133 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2587651133
Directory	/workspace/3.chip_tap_straps_rma/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.4146580650
Short name	T58
Test name
Test status
Simulation time	3804919480 ps
CPU time	237.95 seconds
Started	Jul 24 07:57:12 PM PDT 24
Finished	Jul 24 08:01:11 PM PDT 24
Peak memory	609812 kb
Host	smart-6e4cd7bd-1d80-4bbc-9fce-34a6e3aa83ae
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146580650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.4146580650
Directory	/workspace/0.chip_sw_sleep_pin_wake/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.561488973
Short name	T114
Test name
Test status
Simulation time	2647100784 ps
CPU time	249.83 seconds
Started	Jul 24 08:14:05 PM PDT 24
Finished	Jul 24 08:18:15 PM PDT 24
Peak memory	610688 kb
Host	smart-1490f462-1d9e-4761-aba4-2f21fe28b915
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561488973 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.561488973
Directory	/workspace/2.chip_sw_sleep_pin_wake/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.2698939586
Short name	T756
Test name
Test status
Simulation time	583775181 ps
CPU time	147.89 seconds
Started	Jul 24 07:48:00 PM PDT 24
Finished	Jul 24 07:50:28 PM PDT 24
Peak memory	577156 kb
Host	smart-1c67e5c0-bd46-4ec0-ab51-2b622f4e1f23
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698939586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.2698939586
Directory	/workspace/94.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/29.chip_tl_errors.513717004
Short name	T618
Test name
Test status
Simulation time	4356454520 ps
CPU time	332.05 seconds
Started	Jul 24 07:38:12 PM PDT 24
Finished	Jul 24 07:43:44 PM PDT 24
Peak memory	604588 kb
Host	smart-5a73ad77-07ed-48a1-b6f8-05079e7962f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513717004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.513717004
Directory	/workspace/29.chip_tl_errors/latest

---

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.728200033
Short name	T200
Test name
Test status
Simulation time	78790698558 ps
CPU time	13469.7 seconds
Started	Jul 24 07:56:44 PM PDT 24
Finished	Jul 24 11:41:15 PM PDT 24
Peak memory	636632 kb
Host	smart-315d9326-ad06-4c76-9be3-432dae1a3e1a
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=728200033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.728200033
Directory	/workspace/0.chip_sw_uart_tx_rx_bootstrap/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3820703418
Short name	T174
Test name
Test status
Simulation time	3782024761 ps
CPU time	297.34 seconds
Started	Jul 24 07:55:29 PM PDT 24
Finished	Jul 24 08:00:28 PM PDT 24
Peak memory	622200 kb
Host	smart-814fb10c-8fd7-4359-b941-3714299f6381
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38207034 18 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.3820703418
Directory	/workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.134105814
Short name	T183
Test name
Test status
Simulation time	42803714802 ps
CPU time	5262.98 seconds
Started	Jul 24 07:56:55 PM PDT 24
Finished	Jul 24 09:24:39 PM PDT 24
Peak memory	621312 kb
Host	smart-7ec4db6f-97bd-4623-8517-66deedda5623
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=134105814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.134105814
Directory	/workspace/0.chip_sw_flash_rma_unlocked/latest

---

Test location	/workspace/coverage/default/47.chip_sw_all_escalation_resets.1713518790
Short name	T218
Test name
Test status
Simulation time	5281848360 ps
CPU time	526.37 seconds
Started	Jul 24 08:27:02 PM PDT 24
Finished	Jul 24 08:35:49 PM PDT 24
Peak memory	650748 kb
Host	smart-ab023d11-1637-4a47-963b-324569e7b9f7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1713518790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.1713518790
Directory	/workspace/47.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1542380610
Short name	T954
Test name
Test status
Simulation time	10385561707 ps
CPU time	548.7 seconds
Started	Jul 24 07:34:37 PM PDT 24
Finished	Jul 24 07:43:46 PM PDT 24
Peak memory	577252 kb
Host	smart-787e0979-0e19-43bf-9ed1-42b2a26f548e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542380610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.1542380610
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_0.137669682
Short name	T333
Test name
Test status
Simulation time	6425220756 ps
CPU time	1463.22 seconds
Started	Jul 24 07:59:05 PM PDT 24
Finished	Jul 24 08:23:29 PM PDT 24
Peak memory	610400 kb
Host	smart-b9ad96e2-bec5-416e-be6e-7d83087dacd7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137669682 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_plic_all_irqs_0.137669682
Directory	/workspace/0.chip_plic_all_irqs_0/latest

---

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1175566091
Short name	T136
Test name
Test status
Simulation time	5087517100 ps
CPU time	332.87 seconds
Started	Jul 24 07:32:38 PM PDT 24
Finished	Jul 24 07:38:11 PM PDT 24
Peak memory	663356 kb
Host	smart-28025a9f-3f3c-4bd6-9f31-7d523ef659c5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175566091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.1175566091
Directory	/workspace/0.chip_csr_hw_reset/latest

---

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.328704763
Short name	T1017
Test name
Test status
Simulation time	8701684132 ps
CPU time	1061.23 seconds
Started	Jul 24 08:24:20 PM PDT 24
Finished	Jul 24 08:42:04 PM PDT 24
Peak memory	619136 kb
Host	smart-d4d3b29f-0eb0-44f6-8584-8bc25b521913
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328704763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.328704763
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1422129941
Short name	T485
Test name
Test status
Simulation time	11806692390 ps
CPU time	1059.3 seconds
Started	Jul 24 07:44:33 PM PDT 24
Finished	Jul 24 08:02:12 PM PDT 24
Peak memory	576476 kb
Host	smart-054b7dc5-525b-4983-8b12-cf39a2ba0e95
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422129941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.1422129941
Directory	/workspace/69.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all.1045879598
Short name	T550
Test name
Test status
Simulation time	5123626515 ps
CPU time	171.86 seconds
Started	Jul 24 07:35:36 PM PDT 24
Finished	Jul 24 07:38:28 PM PDT 24
Peak memory	577180 kb
Host	smart-14d1c520-44ef-4fd9-b5a9-76d1205af94f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045879598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1045879598
Directory	/workspace/16.xbar_stress_all/latest

---

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_20.881836526
Short name	T325
Test name
Test status
Simulation time	5372819988 ps
CPU time	1043.07 seconds
Started	Jul 24 08:06:43 PM PDT 24
Finished	Jul 24 08:24:06 PM PDT 24
Peak memory	609916 kb
Host	smart-3eff1047-74f1-4cbb-a1c5-2926873a97a3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881836526 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_20.881836526
Directory	/workspace/1.chip_plic_all_irqs_20/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_shutdown_output.2508064514
Short name	T46
Test name
Test status
Simulation time	27906725060 ps
CPU time	3248.71 seconds
Started	Jul 24 08:13:45 PM PDT 24
Finished	Jul 24 09:07:54 PM PDT 24
Peak memory	611844 kb
Host	smart-5f7181ea-c41f-4ca6-bdb0-5b87ce37bed1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508064514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.2508064514
Directory	/workspace/1.rom_e2e_shutdown_output/latest

---

Test location	/workspace/coverage/cover_reg_top/9.chip_csr_rw.1768329431
Short name	T143
Test name
Test status
Simulation time	3893957656 ps
CPU time	285.71 seconds
Started	Jul 24 07:34:09 PM PDT 24
Finished	Jul 24 07:38:55 PM PDT 24
Peak memory	598132 kb
Host	smart-d7aa5339-9605-4cd8-a477-ba3c44de0099
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768329431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.1768329431
Directory	/workspace/9.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2394217691
Short name	T498
Test name
Test status
Simulation time	7843363101 ps
CPU time	916.42 seconds
Started	Jul 24 07:38:16 PM PDT 24
Finished	Jul 24 07:53:32 PM PDT 24
Peak memory	576508 kb
Host	smart-49938d58-fecb-42de-bb03-a033190d7783
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394217691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.2394217691
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3439279756
Short name	T113
Test name
Test status
Simulation time	4446353820 ps
CPU time	427.76 seconds
Started	Jul 24 08:02:51 PM PDT 24
Finished	Jul 24 08:09:59 PM PDT 24
Peak memory	621396 kb
Host	smart-ec0a9f24-6804-4834-ada4-fe476333ea17
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 439279756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.3439279756
Directory	/workspace/0.chip_rv_dm_ndm_reset_req/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2335295393
Short name	T137
Test name
Test status
Simulation time	6025242648 ps
CPU time	921.38 seconds
Started	Jul 24 08:00:40 PM PDT 24
Finished	Jul 24 08:16:03 PM PDT 24
Peak memory	610628 kb
Host	smart-abdefd9d-65a5-4dfe-b68e-1299576aec62
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23352953 93 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.2335295393
Directory	/workspace/0.chip_sw_sensor_ctrl_alert/latest

---

Test location	/workspace/coverage/cover_reg_top/24.chip_tl_errors.3128851308
Short name	T566
Test name
Test status
Simulation time	3203031360 ps
CPU time	325.51 seconds
Started	Jul 24 07:37:41 PM PDT 24
Finished	Jul 24 07:43:06 PM PDT 24
Peak memory	599488 kb
Host	smart-d4fca1c4-a4ef-47a2-8d4d-4774b2e98b48
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128851308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3128851308
Directory	/workspace/24.chip_tl_errors/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2509221894
Short name	T170
Test name
Test status
Simulation time	51901053975 ps
CPU time	5975.86 seconds
Started	Jul 24 07:57:58 PM PDT 24
Finished	Jul 24 09:37:35 PM PDT 24
Peak memory	620836 kb
Host	smart-1b1050a0-178d-4807-a314-005d1fda7991
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509221894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.2509221894
Directory	/workspace/0.chip_sw_lc_walkthrough_dev/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3183716210
Short name	T260
Test name
Test status
Simulation time	10830012012 ps
CPU time	1865.74 seconds
Started	Jul 24 08:02:08 PM PDT 24
Finished	Jul 24 08:33:15 PM PDT 24
Peak memory	624300 kb
Host	smart-c3e1c24d-829f-4b7f-8771-a748033816c4
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31837 16210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.3183716210
Directory	/workspace/0.rom_e2e_jtag_debug_dev/latest

---

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_10.3387071068
Short name	T154
Test name
Test status
Simulation time	3460351084 ps
CPU time	617.35 seconds
Started	Jul 24 08:07:41 PM PDT 24
Finished	Jul 24 08:17:59 PM PDT 24
Peak memory	609856 kb
Host	smart-62a76858-5fae-4347-887b-2c9908ad9d3c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387071068 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.3387071068
Directory	/workspace/1.chip_plic_all_irqs_10/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.771230654
Short name	T948
Test name
Test status
Simulation time	10199300633 ps
CPU time	499.97 seconds
Started	Jul 24 07:35:54 PM PDT 24
Finished	Jul 24 07:44:14 PM PDT 24
Peak memory	576456 kb
Host	smart-473e2149-b10b-4817-a6b4-50dc6eba092e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771230654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_ with_rand_reset.771230654
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.511203484
Short name	T534
Test name
Test status
Simulation time	779175667 ps
CPU time	232.68 seconds
Started	Jul 24 07:43:41 PM PDT 24
Finished	Jul 24 07:47:34 PM PDT 24
Peak memory	576320 kb
Host	smart-076c0519-e5ee-4031-91bc-89da798e7c49
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511203484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_ with_rand_reset.511203484
Directory	/workspace/62.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1444437671
Short name	T184
Test name
Test status
Simulation time	43413735240 ps
CPU time	5068.37 seconds
Started	Jul 24 08:02:38 PM PDT 24
Finished	Jul 24 09:27:08 PM PDT 24
Peak memory	621344 kb
Host	smart-4edec8be-99d3-4001-b0c8-25940e170ed0
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1444437671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.1444437671
Directory	/workspace/1.chip_sw_flash_rma_unlocked/latest

---

Test location	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3066947521
Short name	T38
Test name
Test status
Simulation time	3547983496 ps
CPU time	257.54 seconds
Started	Jul 24 07:58:31 PM PDT 24
Finished	Jul 24 08:02:48 PM PDT 24
Peak memory	610692 kb
Host	smart-a83ecd9d-c4f5-4112-88f0-c7fadb812e43
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066947521 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.3066947521
Directory	/workspace/0.chip_sw_spi_host_tx_rx/latest

---

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_20.1313540074
Short name	T331
Test name
Test status
Simulation time	5554560754 ps
CPU time	865.91 seconds
Started	Jul 24 08:08:10 PM PDT 24
Finished	Jul 24 08:22:37 PM PDT 24
Peak memory	610328 kb
Host	smart-a1a760ac-498d-4dfc-be1f-4cd7c0d07cde
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313540074 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.1313540074
Directory	/workspace/0.chip_plic_all_irqs_20/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1185282871
Short name	T914
Test name
Test status
Simulation time	18258248843 ps
CPU time	649.95 seconds
Started	Jul 24 07:39:20 PM PDT 24
Finished	Jul 24 07:50:10 PM PDT 24
Peak memory	576388 kb
Host	smart-050ae6ec-8e85-44bf-8f55-85f4a83fd702
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185282871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1185282871
Directory	/workspace/35.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.4214591188
Short name	T951
Test name
Test status
Simulation time	4374525724 ps
CPU time	371.54 seconds
Started	Jul 24 07:42:24 PM PDT 24
Finished	Jul 24 07:48:35 PM PDT 24
Peak memory	577220 kb
Host	smart-1452f1df-249a-4851-9499-7a7c6e4729d0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214591188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.4214591188
Directory	/workspace/53.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/default/0.chip_sw_power_sleep_load.1510506047
Short name	T255
Test name
Test status
Simulation time	4846791532 ps
CPU time	304.99 seconds
Started	Jul 24 07:57:22 PM PDT 24
Finished	Jul 24 08:02:28 PM PDT 24
Peak memory	609932 kb
Host	smart-22a62d6a-e3dc-4cf2-83ea-479231de90b7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510506047 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.1510506047
Directory	/workspace/0.chip_sw_power_sleep_load/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1741063626
Short name	T162
Test name
Test status
Simulation time	2778731262 ps
CPU time	292.35 seconds
Started	Jul 24 08:01:04 PM PDT 24
Finished	Jul 24 08:05:57 PM PDT 24
Peak memory	622152 kb
Host	smart-849d5fd9-fd7c-4bd1-9e25-edfdfb58c85b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741063626 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.1741063626
Directory	/workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all.184739812
Short name	T472
Test name
Test status
Simulation time	8923396300 ps
CPU time	353.75 seconds
Started	Jul 24 07:32:39 PM PDT 24
Finished	Jul 24 07:38:33 PM PDT 24
Peak memory	576452 kb
Host	smart-c70d29d0-1514-417d-ab0f-c62c9236f5a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184739812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.184739812
Directory	/workspace/1.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/13.chip_tl_errors.2148183595
Short name	T645
Test name
Test status
Simulation time	4483586110 ps
CPU time	275.62 seconds
Started	Jul 24 07:34:31 PM PDT 24
Finished	Jul 24 07:39:07 PM PDT 24
Peak memory	600504 kb
Host	smart-a744a974-9247-4626-b9c7-2094177cbcff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148183595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.2148183595
Directory	/workspace/13.chip_tl_errors/latest

---

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx.2676894788
Short name	T301
Test name
Test status
Simulation time	4018352420 ps
CPU time	594.12 seconds
Started	Jul 24 08:21:02 PM PDT 24
Finished	Jul 24 08:30:56 PM PDT 24
Peak memory	625272 kb
Host	smart-27de7e89-d0c9-4c1f-9a02-d416027270fb
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676894788 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2676894788
Directory	/workspace/4.chip_sw_uart_tx_rx/latest

---

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.4067203162
Short name	T133
Test name
Test status
Simulation time	6981461217 ps
CPU time	386.25 seconds
Started	Jul 24 07:33:19 PM PDT 24
Finished	Jul 24 07:39:46 PM PDT 24
Peak memory	662528 kb
Host	smart-1c11ed08-9889-4c52-8991-855dea829d31
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067203162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.4067203162
Directory	/workspace/4.chip_csr_hw_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3578621202
Short name	T123
Test name
Test status
Simulation time	3950931354 ps
CPU time	559.77 seconds
Started	Jul 24 07:59:34 PM PDT 24
Finished	Jul 24 08:08:54 PM PDT 24
Peak memory	613264 kb
Host	smart-1229c0be-5744-485e-a1f9-e77eb0ce1e43
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578621202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3578621202
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3357884988
Short name	T355
Test name
Test status
Simulation time	5250617788 ps
CPU time	658.04 seconds
Started	Jul 24 08:01:25 PM PDT 24
Finished	Jul 24 08:12:24 PM PDT 24
Peak memory	609796 kb
Host	smart-3f700025-211e-42dc-9525-f0beff3604f6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3357884988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3357884988
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2962213063
Short name	T189
Test name
Test status
Simulation time	4982679632 ps
CPU time	212.39 seconds
Started	Jul 24 07:32:21 PM PDT 24
Finished	Jul 24 07:35:54 PM PDT 24
Peak memory	649496 kb
Host	smart-9f8202f7-4996-4d5b-8520-a79417ddb8bf
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962213063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.2962213063
Directory	/workspace/0.chip_padctrl_attributes/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.143377094
Short name	T710
Test name
Test status
Simulation time	1714594671 ps
CPU time	255.56 seconds
Started	Jul 24 07:35:21 PM PDT 24
Finished	Jul 24 07:39:37 PM PDT 24
Peak memory	577112 kb
Host	smart-bf8d2fdf-ef1c-4ead-894e-eefcac141f90
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143377094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_ with_rand_reset.143377094
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.520567871
Short name	T59
Test name
Test status
Simulation time	3719626152 ps
CPU time	479.42 seconds
Started	Jul 24 07:56:43 PM PDT 24
Finished	Jul 24 08:04:42 PM PDT 24
Peak memory	610020 kb
Host	smart-0680769f-8861-4546-9e1f-2b22bea72df9
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520567 871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.520567871
Directory	/workspace/0.chip_sw_usbdev_aon_pullup/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_init.3345041894
Short name	T239
Test name
Test status
Simulation time	17491019636 ps
CPU time	2153.31 seconds
Started	Jul 24 08:02:09 PM PDT 24
Finished	Jul 24 08:38:03 PM PDT 24
Peak memory	614008 kb
Host	smart-9ec99928-d068-491c-aece-4ab433d6645f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345041894 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.3345041894
Directory	/workspace/1.chip_sw_flash_init/latest

---

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.618358425
Short name	T346
Test name
Test status
Simulation time	4995150028 ps
CPU time	824.25 seconds
Started	Jul 24 07:56:23 PM PDT 24
Finished	Jul 24 08:10:08 PM PDT 24
Peak memory	609968 kb
Host	smart-4b257a45-8cff-46bb-9287-baed11b3c0c8
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618358425 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.618358425
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all.1616943658
Short name	T479
Test name
Test status
Simulation time	14211500418 ps
CPU time	499.67 seconds
Started	Jul 24 07:37:40 PM PDT 24
Finished	Jul 24 07:45:59 PM PDT 24
Peak memory	577384 kb
Host	smart-8ebe304d-f52f-406c-944a-8a899d774fc9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616943658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1616943658
Directory	/workspace/23.xbar_stress_all/latest

---

Test location	/workspace/coverage/default/0.chip_sw_gpio.2321948170
Short name	T28
Test name
Test status
Simulation time	3896517160 ps
CPU time	341.82 seconds
Started	Jul 24 07:56:51 PM PDT 24
Finished	Jul 24 08:02:33 PM PDT 24
Peak memory	610672 kb
Host	smart-e28c0567-5cb0-4c4b-b770-d540e2f2128c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321948170 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.2321948170
Directory	/workspace/0.chip_sw_gpio/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2599177260
Short name	T161
Test name
Test status
Simulation time	2254634994 ps
CPU time	197.84 seconds
Started	Jul 24 08:11:50 PM PDT 24
Finished	Jul 24 08:15:08 PM PDT 24
Peak memory	622220 kb
Host	smart-1aa49f14-7404-4bc7-a867-eb199968e93c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599177260 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.2599177260
Directory	/workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.2201852547
Short name	T1537
Test name
Test status
Simulation time	14915218569 ps
CPU time	548.55 seconds
Started	Jul 24 07:41:14 PM PDT 24
Finished	Jul 24 07:50:23 PM PDT 24
Peak memory	577288 kb
Host	smart-12253262-ed84-45ac-9ac1-14f6275cf903
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201852547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2201852547
Directory	/workspace/45.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2159332301
Short name	T21
Test name
Test status
Simulation time	20405759613 ps
CPU time	3266.15 seconds
Started	Jul 24 07:58:46 PM PDT 24
Finished	Jul 24 08:53:13 PM PDT 24
Peak memory	611072 kb
Host	smart-5a0c1191-869e-4a4f-84c3-d61c0b4bece3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159332301 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.2159332301
Directory	/workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3492775638
Short name	T348
Test name
Test status
Simulation time	3994212612 ps
CPU time	423.41 seconds
Started	Jul 24 08:02:14 PM PDT 24
Finished	Jul 24 08:09:18 PM PDT 24
Peak memory	610100 kb
Host	smart-9853c5ad-3a31-4349-90ea-59660f025d08
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492775638 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.3492775638
Directory	/workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest

---

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.1581195467
Short name	T337
Test name
Test status
Simulation time	6368445724 ps
CPU time	1369.3 seconds
Started	Jul 24 08:14:39 PM PDT 24
Finished	Jul 24 08:37:29 PM PDT 24
Peak memory	609956 kb
Host	smart-ebb421db-24ea-4358-a45b-c4a8e26d7218
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1581195467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.1581195467
Directory	/workspace/2.chip_sw_entropy_src_csrng/latest

---

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2745379914
Short name	T328
Test name
Test status
Simulation time	4530403490 ps
CPU time	854.19 seconds
Started	Jul 24 07:58:31 PM PDT 24
Finished	Jul 24 08:12:46 PM PDT 24
Peak memory	609872 kb
Host	smart-7be45974-cf83-42a7-8457-b187f87eadac
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745379914 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.2745379914
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2811167740
Short name	T34
Test name
Test status
Simulation time	4704618696 ps
CPU time	420.98 seconds
Started	Jul 24 08:08:11 PM PDT 24
Finished	Jul 24 08:15:12 PM PDT 24
Peak memory	624752 kb
Host	smart-5164545c-b571-44d2-a3fc-3f94fb30d2e2
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811167740 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.2811167740
Directory	/workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.36603540
Short name	T2558
Test name
Test status
Simulation time	405525328 ps
CPU time	149.2 seconds
Started	Jul 24 07:37:51 PM PDT 24
Finished	Jul 24 07:40:20 PM PDT 24
Peak memory	577160 kb
Host	smart-af72155a-304b-45f8-bac4-3740f13ac6d9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36603540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_ with_reset_error.36603540
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/25.chip_tl_errors.2510897681
Short name	T821
Test name
Test status
Simulation time	3564690760 ps
CPU time	292.57 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:42:45 PM PDT 24
Peak memory	601644 kb
Host	smart-63c5638b-71f6-4e02-97be-7809b5356ac8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510897681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2510897681
Directory	/workspace/25.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.754117916
Short name	T970
Test name
Test status
Simulation time	3545619947 ps
CPU time	236.72 seconds
Started	Jul 24 07:45:36 PM PDT 24
Finished	Jul 24 07:49:32 PM PDT 24
Peak memory	577360 kb
Host	smart-bff17094-463c-40fe-82d8-6fa4a1668e3d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754117916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_ with_rand_reset.754117916
Directory	/workspace/74.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.963475574
Short name	T832
Test name
Test status
Simulation time	3945590168 ps
CPU time	505.76 seconds
Started	Jul 24 08:03:18 PM PDT 24
Finished	Jul 24 08:11:44 PM PDT 24
Peak memory	649160 kb
Host	smart-db2c5128-56b8-43aa-a417-d950abeae59a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963475574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _alert_handler_lpg_sleep_mode_alerts.963475574
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2820170300
Short name	T859
Test name
Test status
Simulation time	6464192688 ps
CPU time	793.88 seconds
Started	Jul 24 08:01:34 PM PDT 24
Finished	Jul 24 08:14:48 PM PDT 24
Peak memory	650908 kb
Host	smart-7130a938-9a0a-4000-b828-72e9dfc25265
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2820170300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.2820170300
Directory	/workspace/1.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/10.chip_sw_all_escalation_resets.879925685
Short name	T307
Test name
Test status
Simulation time	4634605384 ps
CPU time	652.08 seconds
Started	Jul 24 08:22:33 PM PDT 24
Finished	Jul 24 08:33:25 PM PDT 24
Peak memory	650368 kb
Host	smart-4012fcfb-da57-4125-8ab9-ce84f451de71
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 879925685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.879925685
Directory	/workspace/10.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2320378902
Short name	T870
Test name
Test status
Simulation time	3510229932 ps
CPU time	408.95 seconds
Started	Jul 24 08:21:30 PM PDT 24
Finished	Jul 24 08:28:19 PM PDT 24
Peak memory	649192 kb
Host	smart-1012dc8c-dfea-4fd5-8d79-ada07ea47552
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320378902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2320378902
Directory	/workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3867619854
Short name	T808
Test name
Test status
Simulation time	5472020200 ps
CPU time	562.07 seconds
Started	Jul 24 08:22:06 PM PDT 24
Finished	Jul 24 08:31:28 PM PDT 24
Peak memory	650636 kb
Host	smart-c57fdf64-50e4-42da-a7c3-af594882931f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3867619854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.3867619854
Directory	/workspace/11.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2325404228
Short name	T848
Test name
Test status
Simulation time	3585975156 ps
CPU time	484.02 seconds
Started	Jul 24 08:24:42 PM PDT 24
Finished	Jul 24 08:32:46 PM PDT 24
Peak memory	648888 kb
Host	smart-40ced164-e2ef-4b0d-8489-e0f2304ad09e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325404228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2325404228
Directory	/workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2140371554
Short name	T886
Test name
Test status
Simulation time	5883235280 ps
CPU time	527.59 seconds
Started	Jul 24 08:22:12 PM PDT 24
Finished	Jul 24 08:31:00 PM PDT 24
Peak memory	650544 kb
Host	smart-604f1e24-cfda-4678-80e0-3c5454057d65
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2140371554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.2140371554
Directory	/workspace/12.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2057765192
Short name	T322
Test name
Test status
Simulation time	3756300056 ps
CPU time	357.82 seconds
Started	Jul 24 08:22:59 PM PDT 24
Finished	Jul 24 08:28:57 PM PDT 24
Peak memory	649192 kb
Host	smart-0c38df20-2a65-4c7c-bc13-29c1e5864e6c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057765192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2057765192
Directory	/workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2615831898
Short name	T820
Test name
Test status
Simulation time	3104004900 ps
CPU time	532.66 seconds
Started	Jul 24 08:23:13 PM PDT 24
Finished	Jul 24 08:32:06 PM PDT 24
Peak memory	649364 kb
Host	smart-035b3a6d-839c-4fcb-ae65-4ecabc69a3ae
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615831898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2615831898
Directory	/workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/14.chip_sw_all_escalation_resets.2629316169
Short name	T831
Test name
Test status
Simulation time	6111585000 ps
CPU time	643.1 seconds
Started	Jul 24 08:22:19 PM PDT 24
Finished	Jul 24 08:33:02 PM PDT 24
Peak memory	650244 kb
Host	smart-91f37013-0b04-4e16-9380-a6d303923f8c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2629316169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.2629316169
Directory	/workspace/14.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3073973071
Short name	T856
Test name
Test status
Simulation time	6039934578 ps
CPU time	541.49 seconds
Started	Jul 24 08:22:22 PM PDT 24
Finished	Jul 24 08:31:24 PM PDT 24
Peak memory	650704 kb
Host	smart-bc1c1991-6b4c-4c6c-9308-b8cadf5dcf7c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3073973071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.3073973071
Directory	/workspace/15.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/16.chip_sw_all_escalation_resets.1800198506
Short name	T875
Test name
Test status
Simulation time	5317549580 ps
CPU time	457.62 seconds
Started	Jul 24 08:23:28 PM PDT 24
Finished	Jul 24 08:31:06 PM PDT 24
Peak memory	650652 kb
Host	smart-d4110f88-e772-4fde-9065-63719390f5c8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1800198506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.1800198506
Directory	/workspace/16.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.844164933
Short name	T887
Test name
Test status
Simulation time	3727983512 ps
CPU time	313.83 seconds
Started	Jul 24 08:25:09 PM PDT 24
Finished	Jul 24 08:30:23 PM PDT 24
Peak memory	649160 kb
Host	smart-9913ee76-9e79-4214-b129-4b172492ba12
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844164933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_s w_alert_handler_lpg_sleep_mode_alerts.844164933
Directory	/workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1421683978
Short name	T241
Test name
Test status
Simulation time	4382625800 ps
CPU time	582.14 seconds
Started	Jul 24 08:23:42 PM PDT 24
Finished	Jul 24 08:33:25 PM PDT 24
Peak memory	650552 kb
Host	smart-c48decb6-c523-48eb-93f7-df7b8ae0f517
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1421683978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1421683978
Directory	/workspace/17.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3547905741
Short name	T93
Test name
Test status
Simulation time	3163451320 ps
CPU time	405.02 seconds
Started	Jul 24 08:28:56 PM PDT 24
Finished	Jul 24 08:35:41 PM PDT 24
Peak memory	649320 kb
Host	smart-698f28c1-da29-4af1-b34d-8adcf8e693de
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547905741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3547905741
Directory	/workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/18.chip_sw_all_escalation_resets.3762980016
Short name	T419
Test name
Test status
Simulation time	4826210140 ps
CPU time	688.59 seconds
Started	Jul 24 08:23:07 PM PDT 24
Finished	Jul 24 08:34:36 PM PDT 24
Peak memory	650448 kb
Host	smart-1da3cb7c-365f-4040-9f67-9024652bb57b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3762980016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.3762980016
Directory	/workspace/18.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2783908761
Short name	T774
Test name
Test status
Simulation time	4208592476 ps
CPU time	507.64 seconds
Started	Jul 24 08:25:16 PM PDT 24
Finished	Jul 24 08:33:44 PM PDT 24
Peak memory	648912 kb
Host	smart-fa89100b-8c90-4bd8-b1cd-a497182bf58b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783908761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2783908761
Directory	/workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1126702028
Short name	T297
Test name
Test status
Simulation time	5489059080 ps
CPU time	504.57 seconds
Started	Jul 24 08:25:00 PM PDT 24
Finished	Jul 24 08:33:24 PM PDT 24
Peak memory	650412 kb
Host	smart-e534fbde-8768-4e05-af2c-c3f0c0457d31
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1126702028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.1126702028
Directory	/workspace/19.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1077321018
Short name	T771
Test name
Test status
Simulation time	4357144680 ps
CPU time	443.09 seconds
Started	Jul 24 08:20:49 PM PDT 24
Finished	Jul 24 08:28:13 PM PDT 24
Peak memory	649280 kb
Host	smart-7883836f-5020-40fb-b1e6-a610a1853ffb
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077321018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.1077321018
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3204907833
Short name	T1397
Test name
Test status
Simulation time	3609963050 ps
CPU time	429.46 seconds
Started	Jul 24 08:25:46 PM PDT 24
Finished	Jul 24 08:32:56 PM PDT 24
Peak memory	649240 kb
Host	smart-6f2a2a2a-23f3-4bcd-9801-06c7f26d335a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204907833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3204907833
Directory	/workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3459371190
Short name	T381
Test name
Test status
Simulation time	4903151096 ps
CPU time	595.98 seconds
Started	Jul 24 08:23:21 PM PDT 24
Finished	Jul 24 08:33:17 PM PDT 24
Peak memory	650372 kb
Host	smart-f384caf1-82cf-4a52-976e-77416fb92e02
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3459371190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.3459371190
Directory	/workspace/22.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4186164496
Short name	T864
Test name
Test status
Simulation time	4376176660 ps
CPU time	405.53 seconds
Started	Jul 24 08:25:38 PM PDT 24
Finished	Jul 24 08:32:24 PM PDT 24
Peak memory	649552 kb
Host	smart-9daf4623-007b-43ca-893f-9825b135fc61
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186164496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4186164496
Directory	/workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/23.chip_sw_all_escalation_resets.2633523565
Short name	T812
Test name
Test status
Simulation time	5047298462 ps
CPU time	471.39 seconds
Started	Jul 24 08:25:35 PM PDT 24
Finished	Jul 24 08:33:27 PM PDT 24
Peak memory	650284 kb
Host	smart-62e75d4e-2bd5-491d-bcdf-49812d6412a2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2633523565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.2633523565
Directory	/workspace/23.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/24.chip_sw_all_escalation_resets.848489787
Short name	T90
Test name
Test status
Simulation time	6157089110 ps
CPU time	577.18 seconds
Started	Jul 24 08:24:14 PM PDT 24
Finished	Jul 24 08:33:52 PM PDT 24
Peak memory	651000 kb
Host	smart-4ba0f5a5-11a0-4df3-9315-4ab244362fd5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 848489787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.848489787
Directory	/workspace/24.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3045882244
Short name	T846
Test name
Test status
Simulation time	4339864776 ps
CPU time	529.23 seconds
Started	Jul 24 08:25:58 PM PDT 24
Finished	Jul 24 08:34:48 PM PDT 24
Peak memory	649464 kb
Host	smart-ac3fd1d1-e811-4977-8150-cdf0eaf071a7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045882244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3045882244
Directory	/workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/27.chip_sw_all_escalation_resets.3179423763
Short name	T871
Test name
Test status
Simulation time	5885112306 ps
CPU time	683.38 seconds
Started	Jul 24 08:25:06 PM PDT 24
Finished	Jul 24 08:36:29 PM PDT 24
Peak memory	650212 kb
Host	smart-dfe2d526-cbea-4ebb-bc96-bf0bf1525929
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3179423763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3179423763
Directory	/workspace/27.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3955020781
Short name	T825
Test name
Test status
Simulation time	3918551468 ps
CPU time	337.25 seconds
Started	Jul 24 08:24:09 PM PDT 24
Finished	Jul 24 08:29:47 PM PDT 24
Peak memory	649372 kb
Host	smart-fa368b66-9311-4c53-b54f-429b2f08409d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955020781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3955020781
Directory	/workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1695446450
Short name	T428
Test name
Test status
Simulation time	5078531316 ps
CPU time	573.76 seconds
Started	Jul 24 08:23:35 PM PDT 24
Finished	Jul 24 08:33:09 PM PDT 24
Peak memory	650248 kb
Host	smart-078df6f7-275d-4368-9e18-ec405ae930fe
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1695446450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.1695446450
Directory	/workspace/29.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1788811964
Short name	T839
Test name
Test status
Simulation time	5216717540 ps
CPU time	699.89 seconds
Started	Jul 24 08:20:22 PM PDT 24
Finished	Jul 24 08:32:02 PM PDT 24
Peak memory	650364 kb
Host	smart-876aed65-8878-4dc1-85a9-87942e9f84ea
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1788811964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.1788811964
Directory	/workspace/3.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3401944113
Short name	T882
Test name
Test status
Simulation time	4236232348 ps
CPU time	359.31 seconds
Started	Jul 24 08:24:49 PM PDT 24
Finished	Jul 24 08:30:48 PM PDT 24
Peak memory	648852 kb
Host	smart-0c734d04-1924-4101-8d63-adb5b266a290
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401944113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3401944113
Directory	/workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3410027958
Short name	T833
Test name
Test status
Simulation time	3416166224 ps
CPU time	401.46 seconds
Started	Jul 24 08:24:13 PM PDT 24
Finished	Jul 24 08:30:55 PM PDT 24
Peak memory	648920 kb
Host	smart-869b5a4f-1163-45b9-82dc-e6c1f8cdde25
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410027958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3410027958
Directory	/workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/34.chip_sw_all_escalation_resets.2739352834
Short name	T543
Test name
Test status
Simulation time	4912264520 ps
CPU time	710.33 seconds
Started	Jul 24 08:24:53 PM PDT 24
Finished	Jul 24 08:36:44 PM PDT 24
Peak memory	650376 kb
Host	smart-f06f278e-e06b-42e8-b35b-e021b011cbff
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2739352834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2739352834
Directory	/workspace/34.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2340555778
Short name	T849
Test name
Test status
Simulation time	3374472596 ps
CPU time	350.53 seconds
Started	Jul 24 08:26:57 PM PDT 24
Finished	Jul 24 08:32:48 PM PDT 24
Peak memory	649160 kb
Host	smart-b586a685-f8a8-4cec-867b-cfc466975fd9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340555778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2340555778
Directory	/workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3466924998
Short name	T784
Test name
Test status
Simulation time	4279426662 ps
CPU time	595.96 seconds
Started	Jul 24 08:26:47 PM PDT 24
Finished	Jul 24 08:36:43 PM PDT 24
Peak memory	650192 kb
Host	smart-aec73256-056f-4e80-be37-1bd9ba774068
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3466924998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3466924998
Directory	/workspace/37.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1103908478
Short name	T868
Test name
Test status
Simulation time	5292958212 ps
CPU time	602 seconds
Started	Jul 24 08:24:04 PM PDT 24
Finished	Jul 24 08:34:06 PM PDT 24
Peak memory	650500 kb
Host	smart-db48b15c-1e67-42c2-b611-b2d461938b03
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1103908478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1103908478
Directory	/workspace/38.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3687018504
Short name	T817
Test name
Test status
Simulation time	3482912696 ps
CPU time	372.73 seconds
Started	Jul 24 08:22:20 PM PDT 24
Finished	Jul 24 08:28:33 PM PDT 24
Peak memory	649152 kb
Host	smart-e17eed98-09b2-4a18-9f1a-eadd4513d0f1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687018504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.3687018504
Directory	/workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/42.chip_sw_all_escalation_resets.3190485976
Short name	T1341
Test name
Test status
Simulation time	5432844804 ps
CPU time	742.98 seconds
Started	Jul 24 08:24:02 PM PDT 24
Finished	Jul 24 08:36:25 PM PDT 24
Peak memory	650232 kb
Host	smart-964f3a17-7f84-40fb-850b-7ab6dd8ed627
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3190485976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.3190485976
Directory	/workspace/42.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3649731507
Short name	T861
Test name
Test status
Simulation time	3614962850 ps
CPU time	425.56 seconds
Started	Jul 24 08:26:10 PM PDT 24
Finished	Jul 24 08:33:16 PM PDT 24
Peak memory	649232 kb
Host	smart-aca69de1-05dc-4486-b788-07ea611d3753
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649731507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3649731507
Directory	/workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/46.chip_sw_all_escalation_resets.3569723966
Short name	T889
Test name
Test status
Simulation time	5565712060 ps
CPU time	497.99 seconds
Started	Jul 24 08:26:28 PM PDT 24
Finished	Jul 24 08:34:46 PM PDT 24
Peak memory	650308 kb
Host	smart-ad50e979-db52-461d-bdcf-dcf554d8de8d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3569723966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.3569723966
Directory	/workspace/46.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3509095136
Short name	T857
Test name
Test status
Simulation time	3541501546 ps
CPU time	358.17 seconds
Started	Jul 24 08:25:50 PM PDT 24
Finished	Jul 24 08:31:48 PM PDT 24
Peak memory	649548 kb
Host	smart-a1b682a1-aa96-4859-81b1-ad87ed13854c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509095136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3509095136
Directory	/workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/49.chip_sw_all_escalation_resets.2615276463
Short name	T863
Test name
Test status
Simulation time	6223914772 ps
CPU time	650.56 seconds
Started	Jul 24 08:26:28 PM PDT 24
Finished	Jul 24 08:37:19 PM PDT 24
Peak memory	650552 kb
Host	smart-6ffb5201-411a-44e4-a132-59d1ffb16199
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2615276463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.2615276463
Directory	/workspace/49.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1136810164
Short name	T360
Test name
Test status
Simulation time	5211266260 ps
CPU time	531.61 seconds
Started	Jul 24 08:29:08 PM PDT 24
Finished	Jul 24 08:38:00 PM PDT 24
Peak memory	650332 kb
Host	smart-1e59d008-c032-45e6-bf0b-f536f0eef42c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1136810164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.1136810164
Directory	/workspace/50.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.520401088
Short name	T754
Test name
Test status
Simulation time	4010918060 ps
CPU time	494.25 seconds
Started	Jul 24 08:25:25 PM PDT 24
Finished	Jul 24 08:33:40 PM PDT 24
Peak memory	649248 kb
Host	smart-db3c2c29-78c6-4790-8924-b1b11cf2f518
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520401088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.520401088
Directory	/workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.382516024
Short name	T872
Test name
Test status
Simulation time	3830157020 ps
CPU time	355.33 seconds
Started	Jul 24 08:27:17 PM PDT 24
Finished	Jul 24 08:33:12 PM PDT 24
Peak memory	649204 kb
Host	smart-b2a14f28-6f7a-4c0d-87b0-07f9c01c6fe8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382516024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_s w_alert_handler_lpg_sleep_mode_alerts.382516024
Directory	/workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/55.chip_sw_all_escalation_resets.1976283341
Short name	T885
Test name
Test status
Simulation time	5548867660 ps
CPU time	678.09 seconds
Started	Jul 24 08:26:08 PM PDT 24
Finished	Jul 24 08:37:26 PM PDT 24
Peak memory	650576 kb
Host	smart-e4434c59-43d6-4f1b-a91b-759692959067
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1976283341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.1976283341
Directory	/workspace/55.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2070441336
Short name	T873
Test name
Test status
Simulation time	3279775068 ps
CPU time	412.69 seconds
Started	Jul 24 08:28:29 PM PDT 24
Finished	Jul 24 08:35:22 PM PDT 24
Peak memory	648932 kb
Host	smart-17e1ef2f-258b-4091-ae0b-3965221bc057
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070441336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2070441336
Directory	/workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3123831843
Short name	T877
Test name
Test status
Simulation time	3828264936 ps
CPU time	347.95 seconds
Started	Jul 24 08:22:28 PM PDT 24
Finished	Jul 24 08:28:16 PM PDT 24
Peak memory	649156 kb
Host	smart-e9a9f4cc-d82c-436b-bf4c-0deef0e11a18
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123831843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.3123831843
Directory	/workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3318532004
Short name	T837
Test name
Test status
Simulation time	3040001024 ps
CPU time	348.64 seconds
Started	Jul 24 08:25:53 PM PDT 24
Finished	Jul 24 08:31:42 PM PDT 24
Peak memory	648764 kb
Host	smart-d815f64a-6833-4ecb-9223-ab4294df2e28
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318532004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3318532004
Directory	/workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/60.chip_sw_all_escalation_resets.494698903
Short name	T827
Test name
Test status
Simulation time	5757851400 ps
CPU time	700.66 seconds
Started	Jul 24 08:26:24 PM PDT 24
Finished	Jul 24 08:38:05 PM PDT 24
Peak memory	650552 kb
Host	smart-c33ea653-a889-4b0c-a6a1-b728bab86256
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 494698903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.494698903
Directory	/workspace/60.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2919811668
Short name	T880
Test name
Test status
Simulation time	3955692334 ps
CPU time	311.43 seconds
Started	Jul 24 08:26:26 PM PDT 24
Finished	Jul 24 08:31:38 PM PDT 24
Peak memory	649304 kb
Host	smart-90e4d226-4ec2-4150-ae8b-3415a245a1c4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919811668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2919811668
Directory	/workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/62.chip_sw_all_escalation_resets.343448000
Short name	T829
Test name
Test status
Simulation time	5184642256 ps
CPU time	632.58 seconds
Started	Jul 24 08:25:55 PM PDT 24
Finished	Jul 24 08:36:27 PM PDT 24
Peak memory	650424 kb
Host	smart-ec67b736-0061-4fc7-bda4-d1b76a8f3a52
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 343448000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.343448000
Directory	/workspace/62.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.481751544
Short name	T780
Test name
Test status
Simulation time	3301550422 ps
CPU time	347.46 seconds
Started	Jul 24 08:28:25 PM PDT 24
Finished	Jul 24 08:34:12 PM PDT 24
Peak memory	649424 kb
Host	smart-487b54ec-c663-4d0b-92c0-d0bff821ba70
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481751544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_s w_alert_handler_lpg_sleep_mode_alerts.481751544
Directory	/workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/65.chip_sw_all_escalation_resets.2435308154
Short name	T782
Test name
Test status
Simulation time	5964359670 ps
CPU time	542.97 seconds
Started	Jul 24 08:26:40 PM PDT 24
Finished	Jul 24 08:35:43 PM PDT 24
Peak memory	650372 kb
Host	smart-2461ff29-46b2-4c05-9702-5f172d5f6412
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2435308154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.2435308154
Directory	/workspace/65.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/68.chip_sw_all_escalation_resets.2152967716
Short name	T746
Test name
Test status
Simulation time	5610170824 ps
CPU time	646.78 seconds
Started	Jul 24 08:32:09 PM PDT 24
Finished	Jul 24 08:42:56 PM PDT 24
Peak memory	650792 kb
Host	smart-4c7d3bcc-e304-4301-b7ba-1d74ac88a3f5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2152967716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.2152967716
Directory	/workspace/68.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3396339777
Short name	T854
Test name
Test status
Simulation time	3355976996 ps
CPU time	398.67 seconds
Started	Jul 24 08:28:56 PM PDT 24
Finished	Jul 24 08:35:35 PM PDT 24
Peak memory	649532 kb
Host	smart-a51c5e4d-1d35-4ab5-a1e4-56c1f70fde64
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396339777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3396339777
Directory	/workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1183284477
Short name	T890
Test name
Test status
Simulation time	3743004050 ps
CPU time	412.86 seconds
Started	Jul 24 08:21:28 PM PDT 24
Finished	Jul 24 08:28:21 PM PDT 24
Peak memory	649168 kb
Host	smart-8f0a22dd-80e5-44ef-9a9f-109326264712
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183284477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.1183284477
Directory	/workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/7.chip_sw_all_escalation_resets.2241940922
Short name	T883
Test name
Test status
Simulation time	5086730880 ps
CPU time	825.89 seconds
Started	Jul 24 08:21:04 PM PDT 24
Finished	Jul 24 08:34:51 PM PDT 24
Peak memory	650372 kb
Host	smart-2aeb6f50-4dab-40e3-9efc-fa79878667ca
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2241940922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.2241940922
Directory	/workspace/7.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1031133565
Short name	T852
Test name
Test status
Simulation time	3555354180 ps
CPU time	348.94 seconds
Started	Jul 24 08:27:04 PM PDT 24
Finished	Jul 24 08:32:53 PM PDT 24
Peak memory	649204 kb
Host	smart-dc326e94-737a-4845-ba7a-32945b9accc5
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031133565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1031133565
Directory	/workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1985951161
Short name	T822
Test name
Test status
Simulation time	3882771760 ps
CPU time	551.95 seconds
Started	Jul 24 08:33:35 PM PDT 24
Finished	Jul 24 08:42:47 PM PDT 24
Peak memory	649304 kb
Host	smart-150e27b0-cc0c-4180-86a4-34aaf9a546f0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985951161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1985951161
Directory	/workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/78.chip_sw_all_escalation_resets.3848420231
Short name	T783
Test name
Test status
Simulation time	4674620840 ps
CPU time	608.6 seconds
Started	Jul 24 08:33:41 PM PDT 24
Finished	Jul 24 08:43:49 PM PDT 24
Peak memory	650372 kb
Host	smart-6e5551e6-20eb-46cf-9832-1d367bc2f632
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3848420231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.3848420231
Directory	/workspace/78.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/91.chip_sw_all_escalation_resets.663775040
Short name	T879
Test name
Test status
Simulation time	4210372966 ps
CPU time	573.08 seconds
Started	Jul 24 08:35:48 PM PDT 24
Finished	Jul 24 08:45:21 PM PDT 24
Peak memory	649808 kb
Host	smart-411cb515-ae20-4fd6-8790-aa7cb3885f24
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 663775040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.663775040
Directory	/workspace/91.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/93.chip_sw_all_escalation_resets.1128913774
Short name	T862
Test name
Test status
Simulation time	6170967096 ps
CPU time	570.4 seconds
Started	Jul 24 08:29:17 PM PDT 24
Finished	Jul 24 08:38:47 PM PDT 24
Peak memory	650620 kb
Host	smart-8b51a284-f712-45e3-b85c-9e7343949825
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1128913774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.1128913774
Directory	/workspace/93.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/98.chip_sw_all_escalation_resets.3450649522
Short name	T811
Test name
Test status
Simulation time	4833850280 ps
CPU time	673.01 seconds
Started	Jul 24 08:28:57 PM PDT 24
Finished	Jul 24 08:40:11 PM PDT 24
Peak memory	650408 kb
Host	smart-2e8927a0-6928-42c6-b55e-814c222f347f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3450649522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.3450649522
Directory	/workspace/98.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/99.chip_sw_all_escalation_resets.813005435
Short name	T372
Test name
Test status
Simulation time	5614759076 ps
CPU time	759.16 seconds
Started	Jul 24 08:28:41 PM PDT 24
Finished	Jul 24 08:41:20 PM PDT 24
Peak memory	650220 kb
Host	smart-3e93833c-837b-4550-a115-6dcd727904f4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 813005435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.813005435
Directory	/workspace/99.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all.1090124104
Short name	T2204
Test name
Test status
Simulation time	9391336143 ps
CPU time	303.42 seconds
Started	Jul 24 07:34:20 PM PDT 24
Finished	Jul 24 07:39:24 PM PDT 24
Peak memory	577284 kb
Host	smart-2f49ed1a-c6f3-4809-94a6-9409d3365ec0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090124104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1090124104
Directory	/workspace/10.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.1531229944
Short name	T509
Test name
Test status
Simulation time	39597019972 ps
CPU time	760.42 seconds
Started	Jul 24 07:43:34 PM PDT 24
Finished	Jul 24 07:56:15 PM PDT 24
Peak memory	577160 kb
Host	smart-b794c312-c0d0-4ae3-8402-1a852a1ea1d3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531229944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.1531229944
Directory	/workspace/62.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2644444017
Short name	T351
Test name
Test status
Simulation time	3396997766 ps
CPU time	588.14 seconds
Started	Jul 24 08:00:12 PM PDT 24
Finished	Jul 24 08:10:01 PM PDT 24
Peak memory	610304 kb
Host	smart-9954ee22-8c0d-4147-8653-1655ef0f2f7c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644444017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.2644444017
Directory	/workspace/0.chip_sw_flash_ctrl_ops/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2064868022
Short name	T379
Test name
Test status
Simulation time	5618394344 ps
CPU time	424.97 seconds
Started	Jul 24 08:00:28 PM PDT 24
Finished	Jul 24 08:07:33 PM PDT 24
Peak memory	611620 kb
Host	smart-d13f0d6b-e01a-4f14-a7ce-5780cd0d4973
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2064868022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2064868022
Directory	/workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.502012423
Short name	T335
Test name
Test status
Simulation time	14646589200 ps
CPU time	2151.46 seconds
Started	Jul 24 08:00:20 PM PDT 24
Finished	Jul 24 08:36:12 PM PDT 24
Peak memory	611276 kb
Host	smart-92329322-a6db-4434-905b-bb0fdb4a48f3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=502012423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.502012423
Directory	/workspace/0.chip_sw_rstmgr_alert_info/latest

---

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_10.3146886087
Short name	T155
Test name
Test status
Simulation time	4456418622 ps
CPU time	660.43 seconds
Started	Jul 24 08:19:39 PM PDT 24
Finished	Jul 24 08:30:40 PM PDT 24
Peak memory	609852 kb
Host	smart-a28c343a-1e35-4a04-9a0c-49c7ae0d66d5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146886087 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.3146886087
Directory	/workspace/2.chip_plic_all_irqs_10/latest

---

Test location	/workspace/coverage/default/57.chip_sw_all_escalation_resets.4152771232
Short name	T755
Test name
Test status
Simulation time	4199241592 ps
CPU time	500.72 seconds
Started	Jul 24 08:25:42 PM PDT 24
Finished	Jul 24 08:34:03 PM PDT 24
Peak memory	611080 kb
Host	smart-453a0d20-ebc1-4ead-8461-5005d0de9211
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4152771232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.4152771232
Directory	/workspace/57.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4221032327
Short name	T344
Test name
Test status
Simulation time	5332980572 ps
CPU time	929.5 seconds
Started	Jul 24 07:56:26 PM PDT 24
Finished	Jul 24 08:11:56 PM PDT 24
Peak memory	609888 kb
Host	smart-69f5732f-8d3a-4f7e-8646-be0c2fcbdc1a
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221032327 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.4221032327
Directory	/workspace/0.chip_sw_i2c_host_tx_rx/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pattgen_ios.2615971312
Short name	T359
Test name
Test status
Simulation time	3013557046 ps
CPU time	283.56 seconds
Started	Jul 24 08:02:51 PM PDT 24
Finished	Jul 24 08:07:35 PM PDT 24
Peak memory	611904 kb
Host	smart-54e6bac5-9c07-4d34-93d7-134e19e7e842
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615971312 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.2615971312
Directory	/workspace/1.chip_sw_pattgen_ios/latest

---

Test location	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1720556788
Short name	T788
Test name
Test status
Simulation time	3062317136 ps
CPU time	311.7 seconds
Started	Jul 24 07:58:36 PM PDT 24
Finished	Jul 24 08:03:48 PM PDT 24
Peak memory	609832 kb
Host	smart-1ff24e2f-7b66-4aaf-8927-1646bc2bb59e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720556788 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.1720556788
Directory	/workspace/0.chip_sw_plic_sw_irq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.31864251
Short name	T141
Test name
Test status
Simulation time	7582572811 ps
CPU time	565.42 seconds
Started	Jul 24 07:57:47 PM PDT 24
Finished	Jul 24 08:07:13 PM PDT 24
Peak memory	611108 kb
Host	smart-250c5ae3-4936-4cca-84bc-266b5f5af4fe
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31864251 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.31864251
Directory	/workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2739298790
Short name	T365
Test name
Test status
Simulation time	2944950508 ps
CPU time	333.18 seconds
Started	Jul 24 08:06:22 PM PDT 24
Finished	Jul 24 08:11:56 PM PDT 24
Peak memory	609904 kb
Host	smart-fd53473c-3765-4f75-a7d7-88ccaca74f18
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739298790 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.2739298790
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en/latest

---

Test location	/workspace/coverage/default/2.chip_tap_straps_dev.3330241651
Short name	T763
Test name
Test status
Simulation time	15910934528 ps
CPU time	1684.14 seconds
Started	Jul 24 08:16:52 PM PDT 24
Finished	Jul 24 08:44:57 PM PDT 24
Peak memory	621516 kb
Host	smart-015c2b5a-75e8-4704-b90c-7a09cbf6517f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3330241651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.3330241651
Directory	/workspace/2.chip_tap_straps_dev/latest

---

Test location	/workspace/coverage/cover_reg_top/12.chip_tl_errors.2704349645
Short name	T749
Test name
Test status
Simulation time	3844820074 ps
CPU time	206.66 seconds
Started	Jul 24 07:34:19 PM PDT 24
Finished	Jul 24 07:37:46 PM PDT 24
Peak memory	592268 kb
Host	smart-6ed4e7a9-1b9c-4fd9-b43f-982b8fb388a4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704349645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2704349645
Directory	/workspace/12.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.3009186715
Short name	T477
Test name
Test status
Simulation time	82097170385 ps
CPU time	954.17 seconds
Started	Jul 24 07:35:07 PM PDT 24
Finished	Jul 24 07:51:02 PM PDT 24
Peak memory	576416 kb
Host	smart-9007021a-447c-40ca-a083-6a8355a94139
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009186715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3009186715
Directory	/workspace/15.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3974639863
Short name	T751
Test name
Test status
Simulation time	3646653698 ps
CPU time	307.23 seconds
Started	Jul 24 07:36:05 PM PDT 24
Finished	Jul 24 07:41:12 PM PDT 24
Peak memory	577292 kb
Host	smart-3d1351f6-1e84-4dfe-bde8-27efdd7c2f3a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974639863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3974639863
Directory	/workspace/19.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4142626602
Short name	T1286
Test name
Test status
Simulation time	18705438992 ps
CPU time	735.56 seconds
Started	Jul 24 07:58:06 PM PDT 24
Finished	Jul 24 08:10:23 PM PDT 24
Peak memory	619504 kb
Host	smart-6b2a991b-fbf5-43f9-855c-5e03a185140e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4142626602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4142626602
Directory	/workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

---

Test location	/workspace/coverage/default/1.chip_sw_kmac_entropy.3155503706
Short name	T452
Test name
Test status
Simulation time	2600374100 ps
CPU time	274.62 seconds
Started	Jul 24 08:00:44 PM PDT 24
Finished	Jul 24 08:05:18 PM PDT 24
Peak memory	610008 kb
Host	smart-21414ec7-fa76-41ab-85db-f2654ccb0bd0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155503706 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.3155503706
Directory	/workspace/1.chip_sw_kmac_entropy/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.678544440
Short name	T163
Test name
Test status
Simulation time	2048423520 ps
CPU time	188.67 seconds
Started	Jul 24 08:00:06 PM PDT 24
Finished	Jul 24 08:03:16 PM PDT 24
Peak memory	622132 kb
Host	smart-3efd61ee-a401-4993-a9af-2c1c7ff5a776
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678544440 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.678544440
Directory	/workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest

---

Test location	/workspace/coverage/default/2.chip_jtag_csr_rw.181941812
Short name	T52
Test name
Test status
Simulation time	17347433665 ps
CPU time	2060.8 seconds
Started	Jul 24 08:09:03 PM PDT 24
Finished	Jul 24 08:43:25 PM PDT 24
Peak memory	604340 kb
Host	smart-73d00637-5780-4d2b-9c77-9e8827ad2bce
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181941812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_jtag_csr_rw.181941812
Directory	/workspace/2.chip_jtag_csr_rw/latest

---

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3248095588
Short name	T229
Test name
Test status
Simulation time	16518429054 ps
CPU time	4106.51 seconds
Started	Jul 24 08:02:16 PM PDT 24
Finished	Jul 24 09:10:43 PM PDT 24
Peak memory	610264 kb
Host	smart-18770e7d-78cc-4e93-8212-1852ebd5576e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32480 95588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.3248095588
Directory	/workspace/0.chip_sw_keymgr_sideload_otbn/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3272809357
Short name	T168
Test name
Test status
Simulation time	4688389632 ps
CPU time	591.83 seconds
Started	Jul 24 08:00:11 PM PDT 24
Finished	Jul 24 08:10:03 PM PDT 24
Peak memory	611452 kb
Host	smart-17f036f6-035c-4191-8c5b-3ab1f2430136
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3272809357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.3272809357
Directory	/workspace/0.chip_sw_lc_ctrl_program_error/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2452379148
Short name	T107
Test name
Test status
Simulation time	49455791392 ps
CPU time	5790.42 seconds
Started	Jul 24 07:59:46 PM PDT 24
Finished	Jul 24 09:36:18 PM PDT 24
Peak memory	620940 kb
Host	smart-1a3cf16a-ca29-4b1c-82e0-5cc30ef783d8
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452379148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.2452379148
Directory	/workspace/0.chip_sw_lc_walkthrough_prod/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3481896428
Short name	T1199
Test name
Test status
Simulation time	24722059326 ps
CPU time	3925.43 seconds
Started	Jul 24 07:59:42 PM PDT 24
Finished	Jul 24 09:05:09 PM PDT 24
Peak memory	610676 kb
Host	smart-c0e84851-4c92-4766-ba39-2af4f9893e79
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481896428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3481896428
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.756156317
Short name	T1161
Test name
Test status
Simulation time	6455945974 ps
CPU time	365.58 seconds
Started	Jul 24 07:55:51 PM PDT 24
Finished	Jul 24 08:01:57 PM PDT 24
Peak memory	617760 kb
Host	smart-8675b188-6cb5-452b-86ac-c6563fcb9820
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=756156317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.756156317
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2785247163
Short name	T181
Test name
Test status
Simulation time	6550802518 ps
CPU time	714.79 seconds
Started	Jul 24 07:59:34 PM PDT 24
Finished	Jul 24 08:11:29 PM PDT 24
Peak memory	610040 kb
Host	smart-2895e8d9-9af5-4655-bc90-3e7f61460aff
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785247163 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.2785247163
Directory	/workspace/0.chip_sw_sram_ctrl_execution_main/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all.3140095180
Short name	T508
Test name
Test status
Simulation time	4497393523 ps
CPU time	148.64 seconds
Started	Jul 24 07:32:38 PM PDT 24
Finished	Jul 24 07:35:07 PM PDT 24
Peak memory	576476 kb
Host	smart-cef83102-42ec-4869-8654-bf739110d61a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140095180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3140095180
Directory	/workspace/0.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/16.chip_tl_errors.3324254610
Short name	T794
Test name
Test status
Simulation time	4034623300 ps
CPU time	221.99 seconds
Started	Jul 24 07:35:28 PM PDT 24
Finished	Jul 24 07:39:10 PM PDT 24
Peak memory	600548 kb
Host	smart-61af0d08-7a98-44c1-bc38-b208d8fe6015
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324254610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.3324254610
Directory	/workspace/16.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_access_same_device.3633145351
Short name	T935
Test name
Test status
Simulation time	2122831120 ps
CPU time	84.73 seconds
Started	Jul 24 07:35:43 PM PDT 24
Finished	Jul 24 07:37:08 PM PDT 24
Peak memory	576068 kb
Host	smart-16efdb3c-fa60-4ce6-8275-7032a07221fa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633145351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .3633145351
Directory	/workspace/17.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_error_random.1062981225
Short name	T690
Test name
Test status
Simulation time	2017606138 ps
CPU time	64.4 seconds
Started	Jul 24 07:36:34 PM PDT 24
Finished	Jul 24 07:37:39 PM PDT 24
Peak memory	576260 kb
Host	smart-c14c4a7e-e239-492b-b6c5-56a5d20c2396
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062981225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1062981225
Directory	/workspace/22.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2065487886
Short name	T682
Test name
Test status
Simulation time	3999127186 ps
CPU time	389.59 seconds
Started	Jul 24 07:37:48 PM PDT 24
Finished	Jul 24 07:44:18 PM PDT 24
Peak memory	576456 kb
Host	smart-e55beba4-e6db-4ec2-85d6-3b4af340c717
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065487886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.2065487886
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2017275526
Short name	T699
Test name
Test status
Simulation time	2448377050 ps
CPU time	338.33 seconds
Started	Jul 24 07:38:18 PM PDT 24
Finished	Jul 24 07:43:56 PM PDT 24
Peak memory	577188 kb
Host	smart-37136986-e3ba-41da-98b6-8552c4341a3e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017275526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.2017275526
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1601506223
Short name	T674
Test name
Test status
Simulation time	726075966 ps
CPU time	225.14 seconds
Started	Jul 24 07:39:57 PM PDT 24
Finished	Jul 24 07:43:42 PM PDT 24
Peak memory	577136 kb
Host	smart-a0815c37-d9e5-4c9f-ada1-cf16288860a9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601506223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.1601506223
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.918062902
Short name	T676
Test name
Test status
Simulation time	7537625476 ps
CPU time	231.53 seconds
Started	Jul 24 07:42:33 PM PDT 24
Finished	Jul 24 07:46:24 PM PDT 24
Peak memory	577212 kb
Host	smart-7c501e01-73ac-4ff8-8e68-5203d5f52e7a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918062902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.918062902
Directory	/workspace/54.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.3245420783
Short name	T689
Test name
Test status
Simulation time	13850682029 ps
CPU time	454.09 seconds
Started	Jul 24 07:42:30 PM PDT 24
Finished	Jul 24 07:50:05 PM PDT 24
Peak memory	577148 kb
Host	smart-ebe63374-4b8d-4318-b2ec-be1ce9875184
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245420783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.3245420783
Directory	/workspace/55.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.46679754
Short name	T760
Test name
Test status
Simulation time	3008534128 ps
CPU time	103.64 seconds
Started	Jul 24 07:46:18 PM PDT 24
Finished	Jul 24 07:48:02 PM PDT 24
Peak memory	577144 kb
Host	smart-d5d14cb2-c0f8-4233-a1ab-5772a1b814cb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46679754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.46679754
Directory	/workspace/79.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.169356282
Short name	T540
Test name
Test status
Simulation time	4623102348 ps
CPU time	937.38 seconds
Started	Jul 24 08:01:23 PM PDT 24
Finished	Jul 24 08:17:01 PM PDT 24
Peak memory	609828 kb
Host	smart-9a14a0fa-7cce-4066-a26b-559ffc8d546c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16935 6282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.169356282
Directory	/workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1259590262
Short name	T350
Test name
Test status
Simulation time	3146661492 ps
CPU time	481.95 seconds
Started	Jul 24 08:08:42 PM PDT 24
Finished	Jul 24 08:16:44 PM PDT 24
Peak memory	609908 kb
Host	smart-91888053-74f8-4384-ba6a-d035f42351cb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259590262 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.1259590262
Directory	/workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4172139986
Short name	T336
Test name
Test status
Simulation time	14565260760 ps
CPU time	1732.61 seconds
Started	Jul 24 08:18:20 PM PDT 24
Finished	Jul 24 08:47:13 PM PDT 24
Peak memory	611256 kb
Host	smart-59dc73ca-4fcf-435a-90cd-e990f31bd248
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=4172139986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.4172139986
Directory	/workspace/2.chip_sw_rstmgr_alert_info/latest

---

Test location	/workspace/coverage/default/0.chip_tap_straps_testunlock0.4209103772
Short name	T71
Test name
Test status
Simulation time	5204036526 ps
CPU time	468.25 seconds
Started	Jul 24 08:00:13 PM PDT 24
Finished	Jul 24 08:08:01 PM PDT 24
Peak memory	632124 kb
Host	smart-1d6fd996-f02f-498e-b219-56a9def060b0
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209103772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.4209103772
Directory	/workspace/0.chip_tap_straps_testunlock0/latest

---

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2504351018
Short name	T1545
Test name
Test status
Simulation time	31752929014 ps
CPU time	6642.96 seconds
Started	Jul 24 07:32:23 PM PDT 24
Finished	Jul 24 09:23:07 PM PDT 24
Peak memory	594580 kb
Host	smart-7a3776ed-4bf6-4c55-a499-ed04ba945b13
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504351018 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.2504351018
Directory	/workspace/1.chip_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2007078825
Short name	T132
Test name
Test status
Simulation time	5719285752 ps
CPU time	323.71 seconds
Started	Jul 24 07:32:42 PM PDT 24
Finished	Jul 24 07:38:06 PM PDT 24
Peak memory	663772 kb
Host	smart-3ac0f8da-6b85-48bf-a5cb-f1c0ccbef50e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007078825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.2007078825
Directory	/workspace/1.chip_csr_hw_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3666295139
Short name	T743
Test name
Test status
Simulation time	3040744720 ps
CPU time	432.5 seconds
Started	Jul 24 07:57:44 PM PDT 24
Finished	Jul 24 08:04:57 PM PDT 24
Peak memory	609880 kb
Host	smart-7999dc75-415d-4f15-b7e5-91b74234c2d2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666295139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.3666295139
Directory	/workspace/0.chip_sw_edn_boot_mode/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2170207374
Short name	T1174
Test name
Test status
Simulation time	8862398390 ps
CPU time	566.68 seconds
Started	Jul 24 07:58:15 PM PDT 24
Finished	Jul 24 08:07:42 PM PDT 24
Peak memory	610976 kb
Host	smart-292231b9-0908-4e30-b1b5-2aaf82aed455
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170207374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.2170207374
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1380060420
Short name	T400
Test name
Test status
Simulation time	24732646280 ps
CPU time	7043.42 seconds
Started	Jul 24 08:04:45 PM PDT 24
Finished	Jul 24 10:02:10 PM PDT 24
Peak memory	610032 kb
Host	smart-5e754160-d105-410c-9070-9d275e3c27d0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1380060420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1380060420
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest

---

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2988703012
Short name	T1926
Test name
Test status
Simulation time	39195557125 ps
CPU time	6672.53 seconds
Started	Jul 24 07:32:13 PM PDT 24
Finished	Jul 24 09:23:26 PM PDT 24
Peak memory	594448 kb
Host	smart-9f0498b3-b05c-48d3-829f-0241d8a8950e
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988703012 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.2988703012
Directory	/workspace/0.chip_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1124725823
Short name	T2178
Test name
Test status
Simulation time	6520309032 ps
CPU time	476.33 seconds
Started	Jul 24 07:32:27 PM PDT 24
Finished	Jul 24 07:40:23 PM PDT 24
Peak memory	593436 kb
Host	smart-8a880928-61d1-438f-b856-d9116c8c11f4
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124725823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.1124725823
Directory	/workspace/0.chip_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1208818295
Short name	T396
Test name
Test status
Simulation time	5667184015 ps
CPU time	377.81 seconds
Started	Jul 24 07:32:22 PM PDT 24
Finished	Jul 24 07:38:40 PM PDT 24
Peak memory	638308 kb
Host	smart-61bea90b-72bc-4c8a-a93e-b3cf9aad4333
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208818295 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.1208818295
Directory	/workspace/0.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_rw.1310050982
Short name	T2421
Test name
Test status
Simulation time	3948104440 ps
CPU time	312.07 seconds
Started	Jul 24 07:32:21 PM PDT 24
Finished	Jul 24 07:37:33 PM PDT 24
Peak memory	599544 kb
Host	smart-6b921e28-abe9-4a6a-af08-4e9f558a6ca9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310050982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1310050982
Directory	/workspace/0.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3157623806
Short name	T1809
Test name
Test status
Simulation time	7281211718 ps
CPU time	362.23 seconds
Started	Jul 24 07:32:26 PM PDT 24
Finished	Jul 24 07:38:29 PM PDT 24
Peak memory	590504 kb
Host	smart-2f4e1dff-149a-4839-9cb9-3fa8e80c73ec
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157623806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.3157623806
Directory	/workspace/0.chip_prim_tl_access/latest

---

Test location	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2293664621
Short name	T1444
Test name
Test status
Simulation time	18696762212 ps
CPU time	581.87 seconds
Started	Jul 24 07:32:26 PM PDT 24
Finished	Jul 24 07:42:08 PM PDT 24
Peak memory	592028 kb
Host	smart-a2aa14aa-9c3b-4c72-821e-512974795964
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293664621 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.2293664621
Directory	/workspace/0.chip_rv_dm_lc_disabled/latest

---

Test location	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1193672842
Short name	T2352
Test name
Test status
Simulation time	31973806368 ps
CPU time	4614.66 seconds
Started	Jul 24 07:32:13 PM PDT 24
Finished	Jul 24 08:49:08 PM PDT 24
Peak memory	593536 kb
Host	smart-706ba0d9-0735-44f9-9a24-16d779dfe6c3
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193672842 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1193672842
Directory	/workspace/0.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/0.chip_tl_errors.1684368709
Short name	T747
Test name
Test status
Simulation time	3430619248 ps
CPU time	228.69 seconds
Started	Jul 24 07:32:27 PM PDT 24
Finished	Jul 24 07:36:16 PM PDT 24
Peak memory	600476 kb
Host	smart-a09bf5c9-b196-4f36-9872-59b6305558e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684368709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1684368709
Directory	/workspace/0.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1064362976
Short name	T2086
Test name
Test status
Simulation time	552849981 ps
CPU time	19.92 seconds
Started	Jul 24 07:32:35 PM PDT 24
Finished	Jul 24 07:32:55 PM PDT 24
Peak memory	576180 kb
Host	smart-1df30c1c-7245-4307-b170-5a67648853ce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064362976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 1064362976
Directory	/workspace/0.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1846596190
Short name	T912
Test name
Test status
Simulation time	61507652197 ps
CPU time	950.7 seconds
Started	Jul 24 07:32:35 PM PDT 24
Finished	Jul 24 07:48:26 PM PDT 24
Peak memory	577128 kb
Host	smart-b395e950-3609-4364-a1fe-64eaedb233d1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846596190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.1846596190
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1159377544
Short name	T1608
Test name
Test status
Simulation time	72137524 ps
CPU time	6.19 seconds
Started	Jul 24 07:32:25 PM PDT 24
Finished	Jul 24 07:32:31 PM PDT 24
Peak memory	574908 kb
Host	smart-c6ba5d9f-de23-46df-8765-0fdf9644592a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159377544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .1159377544
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_error_random.1651925913
Short name	T2547
Test name
Test status
Simulation time	73925773 ps
CPU time	8.16 seconds
Started	Jul 24 07:32:38 PM PDT 24
Finished	Jul 24 07:32:47 PM PDT 24
Peak memory	576988 kb
Host	smart-4d348473-26d8-437a-b3dd-430d9dee7caa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651925913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1651925913
Directory	/workspace/0.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_random.1312516447
Short name	T695
Test name
Test status
Simulation time	788942633 ps
CPU time	30.68 seconds
Started	Jul 24 07:32:32 PM PDT 24
Finished	Jul 24 07:33:02 PM PDT 24
Peak memory	576156 kb
Host	smart-8dba7577-ad13-4b1e-a3e0-0bc43cb5ce89
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312516447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.1312516447
Directory	/workspace/0.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2614246908
Short name	T1911
Test name
Test status
Simulation time	87598463480 ps
CPU time	902.71 seconds
Started	Jul 24 07:32:38 PM PDT 24
Finished	Jul 24 07:47:41 PM PDT 24
Peak memory	577152 kb
Host	smart-57adea84-7b04-4440-adcb-5e5a258d63bc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614246908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2614246908
Directory	/workspace/0.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1913653763
Short name	T1861
Test name
Test status
Simulation time	3159564534 ps
CPU time	51.88 seconds
Started	Jul 24 07:32:22 PM PDT 24
Finished	Jul 24 07:33:14 PM PDT 24
Peak memory	575068 kb
Host	smart-72d50c46-f864-4864-993b-583affc8783b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913653763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1913653763
Directory	/workspace/0.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.323935525
Short name	T2393
Test name
Test status
Simulation time	170898062 ps
CPU time	16.88 seconds
Started	Jul 24 07:32:35 PM PDT 24
Finished	Jul 24 07:32:52 PM PDT 24
Peak memory	576132 kb
Host	smart-7b3fd3e6-908c-4334-9802-2d40655835a1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323935525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delay s.323935525
Directory	/workspace/0.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_same_source.930792794
Short name	T1894
Test name
Test status
Simulation time	248733752 ps
CPU time	19.08 seconds
Started	Jul 24 07:32:22 PM PDT 24
Finished	Jul 24 07:32:41 PM PDT 24
Peak memory	576884 kb
Host	smart-0c1eca93-f8e9-41a1-99cd-2efa70a837b2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930792794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.930792794
Directory	/workspace/0.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke.2656679711
Short name	T1696
Test name
Test status
Simulation time	32156517 ps
CPU time	5.36 seconds
Started	Jul 24 07:32:32 PM PDT 24
Finished	Jul 24 07:32:38 PM PDT 24
Peak memory	574876 kb
Host	smart-c86833ef-ad30-462c-9786-09db6f490925
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656679711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2656679711
Directory	/workspace/0.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2957539317
Short name	T2863
Test name
Test status
Simulation time	8424938087 ps
CPU time	85.45 seconds
Started	Jul 24 07:32:25 PM PDT 24
Finished	Jul 24 07:33:50 PM PDT 24
Peak memory	575060 kb
Host	smart-05a1c654-f0ea-4e4e-ac76-40d26efffc36
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957539317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2957539317
Directory	/workspace/0.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3833797430
Short name	T1737
Test name
Test status
Simulation time	5683250286 ps
CPU time	92.98 seconds
Started	Jul 24 07:32:25 PM PDT 24
Finished	Jul 24 07:33:58 PM PDT 24
Peak memory	575008 kb
Host	smart-2d62f13c-3aa3-44d9-9ef8-efa1453e6518
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833797430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3833797430
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1273011843
Short name	T2592
Test name
Test status
Simulation time	43487929 ps
CPU time	5.76 seconds
Started	Jul 24 07:32:20 PM PDT 24
Finished	Jul 24 07:32:26 PM PDT 24
Peak memory	574856 kb
Host	smart-b1e35ed3-4f21-4d0a-bd47-d43648b64ea0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273011843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .1273011843
Directory	/workspace/0.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3182465664
Short name	T2621
Test name
Test status
Simulation time	2491165937 ps
CPU time	80.45 seconds
Started	Jul 24 07:32:39 PM PDT 24
Finished	Jul 24 07:33:59 PM PDT 24
Peak memory	577140 kb
Host	smart-f264b768-1525-4c98-bf1a-97adecfb95c3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182465664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3182465664
Directory	/workspace/0.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.122783431
Short name	T2903
Test name
Test status
Simulation time	6761120901 ps
CPU time	369.29 seconds
Started	Jul 24 07:32:30 PM PDT 24
Finished	Jul 24 07:38:39 PM PDT 24
Peak memory	576412 kb
Host	smart-7a70dc17-848b-4340-a8a7-00d1b4ad0605
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122783431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_w ith_rand_reset.122783431
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2718390556
Short name	T2141
Test name
Test status
Simulation time	331081823 ps
CPU time	102.57 seconds
Started	Jul 24 07:32:34 PM PDT 24
Finished	Jul 24 07:34:16 PM PDT 24
Peak memory	577124 kb
Host	smart-d8dfc286-3c34-4eba-a281-c4aa8ceee346
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718390556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.2718390556
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2826724318
Short name	T2551
Test name
Test status
Simulation time	309542107 ps
CPU time	37.63 seconds
Started	Jul 24 07:32:38 PM PDT 24
Finished	Jul 24 07:33:16 PM PDT 24
Peak memory	577076 kb
Host	smart-e81245e8-1dec-4e98-8e58-aa2c021d977d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826724318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2826724318
Directory	/workspace/0.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.191106036
Short name	T1948
Test name
Test status
Simulation time	11335652976 ps
CPU time	1360.66 seconds
Started	Jul 24 07:32:32 PM PDT 24
Finished	Jul 24 07:55:13 PM PDT 24
Peak memory	593012 kb
Host	smart-9befa900-7ffa-4c11-91df-b7ec2bb2e46c
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191106036 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.191106036
Directory	/workspace/1.chip_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3427744144
Short name	T1750
Test name
Test status
Simulation time	9441802644 ps
CPU time	865.81 seconds
Started	Jul 24 07:33:04 PM PDT 24
Finished	Jul 24 07:47:30 PM PDT 24
Peak memory	653808 kb
Host	smart-09444721-5110-4fc6-a157-e7844a7104d3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427744144 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.3427744144
Directory	/workspace/1.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_rw.494644801
Short name	T2463
Test name
Test status
Simulation time	5767811829 ps
CPU time	512.05 seconds
Started	Jul 24 07:32:57 PM PDT 24
Finished	Jul 24 07:41:29 PM PDT 24
Peak memory	599472 kb
Host	smart-0de4992c-7931-4859-b2ca-560b55245ef5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494644801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.494644801
Directory	/workspace/1.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2810112697
Short name	T2097
Test name
Test status
Simulation time	3099061655 ps
CPU time	121.79 seconds
Started	Jul 24 07:32:40 PM PDT 24
Finished	Jul 24 07:34:42 PM PDT 24
Peak memory	590108 kb
Host	smart-83e13154-31e9-47b7-a7f9-a23f37364cb6
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810112697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.2810112697
Directory	/workspace/1.chip_prim_tl_access/latest

---

Test location	/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.76430079
Short name	T1916
Test name
Test status
Simulation time	9767186531 ps
CPU time	520.83 seconds
Started	Jul 24 07:32:43 PM PDT 24
Finished	Jul 24 07:41:24 PM PDT 24
Peak memory	591840 kb
Host	smart-a822bf8c-5af1-4847-90db-90fd611a81c7
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76430079 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.chip_rv_dm_lc_disabled.76430079
Directory	/workspace/1.chip_rv_dm_lc_disabled/latest

---

Test location	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1244756430
Short name	T444
Test name
Test status
Simulation time	15509068756 ps
CPU time	1732.32 seconds
Started	Jul 24 07:32:32 PM PDT 24
Finished	Jul 24 08:01:26 PM PDT 24
Peak memory	593896 kb
Host	smart-bd1e337a-4bee-444f-8640-d4cbbbccbf60
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244756430 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.1244756430
Directory	/workspace/1.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/1.chip_tl_errors.339188923
Short name	T567
Test name
Test status
Simulation time	2883177779 ps
CPU time	221.74 seconds
Started	Jul 24 07:32:39 PM PDT 24
Finished	Jul 24 07:36:21 PM PDT 24
Peak memory	604532 kb
Host	smart-2e0389ca-db53-49e2-9a1f-06a81bdcb260
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339188923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.339188923
Directory	/workspace/1.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_access_same_device.464195880
Short name	T2521
Test name
Test status
Simulation time	15866810 ps
CPU time	6.55 seconds
Started	Jul 24 07:32:48 PM PDT 24
Finished	Jul 24 07:32:55 PM PDT 24
Peak memory	574908 kb
Host	smart-24d4e765-9313-4942-aa5e-83eaef1b4c5c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464195880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.464195880
Directory	/workspace/1.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3239722691
Short name	T2806
Test name
Test status
Simulation time	70600801215 ps
CPU time	1252.52 seconds
Started	Jul 24 07:32:42 PM PDT 24
Finished	Jul 24 07:53:34 PM PDT 24
Peak memory	577148 kb
Host	smart-07d07ad1-1182-4e72-a03d-5127abef2354
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239722691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.3239722691
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1910280717
Short name	T2389
Test name
Test status
Simulation time	163494389 ps
CPU time	18.81 seconds
Started	Jul 24 07:32:42 PM PDT 24
Finished	Jul 24 07:33:01 PM PDT 24
Peak memory	575880 kb
Host	smart-691bd34f-3555-4c67-9a27-b3b2c2063404
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910280717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .1910280717
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_error_random.2900182468
Short name	T1447
Test name
Test status
Simulation time	534378629 ps
CPU time	41.8 seconds
Started	Jul 24 07:32:56 PM PDT 24
Finished	Jul 24 07:33:38 PM PDT 24
Peak memory	576152 kb
Host	smart-c677ef1a-fef7-45e8-8289-eab345fc5838
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900182468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2900182468
Directory	/workspace/1.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_random.2407264567
Short name	T1479
Test name
Test status
Simulation time	267948242 ps
CPU time	25.34 seconds
Started	Jul 24 07:32:48 PM PDT 24
Finished	Jul 24 07:33:14 PM PDT 24
Peak memory	576172 kb
Host	smart-e309f248-d8a1-4748-8ae6-95c1e3807e86
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407264567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.2407264567
Directory	/workspace/1.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2390310926
Short name	T709
Test name
Test status
Simulation time	70523288173 ps
CPU time	758.47 seconds
Started	Jul 24 07:32:39 PM PDT 24
Finished	Jul 24 07:45:18 PM PDT 24
Peak memory	576252 kb
Host	smart-858f0ff6-1589-41f2-a0a1-d1976bb2c5d4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390310926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2390310926
Directory	/workspace/1.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.4011381980
Short name	T2578
Test name
Test status
Simulation time	56968130223 ps
CPU time	1063.61 seconds
Started	Jul 24 07:32:39 PM PDT 24
Finished	Jul 24 07:50:23 PM PDT 24
Peak memory	576320 kb
Host	smart-3964655c-957e-4ad1-b72e-9f930ecdab49
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011381980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.4011381980
Directory	/workspace/1.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.440507711
Short name	T2857
Test name
Test status
Simulation time	54814183 ps
CPU time	8.57 seconds
Started	Jul 24 07:32:57 PM PDT 24
Finished	Jul 24 07:33:06 PM PDT 24
Peak memory	574960 kb
Host	smart-b6ff9817-970c-498a-b24f-5faa9b8b6654
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440507711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delay s.440507711
Directory	/workspace/1.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_same_source.125982846
Short name	T2188
Test name
Test status
Simulation time	97768554 ps
CPU time	10.47 seconds
Started	Jul 24 07:32:39 PM PDT 24
Finished	Jul 24 07:32:50 PM PDT 24
Peak memory	576952 kb
Host	smart-48f3b52b-9b13-4a3a-8cca-7d6f527cc99f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125982846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.125982846
Directory	/workspace/1.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke.250216838
Short name	T1883
Test name
Test status
Simulation time	38080694 ps
CPU time	6.18 seconds
Started	Jul 24 07:32:49 PM PDT 24
Finished	Jul 24 07:32:56 PM PDT 24
Peak memory	574836 kb
Host	smart-d812d419-9b9a-4ea6-8ec1-73cdb4001a9a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250216838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.250216838
Directory	/workspace/1.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2196753108
Short name	T2001
Test name
Test status
Simulation time	6533842692 ps
CPU time	63.56 seconds
Started	Jul 24 07:32:57 PM PDT 24
Finished	Jul 24 07:34:01 PM PDT 24
Peak memory	575020 kb
Host	smart-d3418a6c-2d65-49f0-bf0a-1d089f44b5e5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196753108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2196753108
Directory	/workspace/1.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1480326820
Short name	T2228
Test name
Test status
Simulation time	5210003763 ps
CPU time	85.01 seconds
Started	Jul 24 07:32:46 PM PDT 24
Finished	Jul 24 07:34:11 PM PDT 24
Peak memory	574964 kb
Host	smart-ba0c5772-d30b-4145-8e3f-29c9f8bcbb81
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480326820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1480326820
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1280475521
Short name	T2595
Test name
Test status
Simulation time	47350695 ps
CPU time	6.69 seconds
Started	Jul 24 07:32:58 PM PDT 24
Finished	Jul 24 07:33:04 PM PDT 24
Peak memory	574956 kb
Host	smart-fa522629-4dd2-4a7a-a1e8-3fe9294146b4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280475521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .1280475521
Directory	/workspace/1.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1324487172
Short name	T2392
Test name
Test status
Simulation time	2166899938 ps
CPU time	81.08 seconds
Started	Jul 24 07:32:40 PM PDT 24
Finished	Jul 24 07:34:02 PM PDT 24
Peak memory	577064 kb
Host	smart-eb8c74fa-6bb0-40a0-9562-694f3feb649e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324487172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1324487172
Directory	/workspace/1.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3757806193
Short name	T2358
Test name
Test status
Simulation time	1198034164 ps
CPU time	359.33 seconds
Started	Jul 24 07:32:57 PM PDT 24
Finished	Jul 24 07:38:56 PM PDT 24
Peak memory	576364 kb
Host	smart-94f6241c-0da3-4a3a-99e7-c7e84d2f60e4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757806193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.3757806193
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2427384942
Short name	T1554
Test name
Test status
Simulation time	8324602845 ps
CPU time	725.76 seconds
Started	Jul 24 07:32:43 PM PDT 24
Finished	Jul 24 07:44:49 PM PDT 24
Peak memory	577104 kb
Host	smart-f2fa8bfd-f274-45f2-80da-0efa2d8479d5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427384942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.2427384942
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.894704476
Short name	T2003
Test name
Test status
Simulation time	58635975 ps
CPU time	9.69 seconds
Started	Jul 24 07:32:57 PM PDT 24
Finished	Jul 24 07:33:07 PM PDT 24
Peak memory	577048 kb
Host	smart-bae631ce-e8c8-41a1-bd7e-c5abce5c6e42
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894704476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.894704476
Directory	/workspace/1.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/10.chip_csr_rw.3638162395
Short name	T2435
Test name
Test status
Simulation time	4576136260 ps
CPU time	304.29 seconds
Started	Jul 24 07:34:30 PM PDT 24
Finished	Jul 24 07:39:34 PM PDT 24
Peak memory	598188 kb
Host	smart-73c0e80c-299d-41be-826f-932b23afcde6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638162395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.3638162395
Directory	/workspace/10.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3624808318
Short name	T2370
Test name
Test status
Simulation time	16105680494 ps
CPU time	1736.57 seconds
Started	Jul 24 07:34:09 PM PDT 24
Finished	Jul 24 08:03:07 PM PDT 24
Peak memory	593872 kb
Host	smart-8ff0a20a-aea3-4678-9f51-7e0e41604b40
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624808318 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.3624808318
Directory	/workspace/10.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/10.chip_tl_errors.2552021493
Short name	T568
Test name
Test status
Simulation time	3952101380 ps
CPU time	216.93 seconds
Started	Jul 24 07:34:08 PM PDT 24
Finished	Jul 24 07:37:45 PM PDT 24
Peak memory	604564 kb
Host	smart-7d838967-d392-4441-90fd-90385f203a40
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552021493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.2552021493
Directory	/workspace/10.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1517853267
Short name	T901
Test name
Test status
Simulation time	218255167 ps
CPU time	17.3 seconds
Started	Jul 24 07:34:28 PM PDT 24
Finished	Jul 24 07:34:46 PM PDT 24
Peak memory	577104 kb
Host	smart-317ad125-fdd7-4911-b0f8-74e2c0f81071
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517853267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .1517853267
Directory	/workspace/10.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2520655522
Short name	T2340
Test name
Test status
Simulation time	279330254 ps
CPU time	26.5 seconds
Started	Jul 24 07:34:30 PM PDT 24
Finished	Jul 24 07:34:57 PM PDT 24
Peak memory	577096 kb
Host	smart-7096b4ff-f130-45b4-a1f5-f82f9efa58f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520655522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.2520655522
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_error_random.4049859720
Short name	T1533
Test name
Test status
Simulation time	57190347 ps
CPU time	7.89 seconds
Started	Jul 24 07:34:12 PM PDT 24
Finished	Jul 24 07:34:20 PM PDT 24
Peak memory	574980 kb
Host	smart-c09d0932-0e17-4a73-8950-362041acd197
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049859720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4049859720
Directory	/workspace/10.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_random.3859626015
Short name	T1885
Test name
Test status
Simulation time	2139524785 ps
CPU time	71.22 seconds
Started	Jul 24 07:34:27 PM PDT 24
Finished	Jul 24 07:35:38 PM PDT 24
Peak memory	576260 kb
Host	smart-8f034e10-48d7-44b0-a2f7-2fb1c1b94acf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859626015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.3859626015
Directory	/workspace/10.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.291257390
Short name	T2249
Test name
Test status
Simulation time	31923004694 ps
CPU time	322.63 seconds
Started	Jul 24 07:34:26 PM PDT 24
Finished	Jul 24 07:39:49 PM PDT 24
Peak memory	576432 kb
Host	smart-8956f1c9-a321-4a44-8794-847ddac909ee
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291257390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.291257390
Directory	/workspace/10.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3632144504
Short name	T1560
Test name
Test status
Simulation time	21156498406 ps
CPU time	381.43 seconds
Started	Jul 24 07:34:11 PM PDT 24
Finished	Jul 24 07:40:32 PM PDT 24
Peak memory	577144 kb
Host	smart-696f69aa-3a85-4a79-9365-09498ca18d1a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632144504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3632144504
Directory	/workspace/10.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1352153801
Short name	T2865
Test name
Test status
Simulation time	263666241 ps
CPU time	24.86 seconds
Started	Jul 24 07:34:09 PM PDT 24
Finished	Jul 24 07:34:34 PM PDT 24
Peak memory	576232 kb
Host	smart-4493f2f2-cfcf-4cb7-90d5-a95f6136a66b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352153801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.1352153801
Directory	/workspace/10.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_same_source.305262008
Short name	T2483
Test name
Test status
Simulation time	981924719 ps
CPU time	29.53 seconds
Started	Jul 24 07:34:10 PM PDT 24
Finished	Jul 24 07:34:40 PM PDT 24
Peak memory	576112 kb
Host	smart-d05133c4-bdb0-46ce-9d22-f5bfb307b8b6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305262008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.305262008
Directory	/workspace/10.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke.844078482
Short name	T2631
Test name
Test status
Simulation time	226791778 ps
CPU time	10.53 seconds
Started	Jul 24 07:34:05 PM PDT 24
Finished	Jul 24 07:34:16 PM PDT 24
Peak memory	574892 kb
Host	smart-a094e9bc-2917-4824-bcb6-9b5854c2c958
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844078482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.844078482
Directory	/workspace/10.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.29031642
Short name	T2883
Test name
Test status
Simulation time	9170493824 ps
CPU time	94.4 seconds
Started	Jul 24 07:34:08 PM PDT 24
Finished	Jul 24 07:35:42 PM PDT 24
Peak memory	575084 kb
Host	smart-bb9284e2-9888-46c0-8f8a-716b09f2a7c6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29031642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.29031642
Directory	/workspace/10.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.510012406
Short name	T2445
Test name
Test status
Simulation time	5694543764 ps
CPU time	91.14 seconds
Started	Jul 24 07:34:30 PM PDT 24
Finished	Jul 24 07:36:01 PM PDT 24
Peak memory	576364 kb
Host	smart-725ce037-1219-4c1e-a97f-f4ffeda59639
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510012406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.510012406
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.356403444
Short name	T1527
Test name
Test status
Simulation time	54170772 ps
CPU time	6.83 seconds
Started	Jul 24 07:34:14 PM PDT 24
Finished	Jul 24 07:34:21 PM PDT 24
Peak memory	576152 kb
Host	smart-fcb0dc2d-dfc8-4a72-b7ab-1cafe225dd3e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356403444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays .356403444
Directory	/workspace/10.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1178249611
Short name	T2226
Test name
Test status
Simulation time	6060375195 ps
CPU time	216.21 seconds
Started	Jul 24 07:34:15 PM PDT 24
Finished	Jul 24 07:37:51 PM PDT 24
Peak memory	577228 kb
Host	smart-6fdd636c-d955-42a6-825a-acdc2190148c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178249611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1178249611
Directory	/workspace/10.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3449281467
Short name	T571
Test name
Test status
Simulation time	292673936 ps
CPU time	153.38 seconds
Started	Jul 24 07:34:26 PM PDT 24
Finished	Jul 24 07:36:59 PM PDT 24
Peak memory	576448 kb
Host	smart-d7e3ea6e-3b64-495e-bd05-1cee526feb89
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449281467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.3449281467
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2849870943
Short name	T2300
Test name
Test status
Simulation time	3709091462 ps
CPU time	392.5 seconds
Started	Jul 24 07:34:07 PM PDT 24
Finished	Jul 24 07:40:40 PM PDT 24
Peak memory	577256 kb
Host	smart-06f17d90-0612-400b-9cdc-f1a5b628b8df
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849870943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.2849870943
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.404753201
Short name	T1576
Test name
Test status
Simulation time	353904807 ps
CPU time	16.42 seconds
Started	Jul 24 07:34:14 PM PDT 24
Finished	Jul 24 07:34:30 PM PDT 24
Peak memory	576152 kb
Host	smart-815af038-cc0d-4bbc-aae7-ecf2b32d1d84
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404753201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.404753201
Directory	/workspace/10.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.420724594
Short name	T2501
Test name
Test status
Simulation time	7066705892 ps
CPU time	406.33 seconds
Started	Jul 24 07:34:31 PM PDT 24
Finished	Jul 24 07:41:17 PM PDT 24
Peak memory	639356 kb
Host	smart-902a0ec3-110a-40e3-a595-7ed3b7bcce71
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420724594 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.420724594
Directory	/workspace/11.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/11.chip_csr_rw.478347828
Short name	T2268
Test name
Test status
Simulation time	3688593448 ps
CPU time	309.4 seconds
Started	Jul 24 07:34:41 PM PDT 24
Finished	Jul 24 07:39:51 PM PDT 24
Peak memory	597772 kb
Host	smart-1ffb3a72-aeb3-436d-80d1-a5792b4c7687
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478347828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.478347828
Directory	/workspace/11.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3636922365
Short name	T2350
Test name
Test status
Simulation time	15447540351 ps
CPU time	1863.64 seconds
Started	Jul 24 07:34:28 PM PDT 24
Finished	Jul 24 08:05:32 PM PDT 24
Peak memory	593856 kb
Host	smart-77cb5c44-0bca-4c7d-a014-deee1e06055d
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636922365 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.3636922365
Directory	/workspace/11.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/11.chip_tl_errors.1777161385
Short name	T791
Test name
Test status
Simulation time	2936781229 ps
CPU time	247.48 seconds
Started	Jul 24 07:34:28 PM PDT 24
Finished	Jul 24 07:38:36 PM PDT 24
Peak memory	600524 kb
Host	smart-13e51faa-5dd3-42e8-b105-14fdec728640
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777161385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.1777161385
Directory	/workspace/11.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2706202761
Short name	T898
Test name
Test status
Simulation time	1370389123 ps
CPU time	53.72 seconds
Started	Jul 24 07:34:18 PM PDT 24
Finished	Jul 24 07:35:12 PM PDT 24
Peak memory	576160 kb
Host	smart-8c28580d-5307-4e5d-a7fc-a59b66acd957
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706202761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .2706202761
Directory	/workspace/11.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1822294005
Short name	T2502
Test name
Test status
Simulation time	81849175486 ps
CPU time	1344.02 seconds
Started	Jul 24 07:34:17 PM PDT 24
Finished	Jul 24 07:56:41 PM PDT 24
Peak memory	577160 kb
Host	smart-0317852a-2190-4249-8965-cbe815973f61
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822294005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.1822294005
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2622495547
Short name	T1901
Test name
Test status
Simulation time	195602605 ps
CPU time	21.98 seconds
Started	Jul 24 07:34:18 PM PDT 24
Finished	Jul 24 07:34:40 PM PDT 24
Peak memory	576176 kb
Host	smart-5faecd11-6d15-47b2-a490-eaeabd68b74f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622495547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.2622495547
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_error_random.4163878559
Short name	T1802
Test name
Test status
Simulation time	1430536845 ps
CPU time	41.01 seconds
Started	Jul 24 07:34:18 PM PDT 24
Finished	Jul 24 07:34:59 PM PDT 24
Peak memory	577000 kb
Host	smart-9d8adb7b-5667-45ff-8287-d2a300c54d30
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163878559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.4163878559
Directory	/workspace/11.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_random.1248369052
Short name	T622
Test name
Test status
Simulation time	553168118 ps
CPU time	44.52 seconds
Started	Jul 24 07:34:18 PM PDT 24
Finished	Jul 24 07:35:03 PM PDT 24
Peak memory	576168 kb
Host	smart-ef3bf6ee-5e6e-4c00-b168-5f0d068a948a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248369052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1248369052
Directory	/workspace/11.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3175248704
Short name	T2669
Test name
Test status
Simulation time	40594468294 ps
CPU time	397.03 seconds
Started	Jul 24 07:34:42 PM PDT 24
Finished	Jul 24 07:41:19 PM PDT 24
Peak memory	576432 kb
Host	smart-596f79c4-e136-4397-b8db-af4b8dc58a9b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175248704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3175248704
Directory	/workspace/11.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.586034649
Short name	T2705
Test name
Test status
Simulation time	55560368432 ps
CPU time	893.67 seconds
Started	Jul 24 07:34:31 PM PDT 24
Finished	Jul 24 07:49:25 PM PDT 24
Peak memory	577116 kb
Host	smart-d7cdbcbf-6928-40b2-9e75-b2b99953e176
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586034649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.586034649
Directory	/workspace/11.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1115581434
Short name	T2931
Test name
Test status
Simulation time	519031713 ps
CPU time	49.05 seconds
Started	Jul 24 07:34:17 PM PDT 24
Finished	Jul 24 07:35:06 PM PDT 24
Peak memory	576128 kb
Host	smart-13ae2c01-9f0e-471e-bd85-4696643d1c56
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115581434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.1115581434
Directory	/workspace/11.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_same_source.102202241
Short name	T577
Test name
Test status
Simulation time	1358163408 ps
CPU time	37.66 seconds
Started	Jul 24 07:34:42 PM PDT 24
Finished	Jul 24 07:35:20 PM PDT 24
Peak memory	576260 kb
Host	smart-c21719d8-0b93-4576-8fa0-1be4dae986a1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102202241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.102202241
Directory	/workspace/11.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke.908506479
Short name	T1607
Test name
Test status
Simulation time	51411148 ps
CPU time	6.36 seconds
Started	Jul 24 07:34:21 PM PDT 24
Finished	Jul 24 07:34:27 PM PDT 24
Peak memory	574896 kb
Host	smart-d34be81f-836c-4a85-bfc4-5befd472548f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908506479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.908506479
Directory	/workspace/11.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4014653429
Short name	T1688
Test name
Test status
Simulation time	6115709013 ps
CPU time	63.5 seconds
Started	Jul 24 07:34:16 PM PDT 24
Finished	Jul 24 07:35:20 PM PDT 24
Peak memory	576280 kb
Host	smart-3c855821-5b05-450c-8de6-597077ef2fee
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014653429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.4014653429
Directory	/workspace/11.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2346908902
Short name	T1600
Test name
Test status
Simulation time	5803808824 ps
CPU time	104.89 seconds
Started	Jul 24 07:34:16 PM PDT 24
Finished	Jul 24 07:36:01 PM PDT 24
Peak memory	575044 kb
Host	smart-76c7dfb9-4212-4984-ab4d-5c82c692bc49
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346908902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2346908902
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3466531012
Short name	T2020
Test name
Test status
Simulation time	58729029 ps
CPU time	6.96 seconds
Started	Jul 24 07:34:17 PM PDT 24
Finished	Jul 24 07:34:24 PM PDT 24
Peak memory	574972 kb
Host	smart-d55ac0ae-5337-40d0-bd2c-32bca8db3a99
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466531012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.3466531012
Directory	/workspace/11.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all.3635465358
Short name	T535
Test name
Test status
Simulation time	2410663722 ps
CPU time	90.76 seconds
Started	Jul 24 07:34:30 PM PDT 24
Finished	Jul 24 07:36:01 PM PDT 24
Peak memory	576420 kb
Host	smart-3a6bd09d-a36f-46f4-b69c-a9d3a9e813c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635465358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3635465358
Directory	/workspace/11.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.689249333
Short name	T2478
Test name
Test status
Simulation time	9070148055 ps
CPU time	279.83 seconds
Started	Jul 24 07:34:42 PM PDT 24
Finished	Jul 24 07:39:22 PM PDT 24
Peak memory	576480 kb
Host	smart-a093ff63-22ca-404b-936f-4e232942d1a9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689249333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.689249333
Directory	/workspace/11.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3690639094
Short name	T1624
Test name
Test status
Simulation time	781060723 ps
CPU time	311.86 seconds
Started	Jul 24 07:34:15 PM PDT 24
Finished	Jul 24 07:39:27 PM PDT 24
Peak memory	577180 kb
Host	smart-451d477e-e79e-4682-aeb5-53f7e6da1d00
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690639094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.3690639094
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2177639659
Short name	T2414
Test name
Test status
Simulation time	2639824534 ps
CPU time	225.66 seconds
Started	Jul 24 07:34:40 PM PDT 24
Finished	Jul 24 07:38:26 PM PDT 24
Peak memory	577372 kb
Host	smart-510b04f5-1d6b-400a-9185-6dbe3d04d26a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177639659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.2177639659
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1758866072
Short name	T2897
Test name
Test status
Simulation time	235885408 ps
CPU time	11.59 seconds
Started	Jul 24 07:34:30 PM PDT 24
Finished	Jul 24 07:34:42 PM PDT 24
Peak memory	576184 kb
Host	smart-a9eb7bd0-be3d-475e-890f-01914bba43c0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758866072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1758866072
Directory	/workspace/11.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2157866284
Short name	T406
Test name
Test status
Simulation time	8203512767 ps
CPU time	718.1 seconds
Started	Jul 24 07:34:28 PM PDT 24
Finished	Jul 24 07:46:26 PM PDT 24
Peak memory	653652 kb
Host	smart-dd99f38f-43d1-443f-b922-e0ddbc81e968
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157866284 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.2157866284
Directory	/workspace/12.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/12.chip_csr_rw.1720041049
Short name	T2332
Test name
Test status
Simulation time	5324028710 ps
CPU time	509.1 seconds
Started	Jul 24 07:34:27 PM PDT 24
Finished	Jul 24 07:42:56 PM PDT 24
Peak memory	599172 kb
Host	smart-2eec1c1a-29fb-43d1-a61e-b89831acb9d1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720041049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.1720041049
Directory	/workspace/12.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1683639428
Short name	T2790
Test name
Test status
Simulation time	27490291198 ps
CPU time	3758.82 seconds
Started	Jul 24 07:34:18 PM PDT 24
Finished	Jul 24 08:36:57 PM PDT 24
Peak memory	594096 kb
Host	smart-890fa0d1-1cf5-47a0-acd7-13777d27889c
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683639428 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.1683639428
Directory	/workspace/12.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1077690897
Short name	T2068
Test name
Test status
Simulation time	225221017 ps
CPU time	13.59 seconds
Started	Jul 24 07:34:30 PM PDT 24
Finished	Jul 24 07:34:44 PM PDT 24
Peak memory	576112 kb
Host	smart-d04e1978-5e94-4d76-8a44-f2f79c0b00cd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077690897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .1077690897
Directory	/workspace/12.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3980738540
Short name	T1747
Test name
Test status
Simulation time	18130851498 ps
CPU time	298.07 seconds
Started	Jul 24 07:34:26 PM PDT 24
Finished	Jul 24 07:39:25 PM PDT 24
Peak memory	576324 kb
Host	smart-cc542dc5-1b0a-44e6-bd67-a818bbe4c214
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980738540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.3980738540
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2993681071
Short name	T2057
Test name
Test status
Simulation time	241086909 ps
CPU time	12.78 seconds
Started	Jul 24 07:34:27 PM PDT 24
Finished	Jul 24 07:34:40 PM PDT 24
Peak memory	577012 kb
Host	smart-770c62b1-3976-47f7-9aa2-49adced62ecb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993681071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.2993681071
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_error_random.1420388798
Short name	T1518
Test name
Test status
Simulation time	722492384 ps
CPU time	24.66 seconds
Started	Jul 24 07:34:29 PM PDT 24
Finished	Jul 24 07:34:54 PM PDT 24
Peak memory	576120 kb
Host	smart-f96a9dba-f1f2-4356-83d9-ceed2e6590d4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420388798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1420388798
Directory	/workspace/12.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_random.3256237698
Short name	T2437
Test name
Test status
Simulation time	2126916693 ps
CPU time	68.24 seconds
Started	Jul 24 07:34:30 PM PDT 24
Finished	Jul 24 07:35:39 PM PDT 24
Peak memory	577008 kb
Host	smart-e1861aac-b647-4f9f-8573-24ca638da466
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256237698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.3256237698
Directory	/workspace/12.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.4059212847
Short name	T1742
Test name
Test status
Simulation time	95931774149 ps
CPU time	1051.04 seconds
Started	Jul 24 07:34:29 PM PDT 24
Finished	Jul 24 07:52:01 PM PDT 24
Peak memory	576280 kb
Host	smart-c613569b-383a-4eef-a1e0-74f5984f5a42
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059212847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.4059212847
Directory	/workspace/12.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.215867834
Short name	T1465
Test name
Test status
Simulation time	14559939474 ps
CPU time	250.89 seconds
Started	Jul 24 07:34:29 PM PDT 24
Finished	Jul 24 07:38:40 PM PDT 24
Peak memory	576396 kb
Host	smart-2e23b200-5da1-4681-9c7b-934d4bb084dd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215867834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.215867834
Directory	/workspace/12.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3787455068
Short name	T2856
Test name
Test status
Simulation time	125044739 ps
CPU time	13.01 seconds
Started	Jul 24 07:34:29 PM PDT 24
Finished	Jul 24 07:34:42 PM PDT 24
Peak memory	577080 kb
Host	smart-87ed33e5-fa8a-473a-8529-05514486a173
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787455068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.3787455068
Directory	/workspace/12.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_same_source.3884248834
Short name	T2402
Test name
Test status
Simulation time	2600127063 ps
CPU time	72.9 seconds
Started	Jul 24 07:34:43 PM PDT 24
Finished	Jul 24 07:35:56 PM PDT 24
Peak memory	576384 kb
Host	smart-fc9269d7-5a37-4b96-8f8a-967135675f30
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884248834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3884248834
Directory	/workspace/12.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke.274168958
Short name	T1540
Test name
Test status
Simulation time	240456548 ps
CPU time	9.03 seconds
Started	Jul 24 07:34:42 PM PDT 24
Finished	Jul 24 07:34:51 PM PDT 24
Peak memory	574988 kb
Host	smart-4a27fe93-379d-43c2-8390-b6a65ee1bc2f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274168958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.274168958
Directory	/workspace/12.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2996623910
Short name	T1480
Test name
Test status
Simulation time	5332035482 ps
CPU time	56.16 seconds
Started	Jul 24 07:34:23 PM PDT 24
Finished	Jul 24 07:35:20 PM PDT 24
Peak memory	574964 kb
Host	smart-6b61c439-ba30-4066-9c99-fe10dbd712e8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996623910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2996623910
Directory	/workspace/12.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.42614168
Short name	T2837
Test name
Test status
Simulation time	4812390787 ps
CPU time	82.77 seconds
Started	Jul 24 07:34:42 PM PDT 24
Finished	Jul 24 07:36:05 PM PDT 24
Peak memory	575096 kb
Host	smart-63add6bc-71df-44ae-a8d9-7bf1d42bf91b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42614168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.42614168
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1258272500
Short name	T1913
Test name
Test status
Simulation time	43024320 ps
CPU time	6.35 seconds
Started	Jul 24 07:34:30 PM PDT 24
Finished	Jul 24 07:34:36 PM PDT 24
Peak memory	576232 kb
Host	smart-c8266a49-b940-454c-bc8d-43025940dc9c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258272500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.1258272500
Directory	/workspace/12.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all.4145901409
Short name	T1985
Test name
Test status
Simulation time	12033941709 ps
CPU time	594.82 seconds
Started	Jul 24 07:34:31 PM PDT 24
Finished	Jul 24 07:44:26 PM PDT 24
Peak memory	576436 kb
Host	smart-93b84d5f-375f-42df-b104-ead29def4d33
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145901409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.4145901409
Directory	/workspace/12.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4094676563
Short name	T2714
Test name
Test status
Simulation time	6634123653 ps
CPU time	207.56 seconds
Started	Jul 24 07:34:43 PM PDT 24
Finished	Jul 24 07:38:10 PM PDT 24
Peak memory	577352 kb
Host	smart-6c749fa4-a666-4f65-a6db-735136d0ee0e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094676563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.4094676563
Directory	/workspace/12.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1704952693
Short name	T2417
Test name
Test status
Simulation time	273217775 ps
CPU time	152.37 seconds
Started	Jul 24 07:34:29 PM PDT 24
Finished	Jul 24 07:37:01 PM PDT 24
Peak memory	576368 kb
Host	smart-5c28b912-3297-43ca-b0bf-00b4b4289450
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704952693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.1704952693
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2136260633
Short name	T2642
Test name
Test status
Simulation time	1882042561 ps
CPU time	215.3 seconds
Started	Jul 24 07:34:29 PM PDT 24
Finished	Jul 24 07:38:04 PM PDT 24
Peak memory	576280 kb
Host	smart-c64a3cc7-ec8f-4850-bf26-97403973d9eb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136260633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.2136260633
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3216940256
Short name	T1778
Test name
Test status
Simulation time	102030159 ps
CPU time	13.08 seconds
Started	Jul 24 07:34:28 PM PDT 24
Finished	Jul 24 07:34:42 PM PDT 24
Peak memory	577008 kb
Host	smart-fb815add-8d66-4cfb-bd8c-675023ba044a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216940256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3216940256
Directory	/workspace/12.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3494397876
Short name	T2080
Test name
Test status
Simulation time	4619173463 ps
CPU time	450.61 seconds
Started	Jul 24 07:34:47 PM PDT 24
Finished	Jul 24 07:42:18 PM PDT 24
Peak memory	645328 kb
Host	smart-f2f46a4e-4e52-4843-aa5d-8b92c0944f2a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494397876 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.3494397876
Directory	/workspace/13.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/13.chip_csr_rw.889221637
Short name	T145
Test name
Test status
Simulation time	5664068736 ps
CPU time	525.16 seconds
Started	Jul 24 07:34:40 PM PDT 24
Finished	Jul 24 07:43:25 PM PDT 24
Peak memory	599264 kb
Host	smart-6616d687-b30f-4af4-8df9-e96bd26793b1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889221637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.889221637
Directory	/workspace/13.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3447853829
Short name	T2694
Test name
Test status
Simulation time	15492555871 ps
CPU time	1650.38 seconds
Started	Jul 24 07:34:44 PM PDT 24
Finished	Jul 24 08:02:14 PM PDT 24
Peak memory	594048 kb
Host	smart-3ed3491a-cd6f-45e2-938d-f3aa2f254263
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447853829 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.3447853829
Directory	/workspace/13.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2729305679
Short name	T2670
Test name
Test status
Simulation time	157645690 ps
CPU time	8.43 seconds
Started	Jul 24 07:34:43 PM PDT 24
Finished	Jul 24 07:34:52 PM PDT 24
Peak memory	574816 kb
Host	smart-98fb6616-8c13-4d16-8687-a03ed7cd65d3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729305679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .2729305679
Directory	/workspace/13.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.742184197
Short name	T2659
Test name
Test status
Simulation time	21113261629 ps
CPU time	353.35 seconds
Started	Jul 24 07:34:42 PM PDT 24
Finished	Jul 24 07:40:35 PM PDT 24
Peak memory	577160 kb
Host	smart-76058b4d-f22f-4d99-b968-1f139d78b508
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742184197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_d evice_slow_rsp.742184197
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1681969713
Short name	T2214
Test name
Test status
Simulation time	254915515 ps
CPU time	14.89 seconds
Started	Jul 24 07:34:39 PM PDT 24
Finished	Jul 24 07:34:54 PM PDT 24
Peak memory	576956 kb
Host	smart-d6bf8d00-2936-483c-95ad-7ae3e9cb2a20
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681969713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.1681969713
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_error_random.3499017370
Short name	T2362
Test name
Test status
Simulation time	41882278 ps
CPU time	6.05 seconds
Started	Jul 24 07:34:39 PM PDT 24
Finished	Jul 24 07:34:45 PM PDT 24
Peak memory	576060 kb
Host	smart-b07a99cd-6cb1-4c39-97bd-1de315b35042
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499017370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3499017370
Directory	/workspace/13.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_random.475764521
Short name	T2365
Test name
Test status
Simulation time	1750355655 ps
CPU time	69.71 seconds
Started	Jul 24 07:34:39 PM PDT 24
Finished	Jul 24 07:35:49 PM PDT 24
Peak memory	576208 kb
Host	smart-284d7110-082f-478c-9db0-4166d557d9d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475764521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.475764521
Directory	/workspace/13.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3142409106
Short name	T2735
Test name
Test status
Simulation time	59211300598 ps
CPU time	570.79 seconds
Started	Jul 24 07:34:40 PM PDT 24
Finished	Jul 24 07:44:11 PM PDT 24
Peak memory	577140 kb
Host	smart-489c6030-c5cc-4797-a9be-447370fc0518
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142409106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3142409106
Directory	/workspace/13.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2951739941
Short name	T1897
Test name
Test status
Simulation time	2369403652 ps
CPU time	40.06 seconds
Started	Jul 24 07:34:43 PM PDT 24
Finished	Jul 24 07:35:24 PM PDT 24
Peak memory	576148 kb
Host	smart-183fd8e8-56bb-411d-a3e8-c6dc3864eb98
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951739941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2951739941
Directory	/workspace/13.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3752970714
Short name	T2224
Test name
Test status
Simulation time	441354329 ps
CPU time	38.8 seconds
Started	Jul 24 07:34:41 PM PDT 24
Finished	Jul 24 07:35:20 PM PDT 24
Peak memory	576188 kb
Host	smart-dff0a2ad-41c1-46b4-b917-c8e7136fd6c2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752970714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.3752970714
Directory	/workspace/13.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_same_source.1210134118
Short name	T2307
Test name
Test status
Simulation time	223916861 ps
CPU time	19.08 seconds
Started	Jul 24 07:34:39 PM PDT 24
Finished	Jul 24 07:34:59 PM PDT 24
Peak memory	576996 kb
Host	smart-48afe1b4-10f1-4c8d-8f93-fa7091d82de3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210134118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1210134118
Directory	/workspace/13.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke.2093597819
Short name	T1552
Test name
Test status
Simulation time	41936408 ps
CPU time	5.53 seconds
Started	Jul 24 07:34:32 PM PDT 24
Finished	Jul 24 07:34:38 PM PDT 24
Peak memory	574916 kb
Host	smart-3605163c-a5b8-4b42-b49e-2279798beb07
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093597819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2093597819
Directory	/workspace/13.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.896071379
Short name	T1814
Test name
Test status
Simulation time	9150322631 ps
CPU time	101.73 seconds
Started	Jul 24 07:34:38 PM PDT 24
Finished	Jul 24 07:36:19 PM PDT 24
Peak memory	575004 kb
Host	smart-fab4f7fd-e0b0-4af2-af30-a4361cd90955
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896071379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.896071379
Directory	/workspace/13.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2445027291
Short name	T707
Test name
Test status
Simulation time	6237752170 ps
CPU time	102.36 seconds
Started	Jul 24 07:34:43 PM PDT 24
Finished	Jul 24 07:36:26 PM PDT 24
Peak memory	575080 kb
Host	smart-77144bce-c4ac-4cf7-abd8-e6f02fabf4e6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445027291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2445027291
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.153375835
Short name	T1453
Test name
Test status
Simulation time	49560577 ps
CPU time	5.91 seconds
Started	Jul 24 07:34:33 PM PDT 24
Finished	Jul 24 07:34:39 PM PDT 24
Peak memory	574888 kb
Host	smart-09faa121-5c0b-4f92-a941-87cb49c7e47e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153375835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays .153375835
Directory	/workspace/13.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all.1437793496
Short name	T528
Test name
Test status
Simulation time	2552120705 ps
CPU time	221.89 seconds
Started	Jul 24 07:34:41 PM PDT 24
Finished	Jul 24 07:38:23 PM PDT 24
Peak memory	576448 kb
Host	smart-678b7f19-67d6-46ff-9f64-9a7f4ae2f8d4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437793496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1437793496
Directory	/workspace/13.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.4213142347
Short name	T2130
Test name
Test status
Simulation time	7710309673 ps
CPU time	307.14 seconds
Started	Jul 24 07:34:39 PM PDT 24
Finished	Jul 24 07:39:46 PM PDT 24
Peak memory	576428 kb
Host	smart-fb2b36eb-b981-44ab-9ef6-b5aed5398673
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213142347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4213142347
Directory	/workspace/13.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1905980498
Short name	T2082
Test name
Test status
Simulation time	1698564109 ps
CPU time	247.66 seconds
Started	Jul 24 07:34:41 PM PDT 24
Finished	Jul 24 07:38:49 PM PDT 24
Peak memory	577176 kb
Host	smart-f3153f5b-d50d-4c7e-8d3c-c271530d6ed5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905980498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.1905980498
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1348457385
Short name	T1564
Test name
Test status
Simulation time	101913640 ps
CPU time	16.4 seconds
Started	Jul 24 07:34:39 PM PDT 24
Finished	Jul 24 07:34:55 PM PDT 24
Peak memory	577004 kb
Host	smart-f51d7301-d599-44fc-bc3f-e55670831727
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348457385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1348457385
Directory	/workspace/13.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3762508421
Short name	T2715
Test name
Test status
Simulation time	6391386577 ps
CPU time	543.92 seconds
Started	Jul 24 07:35:07 PM PDT 24
Finished	Jul 24 07:44:11 PM PDT 24
Peak memory	641316 kb
Host	smart-490691ad-616a-470c-af82-dbf41278812b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762508421 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.3762508421
Directory	/workspace/14.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/14.chip_csr_rw.1107905956
Short name	T1974
Test name
Test status
Simulation time	4745090533 ps
CPU time	299.36 seconds
Started	Jul 24 07:35:08 PM PDT 24
Finished	Jul 24 07:40:07 PM PDT 24
Peak memory	598888 kb
Host	smart-7baa10e9-630a-416f-a3a6-59e61b85e61d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107905956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.1107905956
Directory	/workspace/14.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.407292163
Short name	T1588
Test name
Test status
Simulation time	28454425524 ps
CPU time	3734.71 seconds
Started	Jul 24 07:34:49 PM PDT 24
Finished	Jul 24 08:37:04 PM PDT 24
Peak memory	594352 kb
Host	smart-2cb556bb-4b5a-4a2d-b539-c672abdce656
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407292163 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.chip_same_csr_outstanding.407292163
Directory	/workspace/14.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/14.chip_tl_errors.364493503
Short name	T793
Test name
Test status
Simulation time	3400916956 ps
CPU time	177.63 seconds
Started	Jul 24 07:34:48 PM PDT 24
Finished	Jul 24 07:37:46 PM PDT 24
Peak memory	598340 kb
Host	smart-bb91b795-2b4e-4296-8392-76de0ac3b4a3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364493503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.364493503
Directory	/workspace/14.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2948300572
Short name	T2702
Test name
Test status
Simulation time	245213706 ps
CPU time	33.6 seconds
Started	Jul 24 07:35:00 PM PDT 24
Finished	Jul 24 07:35:34 PM PDT 24
Peak memory	576928 kb
Host	smart-f745986c-243c-4654-b1cc-049a06454c37
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948300572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .2948300572
Directory	/workspace/14.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.966533416
Short name	T2764
Test name
Test status
Simulation time	110186576992 ps
CPU time	1943.88 seconds
Started	Jul 24 07:34:57 PM PDT 24
Finished	Jul 24 08:07:22 PM PDT 24
Peak memory	576372 kb
Host	smart-8b5d4518-5981-436f-b36a-29adc0c8c40b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966533416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_d evice_slow_rsp.966533416
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.4257388755
Short name	T2409
Test name
Test status
Simulation time	202697752 ps
CPU time	11.57 seconds
Started	Jul 24 07:35:01 PM PDT 24
Finished	Jul 24 07:35:13 PM PDT 24
Peak memory	576104 kb
Host	smart-a504a2b1-1744-4869-a665-7518cf48193a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257388755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.4257388755
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_error_random.2754546432
Short name	T2899
Test name
Test status
Simulation time	940826205 ps
CPU time	35.35 seconds
Started	Jul 24 07:35:02 PM PDT 24
Finished	Jul 24 07:35:38 PM PDT 24
Peak memory	576120 kb
Host	smart-e53f1395-bf64-496d-add5-e1a3b858b55a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754546432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2754546432
Directory	/workspace/14.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_random.3660877492
Short name	T1553
Test name
Test status
Simulation time	316441324 ps
CPU time	28.12 seconds
Started	Jul 24 07:34:56 PM PDT 24
Finished	Jul 24 07:35:25 PM PDT 24
Peak memory	577100 kb
Host	smart-a87e57a0-8293-42d3-a342-cbdfc1c830c3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660877492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.3660877492
Directory	/workspace/14.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3468231066
Short name	T2667
Test name
Test status
Simulation time	9224818369 ps
CPU time	95.62 seconds
Started	Jul 24 07:34:57 PM PDT 24
Finished	Jul 24 07:36:33 PM PDT 24
Peak memory	576336 kb
Host	smart-438a32b4-7f7d-4a14-8bd4-d0a407c0e4c7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468231066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3468231066
Directory	/workspace/14.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.139792276
Short name	T613
Test name
Test status
Simulation time	63180537818 ps
CPU time	1050.41 seconds
Started	Jul 24 07:35:00 PM PDT 24
Finished	Jul 24 07:52:30 PM PDT 24
Peak memory	577184 kb
Host	smart-d50fedac-f8ea-46a2-9705-89a87a4490b8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139792276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.139792276
Directory	/workspace/14.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2304263356
Short name	T2429
Test name
Test status
Simulation time	127187787 ps
CPU time	14.44 seconds
Started	Jul 24 07:34:58 PM PDT 24
Finished	Jul 24 07:35:13 PM PDT 24
Peak memory	576084 kb
Host	smart-72c06060-0297-4148-9be3-07104012eae2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304263356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.2304263356
Directory	/workspace/14.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_same_source.4167174724
Short name	T491
Test name
Test status
Simulation time	1810152131 ps
CPU time	58.64 seconds
Started	Jul 24 07:34:58 PM PDT 24
Finished	Jul 24 07:35:57 PM PDT 24
Peak memory	576220 kb
Host	smart-a03f94e8-62c8-49a3-917e-246896e9693d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167174724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4167174724
Directory	/workspace/14.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke.2753009850
Short name	T1458
Test name
Test status
Simulation time	177360818 ps
CPU time	8.41 seconds
Started	Jul 24 07:34:49 PM PDT 24
Finished	Jul 24 07:34:57 PM PDT 24
Peak memory	574984 kb
Host	smart-5cc76410-90ba-47be-9d07-d1db07aafaa8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753009850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2753009850
Directory	/workspace/14.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3076251604
Short name	T2824
Test name
Test status
Simulation time	5594890113 ps
CPU time	57.08 seconds
Started	Jul 24 07:34:50 PM PDT 24
Finished	Jul 24 07:35:47 PM PDT 24
Peak memory	575036 kb
Host	smart-b0377256-7d9a-467e-a1fb-9d91daf68ae9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076251604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3076251604
Directory	/workspace/14.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2185751874
Short name	T1548
Test name
Test status
Simulation time	4242391987 ps
CPU time	62.86 seconds
Started	Jul 24 07:34:47 PM PDT 24
Finished	Jul 24 07:35:50 PM PDT 24
Peak memory	576208 kb
Host	smart-62f27d8c-2bff-485f-9bbb-3614af255ede
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185751874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2185751874
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.536397424
Short name	T587
Test name
Test status
Simulation time	47855466 ps
CPU time	6.12 seconds
Started	Jul 24 07:34:47 PM PDT 24
Finished	Jul 24 07:34:53 PM PDT 24
Peak memory	574952 kb
Host	smart-ce29f687-788a-4195-91a7-50215c1eb455
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536397424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays .536397424
Directory	/workspace/14.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all.2491376350
Short name	T2026
Test name
Test status
Simulation time	2126736994 ps
CPU time	96.16 seconds
Started	Jul 24 07:34:59 PM PDT 24
Finished	Jul 24 07:36:36 PM PDT 24
Peak memory	577172 kb
Host	smart-3db7e053-ff4b-4259-8843-5735462ee163
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491376350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2491376350
Directory	/workspace/14.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.4149391390
Short name	T1592
Test name
Test status
Simulation time	1839004103 ps
CPU time	138.04 seconds
Started	Jul 24 07:35:02 PM PDT 24
Finished	Jul 24 07:37:20 PM PDT 24
Peak memory	576308 kb
Host	smart-0c2d1077-40bf-47a0-9fb5-5cc782d01711
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149391390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.4149391390
Directory	/workspace/14.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2995905631
Short name	T2834
Test name
Test status
Simulation time	2249112314 ps
CPU time	176.62 seconds
Started	Jul 24 07:35:00 PM PDT 24
Finished	Jul 24 07:37:57 PM PDT 24
Peak memory	576488 kb
Host	smart-150a9e03-f544-4d11-ba2a-796accd64eff
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995905631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.2995905631
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.238815484
Short name	T2543
Test name
Test status
Simulation time	404369558 ps
CPU time	122.54 seconds
Started	Jul 24 07:35:09 PM PDT 24
Finished	Jul 24 07:37:12 PM PDT 24
Peak memory	576336 kb
Host	smart-8c728e54-aa16-4ebb-a4db-8557062d854a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238815484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_reset_error.238815484
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3361604150
Short name	T2782
Test name
Test status
Simulation time	1239680757 ps
CPU time	49.95 seconds
Started	Jul 24 07:34:57 PM PDT 24
Finished	Jul 24 07:35:47 PM PDT 24
Peak memory	577048 kb
Host	smart-6e13b12e-7235-47f6-beb5-a12cdc8efdfc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361604150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3361604150
Directory	/workspace/14.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1333204500
Short name	T2029
Test name
Test status
Simulation time	6410990775 ps
CPU time	478.43 seconds
Started	Jul 24 07:35:25 PM PDT 24
Finished	Jul 24 07:43:23 PM PDT 24
Peak memory	645808 kb
Host	smart-e68ebdd8-07b2-4563-8976-1ceea7abb9e3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333204500 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.1333204500
Directory	/workspace/15.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/15.chip_csr_rw.2416221753
Short name	T2127
Test name
Test status
Simulation time	5875398974 ps
CPU time	566.08 seconds
Started	Jul 24 07:35:21 PM PDT 24
Finished	Jul 24 07:44:47 PM PDT 24
Peak memory	598628 kb
Host	smart-f7206ecf-bd64-4877-91e9-739ae2498d8b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416221753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.2416221753
Directory	/workspace/15.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3689409734
Short name	T2397
Test name
Test status
Simulation time	32893218744 ps
CPU time	4878.03 seconds
Started	Jul 24 07:35:08 PM PDT 24
Finished	Jul 24 08:56:27 PM PDT 24
Peak memory	594032 kb
Host	smart-c341a4a0-007d-4b83-8280-3cc15f429d68
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689409734 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3689409734
Directory	/workspace/15.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_access_same_device.813615765
Short name	T2448
Test name
Test status
Simulation time	1860563732 ps
CPU time	69.66 seconds
Started	Jul 24 07:35:10 PM PDT 24
Finished	Jul 24 07:36:20 PM PDT 24
Peak memory	576272 kb
Host	smart-35f1f4b2-d44a-4412-a2d0-a579b4228781
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813615765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device. 813615765
Directory	/workspace/15.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3637915127
Short name	T2841
Test name
Test status
Simulation time	23253146316 ps
CPU time	380.97 seconds
Started	Jul 24 07:35:09 PM PDT 24
Finished	Jul 24 07:41:30 PM PDT 24
Peak memory	576228 kb
Host	smart-5cdc4325-1f0b-4791-994b-f3041ae94761
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637915127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.3637915127
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3076978794
Short name	T1704
Test name
Test status
Simulation time	1484448602 ps
CPU time	61.3 seconds
Started	Jul 24 07:35:27 PM PDT 24
Finished	Jul 24 07:36:28 PM PDT 24
Peak memory	576112 kb
Host	smart-4590d6ca-d5ea-4b2f-9271-109e1f4e8608
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076978794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.3076978794
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_error_random.462541709
Short name	T2548
Test name
Test status
Simulation time	426195251 ps
CPU time	18.3 seconds
Started	Jul 24 07:35:05 PM PDT 24
Finished	Jul 24 07:35:24 PM PDT 24
Peak memory	576984 kb
Host	smart-cdb945e1-713b-4fd4-bd8e-41f3e41ab49c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462541709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.462541709
Directory	/workspace/15.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_random.3229719895
Short name	T2873
Test name
Test status
Simulation time	1794038690 ps
CPU time	59.8 seconds
Started	Jul 24 07:35:10 PM PDT 24
Finished	Jul 24 07:36:10 PM PDT 24
Peak memory	576168 kb
Host	smart-5eb6941f-3ac1-418b-8d66-7b3d6353671d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229719895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3229719895
Directory	/workspace/15.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1851167832
Short name	T2688
Test name
Test status
Simulation time	12577256854 ps
CPU time	214.93 seconds
Started	Jul 24 07:35:07 PM PDT 24
Finished	Jul 24 07:38:42 PM PDT 24
Peak memory	576320 kb
Host	smart-a2861d96-b85e-4f26-b014-1517cd617b04
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851167832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1851167832
Directory	/workspace/15.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.3128892549
Short name	T2486
Test name
Test status
Simulation time	100571635 ps
CPU time	10.58 seconds
Started	Jul 24 07:35:09 PM PDT 24
Finished	Jul 24 07:35:20 PM PDT 24
Peak memory	576204 kb
Host	smart-f07ec95a-f832-4144-b6f4-73aa1f9a5944
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128892549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.3128892549
Directory	/workspace/15.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_same_source.3902690157
Short name	T1838
Test name
Test status
Simulation time	1905761641 ps
CPU time	57.26 seconds
Started	Jul 24 07:35:09 PM PDT 24
Finished	Jul 24 07:36:06 PM PDT 24
Peak memory	576156 kb
Host	smart-43c0a70c-c4b5-4310-baa4-a117930fd372
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902690157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3902690157
Directory	/workspace/15.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke.3423636298
Short name	T2630
Test name
Test status
Simulation time	40362424 ps
CPU time	5.65 seconds
Started	Jul 24 07:35:07 PM PDT 24
Finished	Jul 24 07:35:13 PM PDT 24
Peak memory	574892 kb
Host	smart-0efc0507-9f34-4d48-80bf-7037cec4535a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423636298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3423636298
Directory	/workspace/15.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2645462949
Short name	T2651
Test name
Test status
Simulation time	7080740509 ps
CPU time	71.45 seconds
Started	Jul 24 07:35:09 PM PDT 24
Finished	Jul 24 07:36:20 PM PDT 24
Peak memory	575052 kb
Host	smart-f58b4799-4571-4674-b62b-a183dcb06e1d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645462949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2645462949
Directory	/workspace/15.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.495497460
Short name	T2323
Test name
Test status
Simulation time	4969033601 ps
CPU time	86.03 seconds
Started	Jul 24 07:35:11 PM PDT 24
Finished	Jul 24 07:36:37 PM PDT 24
Peak memory	575048 kb
Host	smart-f0d47de1-0e16-4a14-8515-70cf142dcc0f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495497460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.495497460
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3063908234
Short name	T1758
Test name
Test status
Simulation time	40871244 ps
CPU time	6.39 seconds
Started	Jul 24 07:35:11 PM PDT 24
Finished	Jul 24 07:35:17 PM PDT 24
Peak memory	576184 kb
Host	smart-7bf65a42-c4ef-455f-8be9-06ba01806438
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063908234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.3063908234
Directory	/workspace/15.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all.849102938
Short name	T2196
Test name
Test status
Simulation time	22695360247 ps
CPU time	762.27 seconds
Started	Jul 24 07:35:27 PM PDT 24
Finished	Jul 24 07:48:09 PM PDT 24
Peak memory	576476 kb
Host	smart-4b56c380-6e47-46e4-b118-903bd2a311fa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849102938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.849102938
Directory	/workspace/15.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.69907061
Short name	T1978
Test name
Test status
Simulation time	9347531032 ps
CPU time	341.9 seconds
Started	Jul 24 07:35:22 PM PDT 24
Finished	Jul 24 07:41:05 PM PDT 24
Peak memory	576312 kb
Host	smart-ca954206-8bea-4b02-9239-8f8e83a5a996
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69907061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.69907061
Directory	/workspace/15.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3292442876
Short name	T2613
Test name
Test status
Simulation time	265782003 ps
CPU time	71.22 seconds
Started	Jul 24 07:35:23 PM PDT 24
Finished	Jul 24 07:36:34 PM PDT 24
Peak memory	576100 kb
Host	smart-70ebc6cc-848c-4ed8-b68d-1bf700b0669e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292442876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.3292442876
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2496790133
Short name	T2526
Test name
Test status
Simulation time	592988287 ps
CPU time	29.23 seconds
Started	Jul 24 07:35:21 PM PDT 24
Finished	Jul 24 07:35:50 PM PDT 24
Peak memory	576184 kb
Host	smart-b9712c84-3f7c-4d34-82d1-a898bb75b312
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496790133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2496790133
Directory	/workspace/15.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.2344923666
Short name	T446
Test name
Test status
Simulation time	11837698178 ps
CPU time	1052.61 seconds
Started	Jul 24 07:35:31 PM PDT 24
Finished	Jul 24 07:53:04 PM PDT 24
Peak memory	647684 kb
Host	smart-43b83ed5-27f3-476d-8b05-76aa412e39c5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344923666 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.2344923666
Directory	/workspace/16.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/16.chip_csr_rw.3356986077
Short name	T144
Test name
Test status
Simulation time	4790632899 ps
CPU time	446.35 seconds
Started	Jul 24 07:35:38 PM PDT 24
Finished	Jul 24 07:43:04 PM PDT 24
Peak memory	599500 kb
Host	smart-f22b6fdc-c6e5-4e65-bce0-8e7340ed3ca6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356986077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.3356986077
Directory	/workspace/16.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.158978637
Short name	T448
Test name
Test status
Simulation time	29523591749 ps
CPU time	3973.55 seconds
Started	Jul 24 07:35:23 PM PDT 24
Finished	Jul 24 08:41:37 PM PDT 24
Peak memory	594372 kb
Host	smart-50c7fb98-8caf-4b1d-a254-537fed554ffa
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158978637 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.chip_same_csr_outstanding.158978637
Directory	/workspace/16.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_access_same_device.874005291
Short name	T2412
Test name
Test status
Simulation time	1142154580 ps
CPU time	89.06 seconds
Started	Jul 24 07:35:37 PM PDT 24
Finished	Jul 24 07:37:06 PM PDT 24
Peak memory	577076 kb
Host	smart-45771e31-e471-497f-80d1-4743d44b224b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874005291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device. 874005291
Directory	/workspace/16.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3747126161
Short name	T2519
Test name
Test status
Simulation time	7324098172 ps
CPU time	120.52 seconds
Started	Jul 24 07:35:34 PM PDT 24
Finished	Jul 24 07:37:35 PM PDT 24
Peak memory	577216 kb
Host	smart-dbb10dfa-d773-4598-afff-75150b11307e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747126161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.3747126161
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3688133926
Short name	T1675
Test name
Test status
Simulation time	771847966 ps
CPU time	31.12 seconds
Started	Jul 24 07:35:32 PM PDT 24
Finished	Jul 24 07:36:04 PM PDT 24
Peak memory	576956 kb
Host	smart-6a4383a0-caff-42d1-a762-0aee9946b2e2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688133926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.3688133926
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_error_random.2417199579
Short name	T1464
Test name
Test status
Simulation time	533455970 ps
CPU time	19.27 seconds
Started	Jul 24 07:35:36 PM PDT 24
Finished	Jul 24 07:35:55 PM PDT 24
Peak memory	576900 kb
Host	smart-08d57820-dfd6-4586-ab68-97c764083866
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417199579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2417199579
Directory	/workspace/16.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_random.410034695
Short name	T525
Test name
Test status
Simulation time	346315458 ps
CPU time	35.93 seconds
Started	Jul 24 07:35:22 PM PDT 24
Finished	Jul 24 07:35:58 PM PDT 24
Peak memory	576980 kb
Host	smart-a21dab98-099e-4432-886e-eadf26a33ce2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410034695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.410034695
Directory	/workspace/16.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.1694721203
Short name	T2021
Test name
Test status
Simulation time	40279731702 ps
CPU time	415.86 seconds
Started	Jul 24 07:35:23 PM PDT 24
Finished	Jul 24 07:42:19 PM PDT 24
Peak memory	576340 kb
Host	smart-d7b60b77-f8b7-4015-875c-7e931d1233c0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694721203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1694721203
Directory	/workspace/16.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2253983978
Short name	T2059
Test name
Test status
Simulation time	16732278851 ps
CPU time	276.28 seconds
Started	Jul 24 07:35:22 PM PDT 24
Finished	Jul 24 07:39:58 PM PDT 24
Peak memory	576336 kb
Host	smart-f9417256-4f5f-4fa0-8574-ea22a95dc287
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253983978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2253983978
Directory	/workspace/16.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3189117160
Short name	T2574
Test name
Test status
Simulation time	618470844 ps
CPU time	49.33 seconds
Started	Jul 24 07:35:23 PM PDT 24
Finished	Jul 24 07:36:12 PM PDT 24
Peak memory	576176 kb
Host	smart-2db5185b-cb0b-494f-9ad0-55628e4fa3fc
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189117160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.3189117160
Directory	/workspace/16.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_same_source.2907372768
Short name	T1965
Test name
Test status
Simulation time	90652030 ps
CPU time	10.13 seconds
Started	Jul 24 07:35:33 PM PDT 24
Finished	Jul 24 07:35:43 PM PDT 24
Peak memory	576208 kb
Host	smart-e697665f-063e-4b2d-9b5e-60e1c9cea4aa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907372768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2907372768
Directory	/workspace/16.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke.2235046808
Short name	T2418
Test name
Test status
Simulation time	48311467 ps
CPU time	6.42 seconds
Started	Jul 24 07:35:22 PM PDT 24
Finished	Jul 24 07:35:28 PM PDT 24
Peak memory	574940 kb
Host	smart-36eceeb1-0397-4a24-a6de-051a7af576ee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235046808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2235046808
Directory	/workspace/16.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1690126789
Short name	T1606
Test name
Test status
Simulation time	10130034666 ps
CPU time	109.82 seconds
Started	Jul 24 07:35:21 PM PDT 24
Finished	Jul 24 07:37:11 PM PDT 24
Peak memory	574948 kb
Host	smart-8192927c-d023-4c40-a458-b085fa160e3c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690126789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1690126789
Directory	/workspace/16.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.605796570
Short name	T2693
Test name
Test status
Simulation time	5849124941 ps
CPU time	99.13 seconds
Started	Jul 24 07:35:22 PM PDT 24
Finished	Jul 24 07:37:02 PM PDT 24
Peak memory	575000 kb
Host	smart-57d37851-7144-4a55-847f-ec9fdff58d21
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605796570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.605796570
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1596302379
Short name	T1787
Test name
Test status
Simulation time	57689483 ps
CPU time	6.89 seconds
Started	Jul 24 07:35:22 PM PDT 24
Finished	Jul 24 07:35:30 PM PDT 24
Peak memory	574860 kb
Host	smart-3f721d5c-39c2-4421-b49b-03be3540aa12
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596302379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.1596302379
Directory	/workspace/16.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2176397112
Short name	T2469
Test name
Test status
Simulation time	215012495 ps
CPU time	9.2 seconds
Started	Jul 24 07:35:32 PM PDT 24
Finished	Jul 24 07:35:41 PM PDT 24
Peak memory	574884 kb
Host	smart-657e8b5a-2ec0-41e0-b6b3-6e8bbceb14bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176397112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2176397112
Directory	/workspace/16.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2368178777
Short name	T1968
Test name
Test status
Simulation time	7692847640 ps
CPU time	316.95 seconds
Started	Jul 24 07:35:33 PM PDT 24
Finished	Jul 24 07:40:50 PM PDT 24
Peak memory	577268 kb
Host	smart-f7514bbf-c9b0-4d11-9505-b1e55e8b6890
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368178777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.2368178777
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3345615643
Short name	T1969
Test name
Test status
Simulation time	5479306508 ps
CPU time	407.94 seconds
Started	Jul 24 07:35:31 PM PDT 24
Finished	Jul 24 07:42:20 PM PDT 24
Peak memory	577276 kb
Host	smart-1ea83122-7735-4e85-a34d-2d57c6622419
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345615643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.3345615643
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1162188260
Short name	T2131
Test name
Test status
Simulation time	336230271 ps
CPU time	33.6 seconds
Started	Jul 24 07:35:34 PM PDT 24
Finished	Jul 24 07:36:08 PM PDT 24
Peak memory	576292 kb
Host	smart-f3642112-78d9-4470-bc0a-46489729b5d5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162188260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1162188260
Directory	/workspace/16.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3856181965
Short name	T1846
Test name
Test status
Simulation time	11906027645 ps
CPU time	715.26 seconds
Started	Jul 24 07:35:46 PM PDT 24
Finished	Jul 24 07:47:42 PM PDT 24
Peak memory	653624 kb
Host	smart-b364ade7-8548-4ad8-9532-b2f6c0727674
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856181965 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.3856181965
Directory	/workspace/17.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/17.chip_csr_rw.4119870316
Short name	T2327
Test name
Test status
Simulation time	4872329538 ps
CPU time	301.07 seconds
Started	Jul 24 07:35:42 PM PDT 24
Finished	Jul 24 07:40:43 PM PDT 24
Peak memory	599092 kb
Host	smart-0e6dea11-76fc-45b1-ba74-c1d878e9ebbb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119870316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.4119870316
Directory	/workspace/17.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3121703843
Short name	T2111
Test name
Test status
Simulation time	15829050343 ps
CPU time	1814.72 seconds
Started	Jul 24 07:35:33 PM PDT 24
Finished	Jul 24 08:05:48 PM PDT 24
Peak memory	594016 kb
Host	smart-6e5022fa-ba22-4f41-b9fe-72e16bd6b7eb
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121703843 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.3121703843
Directory	/workspace/17.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.782042718
Short name	T2840
Test name
Test status
Simulation time	45808826198 ps
CPU time	784.71 seconds
Started	Jul 24 07:35:45 PM PDT 24
Finished	Jul 24 07:48:49 PM PDT 24
Peak memory	576364 kb
Host	smart-7245de05-1eab-4d24-8ea6-ef1ddb65c521
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782042718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_d evice_slow_rsp.782042718
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3323634534
Short name	T2697
Test name
Test status
Simulation time	146848972 ps
CPU time	8.56 seconds
Started	Jul 24 07:35:45 PM PDT 24
Finished	Jul 24 07:35:54 PM PDT 24
Peak memory	576156 kb
Host	smart-ed83a5fa-8996-4453-adeb-7b9a7f0733b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323634534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.3323634534
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_error_random.2743849290
Short name	T1597
Test name
Test status
Simulation time	508487650 ps
CPU time	46.9 seconds
Started	Jul 24 07:35:49 PM PDT 24
Finished	Jul 24 07:36:36 PM PDT 24
Peak memory	577012 kb
Host	smart-54e77404-7cae-4e91-b3d1-42c3a08213f3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743849290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2743849290
Directory	/workspace/17.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_random.928607215
Short name	T2304
Test name
Test status
Simulation time	115454718 ps
CPU time	6.99 seconds
Started	Jul 24 07:35:34 PM PDT 24
Finished	Jul 24 07:35:41 PM PDT 24
Peak memory	574872 kb
Host	smart-a0e5f5b1-037a-4364-8c5f-213eea98a0f0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928607215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.928607215
Directory	/workspace/17.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3909758286
Short name	T499
Test name
Test status
Simulation time	45761111848 ps
CPU time	464.52 seconds
Started	Jul 24 07:35:47 PM PDT 24
Finished	Jul 24 07:43:32 PM PDT 24
Peak memory	576200 kb
Host	smart-7374f368-e2be-4951-abc4-8fdc4b465cae
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909758286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3909758286
Directory	/workspace/17.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.2824205090
Short name	T510
Test name
Test status
Simulation time	54585185684 ps
CPU time	926.34 seconds
Started	Jul 24 07:35:42 PM PDT 24
Finished	Jul 24 07:51:09 PM PDT 24
Peak memory	577100 kb
Host	smart-03692f72-f270-40b0-b76c-4e8471c40b3e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824205090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2824205090
Directory	/workspace/17.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2888666487
Short name	T1794
Test name
Test status
Simulation time	317222775 ps
CPU time	29.53 seconds
Started	Jul 24 07:35:43 PM PDT 24
Finished	Jul 24 07:36:13 PM PDT 24
Peak memory	576232 kb
Host	smart-a7e1cae2-0415-4e01-9445-bc7598b6b996
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888666487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.2888666487
Directory	/workspace/17.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_same_source.1916151145
Short name	T672
Test name
Test status
Simulation time	387962969 ps
CPU time	26.35 seconds
Started	Jul 24 07:35:45 PM PDT 24
Finished	Jul 24 07:36:12 PM PDT 24
Peak memory	576248 kb
Host	smart-42fb2182-34b3-4e23-a059-efb73fb13c36
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916151145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1916151145
Directory	/workspace/17.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke.3121327072
Short name	T2017
Test name
Test status
Simulation time	176762215 ps
CPU time	7.95 seconds
Started	Jul 24 07:35:35 PM PDT 24
Finished	Jul 24 07:35:43 PM PDT 24
Peak memory	574880 kb
Host	smart-3c2601e7-412f-4d14-92c2-e0d8739ddea2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121327072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3121327072
Directory	/workspace/17.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1287058725
Short name	T2489
Test name
Test status
Simulation time	7418641760 ps
CPU time	70.87 seconds
Started	Jul 24 07:35:33 PM PDT 24
Finished	Jul 24 07:36:44 PM PDT 24
Peak memory	576260 kb
Host	smart-a5d979f5-db1a-46f4-9f38-2d87794e8ce2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287058725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1287058725
Directory	/workspace/17.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3702163257
Short name	T658
Test name
Test status
Simulation time	6117190458 ps
CPU time	105.12 seconds
Started	Jul 24 07:35:33 PM PDT 24
Finished	Jul 24 07:37:19 PM PDT 24
Peak memory	575000 kb
Host	smart-ed0c32e0-a9a9-4a4e-b664-9a77d2169f22
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702163257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3702163257
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3719995190
Short name	T490
Test name
Test status
Simulation time	43899449 ps
CPU time	6.51 seconds
Started	Jul 24 07:35:35 PM PDT 24
Finished	Jul 24 07:35:42 PM PDT 24
Peak memory	576192 kb
Host	smart-5c5fc971-cdf8-46bd-a4f5-c6ea7b76cdd3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719995190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.3719995190
Directory	/workspace/17.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all.1939078785
Short name	T2067
Test name
Test status
Simulation time	9183428806 ps
CPU time	375.04 seconds
Started	Jul 24 07:35:44 PM PDT 24
Finished	Jul 24 07:42:00 PM PDT 24
Peak memory	576464 kb
Host	smart-7955dc6b-2423-4c49-9035-a788724fe350
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939078785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1939078785
Directory	/workspace/17.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.4051214224
Short name	T2312
Test name
Test status
Simulation time	208590616 ps
CPU time	19.34 seconds
Started	Jul 24 07:35:43 PM PDT 24
Finished	Jul 24 07:36:02 PM PDT 24
Peak memory	577000 kb
Host	smart-82cc2808-bd91-4d6b-83d8-9b9784e3e7c3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051214224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.4051214224
Directory	/workspace/17.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1440326023
Short name	T2183
Test name
Test status
Simulation time	4217385081 ps
CPU time	592.38 seconds
Started	Jul 24 07:35:50 PM PDT 24
Finished	Jul 24 07:45:42 PM PDT 24
Peak memory	576444 kb
Host	smart-a704b03a-cded-43c8-bd1a-dcdfcdaaa531
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440326023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.1440326023
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1911697492
Short name	T1599
Test name
Test status
Simulation time	809692460 ps
CPU time	102.43 seconds
Started	Jul 24 07:35:50 PM PDT 24
Finished	Jul 24 07:37:33 PM PDT 24
Peak memory	577168 kb
Host	smart-db914563-0313-4c09-8404-9cef405ef31f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911697492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.1911697492
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.1377371159
Short name	T2503
Test name
Test status
Simulation time	86326058 ps
CPU time	12.7 seconds
Started	Jul 24 07:35:44 PM PDT 24
Finished	Jul 24 07:35:57 PM PDT 24
Peak memory	576208 kb
Host	smart-728faa36-5713-44dc-ac20-c15b31e1f01c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377371159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1377371159
Directory	/workspace/17.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.525511953
Short name	T2644
Test name
Test status
Simulation time	7016415608 ps
CPU time	631.43 seconds
Started	Jul 24 07:35:53 PM PDT 24
Finished	Jul 24 07:46:25 PM PDT 24
Peak memory	643508 kb
Host	smart-163b1a56-7010-468d-8676-a5a79e9ce60c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525511953 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.525511953
Directory	/workspace/18.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/18.chip_csr_rw.4127314446
Short name	T2868
Test name
Test status
Simulation time	4372007020 ps
CPU time	352.43 seconds
Started	Jul 24 07:35:55 PM PDT 24
Finished	Jul 24 07:41:48 PM PDT 24
Peak memory	597444 kb
Host	smart-be5f26d2-f3a5-4d5e-b6da-f14653c2d1aa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127314446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.4127314446
Directory	/workspace/18.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/18.chip_tl_errors.8223082
Short name	T789
Test name
Test status
Simulation time	3315254899 ps
CPU time	249.32 seconds
Started	Jul 24 07:35:43 PM PDT 24
Finished	Jul 24 07:39:52 PM PDT 24
Peak memory	604544 kb
Host	smart-5b5bca58-6da3-48d4-a2e5-262c4e7c2721
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8223082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.8223082
Directory	/workspace/18.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_access_same_device.2010511443
Short name	T2911
Test name
Test status
Simulation time	414648910 ps
CPU time	41.65 seconds
Started	Jul 24 07:35:57 PM PDT 24
Finished	Jul 24 07:36:39 PM PDT 24
Peak memory	577040 kb
Host	smart-d7a039a0-1abc-467d-af03-31a47847ba1d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010511443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .2010511443
Directory	/workspace/18.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1492820976
Short name	T1762
Test name
Test status
Simulation time	35347335444 ps
CPU time	654.81 seconds
Started	Jul 24 07:35:52 PM PDT 24
Finished	Jul 24 07:46:47 PM PDT 24
Peak memory	576276 kb
Host	smart-2ed6cf15-e5a9-4289-a754-212fb815c68a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492820976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.1492820976
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.3148679207
Short name	T1994
Test name
Test status
Simulation time	70898372 ps
CPU time	10.13 seconds
Started	Jul 24 07:35:51 PM PDT 24
Finished	Jul 24 07:36:01 PM PDT 24
Peak memory	576220 kb
Host	smart-c5cd96dc-cd2e-45ef-9c1e-1561b101ffea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148679207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.3148679207
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_error_random.1851714351
Short name	T2480
Test name
Test status
Simulation time	148521947 ps
CPU time	14.62 seconds
Started	Jul 24 07:35:52 PM PDT 24
Finished	Jul 24 07:36:06 PM PDT 24
Peak memory	576088 kb
Host	smart-91fb564a-de3c-4c23-9763-9b1a5ccf1d63
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851714351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1851714351
Directory	/workspace/18.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_random.2424518978
Short name	T1484
Test name
Test status
Simulation time	39383144 ps
CPU time	6.5 seconds
Started	Jul 24 07:35:43 PM PDT 24
Finished	Jul 24 07:35:50 PM PDT 24
Peak memory	575008 kb
Host	smart-0fbe6e49-5965-4e0e-b758-9e51404fa89a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424518978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.2424518978
Directory	/workspace/18.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_random_large_delays.4146585524
Short name	T507
Test name
Test status
Simulation time	48085447888 ps
CPU time	530.44 seconds
Started	Jul 24 07:35:52 PM PDT 24
Finished	Jul 24 07:44:43 PM PDT 24
Peak memory	577216 kb
Host	smart-c99402aa-80d5-4854-98c6-cb542ba02a8f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146585524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.4146585524
Directory	/workspace/18.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1725432444
Short name	T1559
Test name
Test status
Simulation time	28440323024 ps
CPU time	433.45 seconds
Started	Jul 24 07:35:53 PM PDT 24
Finished	Jul 24 07:43:07 PM PDT 24
Peak memory	576308 kb
Host	smart-c9335237-b545-4576-88e9-9cdebb0d159d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725432444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1725432444
Directory	/workspace/18.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.1058786275
Short name	T501
Test name
Test status
Simulation time	188975851 ps
CPU time	17.57 seconds
Started	Jul 24 07:35:42 PM PDT 24
Finished	Jul 24 07:36:00 PM PDT 24
Peak memory	576972 kb
Host	smart-98dd155d-ad51-4f41-9b77-f0053da701a6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058786275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.1058786275
Directory	/workspace/18.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_same_source.3266529050
Short name	T2401
Test name
Test status
Simulation time	2717813470 ps
CPU time	72.74 seconds
Started	Jul 24 07:35:56 PM PDT 24
Finished	Jul 24 07:37:09 PM PDT 24
Peak memory	577060 kb
Host	smart-b69322e3-876a-4a17-bd02-d9d7c6b685c5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266529050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3266529050
Directory	/workspace/18.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke.2009073406
Short name	T2042
Test name
Test status
Simulation time	56525811 ps
CPU time	6.38 seconds
Started	Jul 24 07:35:48 PM PDT 24
Finished	Jul 24 07:35:54 PM PDT 24
Peak memory	574756 kb
Host	smart-7875e9e7-033d-4a6a-a1ef-d03a447c44d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009073406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2009073406
Directory	/workspace/18.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.828967091
Short name	T1875
Test name
Test status
Simulation time	7531791327 ps
CPU time	77.09 seconds
Started	Jul 24 07:35:47 PM PDT 24
Finished	Jul 24 07:37:04 PM PDT 24
Peak memory	575072 kb
Host	smart-991716a3-133c-41ec-a426-871c32336100
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828967091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.828967091
Directory	/workspace/18.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2599703244
Short name	T2733
Test name
Test status
Simulation time	5353530461 ps
CPU time	86.57 seconds
Started	Jul 24 07:35:47 PM PDT 24
Finished	Jul 24 07:37:14 PM PDT 24
Peak memory	575064 kb
Host	smart-36f57667-7715-48e0-bd14-0be174cf0995
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599703244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2599703244
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.3978390320
Short name	T1538
Test name
Test status
Simulation time	53426701 ps
CPU time	6.69 seconds
Started	Jul 24 07:35:42 PM PDT 24
Finished	Jul 24 07:35:49 PM PDT 24
Peak memory	574832 kb
Host	smart-25dc84db-fe6a-4482-939f-dd28bb757546
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978390320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.3978390320
Directory	/workspace/18.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all.2582216280
Short name	T2885
Test name
Test status
Simulation time	2357049458 ps
CPU time	176.49 seconds
Started	Jul 24 07:35:56 PM PDT 24
Finished	Jul 24 07:38:52 PM PDT 24
Peak memory	577224 kb
Host	smart-75030c73-3b9a-40e9-9967-e39fb624293c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582216280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2582216280
Directory	/workspace/18.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3833223331
Short name	T1988
Test name
Test status
Simulation time	3737812517 ps
CPU time	158.57 seconds
Started	Jul 24 07:35:56 PM PDT 24
Finished	Jul 24 07:38:35 PM PDT 24
Peak memory	577296 kb
Host	smart-db426880-1220-4ba1-b4ec-8aa4d5f95843
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833223331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3833223331
Directory	/workspace/18.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3909795160
Short name	T931
Test name
Test status
Simulation time	6539310670 ps
CPU time	316.34 seconds
Started	Jul 24 07:35:56 PM PDT 24
Finished	Jul 24 07:41:13 PM PDT 24
Peak memory	577288 kb
Host	smart-52e9996c-5ebd-4b75-88fa-0478a061d683
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909795160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.3909795160
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.385188010
Short name	T2291
Test name
Test status
Simulation time	109799210 ps
CPU time	14.85 seconds
Started	Jul 24 07:35:52 PM PDT 24
Finished	Jul 24 07:36:07 PM PDT 24
Peak memory	577148 kb
Host	smart-da566ab3-4ba8-4f0b-85d1-3971da7cb7c0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385188010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.385188010
Directory	/workspace/18.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3345074606
Short name	T403
Test name
Test status
Simulation time	6111393388 ps
CPU time	378.96 seconds
Started	Jul 24 07:36:09 PM PDT 24
Finished	Jul 24 07:42:28 PM PDT 24
Peak memory	640396 kb
Host	smart-557cef31-a7ed-4d7e-b5b1-346a26ce7c63
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345074606 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.3345074606
Directory	/workspace/19.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/19.chip_csr_rw.909850743
Short name	T447
Test name
Test status
Simulation time	3969663072 ps
CPU time	301.57 seconds
Started	Jul 24 07:36:01 PM PDT 24
Finished	Jul 24 07:41:03 PM PDT 24
Peak memory	597692 kb
Host	smart-e5df195c-e0d5-4be7-8682-87642e04a7cd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909850743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.909850743
Directory	/workspace/19.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.1719989523
Short name	T2780
Test name
Test status
Simulation time	14564156985 ps
CPU time	1573.72 seconds
Started	Jul 24 07:35:53 PM PDT 24
Finished	Jul 24 08:02:07 PM PDT 24
Peak memory	593612 kb
Host	smart-066607c6-edae-45ab-8295-957266031161
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719989523 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.1719989523
Directory	/workspace/19.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/19.chip_tl_errors.1227106496
Short name	T2891
Test name
Test status
Simulation time	3751023064 ps
CPU time	229.63 seconds
Started	Jul 24 07:35:52 PM PDT 24
Finished	Jul 24 07:39:41 PM PDT 24
Peak memory	600488 kb
Host	smart-60d2a244-2367-48ee-8ab7-b485916182a1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227106496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.1227106496
Directory	/workspace/19.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_access_same_device.824316168
Short name	T2061
Test name
Test status
Simulation time	2109506986 ps
CPU time	83.68 seconds
Started	Jul 24 07:36:01 PM PDT 24
Finished	Jul 24 07:37:25 PM PDT 24
Peak memory	577012 kb
Host	smart-bc1e40f9-a943-490d-aaec-d27fd215fde6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824316168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device. 824316168
Directory	/workspace/19.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2748763328
Short name	T1635
Test name
Test status
Simulation time	95641903817 ps
CPU time	1641.97 seconds
Started	Jul 24 07:36:05 PM PDT 24
Finished	Jul 24 08:03:28 PM PDT 24
Peak memory	576320 kb
Host	smart-329f22b3-03ab-4c73-ac5a-89d7b8d4c7a1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748763328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.2748763328
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1027005604
Short name	T1997
Test name
Test status
Simulation time	166501028 ps
CPU time	21 seconds
Started	Jul 24 07:36:03 PM PDT 24
Finished	Jul 24 07:36:24 PM PDT 24
Peak memory	576172 kb
Host	smart-fd055b0c-043b-4268-ba9d-61fa446eaefe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027005604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.1027005604
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_error_random.2455480045
Short name	T1544
Test name
Test status
Simulation time	40220499 ps
CPU time	6.1 seconds
Started	Jul 24 07:36:03 PM PDT 24
Finished	Jul 24 07:36:09 PM PDT 24
Peak memory	576136 kb
Host	smart-dc055dba-269d-4682-be1d-2afb12050a9a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455480045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2455480045
Directory	/workspace/19.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_random.3786364381
Short name	T2205
Test name
Test status
Simulation time	501536159 ps
CPU time	39.13 seconds
Started	Jul 24 07:35:56 PM PDT 24
Finished	Jul 24 07:36:35 PM PDT 24
Peak memory	577100 kb
Host	smart-c2a89df6-4b87-4d11-a3c6-4febe7321ad8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786364381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.3786364381
Directory	/workspace/19.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_random_large_delays.3496414696
Short name	T1859
Test name
Test status
Simulation time	71404370813 ps
CPU time	734.88 seconds
Started	Jul 24 07:35:57 PM PDT 24
Finished	Jul 24 07:48:12 PM PDT 24
Peak memory	577124 kb
Host	smart-6fc35862-56d9-4559-950d-31d1c6d55a9a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496414696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3496414696
Directory	/workspace/19.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2237749209
Short name	T2005
Test name
Test status
Simulation time	29309444453 ps
CPU time	496.68 seconds
Started	Jul 24 07:36:03 PM PDT 24
Finished	Jul 24 07:44:20 PM PDT 24
Peak memory	577256 kb
Host	smart-6be1ffe3-aa06-4cbc-b877-bd16fff51c04
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237749209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2237749209
Directory	/workspace/19.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.462930305
Short name	T1949
Test name
Test status
Simulation time	532629552 ps
CPU time	42.28 seconds
Started	Jul 24 07:35:54 PM PDT 24
Finished	Jul 24 07:36:37 PM PDT 24
Peak memory	576124 kb
Host	smart-33a6adbd-0d7e-4d7a-bc2d-ea9fd9a3cb06
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462930305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_dela ys.462930305
Directory	/workspace/19.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_same_source.2409658079
Short name	T2216
Test name
Test status
Simulation time	727961405 ps
CPU time	23.81 seconds
Started	Jul 24 07:36:03 PM PDT 24
Finished	Jul 24 07:36:27 PM PDT 24
Peak memory	576896 kb
Host	smart-57e56424-0cf4-44d5-86a6-040c90c8046c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409658079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2409658079
Directory	/workspace/19.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke.3505709323
Short name	T2877
Test name
Test status
Simulation time	216825168 ps
CPU time	9.7 seconds
Started	Jul 24 07:35:53 PM PDT 24
Finished	Jul 24 07:36:03 PM PDT 24
Peak memory	576028 kb
Host	smart-41d8f748-fe0c-4676-aa13-6138a2808fca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505709323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3505709323
Directory	/workspace/19.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.3467923866
Short name	T1925
Test name
Test status
Simulation time	5504740231 ps
CPU time	61.83 seconds
Started	Jul 24 07:35:52 PM PDT 24
Finished	Jul 24 07:36:54 PM PDT 24
Peak memory	575004 kb
Host	smart-b378bb3b-9cc0-4966-97db-72ecff600b83
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467923866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3467923866
Directory	/workspace/19.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3132071158
Short name	T2588
Test name
Test status
Simulation time	6645312479 ps
CPU time	117.9 seconds
Started	Jul 24 07:35:55 PM PDT 24
Finished	Jul 24 07:37:53 PM PDT 24
Peak memory	575028 kb
Host	smart-53ca6b39-b527-4fe0-a59f-7de6de4c85c0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132071158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3132071158
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.513513392
Short name	T2569
Test name
Test status
Simulation time	41851588 ps
CPU time	6.22 seconds
Started	Jul 24 07:35:54 PM PDT 24
Finished	Jul 24 07:36:00 PM PDT 24
Peak memory	574968 kb
Host	smart-71cc8f40-566e-4a4f-95cb-e888baaa6968
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513513392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays .513513392
Directory	/workspace/19.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all.4020071767
Short name	T2113
Test name
Test status
Simulation time	263356534 ps
CPU time	30.48 seconds
Started	Jul 24 07:36:02 PM PDT 24
Finished	Jul 24 07:36:32 PM PDT 24
Peak memory	577128 kb
Host	smart-d01b2707-95c9-44c2-b5fb-ec888fefe42e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020071767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.4020071767
Directory	/workspace/19.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.105508793
Short name	T2759
Test name
Test status
Simulation time	4154607550 ps
CPU time	342.35 seconds
Started	Jul 24 07:36:00 PM PDT 24
Finished	Jul 24 07:41:43 PM PDT 24
Peak memory	577224 kb
Host	smart-0437ffb5-a27b-4168-bf61-305b02506719
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105508793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_ with_rand_reset.105508793
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.907398289
Short name	T1804
Test name
Test status
Simulation time	36823592 ps
CPU time	18.62 seconds
Started	Jul 24 07:36:04 PM PDT 24
Finished	Jul 24 07:36:23 PM PDT 24
Peak memory	576996 kb
Host	smart-1b520b32-efe5-440a-a987-6528178db1e5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907398289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_reset_error.907398289
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.507107356
Short name	T1766
Test name
Test status
Simulation time	128092904 ps
CPU time	8.98 seconds
Started	Jul 24 07:36:00 PM PDT 24
Finished	Jul 24 07:36:09 PM PDT 24
Peak memory	574892 kb
Host	smart-358ce437-1289-49ee-8c87-873f92490eed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507107356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.507107356
Directory	/workspace/19.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/2.chip_csr_aliasing.2454092810
Short name	T2247
Test name
Test status
Simulation time	36701991123 ps
CPU time	6366.45 seconds
Started	Jul 24 07:32:52 PM PDT 24
Finished	Jul 24 09:19:00 PM PDT 24
Peak memory	594728 kb
Host	smart-405b2593-254e-4890-b669-f5207eff7118
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454092810 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.chip_csr_aliasing.2454092810
Directory	/workspace/2.chip_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.922038795
Short name	T2907
Test name
Test status
Simulation time	43736842600 ps
CPU time	5007.1 seconds
Started	Jul 24 07:32:51 PM PDT 24
Finished	Jul 24 08:56:19 PM PDT 24
Peak memory	590084 kb
Host	smart-4dae3489-bb93-4958-8b06-6fa00e22a136
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922038795 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.922038795
Directory	/workspace/2.chip_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3066630133
Short name	T134
Test name
Test status
Simulation time	4842240572 ps
CPU time	239.8 seconds
Started	Jul 24 07:33:04 PM PDT 24
Finished	Jul 24 07:37:04 PM PDT 24
Peak memory	665584 kb
Host	smart-fb9d6f69-fd5b-4883-9703-9d3de720a15f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066630133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.3066630133
Directory	/workspace/2.chip_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.4184736347
Short name	T410
Test name
Test status
Simulation time	9778627280 ps
CPU time	940.19 seconds
Started	Jul 24 07:33:01 PM PDT 24
Finished	Jul 24 07:48:41 PM PDT 24
Peak memory	652304 kb
Host	smart-1be2485f-31db-4cd8-a766-c6109a2f6a97
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184736347 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.4184736347
Directory	/workspace/2.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/2.chip_csr_rw.175462575
Short name	T445
Test name
Test status
Simulation time	5890226120 ps
CPU time	489.49 seconds
Started	Jul 24 07:33:04 PM PDT 24
Finished	Jul 24 07:41:14 PM PDT 24
Peak memory	599104 kb
Host	smart-06a62e91-9896-4661-bd79-ade79b16c6c3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175462575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.175462575
Directory	/workspace/2.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/2.chip_prim_tl_access.464752740
Short name	T1514
Test name
Test status
Simulation time	6937045642 ps
CPU time	263.74 seconds
Started	Jul 24 07:32:53 PM PDT 24
Finished	Jul 24 07:37:17 PM PDT 24
Peak memory	591136 kb
Host	smart-bae199c2-7749-4aa6-9c1c-f5081ac0815c
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464752740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2 .chip_prim_tl_access.464752740
Directory	/workspace/2.chip_prim_tl_access/latest

---

Test location	/workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3624539462
Short name	T2073
Test name
Test status
Simulation time	10199076728 ps
CPU time	561.55 seconds
Started	Jul 24 07:32:53 PM PDT 24
Finished	Jul 24 07:42:14 PM PDT 24
Peak memory	592088 kb
Host	smart-0efd8ef9-46c8-4ed3-b474-e3a0ba7a7182
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624539462 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.3624539462
Directory	/workspace/2.chip_rv_dm_lc_disabled/latest

---

Test location	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.227444062
Short name	T458
Test name
Test status
Simulation time	25030285325 ps
CPU time	3576.92 seconds
Started	Jul 24 07:32:47 PM PDT 24
Finished	Jul 24 08:32:24 PM PDT 24
Peak memory	593632 kb
Host	smart-e4945b63-9813-4782-b19a-306916b9527c
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227444062 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.chip_same_csr_outstanding.227444062
Directory	/workspace/2.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/2.chip_tl_errors.3651784013
Short name	T792
Test name
Test status
Simulation time	4656450824 ps
CPU time	442.67 seconds
Started	Jul 24 07:33:00 PM PDT 24
Finished	Jul 24 07:40:23 PM PDT 24
Peak memory	601696 kb
Host	smart-53e0a40d-efaa-4ab6-93b7-680158142e82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651784013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.3651784013
Directory	/workspace/2.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_access_same_device.2501143401
Short name	T2179
Test name
Test status
Simulation time	2035207482 ps
CPU time	92.52 seconds
Started	Jul 24 07:32:51 PM PDT 24
Finished	Jul 24 07:34:24 PM PDT 24
Peak memory	576124 kb
Host	smart-12c69e56-4712-4b66-b1bd-fe155e002cec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501143401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 2501143401
Directory	/workspace/2.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.38650506
Short name	T917
Test name
Test status
Simulation time	96311568355 ps
CPU time	1707.75 seconds
Started	Jul 24 07:32:54 PM PDT 24
Finished	Jul 24 08:01:22 PM PDT 24
Peak memory	577184 kb
Host	smart-d90c76a7-1f96-473f-b7d8-ed226beee84b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38650506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_dev ice_slow_rsp.38650506
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1143636797
Short name	T2537
Test name
Test status
Simulation time	205263516 ps
CPU time	22.12 seconds
Started	Jul 24 07:33:01 PM PDT 24
Finished	Jul 24 07:33:23 PM PDT 24
Peak memory	576972 kb
Host	smart-973b939d-38e4-43d7-8f1a-309fabdce4c3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143636797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .1143636797
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_error_random.2813433268
Short name	T1687
Test name
Test status
Simulation time	303810438 ps
CPU time	21.87 seconds
Started	Jul 24 07:33:04 PM PDT 24
Finished	Jul 24 07:33:26 PM PDT 24
Peak memory	576980 kb
Host	smart-c5a1bed1-eada-4504-a3cf-11417badf8b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813433268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2813433268
Directory	/workspace/2.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_random.80237642
Short name	T2471
Test name
Test status
Simulation time	1239092157 ps
CPU time	42.5 seconds
Started	Jul 24 07:32:50 PM PDT 24
Finished	Jul 24 07:33:33 PM PDT 24
Peak memory	576120 kb
Host	smart-a05c8069-dfcf-4d00-bea7-032ef9104201
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80237642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.80237642
Directory	/workspace/2.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_random_large_delays.3341522356
Short name	T2481
Test name
Test status
Simulation time	29773266011 ps
CPU time	312.16 seconds
Started	Jul 24 07:32:49 PM PDT 24
Finished	Jul 24 07:38:01 PM PDT 24
Peak memory	576220 kb
Host	smart-87360626-5ded-4363-af7e-532faeb7dc87
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341522356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3341522356
Directory	/workspace/2.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.1115409320
Short name	T1724
Test name
Test status
Simulation time	8072073354 ps
CPU time	121.91 seconds
Started	Jul 24 07:32:52 PM PDT 24
Finished	Jul 24 07:34:54 PM PDT 24
Peak memory	577040 kb
Host	smart-616645d4-8431-4f2b-9ce5-9f8784d8c884
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115409320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1115409320
Directory	/workspace/2.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.2652477219
Short name	T582
Test name
Test status
Simulation time	389310077 ps
CPU time	37.18 seconds
Started	Jul 24 07:32:50 PM PDT 24
Finished	Jul 24 07:33:27 PM PDT 24
Peak memory	577016 kb
Host	smart-3289fc10-7fbe-4a9d-9791-8abb64da73a1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652477219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.2652477219
Directory	/workspace/2.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_same_source.1259718227
Short name	T1834
Test name
Test status
Simulation time	206183735 ps
CPU time	9.48 seconds
Started	Jul 24 07:32:49 PM PDT 24
Finished	Jul 24 07:32:58 PM PDT 24
Peak memory	574836 kb
Host	smart-da7c1a5f-7ee1-4efe-aa37-d7c6c215b839
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259718227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1259718227
Directory	/workspace/2.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke.1705115594
Short name	T2830
Test name
Test status
Simulation time	41384100 ps
CPU time	5.6 seconds
Started	Jul 24 07:33:01 PM PDT 24
Finished	Jul 24 07:33:06 PM PDT 24
Peak memory	574908 kb
Host	smart-5d7ee6cc-fe51-496d-89bc-8399f9aca4bc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705115594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1705115594
Directory	/workspace/2.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.919311508
Short name	T1730
Test name
Test status
Simulation time	6758607172 ps
CPU time	66.59 seconds
Started	Jul 24 07:32:54 PM PDT 24
Finished	Jul 24 07:34:01 PM PDT 24
Peak memory	575004 kb
Host	smart-c003758a-37de-4871-b082-0ee378c51400
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919311508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.919311508
Directory	/workspace/2.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2786978282
Short name	T2625
Test name
Test status
Simulation time	5682655498 ps
CPU time	95.69 seconds
Started	Jul 24 07:33:01 PM PDT 24
Finished	Jul 24 07:34:37 PM PDT 24
Peak memory	576224 kb
Host	smart-b692387f-be93-4611-a618-6b559d56d9e1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786978282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2786978282
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3094240647
Short name	T1784
Test name
Test status
Simulation time	60622330 ps
CPU time	7.04 seconds
Started	Jul 24 07:32:50 PM PDT 24
Finished	Jul 24 07:32:57 PM PDT 24
Peak memory	574972 kb
Host	smart-1f6f4fec-5a99-4c03-992a-74ef99db0135
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094240647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .3094240647
Directory	/workspace/2.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all.49800930
Short name	T2404
Test name
Test status
Simulation time	717646822 ps
CPU time	59.46 seconds
Started	Jul 24 07:32:49 PM PDT 24
Finished	Jul 24 07:33:48 PM PDT 24
Peak memory	576268 kb
Host	smart-899544b4-9f1e-4309-ae1f-ee2421859e32
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49800930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.49800930
Directory	/workspace/2.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.2907226794
Short name	T1983
Test name
Test status
Simulation time	8772363757 ps
CPU time	348.04 seconds
Started	Jul 24 07:32:52 PM PDT 24
Finished	Jul 24 07:38:40 PM PDT 24
Peak memory	577164 kb
Host	smart-9cb32f28-75c8-49aa-8787-5264eb333d18
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907226794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2907226794
Directory	/workspace/2.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.227860667
Short name	T2567
Test name
Test status
Simulation time	346346100 ps
CPU time	81.28 seconds
Started	Jul 24 07:32:51 PM PDT 24
Finished	Jul 24 07:34:12 PM PDT 24
Peak memory	576372 kb
Host	smart-9066e806-302a-4f39-b3bf-24dc9767dbea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227860667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_w ith_rand_reset.227860667
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.550453963
Short name	T1616
Test name
Test status
Simulation time	31936627 ps
CPU time	31.2 seconds
Started	Jul 24 07:33:02 PM PDT 24
Finished	Jul 24 07:33:34 PM PDT 24
Peak memory	577148 kb
Host	smart-09b6be71-c72c-44b6-b1fb-85f136f64283
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550453963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_reset_error.550453963
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.1183409268
Short name	T2727
Test name
Test status
Simulation time	1288068168 ps
CPU time	54.2 seconds
Started	Jul 24 07:32:52 PM PDT 24
Finished	Jul 24 07:33:46 PM PDT 24
Peak memory	576968 kb
Host	smart-2dda7f84-50c1-4fd5-bd9e-4b77f2959542
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183409268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1183409268
Directory	/workspace/2.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/20.chip_tl_errors.325542812
Short name	T790
Test name
Test status
Simulation time	3987298134 ps
CPU time	243.53 seconds
Started	Jul 24 07:36:03 PM PDT 24
Finished	Jul 24 07:40:07 PM PDT 24
Peak memory	600840 kb
Host	smart-a8da4ff4-332c-4f42-b630-d06b115791aa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325542812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.325542812
Directory	/workspace/20.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_access_same_device.1187236807
Short name	T1640
Test name
Test status
Simulation time	866446555 ps
CPU time	44.11 seconds
Started	Jul 24 07:36:15 PM PDT 24
Finished	Jul 24 07:37:00 PM PDT 24
Peak memory	577000 kb
Host	smart-78c5636f-5bc2-495a-8afc-b19e73a619dc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187236807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .1187236807
Directory	/workspace/20.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2884413377
Short name	T2850
Test name
Test status
Simulation time	2931401609 ps
CPU time	52.79 seconds
Started	Jul 24 07:36:13 PM PDT 24
Finished	Jul 24 07:37:06 PM PDT 24
Peak memory	576220 kb
Host	smart-2323ab06-e4c1-42c2-9445-7144b1ee130b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884413377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.2884413377
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.1250115984
Short name	T1546
Test name
Test status
Simulation time	895874050 ps
CPU time	38.04 seconds
Started	Jul 24 07:36:14 PM PDT 24
Finished	Jul 24 07:36:52 PM PDT 24
Peak memory	576956 kb
Host	smart-75948af7-ce07-4eca-964a-d1d195287ff8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250115984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.1250115984
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_error_random.3960251127
Short name	T544
Test name
Test status
Simulation time	1527505043 ps
CPU time	54.27 seconds
Started	Jul 24 07:36:14 PM PDT 24
Finished	Jul 24 07:37:09 PM PDT 24
Peak memory	576168 kb
Host	smart-c476af39-5725-444b-9af9-eb9a255feff0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960251127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3960251127
Directory	/workspace/20.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_random.1254789242
Short name	T2579
Test name
Test status
Simulation time	379103596 ps
CPU time	35.9 seconds
Started	Jul 24 07:36:15 PM PDT 24
Finished	Jul 24 07:36:51 PM PDT 24
Peak memory	577012 kb
Host	smart-98ac507b-8b61-46cb-a4c8-166f02911e14
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254789242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.1254789242
Directory	/workspace/20.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3212813656
Short name	T2876
Test name
Test status
Simulation time	78167165458 ps
CPU time	843.64 seconds
Started	Jul 24 07:36:19 PM PDT 24
Finished	Jul 24 07:50:23 PM PDT 24
Peak memory	577160 kb
Host	smart-b5cb0801-fc92-4824-907a-de547b95ea3a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212813656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3212813656
Directory	/workspace/20.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3443291181
Short name	T2751
Test name
Test status
Simulation time	2209492676 ps
CPU time	37.94 seconds
Started	Jul 24 07:36:13 PM PDT 24
Finished	Jul 24 07:36:51 PM PDT 24
Peak memory	574992 kb
Host	smart-80625bfa-9b10-439a-9ff9-64ea04ca862c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443291181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3443291181
Directory	/workspace/20.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.2807192010
Short name	T2918
Test name
Test status
Simulation time	292371317 ps
CPU time	29.93 seconds
Started	Jul 24 07:36:12 PM PDT 24
Finished	Jul 24 07:36:42 PM PDT 24
Peak memory	576984 kb
Host	smart-e82712ad-020f-46a3-aea3-bb4471c89d2c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807192010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.2807192010
Directory	/workspace/20.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_same_source.1571635325
Short name	T1805
Test name
Test status
Simulation time	2586292384 ps
CPU time	75.25 seconds
Started	Jul 24 07:36:19 PM PDT 24
Finished	Jul 24 07:37:35 PM PDT 24
Peak memory	577088 kb
Host	smart-c38e34e0-4d12-4696-8d84-9466b88a1f9d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571635325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1571635325
Directory	/workspace/20.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke.473470117
Short name	T1542
Test name
Test status
Simulation time	242292346 ps
CPU time	10.68 seconds
Started	Jul 24 07:36:03 PM PDT 24
Finished	Jul 24 07:36:14 PM PDT 24
Peak memory	574796 kb
Host	smart-9593f954-70e8-4d27-b8f8-61f6a3ce7012
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473470117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.473470117
Directory	/workspace/20.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.2473668014
Short name	T1556
Test name
Test status
Simulation time	9372868169 ps
CPU time	98.51 seconds
Started	Jul 24 07:36:03 PM PDT 24
Finished	Jul 24 07:37:41 PM PDT 24
Peak memory	575012 kb
Host	smart-e559f0d7-714d-4a63-8af6-3cb873d08b06
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473668014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2473668014
Directory	/workspace/20.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2826881528
Short name	T1573
Test name
Test status
Simulation time	5193208633 ps
CPU time	92.56 seconds
Started	Jul 24 07:36:03 PM PDT 24
Finished	Jul 24 07:37:36 PM PDT 24
Peak memory	576180 kb
Host	smart-6c0c86ff-c139-4531-a20e-69a077396c6e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826881528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2826881528
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.1894824688
Short name	T1565
Test name
Test status
Simulation time	43317674 ps
CPU time	6.44 seconds
Started	Jul 24 07:36:02 PM PDT 24
Finished	Jul 24 07:36:09 PM PDT 24
Peak memory	574768 kb
Host	smart-d5c10198-07a2-464b-8cb5-47542fef8cb3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894824688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.1894824688
Directory	/workspace/20.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all.3607709466
Short name	T2199
Test name
Test status
Simulation time	3999250493 ps
CPU time	139.41 seconds
Started	Jul 24 07:36:14 PM PDT 24
Finished	Jul 24 07:38:34 PM PDT 24
Peak memory	577216 kb
Host	smart-35f04ea7-ba51-4e8e-a89a-2681ff9998dc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607709466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3607709466
Directory	/workspace/20.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.375050193
Short name	T2217
Test name
Test status
Simulation time	6123904838 ps
CPU time	202.95 seconds
Started	Jul 24 07:36:15 PM PDT 24
Finished	Jul 24 07:39:38 PM PDT 24
Peak memory	577248 kb
Host	smart-fc9cff14-92f8-4302-8623-7e173fd690c4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375050193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.375050193
Directory	/workspace/20.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1557000561
Short name	T1843
Test name
Test status
Simulation time	294480391 ps
CPU time	105.33 seconds
Started	Jul 24 07:36:13 PM PDT 24
Finished	Jul 24 07:37:58 PM PDT 24
Peak memory	577112 kb
Host	smart-3e57ee1c-cfee-4049-aa2e-0853b0b53b89
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557000561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.1557000561
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.294493009
Short name	T2126
Test name
Test status
Simulation time	553703126 ps
CPU time	149.43 seconds
Started	Jul 24 07:36:12 PM PDT 24
Finished	Jul 24 07:38:42 PM PDT 24
Peak memory	577140 kb
Host	smart-5691cb02-a591-401d-ad2c-629be76e8ff8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294493009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_reset_error.294493009
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.2114713768
Short name	T1892
Test name
Test status
Simulation time	99519047 ps
CPU time	13.54 seconds
Started	Jul 24 07:36:21 PM PDT 24
Finished	Jul 24 07:36:34 PM PDT 24
Peak memory	576192 kb
Host	smart-0f07bea6-d68e-4ae9-a6b2-f7e0b637e7b8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114713768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2114713768
Directory	/workspace/20.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/21.chip_tl_errors.1316256006
Short name	T725
Test name
Test status
Simulation time	4440273101 ps
CPU time	401.83 seconds
Started	Jul 24 07:36:13 PM PDT 24
Finished	Jul 24 07:42:55 PM PDT 24
Peak memory	604488 kb
Host	smart-4495c09a-ccf3-49d5-b88a-7e13921f7287
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316256006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.1316256006
Directory	/workspace/21.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_access_same_device.976442415
Short name	T946
Test name
Test status
Simulation time	107206034 ps
CPU time	8.72 seconds
Started	Jul 24 07:36:26 PM PDT 24
Finished	Jul 24 07:36:35 PM PDT 24
Peak memory	574964 kb
Host	smart-92200649-fcd4-41d7-abb1-fcedc6345d56
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976442415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device. 976442415
Directory	/workspace/21.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2043621204
Short name	T1710
Test name
Test status
Simulation time	59222305621 ps
CPU time	965.89 seconds
Started	Jul 24 07:36:20 PM PDT 24
Finished	Jul 24 07:52:27 PM PDT 24
Peak memory	577136 kb
Host	smart-35b574f9-e78e-4753-92df-7872e5726413
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043621204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.2043621204
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1923830740
Short name	T1496
Test name
Test status
Simulation time	289456390 ps
CPU time	27.97 seconds
Started	Jul 24 07:36:32 PM PDT 24
Finished	Jul 24 07:37:00 PM PDT 24
Peak memory	577064 kb
Host	smart-c7f1d465-677f-4892-b7d0-502f716a633f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923830740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.1923830740
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_error_random.3081741418
Short name	T722
Test name
Test status
Simulation time	1725715339 ps
CPU time	56.89 seconds
Started	Jul 24 07:36:25 PM PDT 24
Finished	Jul 24 07:37:22 PM PDT 24
Peak memory	577040 kb
Host	smart-2b5ed4f5-9f81-411f-944e-6a26f1b93160
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081741418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3081741418
Directory	/workspace/21.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_random.4254133531
Short name	T625
Test name
Test status
Simulation time	1049471513 ps
CPU time	35.31 seconds
Started	Jul 24 07:36:21 PM PDT 24
Finished	Jul 24 07:36:56 PM PDT 24
Peak memory	576168 kb
Host	smart-5e6357bd-bc96-45fc-9348-f5a552ed647f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254133531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.4254133531
Directory	/workspace/21.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_random_large_delays.3840383534
Short name	T2137
Test name
Test status
Simulation time	101039636953 ps
CPU time	1067.86 seconds
Started	Jul 24 07:36:26 PM PDT 24
Finished	Jul 24 07:54:14 PM PDT 24
Peak memory	576328 kb
Host	smart-d921487d-aab4-45fd-a876-8f7f4db26c2e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840383534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3840383534
Directory	/workspace/21.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.1025048835
Short name	T2169
Test name
Test status
Simulation time	56704010388 ps
CPU time	940.43 seconds
Started	Jul 24 07:36:21 PM PDT 24
Finished	Jul 24 07:52:01 PM PDT 24
Peak memory	577092 kb
Host	smart-d01fde1a-f05a-4a31-a9b2-c73ac3a9f2c2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025048835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1025048835
Directory	/workspace/21.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3174780759
Short name	T610
Test name
Test status
Simulation time	29372012 ps
CPU time	5.39 seconds
Started	Jul 24 07:36:22 PM PDT 24
Finished	Jul 24 07:36:28 PM PDT 24
Peak memory	574932 kb
Host	smart-c70784d6-2880-48d1-b271-b68505747a1c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174780759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.3174780759
Directory	/workspace/21.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_same_source.1635150755
Short name	T2716
Test name
Test status
Simulation time	2718866720 ps
CPU time	80.13 seconds
Started	Jul 24 07:36:22 PM PDT 24
Finished	Jul 24 07:37:42 PM PDT 24
Peak memory	576288 kb
Host	smart-e4848350-6422-4579-a7a5-47723a9cffe9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635150755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1635150755
Directory	/workspace/21.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke.717118291
Short name	T2553
Test name
Test status
Simulation time	47473259 ps
CPU time	6.5 seconds
Started	Jul 24 07:36:13 PM PDT 24
Finished	Jul 24 07:36:20 PM PDT 24
Peak memory	574848 kb
Host	smart-d082a9c1-d737-402d-92ec-9f1c9b64590f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717118291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.717118291
Directory	/workspace/21.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.1100699014
Short name	T1570
Test name
Test status
Simulation time	6343767531 ps
CPU time	64.92 seconds
Started	Jul 24 07:36:21 PM PDT 24
Finished	Jul 24 07:37:26 PM PDT 24
Peak memory	576268 kb
Host	smart-1be33dd6-9a22-4f95-8d46-bab48ebde31f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100699014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1100699014
Directory	/workspace/21.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.4177372806
Short name	T2155
Test name
Test status
Simulation time	5115649258 ps
CPU time	91.41 seconds
Started	Jul 24 07:36:12 PM PDT 24
Finished	Jul 24 07:37:44 PM PDT 24
Peak memory	575020 kb
Host	smart-c6683c7d-6f5c-4703-8b43-e7d5bf851898
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177372806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.4177372806
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.451706009
Short name	T1506
Test name
Test status
Simulation time	43887984 ps
CPU time	6.39 seconds
Started	Jul 24 07:36:13 PM PDT 24
Finished	Jul 24 07:36:19 PM PDT 24
Peak memory	576148 kb
Host	smart-a0f4db03-66ef-4794-b399-add45d64fcc9
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451706009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays .451706009
Directory	/workspace/21.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all.1224036363
Short name	T512
Test name
Test status
Simulation time	1381106969 ps
CPU time	128.66 seconds
Started	Jul 24 07:36:42 PM PDT 24
Finished	Jul 24 07:38:50 PM PDT 24
Peak memory	576268 kb
Host	smart-cab20bf1-d3c5-4912-a4fb-154bbd601961
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224036363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1224036363
Directory	/workspace/21.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3873302160
Short name	T933
Test name
Test status
Simulation time	13917887097 ps
CPU time	533.57 seconds
Started	Jul 24 07:36:42 PM PDT 24
Finished	Jul 24 07:45:36 PM PDT 24
Peak memory	577184 kb
Host	smart-e38d2a07-00bd-4aa3-9178-4604fee9baca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873302160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3873302160
Directory	/workspace/21.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2604083218
Short name	T2467
Test name
Test status
Simulation time	541943107 ps
CPU time	188.53 seconds
Started	Jul 24 07:36:33 PM PDT 24
Finished	Jul 24 07:39:41 PM PDT 24
Peak memory	576400 kb
Host	smart-e012af64-0636-4736-99b8-353aeabb4e65
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604083218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.2604083218
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.737442554
Short name	T2374
Test name
Test status
Simulation time	5015404957 ps
CPU time	207.76 seconds
Started	Jul 24 07:36:33 PM PDT 24
Finished	Jul 24 07:40:01 PM PDT 24
Peak memory	576432 kb
Host	smart-6c1c746a-bc10-4be4-849c-e286c935595b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737442554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_reset_error.737442554
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.1827720546
Short name	T1986
Test name
Test status
Simulation time	1547900976 ps
CPU time	52.75 seconds
Started	Jul 24 07:36:25 PM PDT 24
Finished	Jul 24 07:37:18 PM PDT 24
Peak memory	577096 kb
Host	smart-45208659-df02-4d0d-9c1b-c17c760dad52
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827720546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1827720546
Directory	/workspace/21.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/22.chip_tl_errors.1609241057
Short name	T750
Test name
Test status
Simulation time	4454906220 ps
CPU time	364.51 seconds
Started	Jul 24 07:36:41 PM PDT 24
Finished	Jul 24 07:42:45 PM PDT 24
Peak memory	604448 kb
Host	smart-50cc3701-ad2f-4d3f-a2cb-ac84a4022198
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609241057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.1609241057
Directory	/workspace/22.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_access_same_device.2236790538
Short name	T2833
Test name
Test status
Simulation time	635838160 ps
CPU time	66.46 seconds
Started	Jul 24 07:36:32 PM PDT 24
Finished	Jul 24 07:37:39 PM PDT 24
Peak memory	577016 kb
Host	smart-2dbf6b56-7689-4114-a98f-f4db1992e5cf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236790538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .2236790538
Directory	/workspace/22.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.362722178
Short name	T937
Test name
Test status
Simulation time	137702491557 ps
CPU time	2470.47 seconds
Started	Jul 24 07:36:34 PM PDT 24
Finished	Jul 24 08:17:45 PM PDT 24
Peak memory	576356 kb
Host	smart-ba399a1a-6370-4b24-aaea-4b7971c78630
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362722178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_d evice_slow_rsp.362722178
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1084557416
Short name	T2750
Test name
Test status
Simulation time	1441427722 ps
CPU time	57.74 seconds
Started	Jul 24 07:36:37 PM PDT 24
Finished	Jul 24 07:37:35 PM PDT 24
Peak memory	576120 kb
Host	smart-12f2a04c-8611-4bac-89dd-2ac7ef9b309c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084557416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.1084557416
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_random.101788618
Short name	T2165
Test name
Test status
Simulation time	1291792289 ps
CPU time	46.6 seconds
Started	Jul 24 07:36:33 PM PDT 24
Finished	Jul 24 07:37:20 PM PDT 24
Peak memory	576960 kb
Host	smart-79667a7b-ee00-450b-8bc2-73ff8e339f2d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101788618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.101788618
Directory	/workspace/22.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_random_large_delays.167411123
Short name	T1662
Test name
Test status
Simulation time	4048917185 ps
CPU time	40.38 seconds
Started	Jul 24 07:36:34 PM PDT 24
Finished	Jul 24 07:37:14 PM PDT 24
Peak memory	575076 kb
Host	smart-34f52deb-0089-4967-9ebd-f3fa7e91a397
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167411123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.167411123
Directory	/workspace/22.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.460998784
Short name	T2632
Test name
Test status
Simulation time	26656456770 ps
CPU time	457.18 seconds
Started	Jul 24 07:36:34 PM PDT 24
Finished	Jul 24 07:44:11 PM PDT 24
Peak memory	576296 kb
Host	smart-fc538758-1103-4ec6-9cbd-ae6add6fb7fc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460998784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.460998784
Directory	/workspace/22.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.1286202999
Short name	T523
Test name
Test status
Simulation time	575933406 ps
CPU time	52.81 seconds
Started	Jul 24 07:36:35 PM PDT 24
Finished	Jul 24 07:37:28 PM PDT 24
Peak memory	577032 kb
Host	smart-0dba5336-8aa3-456a-96e9-69b8c0a68ab2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286202999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.1286202999
Directory	/workspace/22.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_same_source.3033185140
Short name	T2336
Test name
Test status
Simulation time	73843994 ps
CPU time	8.13 seconds
Started	Jul 24 07:36:32 PM PDT 24
Finished	Jul 24 07:36:40 PM PDT 24
Peak memory	576188 kb
Host	smart-864a2f2f-0302-4387-9c92-9fe9e176f83a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033185140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3033185140
Directory	/workspace/22.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke.91531400
Short name	T2541
Test name
Test status
Simulation time	54759861 ps
CPU time	6.86 seconds
Started	Jul 24 07:36:36 PM PDT 24
Finished	Jul 24 07:36:43 PM PDT 24
Peak memory	576092 kb
Host	smart-2fa97b07-bc33-4b26-8c0d-683340950b74
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91531400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.91531400
Directory	/workspace/22.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.1863905688
Short name	T2681
Test name
Test status
Simulation time	8984535794 ps
CPU time	95.38 seconds
Started	Jul 24 07:37:14 PM PDT 24
Finished	Jul 24 07:38:49 PM PDT 24
Peak memory	574988 kb
Host	smart-498a3a66-9cdc-4171-af8e-7f35056f3a04
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863905688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1863905688
Directory	/workspace/22.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.1916744519
Short name	T1793
Test name
Test status
Simulation time	6439682082 ps
CPU time	107.86 seconds
Started	Jul 24 07:36:33 PM PDT 24
Finished	Jul 24 07:38:21 PM PDT 24
Peak memory	575060 kb
Host	smart-8bf781f0-c48d-4d54-9d22-019d35de4a75
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916744519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1916744519
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.805126660
Short name	T1803
Test name
Test status
Simulation time	49380415 ps
CPU time	6.16 seconds
Started	Jul 24 07:36:32 PM PDT 24
Finished	Jul 24 07:36:38 PM PDT 24
Peak memory	574872 kb
Host	smart-3ed825d5-92dd-45da-bf87-52491936c651
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805126660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays .805126660
Directory	/workspace/22.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all.2798257260
Short name	T2433
Test name
Test status
Simulation time	2770968557 ps
CPU time	260.86 seconds
Started	Jul 24 07:36:31 PM PDT 24
Finished	Jul 24 07:40:52 PM PDT 24
Peak memory	577288 kb
Host	smart-95a6ac0e-dcdf-4b46-bbda-23704e3c5afa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798257260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2798257260
Directory	/workspace/22.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.2022291697
Short name	T2038
Test name
Test status
Simulation time	3389097114 ps
CPU time	266.53 seconds
Started	Jul 24 07:37:40 PM PDT 24
Finished	Jul 24 07:42:06 PM PDT 24
Peak memory	577280 kb
Host	smart-0b696efe-b884-44dd-af5a-da4d865c2be3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022291697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2022291697
Directory	/workspace/22.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.4251128584
Short name	T649
Test name
Test status
Simulation time	164447004 ps
CPU time	75.18 seconds
Started	Jul 24 07:37:37 PM PDT 24
Finished	Jul 24 07:38:52 PM PDT 24
Peak memory	577164 kb
Host	smart-99e9ce71-5c2b-4321-9e7d-691ab63b5668
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251128584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.4251128584
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3677598134
Short name	T919
Test name
Test status
Simulation time	4250724536 ps
CPU time	462.36 seconds
Started	Jul 24 07:37:39 PM PDT 24
Finished	Jul 24 07:45:21 PM PDT 24
Peak memory	577272 kb
Host	smart-735fbd10-0346-472e-8e8c-50b753a42973
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677598134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.3677598134
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3643981351
Short name	T694
Test name
Test status
Simulation time	760922331 ps
CPU time	31.45 seconds
Started	Jul 24 07:36:35 PM PDT 24
Finished	Jul 24 07:37:06 PM PDT 24
Peak memory	577064 kb
Host	smart-c60d388a-f548-40bf-8969-06e6f748ce39
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643981351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3643981351
Directory	/workspace/22.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/23.chip_tl_errors.2832571798
Short name	T584
Test name
Test status
Simulation time	3776836962 ps
CPU time	255 seconds
Started	Jul 24 07:37:35 PM PDT 24
Finished	Jul 24 07:41:50 PM PDT 24
Peak memory	604512 kb
Host	smart-4a9a8008-4be9-4c8b-b471-ff4f0d333b9d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832571798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.2832571798
Directory	/workspace/23.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_access_same_device.1004853569
Short name	T934
Test name
Test status
Simulation time	181561992 ps
CPU time	16.06 seconds
Started	Jul 24 07:38:01 PM PDT 24
Finished	Jul 24 07:38:17 PM PDT 24
Peak memory	576988 kb
Host	smart-b9d008b2-a7d9-40d7-bd7c-524bd11b207b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004853569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .1004853569
Directory	/workspace/23.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.3984346997
Short name	T2260
Test name
Test status
Simulation time	97827435780 ps
CPU time	1694.9 seconds
Started	Jul 24 07:37:40 PM PDT 24
Finished	Jul 24 08:05:55 PM PDT 24
Peak memory	576380 kb
Host	smart-249e1de6-5437-4cd3-9e85-dd960ffe7db7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984346997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.3984346997
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3496813232
Short name	T1543
Test name
Test status
Simulation time	163381690 ps
CPU time	16.23 seconds
Started	Jul 24 07:37:36 PM PDT 24
Finished	Jul 24 07:37:53 PM PDT 24
Peak memory	576956 kb
Host	smart-07092c7d-0c85-4879-9067-3b9e23e0fb0b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496813232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.3496813232
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_error_random.2331567762
Short name	T2677
Test name
Test status
Simulation time	1047554631 ps
CPU time	37.84 seconds
Started	Jul 24 07:37:42 PM PDT 24
Finished	Jul 24 07:38:20 PM PDT 24
Peak memory	576964 kb
Host	smart-89612240-ab8d-4071-825f-76a4156ba089
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331567762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2331567762
Directory	/workspace/23.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_random.4037293120
Short name	T2420
Test name
Test status
Simulation time	211159558 ps
CPU time	10.98 seconds
Started	Jul 24 07:37:43 PM PDT 24
Finished	Jul 24 07:37:55 PM PDT 24
Peak memory	576160 kb
Host	smart-032967ba-20ba-47dd-a65c-2a478abcfc95
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037293120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.4037293120
Directory	/workspace/23.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2017710959
Short name	T1775
Test name
Test status
Simulation time	22043475317 ps
CPU time	223.25 seconds
Started	Jul 24 07:37:37 PM PDT 24
Finished	Jul 24 07:41:20 PM PDT 24
Peak memory	577144 kb
Host	smart-ef87137c-55b6-4033-aa37-52dd08458d7b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017710959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2017710959
Directory	/workspace/23.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.4204100095
Short name	T1712
Test name
Test status
Simulation time	24197171297 ps
CPU time	410.86 seconds
Started	Jul 24 07:37:40 PM PDT 24
Finished	Jul 24 07:44:31 PM PDT 24
Peak memory	576260 kb
Host	smart-a828300d-9e2c-4674-a395-a8507129a98a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204100095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.4204100095
Directory	/workspace/23.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.2790293078
Short name	T1445
Test name
Test status
Simulation time	98663709 ps
CPU time	10.4 seconds
Started	Jul 24 07:37:44 PM PDT 24
Finished	Jul 24 07:37:54 PM PDT 24
Peak memory	576164 kb
Host	smart-c4dfe9b8-7ee3-4c2f-afbc-ca85f3a3b8ad
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790293078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.2790293078
Directory	/workspace/23.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_same_source.2043596052
Short name	T2071
Test name
Test status
Simulation time	2501885935 ps
CPU time	65.78 seconds
Started	Jul 24 07:37:36 PM PDT 24
Finished	Jul 24 07:38:41 PM PDT 24
Peak memory	577100 kb
Host	smart-a9ce51c6-7e79-4330-9be0-5ce5cf5bd2bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043596052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2043596052
Directory	/workspace/23.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke.1924613978
Short name	T2316
Test name
Test status
Simulation time	53337510 ps
CPU time	6.23 seconds
Started	Jul 24 07:37:40 PM PDT 24
Finished	Jul 24 07:37:46 PM PDT 24
Peak memory	574908 kb
Host	smart-a3185c70-b777-4ccb-be94-7c4410c45aee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924613978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1924613978
Directory	/workspace/23.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2848002549
Short name	T2474
Test name
Test status
Simulation time	8048800979 ps
CPU time	83.65 seconds
Started	Jul 24 07:37:39 PM PDT 24
Finished	Jul 24 07:39:03 PM PDT 24
Peak memory	576236 kb
Host	smart-04d65a3c-d4a3-4036-bfa7-8bfe048b3133
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848002549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2848002549
Directory	/workspace/23.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.831385108
Short name	T2206
Test name
Test status
Simulation time	4809450022 ps
CPU time	74.84 seconds
Started	Jul 24 07:37:41 PM PDT 24
Finished	Jul 24 07:38:56 PM PDT 24
Peak memory	575060 kb
Host	smart-c4fe6124-34ed-4d64-bc83-4fec5c5f9b9f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831385108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.831385108
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.2426533385
Short name	T1457
Test name
Test status
Simulation time	41518088 ps
CPU time	6.34 seconds
Started	Jul 24 07:37:40 PM PDT 24
Finished	Jul 24 07:37:47 PM PDT 24
Peak memory	576136 kb
Host	smart-f48cf734-7596-4799-af8c-fe81d5115b30
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426533385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.2426533385
Directory	/workspace/23.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2132725507
Short name	T2893
Test name
Test status
Simulation time	9454648628 ps
CPU time	312.51 seconds
Started	Jul 24 07:37:46 PM PDT 24
Finished	Jul 24 07:42:59 PM PDT 24
Peak memory	577268 kb
Host	smart-64602109-1881-4acd-aef4-5088afd3d7d6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132725507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2132725507
Directory	/workspace/23.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2074880353
Short name	T2185
Test name
Test status
Simulation time	2341974154 ps
CPU time	185.29 seconds
Started	Jul 24 07:37:35 PM PDT 24
Finished	Jul 24 07:40:41 PM PDT 24
Peak memory	576532 kb
Host	smart-6001f42d-bed9-4a96-9907-9c52eeb5ec81
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074880353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.2074880353
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.4252349471
Short name	T2337
Test name
Test status
Simulation time	68516172 ps
CPU time	30.91 seconds
Started	Jul 24 07:37:39 PM PDT 24
Finished	Jul 24 07:38:10 PM PDT 24
Peak memory	577024 kb
Host	smart-c9626c90-3c3c-43e7-961d-2abeb36d5827
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252349471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.4252349471
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.3931075449
Short name	T2084
Test name
Test status
Simulation time	753773304 ps
CPU time	28.59 seconds
Started	Jul 24 07:37:41 PM PDT 24
Finished	Jul 24 07:38:10 PM PDT 24
Peak memory	577136 kb
Host	smart-333ba929-a340-4bba-9f8b-dc6f9bf97242
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931075449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3931075449
Directory	/workspace/23.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_access_same_device.127954229
Short name	T1865
Test name
Test status
Simulation time	101714708 ps
CPU time	9.47 seconds
Started	Jul 24 07:37:41 PM PDT 24
Finished	Jul 24 07:37:50 PM PDT 24
Peak memory	574920 kb
Host	smart-fa01d74f-bb70-4790-8d83-0160e45d44d6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127954229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device. 127954229
Directory	/workspace/24.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3210026549
Short name	T2768
Test name
Test status
Simulation time	62077261459 ps
CPU time	1115.34 seconds
Started	Jul 24 07:37:36 PM PDT 24
Finished	Jul 24 07:56:12 PM PDT 24
Peak memory	576372 kb
Host	smart-e57224a8-b8d0-4bc7-8ffb-de7357543cd8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210026549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.3210026549
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1034481645
Short name	T2297
Test name
Test status
Simulation time	279698466 ps
CPU time	26.76 seconds
Started	Jul 24 07:37:42 PM PDT 24
Finished	Jul 24 07:38:09 PM PDT 24
Peak memory	576904 kb
Host	smart-0d7b64f1-7432-4ca2-8040-112f06af17b0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034481645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.1034481645
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_error_random.154104900
Short name	T2330
Test name
Test status
Simulation time	1561091366 ps
CPU time	57.72 seconds
Started	Jul 24 07:38:24 PM PDT 24
Finished	Jul 24 07:39:22 PM PDT 24
Peak memory	576916 kb
Host	smart-e8cd37a1-e18e-4b86-9ba0-33e9f57b7542
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154104900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.154104900
Directory	/workspace/24.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_random.1423013051
Short name	T593
Test name
Test status
Simulation time	1145856084 ps
CPU time	47.45 seconds
Started	Jul 24 07:37:36 PM PDT 24
Finished	Jul 24 07:38:24 PM PDT 24
Peak memory	576144 kb
Host	smart-6f36ad2f-61a8-48e4-8db0-b174af3b654c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423013051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.1423013051
Directory	/workspace/24.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1150622075
Short name	T1818
Test name
Test status
Simulation time	94437480743 ps
CPU time	1022.35 seconds
Started	Jul 24 07:37:36 PM PDT 24
Finished	Jul 24 07:54:38 PM PDT 24
Peak memory	576380 kb
Host	smart-8f5b4e91-67b5-4a7b-90d0-78a857cb3968
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150622075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1150622075
Directory	/workspace/24.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.3180930836
Short name	T2777
Test name
Test status
Simulation time	61673589254 ps
CPU time	972.49 seconds
Started	Jul 24 07:37:39 PM PDT 24
Finished	Jul 24 07:53:52 PM PDT 24
Peak memory	577048 kb
Host	smart-e72d091e-6b61-48fa-8be4-7bbabfec9474
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180930836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3180930836
Directory	/workspace/24.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.2086255756
Short name	T524
Test name
Test status
Simulation time	514208667 ps
CPU time	47.24 seconds
Started	Jul 24 07:37:37 PM PDT 24
Finished	Jul 24 07:38:24 PM PDT 24
Peak memory	576968 kb
Host	smart-41c3ffe8-44e6-4a5a-8c1c-d9f4940d8845
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086255756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.2086255756
Directory	/workspace/24.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_same_source.3916818404
Short name	T2540
Test name
Test status
Simulation time	1787864028 ps
CPU time	50.1 seconds
Started	Jul 24 07:37:38 PM PDT 24
Finished	Jul 24 07:38:28 PM PDT 24
Peak memory	576116 kb
Host	smart-5f08d04b-86f8-475c-bfa2-f45ceb3863ef
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916818404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3916818404
Directory	/workspace/24.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke.267370312
Short name	T2234
Test name
Test status
Simulation time	52924353 ps
CPU time	6.66 seconds
Started	Jul 24 07:37:38 PM PDT 24
Finished	Jul 24 07:37:45 PM PDT 24
Peak memory	574968 kb
Host	smart-a8c05145-0edc-4ab4-b6ef-a06c24f24663
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267370312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.267370312
Directory	/workspace/24.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.1431362065
Short name	T2864
Test name
Test status
Simulation time	9038614294 ps
CPU time	100.91 seconds
Started	Jul 24 07:37:40 PM PDT 24
Finished	Jul 24 07:39:21 PM PDT 24
Peak memory	575008 kb
Host	smart-234fbfb1-f4a3-4417-9a38-087b0fa65840
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431362065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1431362065
Directory	/workspace/24.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3648753233
Short name	T2263
Test name
Test status
Simulation time	4738648523 ps
CPU time	79.78 seconds
Started	Jul 24 07:37:37 PM PDT 24
Finished	Jul 24 07:38:57 PM PDT 24
Peak memory	574984 kb
Host	smart-1c95fcaf-7607-4968-90da-1af02dd015d3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648753233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3648753233
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3485010485
Short name	T662
Test name
Test status
Simulation time	48983912 ps
CPU time	6.28 seconds
Started	Jul 24 07:37:39 PM PDT 24
Finished	Jul 24 07:37:45 PM PDT 24
Peak memory	574840 kb
Host	smart-e2143af9-fd4c-484e-8408-97a74d815579
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485010485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.3485010485
Directory	/workspace/24.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all.2965677466
Short name	T704
Test name
Test status
Simulation time	8698053620 ps
CPU time	335.91 seconds
Started	Jul 24 07:37:41 PM PDT 24
Finished	Jul 24 07:43:18 PM PDT 24
Peak memory	576388 kb
Host	smart-b9432f20-c5f3-4542-a8fc-5e1f256770e7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965677466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2965677466
Directory	/workspace/24.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.1435782848
Short name	T1586
Test name
Test status
Simulation time	1129197469 ps
CPU time	89.01 seconds
Started	Jul 24 07:37:40 PM PDT 24
Finished	Jul 24 07:39:10 PM PDT 24
Peak memory	576240 kb
Host	smart-a36ac41f-2944-459c-9380-a5b88eb01a70
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435782848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1435782848
Directory	/workspace/24.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2033968957
Short name	T1976
Test name
Test status
Simulation time	484821746 ps
CPU time	106.83 seconds
Started	Jul 24 07:37:42 PM PDT 24
Finished	Jul 24 07:39:29 PM PDT 24
Peak memory	576268 kb
Host	smart-790f0545-ecc9-467f-a7c2-5dd52a2b672d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033968957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.2033968957
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.2785604557
Short name	T2170
Test name
Test status
Simulation time	845611045 ps
CPU time	37.98 seconds
Started	Jul 24 07:37:40 PM PDT 24
Finished	Jul 24 07:38:18 PM PDT 24
Peak memory	576260 kb
Host	smart-6b9ca653-d03d-4bfa-9aed-807b997ecc98
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785604557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2785604557
Directory	/workspace/24.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_access_same_device.1657197203
Short name	T1864
Test name
Test status
Simulation time	832319322 ps
CPU time	35.28 seconds
Started	Jul 24 07:37:51 PM PDT 24
Finished	Jul 24 07:38:27 PM PDT 24
Peak memory	576260 kb
Host	smart-fb298ff5-c81a-415f-8a0d-2b627aa37c26
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657197203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .1657197203
Directory	/workspace/25.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1195785692
Short name	T2508
Test name
Test status
Simulation time	26145555784 ps
CPU time	438.47 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:45:11 PM PDT 24
Peak memory	577168 kb
Host	smart-b2269c3e-e1df-491a-a042-41b4ce427e54
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195785692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.1195785692
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1547272238
Short name	T2292
Test name
Test status
Simulation time	220950662 ps
CPU time	11.82 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:38:04 PM PDT 24
Peak memory	576488 kb
Host	smart-5aeaf086-c81a-4b16-ae3c-b4c3cc82fd6b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547272238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.1547272238
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_error_random.1881634503
Short name	T2811
Test name
Test status
Simulation time	159181785 ps
CPU time	14.69 seconds
Started	Jul 24 07:37:53 PM PDT 24
Finished	Jul 24 07:38:07 PM PDT 24
Peak memory	576128 kb
Host	smart-6f917705-2b93-4613-af5a-7aa71eb4a5e2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881634503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1881634503
Directory	/workspace/25.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_random.3860213315
Short name	T2222
Test name
Test status
Simulation time	340062270 ps
CPU time	29.81 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:38:22 PM PDT 24
Peak memory	577120 kb
Host	smart-e4a8b2b8-6ae7-4983-9b0d-1d58f23d4daa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860213315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3860213315
Directory	/workspace/25.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_random_large_delays.4109979414
Short name	T684
Test name
Test status
Simulation time	41584187722 ps
CPU time	432.91 seconds
Started	Jul 24 07:37:53 PM PDT 24
Finished	Jul 24 07:45:06 PM PDT 24
Peak memory	576352 kb
Host	smart-494686da-70a0-4e94-b987-e2617a8d5eb9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109979414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.4109979414
Directory	/workspace/25.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.4255487120
Short name	T2732
Test name
Test status
Simulation time	8784332591 ps
CPU time	145.6 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:40:18 PM PDT 24
Peak memory	575804 kb
Host	smart-b2fe37af-5f50-40bf-9a9d-a79f201562f2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255487120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4255487120
Directory	/workspace/25.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.4292829376
Short name	T2888
Test name
Test status
Simulation time	280799236 ps
CPU time	22.85 seconds
Started	Jul 24 07:37:53 PM PDT 24
Finished	Jul 24 07:38:16 PM PDT 24
Peak memory	576296 kb
Host	smart-6d43c8a1-273d-4df6-bf08-65e03b0580fe
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292829376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.4292829376
Directory	/workspace/25.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_same_source.2923166204
Short name	T1952
Test name
Test status
Simulation time	595084091 ps
CPU time	18.88 seconds
Started	Jul 24 07:37:53 PM PDT 24
Finished	Jul 24 07:38:12 PM PDT 24
Peak memory	576996 kb
Host	smart-ae8e039b-e581-446a-b9bd-79796c11146c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923166204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2923166204
Directory	/workspace/25.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke.3712182477
Short name	T2246
Test name
Test status
Simulation time	238544915 ps
CPU time	10.33 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:38:03 PM PDT 24
Peak memory	574948 kb
Host	smart-394025a3-ae74-45b6-8f08-7126babbff2d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712182477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3712182477
Directory	/workspace/25.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.2282194086
Short name	T728
Test name
Test status
Simulation time	8222728893 ps
CPU time	87.42 seconds
Started	Jul 24 07:37:49 PM PDT 24
Finished	Jul 24 07:39:17 PM PDT 24
Peak memory	576216 kb
Host	smart-60648f9d-0b2d-4d68-aab8-d88d3c856fb6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282194086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2282194086
Directory	/workspace/25.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.4186788683
Short name	T2747
Test name
Test status
Simulation time	4938347051 ps
CPU time	79.03 seconds
Started	Jul 24 07:37:48 PM PDT 24
Finished	Jul 24 07:39:07 PM PDT 24
Peak memory	574944 kb
Host	smart-adafb18b-8cfd-4275-b6b0-c7e88820544e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186788683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.4186788683
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.1360870515
Short name	T2536
Test name
Test status
Simulation time	44789700 ps
CPU time	5.78 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:37:58 PM PDT 24
Peak memory	574804 kb
Host	smart-d2d25fce-66dc-4dcd-aeef-06044d5cdb61
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360870515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.1360870515
Directory	/workspace/25.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all.1730710820
Short name	T2809
Test name
Test status
Simulation time	21753967577 ps
CPU time	803.63 seconds
Started	Jul 24 07:37:46 PM PDT 24
Finished	Jul 24 07:51:10 PM PDT 24
Peak memory	576332 kb
Host	smart-9a18978d-18bf-4564-9d51-7850ae6ba8c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730710820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1730710820
Directory	/workspace/25.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.4113273574
Short name	T928
Test name
Test status
Simulation time	2452948988 ps
CPU time	176.04 seconds
Started	Jul 24 07:37:49 PM PDT 24
Finished	Jul 24 07:40:45 PM PDT 24
Peak memory	576404 kb
Host	smart-1b80dcad-bf3e-424f-9f24-82482af0e238
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113273574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.4113273574
Directory	/workspace/25.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2494449631
Short name	T2115
Test name
Test status
Simulation time	2367315592 ps
CPU time	467.79 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:45:40 PM PDT 24
Peak memory	577368 kb
Host	smart-c8ac16e2-450e-42e1-abd2-3687523451db
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494449631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.2494449631
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.2763440783
Short name	T1964
Test name
Test status
Simulation time	153956806 ps
CPU time	22.19 seconds
Started	Jul 24 07:37:48 PM PDT 24
Finished	Jul 24 07:38:11 PM PDT 24
Peak memory	576192 kb
Host	smart-c481c172-f9c7-4841-b472-827b63671396
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763440783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2763440783
Directory	/workspace/25.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/26.chip_tl_errors.200032440
Short name	T2306
Test name
Test status
Simulation time	3231078515 ps
CPU time	184.46 seconds
Started	Jul 24 07:37:48 PM PDT 24
Finished	Jul 24 07:40:53 PM PDT 24
Peak memory	604508 kb
Host	smart-649ad851-cb4a-499d-968c-416ad88861a3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200032440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.200032440
Directory	/workspace/26.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_access_same_device.4125819310
Short name	T2889
Test name
Test status
Simulation time	133296414 ps
CPU time	16.03 seconds
Started	Jul 24 07:37:48 PM PDT 24
Finished	Jul 24 07:38:05 PM PDT 24
Peak memory	576916 kb
Host	smart-dc152a0e-b5ab-4680-a14d-7bc500082b8c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125819310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .4125819310
Directory	/workspace/26.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2377677438
Short name	T2117
Test name
Test status
Simulation time	43699995335 ps
CPU time	703.61 seconds
Started	Jul 24 07:37:47 PM PDT 24
Finished	Jul 24 07:49:31 PM PDT 24
Peak memory	577228 kb
Host	smart-1cfc61da-9bc6-4b26-bf00-523abbfc4a83
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377677438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.2377677438
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2564713782
Short name	T2296
Test name
Test status
Simulation time	1345131816 ps
CPU time	57.39 seconds
Started	Jul 24 07:37:51 PM PDT 24
Finished	Jul 24 07:38:48 PM PDT 24
Peak memory	577016 kb
Host	smart-e00e1bdf-ca0f-48d1-b88f-69b6027e602f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564713782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.2564713782
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_error_random.3769205787
Short name	T1593
Test name
Test status
Simulation time	510985623 ps
CPU time	35.88 seconds
Started	Jul 24 07:37:49 PM PDT 24
Finished	Jul 24 07:38:25 PM PDT 24
Peak memory	576948 kb
Host	smart-d9744704-0da4-47af-90df-ec6d42de4d68
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769205787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3769205787
Directory	/workspace/26.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_random.1601017626
Short name	T1973
Test name
Test status
Simulation time	2214319906 ps
CPU time	84.24 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:39:17 PM PDT 24
Peak memory	577144 kb
Host	smart-d443ea0d-71e6-4273-9084-2abd402d95ed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601017626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1601017626
Directory	/workspace/26.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_random_large_delays.457497517
Short name	T2720
Test name
Test status
Simulation time	76900669216 ps
CPU time	722.59 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:49:55 PM PDT 24
Peak memory	577108 kb
Host	smart-272f2319-eae8-46e9-8cbf-bbf4b4ccb83f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457497517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.457497517
Directory	/workspace/26.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.2770870368
Short name	T1776
Test name
Test status
Simulation time	53603730190 ps
CPU time	853.82 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:52:06 PM PDT 24
Peak memory	576336 kb
Host	smart-0c25ad3d-066e-44ed-bdb9-a0350e4d2dd8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770870368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2770870368
Directory	/workspace/26.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3054993174
Short name	T2662
Test name
Test status
Simulation time	443210605 ps
CPU time	38.12 seconds
Started	Jul 24 07:37:46 PM PDT 24
Finished	Jul 24 07:38:24 PM PDT 24
Peak memory	576176 kb
Host	smart-691af6c7-ca1b-4044-88ee-07d9923c866c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054993174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.3054993174
Directory	/workspace/26.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_same_source.4125660112
Short name	T2784
Test name
Test status
Simulation time	187672858 ps
CPU time	14.8 seconds
Started	Jul 24 07:37:52 PM PDT 24
Finished	Jul 24 07:38:07 PM PDT 24
Peak memory	576084 kb
Host	smart-fb8dccda-ed95-4759-8df1-809e5611b0cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125660112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.4125660112
Directory	/workspace/26.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke.4201480783
Short name	T1519
Test name
Test status
Simulation time	36745852 ps
CPU time	5.92 seconds
Started	Jul 24 07:37:51 PM PDT 24
Finished	Jul 24 07:37:57 PM PDT 24
Peak memory	576188 kb
Host	smart-e04e6266-57ed-43df-835e-3f13bc7d4613
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201480783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.4201480783
Directory	/workspace/26.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.606216769
Short name	T2731
Test name
Test status
Simulation time	9507990065 ps
CPU time	98.89 seconds
Started	Jul 24 07:37:49 PM PDT 24
Finished	Jul 24 07:39:28 PM PDT 24
Peak memory	575020 kb
Host	smart-f5fbf102-3e5c-4ad9-9747-deae33e0e355
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606216769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.606216769
Directory	/workspace/26.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2921225298
Short name	T1876
Test name
Test status
Simulation time	3277254998 ps
CPU time	55.48 seconds
Started	Jul 24 07:37:48 PM PDT 24
Finished	Jul 24 07:38:44 PM PDT 24
Peak memory	575012 kb
Host	smart-f9f89833-848e-45fa-bad2-41d5fdd0985c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921225298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2921225298
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.544839547
Short name	T559
Test name
Test status
Simulation time	47755895 ps
CPU time	6.67 seconds
Started	Jul 24 07:37:47 PM PDT 24
Finished	Jul 24 07:37:54 PM PDT 24
Peak memory	576132 kb
Host	smart-9873e148-c8bb-4c01-92c0-3d6a024460fb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544839547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays .544839547
Directory	/workspace/26.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all.1248666191
Short name	T486
Test name
Test status
Simulation time	7334365972 ps
CPU time	265.32 seconds
Started	Jul 24 07:38:01 PM PDT 24
Finished	Jul 24 07:42:26 PM PDT 24
Peak memory	576544 kb
Host	smart-8c699c73-ed7b-479a-8004-becf5776729f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248666191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1248666191
Directory	/workspace/26.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.276948287
Short name	T1701
Test name
Test status
Simulation time	16486096422 ps
CPU time	517.12 seconds
Started	Jul 24 07:38:01 PM PDT 24
Finished	Jul 24 07:46:38 PM PDT 24
Peak memory	577288 kb
Host	smart-ce95e08c-cebd-4d61-a132-469b74ede017
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276948287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.276948287
Directory	/workspace/26.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2790521956
Short name	T2564
Test name
Test status
Simulation time	145652728 ps
CPU time	75.34 seconds
Started	Jul 24 07:37:55 PM PDT 24
Finished	Jul 24 07:39:10 PM PDT 24
Peak memory	577116 kb
Host	smart-b647c9c9-daaf-4f71-8f91-e192da67bd81
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790521956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.2790521956
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3603856214
Short name	T2215
Test name
Test status
Simulation time	3967333141 ps
CPU time	422.52 seconds
Started	Jul 24 07:37:56 PM PDT 24
Finished	Jul 24 07:44:59 PM PDT 24
Peak memory	577276 kb
Host	smart-67fe8dc4-8d10-4bc1-a475-c614fb2aa3f9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603856214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.3603856214
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.2704707248
Short name	T546
Test name
Test status
Simulation time	800903352 ps
CPU time	36.43 seconds
Started	Jul 24 07:37:53 PM PDT 24
Finished	Jul 24 07:38:30 PM PDT 24
Peak memory	577184 kb
Host	smart-ca2a8b89-527c-49d4-813f-08af7e3eb587
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704707248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2704707248
Directory	/workspace/26.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_access_same_device.2803848524
Short name	T1673
Test name
Test status
Simulation time	1121388057 ps
CPU time	51.35 seconds
Started	Jul 24 07:37:55 PM PDT 24
Finished	Jul 24 07:38:46 PM PDT 24
Peak memory	577016 kb
Host	smart-caaace84-afe1-4f1c-a072-0149baf3b964
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803848524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .2803848524
Directory	/workspace/27.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.2138540570
Short name	T2015
Test name
Test status
Simulation time	44744764050 ps
CPU time	783.09 seconds
Started	Jul 24 07:37:55 PM PDT 24
Finished	Jul 24 07:50:59 PM PDT 24
Peak memory	576300 kb
Host	smart-9add8b5d-9c6a-4779-bf36-676311c2fe11
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138540570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.2138540570
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2500981491
Short name	T1788
Test name
Test status
Simulation time	637532218 ps
CPU time	23.85 seconds
Started	Jul 24 07:37:59 PM PDT 24
Finished	Jul 24 07:38:23 PM PDT 24
Peak memory	576944 kb
Host	smart-20d34ca4-d5ba-4e0a-ab68-b2e0036d066d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500981491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.2500981491
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_error_random.4250852533
Short name	T1759
Test name
Test status
Simulation time	231478881 ps
CPU time	19.89 seconds
Started	Jul 24 07:37:56 PM PDT 24
Finished	Jul 24 07:38:16 PM PDT 24
Peak memory	575820 kb
Host	smart-76069ece-8845-4576-b76f-7ac7cfc76232
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250852533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.4250852533
Directory	/workspace/27.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_random.1622478482
Short name	T732
Test name
Test status
Simulation time	1260502532 ps
CPU time	49.37 seconds
Started	Jul 24 07:38:03 PM PDT 24
Finished	Jul 24 07:38:52 PM PDT 24
Peak memory	577040 kb
Host	smart-a264ae60-f7ef-4dc7-91cb-190164505ca1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622478482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1622478482
Directory	/workspace/27.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_random_large_delays.154800655
Short name	T2479
Test name
Test status
Simulation time	29248589061 ps
CPU time	295.51 seconds
Started	Jul 24 07:37:56 PM PDT 24
Finished	Jul 24 07:42:51 PM PDT 24
Peak memory	576356 kb
Host	smart-abe06b16-2445-4bc0-bcf1-369ca3534dd3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154800655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.154800655
Directory	/workspace/27.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1210015652
Short name	T2820
Test name
Test status
Simulation time	41664206655 ps
CPU time	702.73 seconds
Started	Jul 24 07:38:03 PM PDT 24
Finished	Jul 24 07:49:46 PM PDT 24
Peak memory	576332 kb
Host	smart-662c0925-eba0-4acd-9eb5-d68405a44d50
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210015652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1210015652
Directory	/workspace/27.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.313872224
Short name	T727
Test name
Test status
Simulation time	27641262 ps
CPU time	5.84 seconds
Started	Jul 24 07:38:01 PM PDT 24
Finished	Jul 24 07:38:07 PM PDT 24
Peak memory	574964 kb
Host	smart-891e0a45-ec8a-4b37-a9c5-c5a38f9a2f60
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313872224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_dela ys.313872224
Directory	/workspace/27.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_same_source.2421784821
Short name	T1714
Test name
Test status
Simulation time	402287730 ps
CPU time	27.18 seconds
Started	Jul 24 07:38:00 PM PDT 24
Finished	Jul 24 07:38:27 PM PDT 24
Peak memory	577000 kb
Host	smart-611984e4-cb4f-4a49-bda5-57de7235e11e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421784821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2421784821
Directory	/workspace/27.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke.3693916724
Short name	T2650
Test name
Test status
Simulation time	53195487 ps
CPU time	6.86 seconds
Started	Jul 24 07:38:00 PM PDT 24
Finished	Jul 24 07:38:07 PM PDT 24
Peak memory	574836 kb
Host	smart-c92fe1bb-8a18-4ca9-ab07-9265ddde5f41
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693916724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3693916724
Directory	/workspace/27.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2291675860
Short name	T1467
Test name
Test status
Simulation time	7607223354 ps
CPU time	78.47 seconds
Started	Jul 24 07:37:58 PM PDT 24
Finished	Jul 24 07:39:16 PM PDT 24
Peak memory	576168 kb
Host	smart-aa6d205e-97eb-49de-9e75-ec3d4e6262cc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291675860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2291675860
Directory	/workspace/27.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.363716164
Short name	T1610
Test name
Test status
Simulation time	5156742474 ps
CPU time	86.57 seconds
Started	Jul 24 07:38:04 PM PDT 24
Finished	Jul 24 07:39:31 PM PDT 24
Peak memory	575052 kb
Host	smart-ebb70b55-686a-4e14-9479-daee959fd0e8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363716164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.363716164
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2415861891
Short name	T1907
Test name
Test status
Simulation time	43590639 ps
CPU time	6.16 seconds
Started	Jul 24 07:38:00 PM PDT 24
Finished	Jul 24 07:38:06 PM PDT 24
Peak memory	574944 kb
Host	smart-0c7c1009-d530-4493-b203-d72afcad9952
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415861891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.2415861891
Directory	/workspace/27.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all.2366371433
Short name	T659
Test name
Test status
Simulation time	2591402640 ps
CPU time	115.27 seconds
Started	Jul 24 07:37:55 PM PDT 24
Finished	Jul 24 07:39:50 PM PDT 24
Peak memory	577196 kb
Host	smart-bbebfdbf-b779-4ca8-9a6b-6a086c09c962
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366371433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2366371433
Directory	/workspace/27.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.2432924375
Short name	T2457
Test name
Test status
Simulation time	11998152718 ps
CPU time	378.39 seconds
Started	Jul 24 07:37:56 PM PDT 24
Finished	Jul 24 07:44:15 PM PDT 24
Peak memory	577272 kb
Host	smart-06586fb3-c2e9-4b12-87e7-f0c5cea8d2be
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432924375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2432924375
Directory	/workspace/27.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3137571204
Short name	T2922
Test name
Test status
Simulation time	174103037 ps
CPU time	45.6 seconds
Started	Jul 24 07:38:03 PM PDT 24
Finished	Jul 24 07:38:49 PM PDT 24
Peak memory	577172 kb
Host	smart-2248fe9a-7a1f-4291-b758-cb65352f6ed7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137571204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.3137571204
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3181916002
Short name	T2254
Test name
Test status
Simulation time	6928804 ps
CPU time	3.99 seconds
Started	Jul 24 07:38:01 PM PDT 24
Finished	Jul 24 07:38:05 PM PDT 24
Peak memory	574824 kb
Host	smart-0280656e-bf90-4b8a-a192-84aca94f50d8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181916002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.3181916002
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.3241978787
Short name	T2219
Test name
Test status
Simulation time	246903193 ps
CPU time	29.9 seconds
Started	Jul 24 07:38:00 PM PDT 24
Finished	Jul 24 07:38:30 PM PDT 24
Peak memory	576180 kb
Host	smart-b9c8f4cb-0da8-41d6-8a81-2dedb47e33d8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241978787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3241978787
Directory	/workspace/27.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/28.chip_tl_errors.3227490270
Short name	T2636
Test name
Test status
Simulation time	3759522411 ps
CPU time	288.69 seconds
Started	Jul 24 07:38:08 PM PDT 24
Finished	Jul 24 07:42:57 PM PDT 24
Peak memory	593244 kb
Host	smart-979b200c-fc1a-4bb1-a7ac-eaee98333f08
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227490270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.3227490270
Directory	/workspace/28.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_access_same_device.3487897996
Short name	T474
Test name
Test status
Simulation time	1982614495 ps
CPU time	79.81 seconds
Started	Jul 24 07:38:08 PM PDT 24
Finished	Jul 24 07:39:28 PM PDT 24
Peak memory	576200 kb
Host	smart-8e544d17-3fbd-4a24-a50e-d3d276afe84b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487897996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .3487897996
Directory	/workspace/28.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2851561595
Short name	T2405
Test name
Test status
Simulation time	67850979169 ps
CPU time	1182.06 seconds
Started	Jul 24 07:38:06 PM PDT 24
Finished	Jul 24 07:57:48 PM PDT 24
Peak memory	576304 kb
Host	smart-a76e2520-99c3-4451-8743-6b5d557c1280
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851561595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.2851561595
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.4080175169
Short name	T1623
Test name
Test status
Simulation time	603319694 ps
CPU time	27.27 seconds
Started	Jul 24 07:38:12 PM PDT 24
Finished	Jul 24 07:38:39 PM PDT 24
Peak memory	576976 kb
Host	smart-4715c683-86de-4edc-827d-a8d8b7691a7e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080175169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.4080175169
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_error_random.3157867799
Short name	T2500
Test name
Test status
Simulation time	302873988 ps
CPU time	22.5 seconds
Started	Jul 24 07:38:07 PM PDT 24
Finished	Jul 24 07:38:29 PM PDT 24
Peak memory	577052 kb
Host	smart-f0328982-2319-488f-97a7-d4de448d4f73
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157867799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3157867799
Directory	/workspace/28.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_random.3329528317
Short name	T1655
Test name
Test status
Simulation time	2314089433 ps
CPU time	86.55 seconds
Started	Jul 24 07:38:05 PM PDT 24
Finished	Jul 24 07:39:32 PM PDT 24
Peak memory	576192 kb
Host	smart-c8528301-3c34-43e7-87de-2416f827cb27
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329528317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.3329528317
Directory	/workspace/28.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_random_large_delays.1967668552
Short name	T698
Test name
Test status
Simulation time	49027808140 ps
CPU time	513.28 seconds
Started	Jul 24 07:38:04 PM PDT 24
Finished	Jul 24 07:46:38 PM PDT 24
Peak memory	577140 kb
Host	smart-0a1d2fdf-11c7-47ce-b886-91c789f79bf5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967668552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1967668552
Directory	/workspace/28.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.714222166
Short name	T2464
Test name
Test status
Simulation time	43443141363 ps
CPU time	708.46 seconds
Started	Jul 24 07:38:09 PM PDT 24
Finished	Jul 24 07:49:57 PM PDT 24
Peak memory	577084 kb
Host	smart-a7a1cae3-46e1-4170-a435-ffb12f07c61f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714222166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.714222166
Directory	/workspace/28.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.1189372753
Short name	T1989
Test name
Test status
Simulation time	375326942 ps
CPU time	30.94 seconds
Started	Jul 24 07:38:04 PM PDT 24
Finished	Jul 24 07:38:35 PM PDT 24
Peak memory	576164 kb
Host	smart-fac02fe8-9c2c-4464-ae40-75947315a7db
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189372753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.1189372753
Directory	/workspace/28.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_same_source.1924131439
Short name	T663
Test name
Test status
Simulation time	264589952 ps
CPU time	10.16 seconds
Started	Jul 24 07:38:05 PM PDT 24
Finished	Jul 24 07:38:16 PM PDT 24
Peak memory	574780 kb
Host	smart-20c5bd8e-a6db-4ea7-b6ca-b3f6eccffd8b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924131439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1924131439
Directory	/workspace/28.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke.1286876466
Short name	T2815
Test name
Test status
Simulation time	41656370 ps
CPU time	6.26 seconds
Started	Jul 24 07:38:11 PM PDT 24
Finished	Jul 24 07:38:18 PM PDT 24
Peak memory	574864 kb
Host	smart-1fc4f4d6-737e-4517-99fc-4eb0d7d37979
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286876466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1286876466
Directory	/workspace/28.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.4157762303
Short name	T1654
Test name
Test status
Simulation time	8127599545 ps
CPU time	79.5 seconds
Started	Jul 24 07:38:11 PM PDT 24
Finished	Jul 24 07:39:31 PM PDT 24
Peak memory	574984 kb
Host	smart-3427e47d-3ec5-4b28-8925-27f870aad4e3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157762303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4157762303
Directory	/workspace/28.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.903313591
Short name	T1583
Test name
Test status
Simulation time	5066555235 ps
CPU time	82.72 seconds
Started	Jul 24 07:38:08 PM PDT 24
Finished	Jul 24 07:39:31 PM PDT 24
Peak memory	575084 kb
Host	smart-a3b8913d-c287-4168-8546-e476caa55456
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903313591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.903313591
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.308404142
Short name	T1785
Test name
Test status
Simulation time	43948620 ps
CPU time	5.83 seconds
Started	Jul 24 07:38:04 PM PDT 24
Finished	Jul 24 07:38:09 PM PDT 24
Peak memory	574924 kb
Host	smart-a3ded31d-39c8-48c9-9835-c165dc5614ca
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308404142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays .308404142
Directory	/workspace/28.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all.4157249543
Short name	T470
Test name
Test status
Simulation time	2690117729 ps
CPU time	123.01 seconds
Started	Jul 24 07:38:08 PM PDT 24
Finished	Jul 24 07:40:11 PM PDT 24
Peak memory	576400 kb
Host	smart-070b740c-6bd6-4992-a789-52f57606579f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157249543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4157249543
Directory	/workspace/28.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.789527903
Short name	T1919
Test name
Test status
Simulation time	4874115941 ps
CPU time	148.74 seconds
Started	Jul 24 07:38:12 PM PDT 24
Finished	Jul 24 07:40:41 PM PDT 24
Peak memory	577252 kb
Host	smart-532c6446-f911-4346-9fad-8ee0156df7bd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789527903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.789527903
Directory	/workspace/28.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1051418528
Short name	T2722
Test name
Test status
Simulation time	1169602660 ps
CPU time	388.75 seconds
Started	Jul 24 07:38:09 PM PDT 24
Finished	Jul 24 07:44:37 PM PDT 24
Peak memory	577244 kb
Host	smart-43aca7cd-faba-4870-853a-b16486c893e1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051418528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.1051418528
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2227292390
Short name	T2472
Test name
Test status
Simulation time	73889915 ps
CPU time	22.18 seconds
Started	Jul 24 07:38:06 PM PDT 24
Finished	Jul 24 07:38:28 PM PDT 24
Peak memory	577076 kb
Host	smart-aab29b8b-249f-4c63-88da-68984a637171
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227292390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.2227292390
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.4017401713
Short name	T1819
Test name
Test status
Simulation time	147854257 ps
CPU time	9.41 seconds
Started	Jul 24 07:38:08 PM PDT 24
Finished	Jul 24 07:38:17 PM PDT 24
Peak memory	576212 kb
Host	smart-43ec7f98-21b8-486e-bb5a-9818e19ffe7a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017401713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.4017401713
Directory	/workspace/28.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_access_same_device.1336588537
Short name	T2010
Test name
Test status
Simulation time	77416774 ps
CPU time	7.81 seconds
Started	Jul 24 07:38:14 PM PDT 24
Finished	Jul 24 07:38:22 PM PDT 24
Peak memory	574936 kb
Host	smart-d67c1cc7-b491-4bbc-b76c-1598361cf053
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336588537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .1336588537
Directory	/workspace/29.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.584335964
Short name	T1853
Test name
Test status
Simulation time	85335415408 ps
CPU time	1456.56 seconds
Started	Jul 24 07:38:13 PM PDT 24
Finished	Jul 24 08:02:30 PM PDT 24
Peak memory	577140 kb
Host	smart-ea26a016-2a31-49bd-ac4a-f3b9d128cf0a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584335964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_d evice_slow_rsp.584335964
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2422421068
Short name	T2740
Test name
Test status
Simulation time	1342535178 ps
CPU time	46.78 seconds
Started	Jul 24 07:38:21 PM PDT 24
Finished	Jul 24 07:39:08 PM PDT 24
Peak memory	577036 kb
Host	smart-c365e451-36fe-4346-8982-81ca33cc6b52
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422421068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.2422421068
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_error_random.1715287729
Short name	T2908
Test name
Test status
Simulation time	155539829 ps
CPU time	16.27 seconds
Started	Jul 24 07:38:15 PM PDT 24
Finished	Jul 24 07:38:32 PM PDT 24
Peak memory	576096 kb
Host	smart-426fdb69-fd6e-4295-94aa-656d63d4e187
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715287729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1715287729
Directory	/workspace/29.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_random.2400696874
Short name	T1939
Test name
Test status
Simulation time	1299645840 ps
CPU time	44.67 seconds
Started	Jul 24 07:38:03 PM PDT 24
Finished	Jul 24 07:38:48 PM PDT 24
Peak memory	576200 kb
Host	smart-34f1840b-6a4a-40ea-a099-542b8490c037
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400696874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.2400696874
Directory	/workspace/29.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_random_large_delays.2347574229
Short name	T495
Test name
Test status
Simulation time	89713893362 ps
CPU time	919.98 seconds
Started	Jul 24 07:38:04 PM PDT 24
Finished	Jul 24 07:53:25 PM PDT 24
Peak memory	577196 kb
Host	smart-033105da-3c40-4357-9643-3c44795e5c0a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347574229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2347574229
Directory	/workspace/29.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.1360560718
Short name	T609
Test name
Test status
Simulation time	22097479403 ps
CPU time	370.34 seconds
Started	Jul 24 07:38:05 PM PDT 24
Finished	Jul 24 07:44:16 PM PDT 24
Peak memory	576252 kb
Host	smart-c8993063-fd63-4a26-9a29-2c1cd0ef3a31
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360560718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1360560718
Directory	/workspace/29.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.1897902207
Short name	T729
Test name
Test status
Simulation time	253060143 ps
CPU time	25.27 seconds
Started	Jul 24 07:38:11 PM PDT 24
Finished	Jul 24 07:38:37 PM PDT 24
Peak memory	576168 kb
Host	smart-af026d69-269a-4f59-b4d0-2b1b305647ba
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897902207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.1897902207
Directory	/workspace/29.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_same_source.3153000878
Short name	T2157
Test name
Test status
Simulation time	458975412 ps
CPU time	33.29 seconds
Started	Jul 24 07:38:23 PM PDT 24
Finished	Jul 24 07:38:56 PM PDT 24
Peak memory	576192 kb
Host	smart-c4c114ff-218e-49dd-bd9b-9f064be329bc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153000878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3153000878
Directory	/workspace/29.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke.2710289505
Short name	T80
Test name
Test status
Simulation time	175474135 ps
CPU time	8.13 seconds
Started	Jul 24 07:38:08 PM PDT 24
Finished	Jul 24 07:38:17 PM PDT 24
Peak memory	576220 kb
Host	smart-92e8c4d9-d649-4b0e-b06c-4b04f674c24d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710289505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2710289505
Directory	/workspace/29.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.3716750556
Short name	T1779
Test name
Test status
Simulation time	8008545936 ps
CPU time	87.03 seconds
Started	Jul 24 07:38:03 PM PDT 24
Finished	Jul 24 07:39:30 PM PDT 24
Peak memory	574984 kb
Host	smart-1c281640-6cff-486a-9f7f-8608d9feaa25
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716750556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3716750556
Directory	/workspace/29.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.4074205683
Short name	T2906
Test name
Test status
Simulation time	5312799859 ps
CPU time	88.87 seconds
Started	Jul 24 07:38:11 PM PDT 24
Finished	Jul 24 07:39:40 PM PDT 24
Peak memory	576220 kb
Host	smart-a7ced2c7-24cc-4e6f-901f-bf5fd6d2046d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074205683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4074205683
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.4089687766
Short name	T1928
Test name
Test status
Simulation time	53613565 ps
CPU time	7.09 seconds
Started	Jul 24 07:38:04 PM PDT 24
Finished	Jul 24 07:38:11 PM PDT 24
Peak memory	574892 kb
Host	smart-eb5802c5-da15-4f56-9793-e4461ebfdc72
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089687766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.4089687766
Directory	/workspace/29.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all.4192718316
Short name	T1936
Test name
Test status
Simulation time	10678264650 ps
CPU time	429.88 seconds
Started	Jul 24 07:38:15 PM PDT 24
Finished	Jul 24 07:45:25 PM PDT 24
Peak memory	576500 kb
Host	smart-1f7f0533-8ef1-4e00-897b-92c2afd308b4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192718316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4192718316
Directory	/workspace/29.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.2397856427
Short name	T1999
Test name
Test status
Simulation time	4461423945 ps
CPU time	316.66 seconds
Started	Jul 24 07:38:14 PM PDT 24
Finished	Jul 24 07:43:30 PM PDT 24
Peak memory	577224 kb
Host	smart-6c7fb9b1-5b44-4982-9c15-5cc0b15946c2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397856427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2397856427
Directory	/workspace/29.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.2900283133
Short name	T664
Test name
Test status
Simulation time	1209488840 ps
CPU time	48.73 seconds
Started	Jul 24 07:38:26 PM PDT 24
Finished	Jul 24 07:39:14 PM PDT 24
Peak memory	576176 kb
Host	smart-ce3516c0-64cb-4dbe-a107-6b2139afdaa1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900283133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2900283133
Directory	/workspace/29.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.931901005
Short name	T1634
Test name
Test status
Simulation time	6809593120 ps
CPU time	632.47 seconds
Started	Jul 24 07:32:50 PM PDT 24
Finished	Jul 24 07:43:23 PM PDT 24
Peak memory	593536 kb
Host	smart-e62105a8-99b8-49c9-a43a-742911f30734
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931901005 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.931901005
Directory	/workspace/3.chip_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.4285595422
Short name	T135
Test name
Test status
Simulation time	5315036498 ps
CPU time	240.72 seconds
Started	Jul 24 07:33:08 PM PDT 24
Finished	Jul 24 07:37:09 PM PDT 24
Peak memory	664328 kb
Host	smart-2792fce4-8036-445c-8e30-f6342caae91f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285595422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.4285595422
Directory	/workspace/3.chip_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2242674270
Short name	T2641
Test name
Test status
Simulation time	9432284137 ps
CPU time	876.79 seconds
Started	Jul 24 07:33:07 PM PDT 24
Finished	Jul 24 07:47:44 PM PDT 24
Peak memory	653540 kb
Host	smart-37b24d9e-14f0-4881-bfe8-0f62b18d6105
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242674270 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.2242674270
Directory	/workspace/3.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_rw.3299007343
Short name	T2225
Test name
Test status
Simulation time	4149767350 ps
CPU time	350.69 seconds
Started	Jul 24 07:33:10 PM PDT 24
Finished	Jul 24 07:39:01 PM PDT 24
Peak memory	598988 kb
Host	smart-6a76ebc3-af53-4914-9f2e-e117355b580d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299007343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.3299007343
Directory	/workspace/3.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.4047333329
Short name	T394
Test name
Test status
Simulation time	16160172550 ps
CPU time	1948.01 seconds
Started	Jul 24 07:32:53 PM PDT 24
Finished	Jul 24 08:05:22 PM PDT 24
Peak memory	594004 kb
Host	smart-c707fdd6-f061-4f00-a3ca-6ace90e9282b
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047333329 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.4047333329
Directory	/workspace/3.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/3.chip_tl_errors.3606742472
Short name	T2403
Test name
Test status
Simulation time	4128109404 ps
CPU time	363.64 seconds
Started	Jul 24 07:32:50 PM PDT 24
Finished	Jul 24 07:38:54 PM PDT 24
Peak memory	604496 kb
Host	smart-b45d87f3-853e-4822-a159-be40a1a4da18
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606742472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.3606742472
Directory	/workspace/3.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_access_same_device.1452073073
Short name	T2761
Test name
Test status
Simulation time	982495199 ps
CPU time	66.14 seconds
Started	Jul 24 07:33:13 PM PDT 24
Finished	Jul 24 07:34:20 PM PDT 24
Peak memory	576140 kb
Host	smart-46954824-347c-44f8-a067-c4b8ae9cde4e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452073073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 1452073073
Directory	/workspace/3.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.1202029058
Short name	T2069
Test name
Test status
Simulation time	43262230430 ps
CPU time	775.38 seconds
Started	Jul 24 07:33:03 PM PDT 24
Finished	Jul 24 07:45:58 PM PDT 24
Peak memory	577112 kb
Host	smart-64669920-53e1-48b6-933a-b60b4e58191d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202029058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.1202029058
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2263755878
Short name	T1611
Test name
Test status
Simulation time	1470009314 ps
CPU time	63.86 seconds
Started	Jul 24 07:32:57 PM PDT 24
Finished	Jul 24 07:34:01 PM PDT 24
Peak memory	577000 kb
Host	smart-d18a2402-f998-45c5-899d-d727e07fb601
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263755878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .2263755878
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_error_random.2317644035
Short name	T2914
Test name
Test status
Simulation time	246051900 ps
CPU time	22.34 seconds
Started	Jul 24 07:32:56 PM PDT 24
Finished	Jul 24 07:33:19 PM PDT 24
Peak memory	576972 kb
Host	smart-e092b8eb-5297-45c1-9807-6e52e2b3b9cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317644035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2317644035
Directory	/workspace/3.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_random.2325648314
Short name	T1660
Test name
Test status
Simulation time	294701602 ps
CPU time	24.71 seconds
Started	Jul 24 07:33:08 PM PDT 24
Finished	Jul 24 07:33:33 PM PDT 24
Peak memory	577016 kb
Host	smart-d7c3e201-5d83-4a07-bb15-8f9bc4156538
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325648314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.2325648314
Directory	/workspace/3.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_random_large_delays.3204366257
Short name	T1628
Test name
Test status
Simulation time	31717508226 ps
CPU time	317.88 seconds
Started	Jul 24 07:33:13 PM PDT 24
Finished	Jul 24 07:38:31 PM PDT 24
Peak memory	577024 kb
Host	smart-53182b74-d1a9-47fe-a80b-c4e042d4357d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204366257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3204366257
Directory	/workspace/3.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.672617419
Short name	T2927
Test name
Test status
Simulation time	57577708 ps
CPU time	8.36 seconds
Started	Jul 24 07:33:03 PM PDT 24
Finished	Jul 24 07:33:11 PM PDT 24
Peak memory	576132 kb
Host	smart-4fb935a8-e41f-4495-be3a-468c02fa599b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672617419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delay s.672617419
Directory	/workspace/3.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_same_source.2287693429
Short name	T2419
Test name
Test status
Simulation time	386683089 ps
CPU time	30.84 seconds
Started	Jul 24 07:32:59 PM PDT 24
Finished	Jul 24 07:33:30 PM PDT 24
Peak memory	576128 kb
Host	smart-c480f8dc-e146-4534-824b-86d50d01184b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287693429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2287693429
Directory	/workspace/3.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke.817532272
Short name	T2838
Test name
Test status
Simulation time	235055337 ps
CPU time	9.32 seconds
Started	Jul 24 07:33:12 PM PDT 24
Finished	Jul 24 07:33:22 PM PDT 24
Peak memory	574716 kb
Host	smart-83bce9d0-9a5e-4ba7-b4ae-ffbe424c82dd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817532272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.817532272
Directory	/workspace/3.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.1183189701
Short name	T1668
Test name
Test status
Simulation time	6384324791 ps
CPU time	64.38 seconds
Started	Jul 24 07:33:12 PM PDT 24
Finished	Jul 24 07:34:17 PM PDT 24
Peak memory	574892 kb
Host	smart-08f819d0-f433-4440-9079-8ea7abb7b4ac
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183189701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1183189701
Directory	/workspace/3.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.447287503
Short name	T2646
Test name
Test status
Simulation time	6027977735 ps
CPU time	102.73 seconds
Started	Jul 24 07:33:08 PM PDT 24
Finished	Jul 24 07:34:51 PM PDT 24
Peak memory	576284 kb
Host	smart-f6d661ba-5f6b-4ca6-9306-a2d89b35303b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447287503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.447287503
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.721113514
Short name	T579
Test name
Test status
Simulation time	42717642 ps
CPU time	5.88 seconds
Started	Jul 24 07:33:13 PM PDT 24
Finished	Jul 24 07:33:20 PM PDT 24
Peak memory	576020 kb
Host	smart-ee2f14c7-bfa4-4cc3-915f-b2b15b88fef0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721113514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays. 721113514
Directory	/workspace/3.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all.17389228
Short name	T2516
Test name
Test status
Simulation time	1223744993 ps
CPU time	109.59 seconds
Started	Jul 24 07:32:58 PM PDT 24
Finished	Jul 24 07:34:47 PM PDT 24
Peak memory	576456 kb
Host	smart-4a9edf3d-73cd-4cdb-9b85-37b1bab9fd67
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17389228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.17389228
Directory	/workspace/3.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.115130954
Short name	T2011
Test name
Test status
Simulation time	3638379347 ps
CPU time	262.94 seconds
Started	Jul 24 07:33:08 PM PDT 24
Finished	Jul 24 07:37:31 PM PDT 24
Peak memory	576384 kb
Host	smart-b4411e0d-7aff-4894-af3f-2a59b5da511f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115130954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.115130954
Directory	/workspace/3.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3813850341
Short name	T2180
Test name
Test status
Simulation time	567387930 ps
CPU time	142.11 seconds
Started	Jul 24 07:33:08 PM PDT 24
Finished	Jul 24 07:35:31 PM PDT 24
Peak memory	577172 kb
Host	smart-2dbbd6e3-b4d6-4646-8731-746887ced575
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813850341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.3813850341
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3539024795
Short name	T2676
Test name
Test status
Simulation time	13923845893 ps
CPU time	547.56 seconds
Started	Jul 24 07:33:14 PM PDT 24
Finished	Jul 24 07:42:22 PM PDT 24
Peak memory	577148 kb
Host	smart-21e925f9-c7c4-48cc-8873-dc89cbe5a69d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539024795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.3539024795
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.4163048290
Short name	T2032
Test name
Test status
Simulation time	228726683 ps
CPU time	24.38 seconds
Started	Jul 24 07:33:13 PM PDT 24
Finished	Jul 24 07:33:38 PM PDT 24
Peak memory	576900 kb
Host	smart-a0ea8d85-b3c7-44e4-85cc-edc0835c4a43
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163048290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.4163048290
Directory	/workspace/3.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_access_same_device.1981876466
Short name	T2154
Test name
Test status
Simulation time	2621622736 ps
CPU time	101.76 seconds
Started	Jul 24 07:38:21 PM PDT 24
Finished	Jul 24 07:40:03 PM PDT 24
Peak memory	576392 kb
Host	smart-c683d848-5991-436f-b3cf-8cb360b6460a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981876466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .1981876466
Directory	/workspace/30.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2511810814
Short name	T2803
Test name
Test status
Simulation time	96259064860 ps
CPU time	1773.4 seconds
Started	Jul 24 07:38:14 PM PDT 24
Finished	Jul 24 08:07:48 PM PDT 24
Peak memory	576416 kb
Host	smart-159bd52e-fc84-45d0-bc05-d321dba0bc27
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511810814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.2511810814
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.4085668331
Short name	T2525
Test name
Test status
Simulation time	519491656 ps
CPU time	22.48 seconds
Started	Jul 24 07:38:29 PM PDT 24
Finished	Jul 24 07:38:51 PM PDT 24
Peak memory	576156 kb
Host	smart-69c65a66-9fcd-443e-a953-74cfeae3d719
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085668331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.4085668331
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_error_random.3249191373
Short name	T2284
Test name
Test status
Simulation time	431679917 ps
CPU time	33.59 seconds
Started	Jul 24 07:38:25 PM PDT 24
Finished	Jul 24 07:38:58 PM PDT 24
Peak memory	576116 kb
Host	smart-2b1e371c-7e57-4027-84da-9325a54bd2f0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249191373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3249191373
Directory	/workspace/30.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_random.3181215320
Short name	T2377
Test name
Test status
Simulation time	2311095781 ps
CPU time	81.22 seconds
Started	Jul 24 07:38:16 PM PDT 24
Finished	Jul 24 07:39:37 PM PDT 24
Peak memory	577184 kb
Host	smart-a4ce5aaf-4f0d-4357-8b65-1cdeb305d34f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181215320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.3181215320
Directory	/workspace/30.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_random_large_delays.3530692065
Short name	T700
Test name
Test status
Simulation time	41105310962 ps
CPU time	409.7 seconds
Started	Jul 24 07:38:16 PM PDT 24
Finished	Jul 24 07:45:06 PM PDT 24
Peak memory	577120 kb
Host	smart-c3317a4e-885d-4e7b-bdd6-9f8503083bad
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530692065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3530692065
Directory	/workspace/30.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.1382371289
Short name	T2024
Test name
Test status
Simulation time	57490316678 ps
CPU time	939.56 seconds
Started	Jul 24 07:38:29 PM PDT 24
Finished	Jul 24 07:54:09 PM PDT 24
Peak memory	576356 kb
Host	smart-57ee817d-3e3f-402c-aa97-ba359f9c3569
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382371289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1382371289
Directory	/workspace/30.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2199035361
Short name	T2187
Test name
Test status
Simulation time	423128838 ps
CPU time	39.54 seconds
Started	Jul 24 07:38:13 PM PDT 24
Finished	Jul 24 07:38:53 PM PDT 24
Peak memory	576900 kb
Host	smart-eb6ab011-278d-4284-b823-d839fc039e23
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199035361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.2199035361
Directory	/workspace/30.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_same_source.1478846791
Short name	T1835
Test name
Test status
Simulation time	400810445 ps
CPU time	13.35 seconds
Started	Jul 24 07:38:16 PM PDT 24
Finished	Jul 24 07:38:29 PM PDT 24
Peak memory	576092 kb
Host	smart-804885ec-8b16-4671-8cf9-b2db08c6ea44
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478846791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1478846791
Directory	/workspace/30.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke.3085293103
Short name	T2779
Test name
Test status
Simulation time	41555962 ps
CPU time	6.09 seconds
Started	Jul 24 07:38:22 PM PDT 24
Finished	Jul 24 07:38:28 PM PDT 24
Peak memory	574928 kb
Host	smart-9018debc-4eaa-4076-9bfa-25edddeac8b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085293103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3085293103
Directory	/workspace/30.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.506790453
Short name	T2760
Test name
Test status
Simulation time	6644111042 ps
CPU time	67.64 seconds
Started	Jul 24 07:38:25 PM PDT 24
Finished	Jul 24 07:39:33 PM PDT 24
Peak memory	576252 kb
Host	smart-0329af4e-5523-445d-bd90-4eae5fc99297
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506790453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.506790453
Directory	/workspace/30.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2509436856
Short name	T2002
Test name
Test status
Simulation time	6797134334 ps
CPU time	109.53 seconds
Started	Jul 24 07:38:13 PM PDT 24
Finished	Jul 24 07:40:03 PM PDT 24
Peak memory	575016 kb
Host	smart-0b699aa7-f5d7-4513-9aa0-d5c98c22b8d2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509436856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2509436856
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.4199463921
Short name	T1526
Test name
Test status
Simulation time	36334620 ps
CPU time	5.68 seconds
Started	Jul 24 07:38:14 PM PDT 24
Finished	Jul 24 07:38:20 PM PDT 24
Peak memory	574908 kb
Host	smart-8835bcda-2d9c-4a37-be30-8162e19b3f59
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199463921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.4199463921
Directory	/workspace/30.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all.2034468232
Short name	T1975
Test name
Test status
Simulation time	551511313 ps
CPU time	48.27 seconds
Started	Jul 24 07:38:24 PM PDT 24
Finished	Jul 24 07:39:13 PM PDT 24
Peak memory	577168 kb
Host	smart-c3e7f87a-8216-4d7e-b194-54983261db1e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034468232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2034468232
Directory	/workspace/30.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.2861238385
Short name	T2527
Test name
Test status
Simulation time	1654384695 ps
CPU time	119.49 seconds
Started	Jul 24 07:38:24 PM PDT 24
Finished	Jul 24 07:40:24 PM PDT 24
Peak memory	577012 kb
Host	smart-53fdf69a-8dcf-4774-9f0d-01c31762a03c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861238385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2861238385
Directory	/workspace/30.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3191099083
Short name	T2410
Test name
Test status
Simulation time	2150646388 ps
CPU time	251.87 seconds
Started	Jul 24 07:38:24 PM PDT 24
Finished	Jul 24 07:42:36 PM PDT 24
Peak memory	576476 kb
Host	smart-3cb12bf8-e234-4f78-8de1-803c39008ff0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191099083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.3191099083
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.4014789501
Short name	T1937
Test name
Test status
Simulation time	993491270 ps
CPU time	253.54 seconds
Started	Jul 24 07:38:29 PM PDT 24
Finished	Jul 24 07:42:43 PM PDT 24
Peak memory	577148 kb
Host	smart-29e6cc4e-6906-4f0f-b78d-5f6029ba1a76
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014789501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.4014789501
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.2095972398
Short name	T556
Test name
Test status
Simulation time	89932998 ps
CPU time	12.27 seconds
Started	Jul 24 07:38:26 PM PDT 24
Finished	Jul 24 07:38:38 PM PDT 24
Peak memory	576180 kb
Host	smart-46e86de5-ef32-48d1-9168-029cbedd2bcb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095972398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2095972398
Directory	/workspace/30.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_access_same_device.2305584036
Short name	T1996
Test name
Test status
Simulation time	320634225 ps
CPU time	24.82 seconds
Started	Jul 24 07:38:24 PM PDT 24
Finished	Jul 24 07:38:49 PM PDT 24
Peak memory	576168 kb
Host	smart-b26f287d-98d8-4598-850c-b63ede4c79b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305584036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .2305584036
Directory	/workspace/31.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2079683891
Short name	T2114
Test name
Test status
Simulation time	71863671801 ps
CPU time	1195.98 seconds
Started	Jul 24 07:38:29 PM PDT 24
Finished	Jul 24 07:58:25 PM PDT 24
Peak memory	577244 kb
Host	smart-b05c4f35-c2b1-463f-b27c-1569ee886132
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079683891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.2079683891
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3510903899
Short name	T2695
Test name
Test status
Simulation time	1199501262 ps
CPU time	47.92 seconds
Started	Jul 24 07:38:40 PM PDT 24
Finished	Jul 24 07:39:28 PM PDT 24
Peak memory	577052 kb
Host	smart-b1608cd7-963e-4d03-9ae9-8cc3184aa7b3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510903899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.3510903899
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_error_random.1009566544
Short name	T1851
Test name
Test status
Simulation time	1542524472 ps
CPU time	51.31 seconds
Started	Jul 24 07:38:32 PM PDT 24
Finished	Jul 24 07:39:24 PM PDT 24
Peak memory	576916 kb
Host	smart-56ebae3b-fde3-414f-ae6c-8d8c4e229bd0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009566544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1009566544
Directory	/workspace/31.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_random.1642943064
Short name	T2439
Test name
Test status
Simulation time	217782027 ps
CPU time	10.79 seconds
Started	Jul 24 07:38:24 PM PDT 24
Finished	Jul 24 07:38:35 PM PDT 24
Peak memory	576168 kb
Host	smart-33a63e5b-5e8b-4e5a-8c1d-2cd24ac4747e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642943064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.1642943064
Directory	/workspace/31.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_random_large_delays.1082196612
Short name	T2163
Test name
Test status
Simulation time	46390786015 ps
CPU time	487.95 seconds
Started	Jul 24 07:38:24 PM PDT 24
Finished	Jul 24 07:46:32 PM PDT 24
Peak memory	576280 kb
Host	smart-f3190dc6-af5a-443f-b932-9f71861bb2cb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082196612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1082196612
Directory	/workspace/31.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2878469999
Short name	T1466
Test name
Test status
Simulation time	20689077398 ps
CPU time	328.48 seconds
Started	Jul 24 07:38:28 PM PDT 24
Finished	Jul 24 07:43:56 PM PDT 24
Peak memory	576348 kb
Host	smart-a0164cc6-c073-4c2d-9077-080aa08e3005
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878469999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2878469999
Directory	/workspace/31.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.4186051519
Short name	T1541
Test name
Test status
Simulation time	285313053 ps
CPU time	28.07 seconds
Started	Jul 24 07:38:31 PM PDT 24
Finished	Jul 24 07:38:59 PM PDT 24
Peak memory	576932 kb
Host	smart-e144968e-c8f0-4a8e-ae63-6173909af3f8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186051519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.4186051519
Directory	/workspace/31.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_same_source.3053598927
Short name	T2241
Test name
Test status
Simulation time	429478632 ps
CPU time	30.14 seconds
Started	Jul 24 07:38:41 PM PDT 24
Finished	Jul 24 07:39:11 PM PDT 24
Peak memory	577032 kb
Host	smart-751e32ae-f207-4506-b926-a4e0a7e6798a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053598927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3053598927
Directory	/workspace/31.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke.2388718290
Short name	T1528
Test name
Test status
Simulation time	213338440 ps
CPU time	10.13 seconds
Started	Jul 24 07:38:23 PM PDT 24
Finished	Jul 24 07:38:33 PM PDT 24
Peak memory	574876 kb
Host	smart-60725b53-065a-425d-8f7b-8d629fa291a5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388718290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2388718290
Directory	/workspace/31.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.2180208946
Short name	T1763
Test name
Test status
Simulation time	8938652928 ps
CPU time	93.77 seconds
Started	Jul 24 07:38:25 PM PDT 24
Finished	Jul 24 07:39:59 PM PDT 24
Peak memory	575012 kb
Host	smart-15eecf9c-83c3-4915-a8d4-787747a12564
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180208946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2180208946
Directory	/workspace/31.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3079500607
Short name	T1511
Test name
Test status
Simulation time	5694615301 ps
CPU time	87.18 seconds
Started	Jul 24 07:38:24 PM PDT 24
Finished	Jul 24 07:39:52 PM PDT 24
Peak memory	574964 kb
Host	smart-2170dfbe-9ad2-411a-ae5f-21eed430fff2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079500607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3079500607
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.852163699
Short name	T2043
Test name
Test status
Simulation time	49126923 ps
CPU time	6.61 seconds
Started	Jul 24 07:38:41 PM PDT 24
Finished	Jul 24 07:38:48 PM PDT 24
Peak memory	574988 kb
Host	smart-7e350df1-1f9e-45b6-9869-0f29382f1bd5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852163699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays .852163699
Directory	/workspace/31.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all.3674393203
Short name	T1904
Test name
Test status
Simulation time	3012149970 ps
CPU time	236.55 seconds
Started	Jul 24 07:38:41 PM PDT 24
Finished	Jul 24 07:42:38 PM PDT 24
Peak memory	577332 kb
Host	smart-778890ee-3088-4b36-a0cb-b54df4af1af9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674393203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3674393203
Directory	/workspace/31.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.4041056384
Short name	T2560
Test name
Test status
Simulation time	331109959 ps
CPU time	29.43 seconds
Started	Jul 24 07:38:26 PM PDT 24
Finished	Jul 24 07:38:55 PM PDT 24
Peak memory	576156 kb
Host	smart-eb9e727f-a0af-4cb1-ae88-4417bde4daf9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041056384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.4041056384
Directory	/workspace/31.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.186266630
Short name	T2462
Test name
Test status
Simulation time	12963931669 ps
CPU time	697.71 seconds
Started	Jul 24 07:38:27 PM PDT 24
Finished	Jul 24 07:50:05 PM PDT 24
Peak memory	577272 kb
Host	smart-b0c31448-a3b6-4d38-aaea-07a499a4dd7a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186266630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.186266630
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.4193781933
Short name	T2901
Test name
Test status
Simulation time	6691841167 ps
CPU time	282.38 seconds
Started	Jul 24 07:38:25 PM PDT 24
Finished	Jul 24 07:43:07 PM PDT 24
Peak memory	577180 kb
Host	smart-6e3736bb-cd93-4766-a592-dfb84b771892
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193781933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.4193781933
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.86104876
Short name	T1601
Test name
Test status
Simulation time	1194213658 ps
CPU time	50.61 seconds
Started	Jul 24 07:38:41 PM PDT 24
Finished	Jul 24 07:39:32 PM PDT 24
Peak memory	576284 kb
Host	smart-20d41e10-e3d6-4fff-b0c9-66c56df3d0d0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86104876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.86104876
Directory	/workspace/31.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_access_same_device.3021906183
Short name	T902
Test name
Test status
Simulation time	2874691983 ps
CPU time	134.28 seconds
Started	Jul 24 07:38:35 PM PDT 24
Finished	Jul 24 07:40:50 PM PDT 24
Peak memory	577168 kb
Host	smart-71ec0790-06c3-431f-b234-9dd2a5c3790a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021906183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .3021906183
Directory	/workspace/32.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1732530442
Short name	T2852
Test name
Test status
Simulation time	110595799656 ps
CPU time	2096.71 seconds
Started	Jul 24 07:38:39 PM PDT 24
Finished	Jul 24 08:13:36 PM PDT 24
Peak memory	576240 kb
Host	smart-99e582c8-0e41-4a9f-a696-1e0510f89eff
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732530442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.1732530442
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3079607319
Short name	T1993
Test name
Test status
Simulation time	170294378 ps
CPU time	9.35 seconds
Started	Jul 24 07:38:51 PM PDT 24
Finished	Jul 24 07:39:00 PM PDT 24
Peak memory	574840 kb
Host	smart-6c92af5e-eb31-4779-adc5-60550c03d50e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079607319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.3079607319
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_error_random.671544530
Short name	T2103
Test name
Test status
Simulation time	698181169 ps
CPU time	24.82 seconds
Started	Jul 24 07:38:36 PM PDT 24
Finished	Jul 24 07:39:01 PM PDT 24
Peak memory	576052 kb
Host	smart-b7da75d3-ef84-44ce-ac26-6adf847cfa06
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671544530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.671544530
Directory	/workspace/32.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_random.2023331600
Short name	T614
Test name
Test status
Simulation time	285557151 ps
CPU time	27.8 seconds
Started	Jul 24 07:38:32 PM PDT 24
Finished	Jul 24 07:39:00 PM PDT 24
Peak memory	576912 kb
Host	smart-9878e377-31af-46c1-a5d9-3dc2ca94b9c4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023331600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.2023331600
Directory	/workspace/32.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_random_large_delays.3167626689
Short name	T2878
Test name
Test status
Simulation time	100471168563 ps
CPU time	1090.01 seconds
Started	Jul 24 07:38:40 PM PDT 24
Finished	Jul 24 07:56:50 PM PDT 24
Peak memory	576240 kb
Host	smart-dd8f9f67-3998-4ba3-b516-0f2220f6d3a8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167626689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3167626689
Directory	/workspace/32.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.837725258
Short name	T597
Test name
Test status
Simulation time	66289010689 ps
CPU time	1192.8 seconds
Started	Jul 24 07:38:37 PM PDT 24
Finished	Jul 24 07:58:31 PM PDT 24
Peak memory	576384 kb
Host	smart-9d30b438-b053-4718-aea9-5a48465faf5a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837725258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.837725258
Directory	/workspace/32.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.3331776960
Short name	T693
Test name
Test status
Simulation time	218511560 ps
CPU time	17.94 seconds
Started	Jul 24 07:38:38 PM PDT 24
Finished	Jul 24 07:38:56 PM PDT 24
Peak memory	576180 kb
Host	smart-a648af1b-1c9f-4eaf-8cde-3e269062942f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331776960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.3331776960
Directory	/workspace/32.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_same_source.3851831729
Short name	T2295
Test name
Test status
Simulation time	1111347382 ps
CPU time	34.97 seconds
Started	Jul 24 07:38:36 PM PDT 24
Finished	Jul 24 07:39:12 PM PDT 24
Peak memory	576888 kb
Host	smart-a7a6609b-009d-4927-9ea5-86c5557f955f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851831729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3851831729
Directory	/workspace/32.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke.4232456418
Short name	T2718
Test name
Test status
Simulation time	219357188 ps
CPU time	8.72 seconds
Started	Jul 24 07:38:26 PM PDT 24
Finished	Jul 24 07:38:35 PM PDT 24
Peak memory	574784 kb
Host	smart-baede50c-6447-45b8-a0a5-451ebeaaa372
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232456418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.4232456418
Directory	/workspace/32.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.1253563765
Short name	T1510
Test name
Test status
Simulation time	9200484473 ps
CPU time	85.84 seconds
Started	Jul 24 07:38:42 PM PDT 24
Finished	Jul 24 07:40:08 PM PDT 24
Peak memory	575048 kb
Host	smart-abaa6a08-e3e9-4cd1-9cc8-1884ac9d16ce
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253563765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1253563765
Directory	/workspace/32.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.818264399
Short name	T1700
Test name
Test status
Simulation time	5115269984 ps
CPU time	82.86 seconds
Started	Jul 24 07:38:41 PM PDT 24
Finished	Jul 24 07:40:04 PM PDT 24
Peak memory	575092 kb
Host	smart-b8470b56-ca9e-4768-903a-b1ad41fd4f5e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818264399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.818264399
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.345296989
Short name	T1944
Test name
Test status
Simulation time	43770015 ps
CPU time	5.97 seconds
Started	Jul 24 07:38:26 PM PDT 24
Finished	Jul 24 07:38:32 PM PDT 24
Peak memory	575008 kb
Host	smart-71d83b1c-7f72-4f06-9fe3-b0cec285b81b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345296989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays .345296989
Directory	/workspace/32.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all.3539241250
Short name	T2822
Test name
Test status
Simulation time	2337556426 ps
CPU time	186.67 seconds
Started	Jul 24 07:38:46 PM PDT 24
Finished	Jul 24 07:41:52 PM PDT 24
Peak memory	576544 kb
Host	smart-9da19bfd-08fd-46dd-b5f7-6dd70927c942
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539241250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3539241250
Directory	/workspace/32.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.2948736596
Short name	T253
Test name
Test status
Simulation time	2510081572 ps
CPU time	81.85 seconds
Started	Jul 24 07:38:50 PM PDT 24
Finished	Jul 24 07:40:12 PM PDT 24
Peak memory	577140 kb
Host	smart-b6ed4e88-4484-4491-b56e-b29486e1a042
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948736596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2948736596
Directory	/workspace/32.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.662725189
Short name	T705
Test name
Test status
Simulation time	1474302664 ps
CPU time	206.07 seconds
Started	Jul 24 07:38:45 PM PDT 24
Finished	Jul 24 07:42:12 PM PDT 24
Peak memory	577024 kb
Host	smart-edfa0694-26c3-46f5-98cf-7ea2c0d66c21
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662725189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_ with_rand_reset.662725189
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3272463877
Short name	T958
Test name
Test status
Simulation time	448534735 ps
CPU time	62.28 seconds
Started	Jul 24 07:38:49 PM PDT 24
Finished	Jul 24 07:39:52 PM PDT 24
Peak memory	577108 kb
Host	smart-9f5e7868-30ec-40a3-b087-65b6f51b0c29
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272463877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.3272463877
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.2388376225
Short name	T2264
Test name
Test status
Simulation time	246099281 ps
CPU time	27.46 seconds
Started	Jul 24 07:38:38 PM PDT 24
Finished	Jul 24 07:39:06 PM PDT 24
Peak memory	576232 kb
Host	smart-c3b40c97-9457-4955-8bd6-aa8dd7d608f1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388376225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2388376225
Directory	/workspace/32.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_access_same_device.3510575908
Short name	T2036
Test name
Test status
Simulation time	254495437 ps
CPU time	24.03 seconds
Started	Jul 24 07:38:49 PM PDT 24
Finished	Jul 24 07:39:13 PM PDT 24
Peak memory	576160 kb
Host	smart-b7162f3a-6c67-423b-9627-cbf949815019
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510575908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .3510575908
Directory	/workspace/33.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1060617776
Short name	T1633
Test name
Test status
Simulation time	74133951447 ps
CPU time	1332.87 seconds
Started	Jul 24 07:38:47 PM PDT 24
Finished	Jul 24 08:01:00 PM PDT 24
Peak memory	577172 kb
Host	smart-8eb67426-90e4-46e6-95ae-1060d39ec720
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060617776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.1060617776
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1719653678
Short name	T1448
Test name
Test status
Simulation time	826666205 ps
CPU time	29.64 seconds
Started	Jul 24 07:39:00 PM PDT 24
Finished	Jul 24 07:39:30 PM PDT 24
Peak memory	576920 kb
Host	smart-89e42b1d-89db-4510-b84d-d316c8a3991a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719653678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.1719653678
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_error_random.4291610539
Short name	T2601
Test name
Test status
Simulation time	1483590095 ps
CPU time	55.32 seconds
Started	Jul 24 07:38:57 PM PDT 24
Finished	Jul 24 07:39:52 PM PDT 24
Peak memory	576976 kb
Host	smart-3328c9cc-c0f8-4fdd-834c-5d5a825ca526
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291610539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.4291610539
Directory	/workspace/33.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_random.4265579825
Short name	T2843
Test name
Test status
Simulation time	520028526 ps
CPU time	19.02 seconds
Started	Jul 24 07:38:52 PM PDT 24
Finished	Jul 24 07:39:12 PM PDT 24
Peak memory	576960 kb
Host	smart-8833a2f4-d521-4e8e-b109-54642e357f33
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265579825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.4265579825
Directory	/workspace/33.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_random_large_delays.4138416894
Short name	T2255
Test name
Test status
Simulation time	75211754123 ps
CPU time	747.9 seconds
Started	Jul 24 07:38:53 PM PDT 24
Finished	Jul 24 07:51:21 PM PDT 24
Peak memory	576272 kb
Host	smart-09c6246e-d3a2-4242-8f61-0171d8194c24
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138416894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.4138416894
Directory	/workspace/33.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.1903265655
Short name	T2328
Test name
Test status
Simulation time	46076374869 ps
CPU time	754.29 seconds
Started	Jul 24 07:38:46 PM PDT 24
Finished	Jul 24 07:51:21 PM PDT 24
Peak memory	577144 kb
Host	smart-2fe29a9b-d7e3-4657-a303-7a23cd62427e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903265655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1903265655
Directory	/workspace/33.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.861516574
Short name	T2775
Test name
Test status
Simulation time	64073263 ps
CPU time	8.96 seconds
Started	Jul 24 07:38:48 PM PDT 24
Finished	Jul 24 07:38:57 PM PDT 24
Peak memory	574956 kb
Host	smart-7b4536e0-2838-43d3-ae31-b12017c963f8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861516574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_dela ys.861516574
Directory	/workspace/33.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_same_source.1176487507
Short name	T2647
Test name
Test status
Simulation time	2630746743 ps
CPU time	86.14 seconds
Started	Jul 24 07:38:51 PM PDT 24
Finished	Jul 24 07:40:17 PM PDT 24
Peak memory	576292 kb
Host	smart-7b66e0d0-06d9-4d5e-8b5f-dbb4f447b4c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176487507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1176487507
Directory	/workspace/33.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke.883053740
Short name	T1914
Test name
Test status
Simulation time	51216859 ps
CPU time	6.28 seconds
Started	Jul 24 07:38:53 PM PDT 24
Finished	Jul 24 07:38:59 PM PDT 24
Peak memory	574820 kb
Host	smart-2c85f3a3-fc5f-456a-96d7-e9293a7154f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883053740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.883053740
Directory	/workspace/33.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.1484690800
Short name	T2152
Test name
Test status
Simulation time	8236698812 ps
CPU time	84.74 seconds
Started	Jul 24 07:38:50 PM PDT 24
Finished	Jul 24 07:40:15 PM PDT 24
Peak memory	574948 kb
Host	smart-503b0a30-ab94-4679-aa85-9d71200706a4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484690800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1484690800
Directory	/workspace/33.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.685510142
Short name	T1703
Test name
Test status
Simulation time	5514634144 ps
CPU time	87.11 seconds
Started	Jul 24 07:38:46 PM PDT 24
Finished	Jul 24 07:40:13 PM PDT 24
Peak memory	575128 kb
Host	smart-095cec71-c300-4a84-a8ec-8943962ea5c0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685510142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.685510142
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1621468961
Short name	T1489
Test name
Test status
Simulation time	43154447 ps
CPU time	6.44 seconds
Started	Jul 24 07:38:49 PM PDT 24
Finished	Jul 24 07:38:56 PM PDT 24
Peak memory	574800 kb
Host	smart-fb02b2c4-8a80-4a71-91ae-51eca90d704a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621468961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.1621468961
Directory	/workspace/33.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all.867001199
Short name	T2671
Test name
Test status
Simulation time	11849314757 ps
CPU time	502.29 seconds
Started	Jul 24 07:38:58 PM PDT 24
Finished	Jul 24 07:47:21 PM PDT 24
Peak memory	576424 kb
Host	smart-fcef2178-3247-419e-a056-5703057ed478
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867001199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.867001199
Directory	/workspace/33.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.4071339565
Short name	T2342
Test name
Test status
Simulation time	620583665 ps
CPU time	18.75 seconds
Started	Jul 24 07:38:58 PM PDT 24
Finished	Jul 24 07:39:17 PM PDT 24
Peak memory	576916 kb
Host	smart-d5730bc2-d681-4571-b2be-b01a76caae98
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071339565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4071339565
Directory	/workspace/33.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.871455234
Short name	T2898
Test name
Test status
Simulation time	9874851026 ps
CPU time	557.93 seconds
Started	Jul 24 07:38:59 PM PDT 24
Finished	Jul 24 07:48:17 PM PDT 24
Peak memory	577280 kb
Host	smart-9c5c44fd-d57f-45c3-b6bb-a70e008554db
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871455234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_ with_rand_reset.871455234
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3156409111
Short name	T2530
Test name
Test status
Simulation time	166657778 ps
CPU time	45.54 seconds
Started	Jul 24 07:38:59 PM PDT 24
Finished	Jul 24 07:39:44 PM PDT 24
Peak memory	576084 kb
Host	smart-17bd798b-62fe-400f-864f-3e0583fcfe28
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156409111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.3156409111
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.3936216295
Short name	T2755
Test name
Test status
Simulation time	988525945 ps
CPU time	47.91 seconds
Started	Jul 24 07:38:59 PM PDT 24
Finished	Jul 24 07:39:47 PM PDT 24
Peak memory	576208 kb
Host	smart-4fecdea3-43c0-4bc0-a43c-eb865f58ddae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936216295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3936216295
Directory	/workspace/33.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_access_same_device.1928133192
Short name	T2795
Test name
Test status
Simulation time	79253791 ps
CPU time	8.24 seconds
Started	Jul 24 07:39:08 PM PDT 24
Finished	Jul 24 07:39:16 PM PDT 24
Peak memory	574936 kb
Host	smart-557d59a5-28c9-46fc-9d6a-9c35e58b05ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928133192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1928133192
Directory	/workspace/34.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1819849664
Short name	T2398
Test name
Test status
Simulation time	204463745 ps
CPU time	22.47 seconds
Started	Jul 24 07:39:09 PM PDT 24
Finished	Jul 24 07:39:31 PM PDT 24
Peak memory	577004 kb
Host	smart-85bb1760-ac86-435c-a526-a61d5fe27466
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819849664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.1819849664
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_error_random.3832762064
Short name	T748
Test name
Test status
Simulation time	2313355007 ps
CPU time	79.01 seconds
Started	Jul 24 07:39:09 PM PDT 24
Finished	Jul 24 07:40:28 PM PDT 24
Peak memory	577028 kb
Host	smart-e8e7624e-24ff-45ec-9252-fbbaddc00a07
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832762064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3832762064
Directory	/workspace/34.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_random.184687624
Short name	T2919
Test name
Test status
Simulation time	1338433765 ps
CPU time	40.86 seconds
Started	Jul 24 07:38:58 PM PDT 24
Finished	Jul 24 07:39:39 PM PDT 24
Peak memory	576180 kb
Host	smart-d61c8b5b-fdab-43cb-886f-0405c7b40e2c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184687624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.184687624
Directory	/workspace/34.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_random_large_delays.1532126150
Short name	T1941
Test name
Test status
Simulation time	102788582907 ps
CPU time	1047.92 seconds
Started	Jul 24 07:38:59 PM PDT 24
Finished	Jul 24 07:56:27 PM PDT 24
Peak memory	577116 kb
Host	smart-d42d8fa6-4248-4e0a-a8cf-a775031eec1d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532126150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1532126150
Directory	/workspace/34.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.574096545
Short name	T713
Test name
Test status
Simulation time	50087246082 ps
CPU time	760.88 seconds
Started	Jul 24 07:39:00 PM PDT 24
Finished	Jul 24 07:51:41 PM PDT 24
Peak memory	576352 kb
Host	smart-1066170a-0941-4a06-bf4b-7f1ba4b2050a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574096545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.574096545
Directory	/workspace/34.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.366632018
Short name	T1869
Test name
Test status
Simulation time	561782616 ps
CPU time	43.45 seconds
Started	Jul 24 07:39:00 PM PDT 24
Finished	Jul 24 07:39:44 PM PDT 24
Peak memory	576180 kb
Host	smart-12c9ee55-4922-4715-882a-7220a30e1fde
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366632018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_dela ys.366632018
Directory	/workspace/34.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_same_source.441973940
Short name	T2924
Test name
Test status
Simulation time	86565615 ps
CPU time	9.35 seconds
Started	Jul 24 07:39:08 PM PDT 24
Finished	Jul 24 07:39:18 PM PDT 24
Peak memory	576936 kb
Host	smart-b55709ab-a7d3-4b23-8a62-8e1e95c402ee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441973940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.441973940
Directory	/workspace/34.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke.456757709
Short name	T1561
Test name
Test status
Simulation time	196954388 ps
CPU time	9.09 seconds
Started	Jul 24 07:38:58 PM PDT 24
Finished	Jul 24 07:39:07 PM PDT 24
Peak memory	576156 kb
Host	smart-b70c6640-91d5-4e48-86c9-aff1bc0d36ed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456757709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.456757709
Directory	/workspace/34.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.1714441816
Short name	T2745
Test name
Test status
Simulation time	6388489207 ps
CPU time	66.94 seconds
Started	Jul 24 07:38:59 PM PDT 24
Finished	Jul 24 07:40:06 PM PDT 24
Peak memory	575032 kb
Host	smart-24dd6d34-563b-4c10-98f5-10592f22264b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714441816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1714441816
Directory	/workspace/34.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1976941445
Short name	T653
Test name
Test status
Simulation time	4908523724 ps
CPU time	80.31 seconds
Started	Jul 24 07:38:59 PM PDT 24
Finished	Jul 24 07:40:20 PM PDT 24
Peak memory	575008 kb
Host	smart-510ca6d8-6f30-4d17-baa7-4420eeccb7c6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976941445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1976941445
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.58872398
Short name	T1938
Test name
Test status
Simulation time	36990243 ps
CPU time	6.1 seconds
Started	Jul 24 07:38:58 PM PDT 24
Finished	Jul 24 07:39:04 PM PDT 24
Peak memory	574820 kb
Host	smart-5a65b64d-de46-47d7-b662-636411debdd4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58872398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.58872398
Directory	/workspace/34.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all.2263111038
Short name	T578
Test name
Test status
Simulation time	4374914228 ps
CPU time	361.33 seconds
Started	Jul 24 07:39:09 PM PDT 24
Finished	Jul 24 07:45:11 PM PDT 24
Peak memory	577276 kb
Host	smart-35469b61-c69a-42bc-80a5-27d74eecc611
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263111038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2263111038
Directory	/workspace/34.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.3012732238
Short name	T2380
Test name
Test status
Simulation time	1465923693 ps
CPU time	111.75 seconds
Started	Jul 24 07:39:08 PM PDT 24
Finished	Jul 24 07:41:00 PM PDT 24
Peak memory	577164 kb
Host	smart-9f61a641-659e-4604-abe8-57eb27e4004e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012732238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3012732238
Directory	/workspace/34.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2588967254
Short name	T2851
Test name
Test status
Simulation time	2534020425 ps
CPU time	314.51 seconds
Started	Jul 24 07:39:08 PM PDT 24
Finished	Jul 24 07:44:23 PM PDT 24
Peak memory	577228 kb
Host	smart-06590727-8842-4cd8-ac7d-695cb4902593
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588967254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.2588967254
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3997083012
Short name	T1745
Test name
Test status
Simulation time	369447182 ps
CPU time	69.06 seconds
Started	Jul 24 07:39:09 PM PDT 24
Finished	Jul 24 07:40:18 PM PDT 24
Peak memory	577216 kb
Host	smart-283179bc-7b94-474e-81d5-dd1eb19e9310
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997083012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.3997083012
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.2576134556
Short name	T545
Test name
Test status
Simulation time	312121209 ps
CPU time	37.03 seconds
Started	Jul 24 07:39:07 PM PDT 24
Finished	Jul 24 07:39:44 PM PDT 24
Peak memory	577068 kb
Host	smart-68680d39-1c53-4c24-b093-2ff218c7f5cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576134556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2576134556
Directory	/workspace/34.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_access_same_device.3817016585
Short name	T1931
Test name
Test status
Simulation time	3811526667 ps
CPU time	164.43 seconds
Started	Jul 24 07:39:20 PM PDT 24
Finished	Jul 24 07:42:04 PM PDT 24
Peak memory	577176 kb
Host	smart-6d53c893-17ef-4f3b-9104-e5c49ea14739
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817016585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .3817016585
Directory	/workspace/35.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1960753799
Short name	T908
Test name
Test status
Simulation time	38213619335 ps
CPU time	644.05 seconds
Started	Jul 24 07:39:18 PM PDT 24
Finished	Jul 24 07:50:03 PM PDT 24
Peak memory	577200 kb
Host	smart-199edee2-1020-4979-be43-9b64702dcc1b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960753799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.1960753799
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3104109659
Short name	T561
Test name
Test status
Simulation time	1203943465 ps
CPU time	50.4 seconds
Started	Jul 24 07:39:23 PM PDT 24
Finished	Jul 24 07:40:13 PM PDT 24
Peak memory	576224 kb
Host	smart-0db8fda9-6ef9-468b-94eb-e05f2489a9ec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104109659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.3104109659
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_error_random.439127681
Short name	T2076
Test name
Test status
Simulation time	188678848 ps
CPU time	19.09 seconds
Started	Jul 24 07:39:21 PM PDT 24
Finished	Jul 24 07:39:40 PM PDT 24
Peak memory	576124 kb
Host	smart-e6616c5b-369a-43ff-a84c-f7c10ccf92b3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439127681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.439127681
Directory	/workspace/35.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_random.2584027593
Short name	T585
Test name
Test status
Simulation time	191265788 ps
CPU time	19.28 seconds
Started	Jul 24 07:39:17 PM PDT 24
Finished	Jul 24 07:39:37 PM PDT 24
Peak memory	576132 kb
Host	smart-60171fe5-c8a9-4db0-bae2-51199bcafd2a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584027593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.2584027593
Directory	/workspace/35.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_random_large_delays.2742464642
Short name	T2087
Test name
Test status
Simulation time	5373584652 ps
CPU time	57.94 seconds
Started	Jul 24 07:39:19 PM PDT 24
Finished	Jul 24 07:40:17 PM PDT 24
Peak memory	575028 kb
Host	smart-238d0d5f-9e56-4fbf-821d-9a477666c78c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742464642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2742464642
Directory	/workspace/35.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.408472629
Short name	T1666
Test name
Test status
Simulation time	43022822836 ps
CPU time	690.74 seconds
Started	Jul 24 07:39:17 PM PDT 24
Finished	Jul 24 07:50:48 PM PDT 24
Peak memory	577104 kb
Host	smart-0a317ce8-c779-4de7-b511-ab250a82bce6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408472629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.408472629
Directory	/workspace/35.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.16119120
Short name	T2375
Test name
Test status
Simulation time	654602272 ps
CPU time	55.03 seconds
Started	Jul 24 07:39:25 PM PDT 24
Finished	Jul 24 07:40:20 PM PDT 24
Peak memory	576940 kb
Host	smart-c86f9696-3af6-46cf-8146-4580b42bd77b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16119120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delay s.16119120
Directory	/workspace/35.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_same_source.2855994961
Short name	T2033
Test name
Test status
Simulation time	1324426116 ps
CPU time	40.69 seconds
Started	Jul 24 07:39:17 PM PDT 24
Finished	Jul 24 07:39:58 PM PDT 24
Peak memory	576164 kb
Host	smart-92287324-5330-494c-a1b1-2fcbb9d508a5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855994961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2855994961
Directory	/workspace/35.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke.2164076101
Short name	T2139
Test name
Test status
Simulation time	52746403 ps
CPU time	6.68 seconds
Started	Jul 24 07:39:10 PM PDT 24
Finished	Jul 24 07:39:16 PM PDT 24
Peak memory	574888 kb
Host	smart-ba691074-4c5e-4688-ac66-cf2b8146113b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164076101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2164076101
Directory	/workspace/35.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.3925815337
Short name	T697
Test name
Test status
Simulation time	6886671617 ps
CPU time	71.43 seconds
Started	Jul 24 07:39:23 PM PDT 24
Finished	Jul 24 07:40:34 PM PDT 24
Peak memory	575124 kb
Host	smart-b2f5f2aa-7675-423f-8226-3b283944a588
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925815337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3925815337
Directory	/workspace/35.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1754011397
Short name	T2507
Test name
Test status
Simulation time	5338607857 ps
CPU time	91.12 seconds
Started	Jul 24 07:39:23 PM PDT 24
Finished	Jul 24 07:40:55 PM PDT 24
Peak memory	575000 kb
Host	smart-8fc52102-8ee0-461c-a263-13024db3f685
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754011397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1754011397
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.765249215
Short name	T1508
Test name
Test status
Simulation time	48920498 ps
CPU time	6.72 seconds
Started	Jul 24 07:39:19 PM PDT 24
Finished	Jul 24 07:39:26 PM PDT 24
Peak memory	574968 kb
Host	smart-c10d56e9-181e-4c69-a65f-cd607ebb2375
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765249215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays .765249215
Directory	/workspace/35.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all.469501083
Short name	T591
Test name
Test status
Simulation time	3069071911 ps
CPU time	285.92 seconds
Started	Jul 24 07:39:22 PM PDT 24
Finished	Jul 24 07:44:08 PM PDT 24
Peak memory	577268 kb
Host	smart-ef1dc534-254e-41f4-8cb1-8ee643ea48f2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469501083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.469501083
Directory	/workspace/35.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.2651162701
Short name	T632
Test name
Test status
Simulation time	6837700933 ps
CPU time	764.33 seconds
Started	Jul 24 07:39:19 PM PDT 24
Finished	Jul 24 07:52:03 PM PDT 24
Peak memory	576440 kb
Host	smart-e03fb567-d6d3-469a-bdec-a940e63e1fc7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651162701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.2651162701
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3097957213
Short name	T723
Test name
Test status
Simulation time	3086485121 ps
CPU time	138.21 seconds
Started	Jul 24 07:39:18 PM PDT 24
Finished	Jul 24 07:41:37 PM PDT 24
Peak memory	576364 kb
Host	smart-cfed1349-5e2a-45fb-bb7f-3106feb15002
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097957213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.3097957213
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1125950379
Short name	T2248
Test name
Test status
Simulation time	118396157 ps
CPU time	17.72 seconds
Started	Jul 24 07:39:20 PM PDT 24
Finished	Jul 24 07:39:37 PM PDT 24
Peak memory	577076 kb
Host	smart-dff4d466-f13e-4ad2-b3e8-3124dbc9726e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125950379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1125950379
Directory	/workspace/35.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_access_same_device.3419681116
Short name	T2835
Test name
Test status
Simulation time	705469608 ps
CPU time	62.93 seconds
Started	Jul 24 07:39:28 PM PDT 24
Finished	Jul 24 07:40:31 PM PDT 24
Peak memory	577008 kb
Host	smart-0dabcf13-e198-4156-83db-4ee055089905
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419681116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .3419681116
Directory	/workspace/36.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1410406980
Short name	T2827
Test name
Test status
Simulation time	80746053376 ps
CPU time	1395.58 seconds
Started	Jul 24 07:39:27 PM PDT 24
Finished	Jul 24 08:02:43 PM PDT 24
Peak memory	576352 kb
Host	smart-24217495-54c6-449b-bc59-cbc6b93bc7c1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410406980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.1410406980
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3940341849
Short name	T1686
Test name
Test status
Simulation time	133457519 ps
CPU time	16.87 seconds
Started	Jul 24 07:39:43 PM PDT 24
Finished	Jul 24 07:40:00 PM PDT 24
Peak memory	576920 kb
Host	smart-a9634523-5ae7-4c49-b4d2-9b2b0b3f3731
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940341849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3940341849
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_error_random.1491673762
Short name	T1824
Test name
Test status
Simulation time	773230751 ps
CPU time	28.78 seconds
Started	Jul 24 07:39:29 PM PDT 24
Finished	Jul 24 07:39:58 PM PDT 24
Peak memory	576992 kb
Host	smart-cf4cb28b-6a03-493f-b97e-97f6265fd0f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491673762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1491673762
Directory	/workspace/36.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_random.3588908257
Short name	T1733
Test name
Test status
Simulation time	154167258 ps
CPU time	14.79 seconds
Started	Jul 24 07:39:21 PM PDT 24
Finished	Jul 24 07:39:36 PM PDT 24
Peak memory	577072 kb
Host	smart-b015347d-79ab-40fa-8484-774d50eb23ca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588908257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.3588908257
Directory	/workspace/36.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_random_large_delays.3896834047
Short name	T601
Test name
Test status
Simulation time	47252735518 ps
CPU time	469.62 seconds
Started	Jul 24 07:39:27 PM PDT 24
Finished	Jul 24 07:47:16 PM PDT 24
Peak memory	577056 kb
Host	smart-fa6083af-c948-4c1e-9299-38322944fb52
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896834047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3896834047
Directory	/workspace/36.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3684389362
Short name	T2454
Test name
Test status
Simulation time	66127924144 ps
CPU time	1140.14 seconds
Started	Jul 24 07:39:29 PM PDT 24
Finished	Jul 24 07:58:30 PM PDT 24
Peak memory	576400 kb
Host	smart-2a7139b5-7a30-4a86-a5c8-982bf0de2c20
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684389362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3684389362
Directory	/workspace/36.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2665756401
Short name	T574
Test name
Test status
Simulation time	563626487 ps
CPU time	55.83 seconds
Started	Jul 24 07:39:18 PM PDT 24
Finished	Jul 24 07:40:14 PM PDT 24
Peak memory	576920 kb
Host	smart-abf1d4b1-bf98-416e-8b66-02648bd671f3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665756401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.2665756401
Directory	/workspace/36.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_same_source.3247103262
Short name	T2053
Test name
Test status
Simulation time	214830425 ps
CPU time	16.95 seconds
Started	Jul 24 07:39:43 PM PDT 24
Finished	Jul 24 07:40:00 PM PDT 24
Peak memory	576076 kb
Host	smart-897a2fa5-9cf0-467f-87d4-2c2a6df9e7c8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247103262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3247103262
Directory	/workspace/36.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke.2265241564
Short name	T1551
Test name
Test status
Simulation time	46148177 ps
CPU time	6.31 seconds
Started	Jul 24 07:39:23 PM PDT 24
Finished	Jul 24 07:39:30 PM PDT 24
Peak memory	574852 kb
Host	smart-0568e231-f289-4fed-9e30-d1d5cfdac273
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265241564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2265241564
Directory	/workspace/36.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.3421676753
Short name	T2449
Test name
Test status
Simulation time	7255977190 ps
CPU time	73.07 seconds
Started	Jul 24 07:39:20 PM PDT 24
Finished	Jul 24 07:40:34 PM PDT 24
Peak memory	576312 kb
Host	smart-609b11ce-eabf-4e10-ad11-205d5abb49ad
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421676753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3421676753
Directory	/workspace/36.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.535787808
Short name	T2440
Test name
Test status
Simulation time	5565850477 ps
CPU time	88.97 seconds
Started	Jul 24 07:39:24 PM PDT 24
Finished	Jul 24 07:40:53 PM PDT 24
Peak memory	574944 kb
Host	smart-eb7a3c9a-b8b8-4aa5-af0c-8ed43fbc7856
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535787808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.535787808
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3772941515
Short name	T2118
Test name
Test status
Simulation time	52851721 ps
CPU time	6.81 seconds
Started	Jul 24 07:39:19 PM PDT 24
Finished	Jul 24 07:39:26 PM PDT 24
Peak memory	574880 kb
Host	smart-6e2f61e7-878f-4eb4-82f0-9d55a639fbd7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772941515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.3772941515
Directory	/workspace/36.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all.354053051
Short name	T2089
Test name
Test status
Simulation time	1253961577 ps
CPU time	117.22 seconds
Started	Jul 24 07:39:30 PM PDT 24
Finished	Jul 24 07:41:27 PM PDT 24
Peak memory	576260 kb
Host	smart-70cae6ba-e89c-434b-b32e-0f666f5acd3a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354053051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.354053051
Directory	/workspace/36.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.2186908825
Short name	T2514
Test name
Test status
Simulation time	12687837851 ps
CPU time	452.86 seconds
Started	Jul 24 07:39:28 PM PDT 24
Finished	Jul 24 07:47:01 PM PDT 24
Peak memory	577204 kb
Host	smart-0514532e-cec9-4da1-bf95-5699741c00c4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186908825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2186908825
Directory	/workspace/36.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3702208458
Short name	T1658
Test name
Test status
Simulation time	55561543 ps
CPU time	6.69 seconds
Started	Jul 24 07:39:30 PM PDT 24
Finished	Jul 24 07:39:37 PM PDT 24
Peak memory	575088 kb
Host	smart-472803c3-ec35-4620-b901-23ec65799b3c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702208458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.3702208458
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.4280687501
Short name	T2150
Test name
Test status
Simulation time	7307866688 ps
CPU time	522.73 seconds
Started	Jul 24 07:39:31 PM PDT 24
Finished	Jul 24 07:48:14 PM PDT 24
Peak memory	578248 kb
Host	smart-cae9677d-fa64-44b8-b2d8-54902236631c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280687501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.4280687501
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.2268237941
Short name	T2663
Test name
Test status
Simulation time	1413945377 ps
CPU time	54.48 seconds
Started	Jul 24 07:39:33 PM PDT 24
Finished	Jul 24 07:40:27 PM PDT 24
Peak memory	577072 kb
Host	smart-402e50f7-5664-4dcb-935a-ddeac680c7b6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268237941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2268237941
Directory	/workspace/36.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_access_same_device.2990258110
Short name	T554
Test name
Test status
Simulation time	882188445 ps
CPU time	70.26 seconds
Started	Jul 24 07:39:42 PM PDT 24
Finished	Jul 24 07:40:52 PM PDT 24
Peak memory	576124 kb
Host	smart-d9c07d90-664c-46e5-9d15-d79ff3c36ff3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990258110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .2990258110
Directory	/workspace/37.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3726659116
Short name	T2882
Test name
Test status
Simulation time	117594089735 ps
CPU time	2269.87 seconds
Started	Jul 24 07:39:38 PM PDT 24
Finished	Jul 24 08:17:28 PM PDT 24
Peak memory	577128 kb
Host	smart-205eb53e-3796-4812-8992-a1694cbde442
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726659116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.3726659116
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3586927830
Short name	T1505
Test name
Test status
Simulation time	1221213414 ps
CPU time	46.18 seconds
Started	Jul 24 07:39:37 PM PDT 24
Finished	Jul 24 07:40:24 PM PDT 24
Peak memory	576968 kb
Host	smart-12d855b7-4c2d-4945-898d-e9a223b5de87
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586927830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.3586927830
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_error_random.4071372999
Short name	T2618
Test name
Test status
Simulation time	1702243765 ps
CPU time	65.25 seconds
Started	Jul 24 07:39:37 PM PDT 24
Finished	Jul 24 07:40:43 PM PDT 24
Peak memory	576960 kb
Host	smart-ff3153c2-e44d-4241-99cb-b0ec40b1a55f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071372999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.4071372999
Directory	/workspace/37.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_random.4112164084
Short name	T1967
Test name
Test status
Simulation time	265293333 ps
CPU time	26.62 seconds
Started	Jul 24 07:39:29 PM PDT 24
Finished	Jul 24 07:39:56 PM PDT 24
Peak memory	576980 kb
Host	smart-cf4c3db5-61c0-4a1c-a62a-d44db62254b5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112164084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.4112164084
Directory	/workspace/37.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_random_large_delays.3624389277
Short name	T720
Test name
Test status
Simulation time	39235140795 ps
CPU time	438.82 seconds
Started	Jul 24 07:39:41 PM PDT 24
Finished	Jul 24 07:47:00 PM PDT 24
Peak memory	577044 kb
Host	smart-33aded86-0be5-4629-bd68-5014c7d1837d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624389277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3624389277
Directory	/workspace/37.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.2090574707
Short name	T2844
Test name
Test status
Simulation time	39346398011 ps
CPU time	628.11 seconds
Started	Jul 24 07:39:34 PM PDT 24
Finished	Jul 24 07:50:02 PM PDT 24
Peak memory	577240 kb
Host	smart-f0ee695d-5b60-4a42-a082-d5518f96b078
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090574707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2090574707
Directory	/workspace/37.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.2246495738
Short name	T724
Test name
Test status
Simulation time	543798761 ps
CPU time	50.31 seconds
Started	Jul 24 07:39:33 PM PDT 24
Finished	Jul 24 07:40:23 PM PDT 24
Peak memory	577048 kb
Host	smart-9bb630d5-e8b4-4cdc-8c11-8fb2be241c22
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246495738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.2246495738
Directory	/workspace/37.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_same_source.3919398167
Short name	T2772
Test name
Test status
Simulation time	1242413943 ps
CPU time	38.41 seconds
Started	Jul 24 07:39:41 PM PDT 24
Finished	Jul 24 07:40:19 PM PDT 24
Peak memory	576984 kb
Host	smart-4efdbca1-e646-4ab5-ae13-9245ac25f88f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919398167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3919398167
Directory	/workspace/37.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke.1325578356
Short name	T1852
Test name
Test status
Simulation time	196625211 ps
CPU time	9.13 seconds
Started	Jul 24 07:39:34 PM PDT 24
Finished	Jul 24 07:39:43 PM PDT 24
Peak memory	575036 kb
Host	smart-af8df3ec-ef4a-4d11-9504-991df3b5adb5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325578356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1325578356
Directory	/workspace/37.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.818826942
Short name	T1491
Test name
Test status
Simulation time	9686242807 ps
CPU time	94.63 seconds
Started	Jul 24 07:39:28 PM PDT 24
Finished	Jul 24 07:41:03 PM PDT 24
Peak memory	576288 kb
Host	smart-71a6725e-2a86-492e-8db5-6b0db9d4bd0b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818826942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.818826942
Directory	/workspace/37.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2422311417
Short name	T1476
Test name
Test status
Simulation time	3649367845 ps
CPU time	59.61 seconds
Started	Jul 24 07:39:29 PM PDT 24
Finished	Jul 24 07:40:28 PM PDT 24
Peak memory	575008 kb
Host	smart-e8b68188-5eb0-40bb-9196-5bcd1e90d9ca
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422311417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2422311417
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.327199018
Short name	T2499
Test name
Test status
Simulation time	46694509 ps
CPU time	6.58 seconds
Started	Jul 24 07:39:33 PM PDT 24
Finished	Jul 24 07:39:40 PM PDT 24
Peak memory	575000 kb
Host	smart-0f5ccaf5-fac3-4d41-b834-6f9ab1edb4a5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327199018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays .327199018
Directory	/workspace/37.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all.367134332
Short name	T462
Test name
Test status
Simulation time	12129875014 ps
CPU time	445.58 seconds
Started	Jul 24 07:39:36 PM PDT 24
Finished	Jul 24 07:47:02 PM PDT 24
Peak memory	576436 kb
Host	smart-1a733a72-6619-40b9-bec0-a15c79abb8a3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367134332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.367134332
Directory	/workspace/37.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.3863900666
Short name	T2194
Test name
Test status
Simulation time	2586835442 ps
CPU time	83.12 seconds
Started	Jul 24 07:39:50 PM PDT 24
Finished	Jul 24 07:41:13 PM PDT 24
Peak memory	577096 kb
Host	smart-22f28470-3f5b-431f-97a2-31a599f0c1fc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863900666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3863900666
Directory	/workspace/37.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3652539863
Short name	T2349
Test name
Test status
Simulation time	79824079 ps
CPU time	15.72 seconds
Started	Jul 24 07:39:38 PM PDT 24
Finished	Jul 24 07:39:54 PM PDT 24
Peak memory	576280 kb
Host	smart-857b27e3-1727-4074-9d8a-7f6450a9174f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652539863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.3652539863
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3428168836
Short name	T962
Test name
Test status
Simulation time	216299719 ps
CPU time	68.12 seconds
Started	Jul 24 07:39:38 PM PDT 24
Finished	Jul 24 07:40:46 PM PDT 24
Peak memory	576168 kb
Host	smart-135a397d-6203-4ab8-a702-63cbec8e217f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428168836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.3428168836
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.657378599
Short name	T2186
Test name
Test status
Simulation time	741875086 ps
CPU time	30.2 seconds
Started	Jul 24 07:39:50 PM PDT 24
Finished	Jul 24 07:40:20 PM PDT 24
Peak memory	576952 kb
Host	smart-7507ea50-c3fe-4d3f-b331-d9adf31060c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657378599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.657378599
Directory	/workspace/37.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_access_same_device.3227778530
Short name	T1950
Test name
Test status
Simulation time	14091547 ps
CPU time	5.87 seconds
Started	Jul 24 07:39:44 PM PDT 24
Finished	Jul 24 07:39:50 PM PDT 24
Peak memory	574888 kb
Host	smart-976bdf89-08fc-444d-bee0-a691d9ae0421
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227778530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .3227778530
Directory	/workspace/38.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2630360600
Short name	T2678
Test name
Test status
Simulation time	85184382053 ps
CPU time	1451.3 seconds
Started	Jul 24 07:39:41 PM PDT 24
Finished	Jul 24 08:03:53 PM PDT 24
Peak memory	577320 kb
Host	smart-a0e088df-c2f3-4a33-a966-320393f3fbc5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630360600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.2630360600
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1411125849
Short name	T1693
Test name
Test status
Simulation time	60539345 ps
CPU time	9.34 seconds
Started	Jul 24 07:39:40 PM PDT 24
Finished	Jul 24 07:39:50 PM PDT 24
Peak memory	577020 kb
Host	smart-673fb342-5c4b-4188-ad27-c24a672eeea8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411125849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.1411125849
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_error_random.2480475439
Short name	T2271
Test name
Test status
Simulation time	389068649 ps
CPU time	33.38 seconds
Started	Jul 24 07:39:39 PM PDT 24
Finished	Jul 24 07:40:12 PM PDT 24
Peak memory	576964 kb
Host	smart-98764d90-12d0-4cca-a0f4-fc8b319a3c6a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480475439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2480475439
Directory	/workspace/38.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_random.433834432
Short name	T1844
Test name
Test status
Simulation time	2444778784 ps
CPU time	90.57 seconds
Started	Jul 24 07:39:50 PM PDT 24
Finished	Jul 24 07:41:21 PM PDT 24
Peak memory	576268 kb
Host	smart-239f5456-6b8f-48c8-98e0-00860ae9fe87
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433834432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.433834432
Directory	/workspace/38.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_random_large_delays.3841551783
Short name	T624
Test name
Test status
Simulation time	78091836470 ps
CPU time	782.87 seconds
Started	Jul 24 07:39:50 PM PDT 24
Finished	Jul 24 07:52:54 PM PDT 24
Peak memory	576260 kb
Host	smart-ebbf287d-c8af-47f0-9567-b01f3f24966e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841551783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3841551783
Directory	/workspace/38.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3557738681
Short name	T539
Test name
Test status
Simulation time	63667427655 ps
CPU time	1120.95 seconds
Started	Jul 24 07:39:38 PM PDT 24
Finished	Jul 24 07:58:19 PM PDT 24
Peak memory	576296 kb
Host	smart-a191babf-1943-469f-bf84-63e21b894945
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557738681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3557738681
Directory	/workspace/38.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.179943168
Short name	T2896
Test name
Test status
Simulation time	544909710 ps
CPU time	47.4 seconds
Started	Jul 24 07:39:40 PM PDT 24
Finished	Jul 24 07:40:27 PM PDT 24
Peak memory	576188 kb
Host	smart-887ea777-e878-4f94-9def-c11183f2610d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179943168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_dela ys.179943168
Directory	/workspace/38.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_same_source.4254188798
Short name	T1924
Test name
Test status
Simulation time	1432186899 ps
CPU time	37.2 seconds
Started	Jul 24 07:39:37 PM PDT 24
Finished	Jul 24 07:40:15 PM PDT 24
Peak memory	577024 kb
Host	smart-4fe40348-33e0-4455-b24d-da2b9baac186
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254188798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.4254188798
Directory	/workspace/38.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke.4273811245
Short name	T1951
Test name
Test status
Simulation time	250138253 ps
CPU time	10.21 seconds
Started	Jul 24 07:39:41 PM PDT 24
Finished	Jul 24 07:39:51 PM PDT 24
Peak memory	574940 kb
Host	smart-3f6acbb1-3340-4f22-8f8c-3682059b39f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273811245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.4273811245
Directory	/workspace/38.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.1820261899
Short name	T2635
Test name
Test status
Simulation time	10423426843 ps
CPU time	114.52 seconds
Started	Jul 24 07:39:38 PM PDT 24
Finished	Jul 24 07:41:33 PM PDT 24
Peak memory	575004 kb
Host	smart-574a88b6-a9fd-40ae-be55-83eff6d91fef
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820261899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1820261899
Directory	/workspace/38.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.156107345
Short name	T1760
Test name
Test status
Simulation time	4763206839 ps
CPU time	76.54 seconds
Started	Jul 24 07:39:39 PM PDT 24
Finished	Jul 24 07:40:56 PM PDT 24
Peak memory	574920 kb
Host	smart-ed748bf8-93d1-4c72-8fad-6ad648ed96ec
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156107345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.156107345
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.4193391549
Short name	T1452
Test name
Test status
Simulation time	45134107 ps
CPU time	5.99 seconds
Started	Jul 24 07:39:40 PM PDT 24
Finished	Jul 24 07:39:46 PM PDT 24
Peak memory	574896 kb
Host	smart-16d07def-f78e-4c83-8db7-4f827fd322ed
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193391549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.4193391549
Directory	/workspace/38.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.4131506107
Short name	T2259
Test name
Test status
Simulation time	13881645765 ps
CPU time	458.43 seconds
Started	Jul 24 07:39:41 PM PDT 24
Finished	Jul 24 07:47:19 PM PDT 24
Peak memory	577248 kb
Host	smart-4dd7de92-bea0-4d74-83d5-54cdfb9463a0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131506107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.4131506107
Directory	/workspace/38.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1202012391
Short name	T719
Test name
Test status
Simulation time	2294955891 ps
CPU time	212.88 seconds
Started	Jul 24 07:39:43 PM PDT 24
Finished	Jul 24 07:43:16 PM PDT 24
Peak memory	576428 kb
Host	smart-18cb5e68-9e36-4f8a-a4ef-4d09fdaa873f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202012391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.1202012391
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2756538553
Short name	T1481
Test name
Test status
Simulation time	105388735 ps
CPU time	18.69 seconds
Started	Jul 24 07:39:51 PM PDT 24
Finished	Jul 24 07:40:10 PM PDT 24
Peak memory	577056 kb
Host	smart-8b774f95-e4bc-4915-8bc4-88b57b5e099c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756538553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2756538553
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1533086776
Short name	T1990
Test name
Test status
Simulation time	1150552945 ps
CPU time	47.86 seconds
Started	Jul 24 07:39:39 PM PDT 24
Finished	Jul 24 07:40:27 PM PDT 24
Peak memory	577156 kb
Host	smart-a9dee80e-b22e-4bdf-a024-a064898a0381
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533086776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1533086776
Directory	/workspace/38.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_access_same_device.1792908428
Short name	T913
Test name
Test status
Simulation time	1744629339 ps
CPU time	71.34 seconds
Started	Jul 24 07:39:50 PM PDT 24
Finished	Jul 24 07:41:02 PM PDT 24
Peak memory	576108 kb
Host	smart-317a0cc2-c7a0-4cda-804d-7f068475d2bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792908428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .1792908428
Directory	/workspace/39.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3526105573
Short name	T2654
Test name
Test status
Simulation time	121773565431 ps
CPU time	2235.45 seconds
Started	Jul 24 07:39:49 PM PDT 24
Finished	Jul 24 08:17:05 PM PDT 24
Peak memory	576408 kb
Host	smart-1239bfa0-8bfe-4a7f-8989-420ab32acaaa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526105573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.3526105573
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.2227888273
Short name	T2794
Test name
Test status
Simulation time	377014380 ps
CPU time	14.55 seconds
Started	Jul 24 07:39:58 PM PDT 24
Finished	Jul 24 07:40:12 PM PDT 24
Peak memory	576988 kb
Host	smart-8265fb8b-c733-4080-b7b4-794c1281bad0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227888273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.2227888273
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_error_random.3703578386
Short name	T1956
Test name
Test status
Simulation time	2349659140 ps
CPU time	84.8 seconds
Started	Jul 24 07:39:52 PM PDT 24
Finished	Jul 24 07:41:17 PM PDT 24
Peak memory	577072 kb
Host	smart-a5612f7d-a42c-45f7-ac6c-195775eed41c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703578386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3703578386
Directory	/workspace/39.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_random.1532735900
Short name	T1856
Test name
Test status
Simulation time	886602808 ps
CPU time	32.7 seconds
Started	Jul 24 07:40:09 PM PDT 24
Finished	Jul 24 07:40:42 PM PDT 24
Peak memory	576952 kb
Host	smart-2a746963-bcba-42cd-b4fd-7eab4f90c786
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532735900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1532735900
Directory	/workspace/39.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3530556959
Short name	T573
Test name
Test status
Simulation time	84930527807 ps
CPU time	906.23 seconds
Started	Jul 24 07:40:09 PM PDT 24
Finished	Jul 24 07:55:16 PM PDT 24
Peak memory	576308 kb
Host	smart-8a42c648-711f-47fa-b150-d48142ed07f4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530556959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3530556959
Directory	/workspace/39.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.1311477960
Short name	T1829
Test name
Test status
Simulation time	25650222953 ps
CPU time	462.86 seconds
Started	Jul 24 07:39:48 PM PDT 24
Finished	Jul 24 07:47:31 PM PDT 24
Peak memory	577080 kb
Host	smart-8128a7c1-d6d6-48b4-8040-9ee5ff0f8cc0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311477960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1311477960
Directory	/workspace/39.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.535598352
Short name	T654
Test name
Test status
Simulation time	563590815 ps
CPU time	52.29 seconds
Started	Jul 24 07:39:51 PM PDT 24
Finished	Jul 24 07:40:43 PM PDT 24
Peak memory	577036 kb
Host	smart-0fe37ffe-6693-4f0f-9e8d-edba36cfebb3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535598352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_dela ys.535598352
Directory	/workspace/39.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_same_source.522801582
Short name	T1562
Test name
Test status
Simulation time	148833315 ps
CPU time	13.35 seconds
Started	Jul 24 07:39:49 PM PDT 24
Finished	Jul 24 07:40:03 PM PDT 24
Peak memory	576980 kb
Host	smart-0cd6e0bf-959f-4cf2-81b5-ecb6b5d087d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522801582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.522801582
Directory	/workspace/39.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke.1288579587
Short name	T1912
Test name
Test status
Simulation time	56450602 ps
CPU time	7.31 seconds
Started	Jul 24 07:39:51 PM PDT 24
Finished	Jul 24 07:39:58 PM PDT 24
Peak memory	574868 kb
Host	smart-9239611c-8f5e-48c7-a799-578ef3b3c79b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288579587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1288579587
Directory	/workspace/39.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.1877489160
Short name	T2133
Test name
Test status
Simulation time	7777255121 ps
CPU time	80.07 seconds
Started	Jul 24 07:39:52 PM PDT 24
Finished	Jul 24 07:41:12 PM PDT 24
Peak memory	575048 kb
Host	smart-c8ed4e35-2e33-4068-a584-5d17485a1716
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877489160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1877489160
Directory	/workspace/39.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1409614357
Short name	T2244
Test name
Test status
Simulation time	3726212739 ps
CPU time	60.76 seconds
Started	Jul 24 07:39:50 PM PDT 24
Finished	Jul 24 07:40:51 PM PDT 24
Peak memory	574980 kb
Host	smart-0fc71ee6-5d8a-4513-bbc9-4e8929a352c6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409614357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1409614357
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.446445962
Short name	T1602
Test name
Test status
Simulation time	50079850 ps
CPU time	6.95 seconds
Started	Jul 24 07:39:49 PM PDT 24
Finished	Jul 24 07:39:56 PM PDT 24
Peak memory	574848 kb
Host	smart-4aa297dc-a010-40c5-a1cf-c65928e21107
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446445962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays .446445962
Directory	/workspace/39.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all.2358556137
Short name	T589
Test name
Test status
Simulation time	2576925828 ps
CPU time	94.15 seconds
Started	Jul 24 07:39:58 PM PDT 24
Finished	Jul 24 07:41:32 PM PDT 24
Peak memory	577264 kb
Host	smart-070314c7-aa50-4890-b2b6-9b99a75a3bf8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358556137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2358556137
Directory	/workspace/39.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.4291964176
Short name	T2628
Test name
Test status
Simulation time	8869548486 ps
CPU time	308 seconds
Started	Jul 24 07:40:01 PM PDT 24
Finished	Jul 24 07:45:09 PM PDT 24
Peak memory	576372 kb
Host	smart-af08fef5-944c-4ad6-b4d9-ed04c2464db5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291964176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.4291964176
Directory	/workspace/39.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3707038402
Short name	T493
Test name
Test status
Simulation time	996899723 ps
CPU time	312.99 seconds
Started	Jul 24 07:39:58 PM PDT 24
Finished	Jul 24 07:45:11 PM PDT 24
Peak memory	577116 kb
Host	smart-371325ad-3938-4e1b-aa9a-4e92a3a1b9a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707038402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.3707038402
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.3313001723
Short name	T712
Test name
Test status
Simulation time	315203425 ps
CPU time	17.51 seconds
Started	Jul 24 07:40:01 PM PDT 24
Finished	Jul 24 07:40:18 PM PDT 24
Peak memory	577048 kb
Host	smart-9ab8bfea-b7e2-4991-92c1-62bee0c0c6dc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313001723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3313001723
Directory	/workspace/39.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_aliasing.672142355
Short name	T1715
Test name
Test status
Simulation time	68935159527 ps
CPU time	9279.28 seconds
Started	Jul 24 07:33:18 PM PDT 24
Finished	Jul 24 10:07:59 PM PDT 24
Peak memory	639148 kb
Host	smart-7cc8af8c-7344-4670-84fd-bc9a652543ed
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672142355 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 4.chip_csr_aliasing.672142355
Directory	/workspace/4.chip_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.625770651
Short name	T1723
Test name
Test status
Simulation time	15025864020 ps
CPU time	2054.1 seconds
Started	Jul 24 07:33:10 PM PDT 24
Finished	Jul 24 08:07:25 PM PDT 24
Peak memory	593128 kb
Host	smart-0571f60d-4f6c-467c-badd-f70241f4bcdf
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625770651 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.625770651
Directory	/workspace/4.chip_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.307927060
Short name	T1810
Test name
Test status
Simulation time	7250973320 ps
CPU time	461.59 seconds
Started	Jul 24 07:33:29 PM PDT 24
Finished	Jul 24 07:41:11 PM PDT 24
Peak memory	638368 kb
Host	smart-1951004d-7b60-4aa5-834a-c39b76b05cbb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307927060 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.307927060
Directory	/workspace/4.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_rw.1731230457
Short name	T443
Test name
Test status
Simulation time	6238330540 ps
CPU time	697.92 seconds
Started	Jul 24 07:33:29 PM PDT 24
Finished	Jul 24 07:45:07 PM PDT 24
Peak memory	599848 kb
Host	smart-b56f8288-be5c-4681-bd1c-109f9c27c833
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731230457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.1731230457
Directory	/workspace/4.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.2827960766
Short name	T409
Test name
Test status
Simulation time	16730810848 ps
CPU time	2261.18 seconds
Started	Jul 24 07:33:07 PM PDT 24
Finished	Jul 24 08:10:49 PM PDT 24
Peak memory	593880 kb
Host	smart-5a1add59-c2a3-45bd-89b8-34e54ceaf4c6
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827960766 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.2827960766
Directory	/workspace/4.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/4.chip_tl_errors.1844346910
Short name	T795
Test name
Test status
Simulation time	3622905366 ps
CPU time	183.54 seconds
Started	Jul 24 07:33:17 PM PDT 24
Finished	Jul 24 07:36:20 PM PDT 24
Peak memory	604424 kb
Host	smart-227d9ef8-e348-442e-87bf-72aea97f72c2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844346910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.1844346910
Directory	/workspace/4.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_access_same_device.2280128513
Short name	T603
Test name
Test status
Simulation time	2237180115 ps
CPU time	95.58 seconds
Started	Jul 24 07:33:10 PM PDT 24
Finished	Jul 24 07:34:46 PM PDT 24
Peak memory	576328 kb
Host	smart-90b3dda7-b4b5-4fe6-800f-a9852d05bf16
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280128513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 2280128513
Directory	/workspace/4.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2981976432
Short name	T2926
Test name
Test status
Simulation time	5261721274 ps
CPU time	85.41 seconds
Started	Jul 24 07:33:14 PM PDT 24
Finished	Jul 24 07:34:40 PM PDT 24
Peak memory	574972 kb
Host	smart-85754b2a-ea90-4b75-85e4-88098434fd1b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981976432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.2981976432
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1011204323
Short name	T2303
Test name
Test status
Simulation time	136103228 ps
CPU time	16.98 seconds
Started	Jul 24 07:33:20 PM PDT 24
Finished	Jul 24 07:33:37 PM PDT 24
Peak memory	576940 kb
Host	smart-6d2c979b-c1e4-400f-b623-429840c600c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011204323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .1011204323
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_error_random.751603426
Short name	T2275
Test name
Test status
Simulation time	2468074046 ps
CPU time	84.6 seconds
Started	Jul 24 07:33:20 PM PDT 24
Finished	Jul 24 07:34:45 PM PDT 24
Peak memory	577140 kb
Host	smart-ccce47aa-e25e-444d-b24e-037ddc8690ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751603426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.751603426
Directory	/workspace/4.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_random.3791555090
Short name	T2741
Test name
Test status
Simulation time	1769224708 ps
CPU time	63.86 seconds
Started	Jul 24 07:33:09 PM PDT 24
Finished	Jul 24 07:34:13 PM PDT 24
Peak memory	576912 kb
Host	smart-00b97ba5-ee12-4947-b1e1-ed3eccc0ba72
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791555090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.3791555090
Directory	/workspace/4.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_random_large_delays.3897606349
Short name	T2708
Test name
Test status
Simulation time	98332886527 ps
CPU time	1001.89 seconds
Started	Jul 24 07:33:19 PM PDT 24
Finished	Jul 24 07:50:01 PM PDT 24
Peak memory	577124 kb
Host	smart-350ee469-eafb-4777-9fc5-7f576bfaa92e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897606349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3897606349
Directory	/workspace/4.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.3859137302
Short name	T527
Test name
Test status
Simulation time	44196845490 ps
CPU time	745.57 seconds
Started	Jul 24 07:33:19 PM PDT 24
Finished	Jul 24 07:45:45 PM PDT 24
Peak memory	576316 kb
Host	smart-1cbecf33-87a4-43a9-9c05-22e76d198883
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859137302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3859137302
Directory	/workspace/4.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3559525363
Short name	T1927
Test name
Test status
Simulation time	92551014 ps
CPU time	10.74 seconds
Started	Jul 24 07:33:09 PM PDT 24
Finished	Jul 24 07:33:20 PM PDT 24
Peak memory	576992 kb
Host	smart-46b01b0b-e2c4-41ee-85d4-042fe9bc188f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559525363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.3559525363
Directory	/workspace/4.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_same_source.3710151796
Short name	T440
Test name
Test status
Simulation time	162262174 ps
CPU time	12.77 seconds
Started	Jul 24 07:33:24 PM PDT 24
Finished	Jul 24 07:33:37 PM PDT 24
Peak memory	576168 kb
Host	smart-ee352870-613d-4370-aad1-a2832b976800
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710151796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3710151796
Directory	/workspace/4.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke.1676592898
Short name	T735
Test name
Test status
Simulation time	253871849 ps
CPU time	10.07 seconds
Started	Jul 24 07:33:10 PM PDT 24
Finished	Jul 24 07:33:21 PM PDT 24
Peak memory	574808 kb
Host	smart-98656499-e3af-418f-970a-211a71be4cb7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676592898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1676592898
Directory	/workspace/4.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2808524987
Short name	T2510
Test name
Test status
Simulation time	5627900047 ps
CPU time	55.2 seconds
Started	Jul 24 07:33:22 PM PDT 24
Finished	Jul 24 07:34:18 PM PDT 24
Peak memory	574948 kb
Host	smart-cf3b7f36-3020-4288-ad69-98767b7fc32e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808524987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2808524987
Directory	/workspace/4.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.476123851
Short name	T1683
Test name
Test status
Simulation time	5155738350 ps
CPU time	81.61 seconds
Started	Jul 24 07:33:14 PM PDT 24
Finished	Jul 24 07:34:36 PM PDT 24
Peak memory	575004 kb
Host	smart-edee19c7-3c4c-4a1d-a813-8f93982eb2a4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476123851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.476123851
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.836061541
Short name	T706
Test name
Test status
Simulation time	48281792 ps
CPU time	6.72 seconds
Started	Jul 24 07:33:07 PM PDT 24
Finished	Jul 24 07:33:14 PM PDT 24
Peak memory	576200 kb
Host	smart-426800f3-c810-4698-8192-f2874b549cb3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836061541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays. 836061541
Directory	/workspace/4.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all.1714325683
Short name	T1795
Test name
Test status
Simulation time	7608567814 ps
CPU time	282.77 seconds
Started	Jul 24 07:33:18 PM PDT 24
Finished	Jul 24 07:38:01 PM PDT 24
Peak memory	576324 kb
Host	smart-b3e5d2e2-443c-4377-8f23-e6221a2f3af7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714325683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1714325683
Directory	/workspace/4.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.1341805774
Short name	T2804
Test name
Test status
Simulation time	17962751698 ps
CPU time	667.03 seconds
Started	Jul 24 07:33:18 PM PDT 24
Finished	Jul 24 07:44:25 PM PDT 24
Peak memory	577200 kb
Host	smart-8b120b9c-21c8-43be-b874-dc58105b7a37
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341805774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1341805774
Directory	/workspace/4.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3490741989
Short name	T530
Test name
Test status
Simulation time	2807738155 ps
CPU time	318.59 seconds
Started	Jul 24 07:33:28 PM PDT 24
Finished	Jul 24 07:38:47 PM PDT 24
Peak memory	576400 kb
Host	smart-026495c3-1ae6-48be-8b52-be026f3131d9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490741989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.3490741989
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1368601523
Short name	T950
Test name
Test status
Simulation time	8091809158 ps
CPU time	354.79 seconds
Started	Jul 24 07:33:17 PM PDT 24
Finished	Jul 24 07:39:12 PM PDT 24
Peak memory	577176 kb
Host	smart-f13ae061-53f9-4522-b546-7f7d82bf49d3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368601523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.1368601523
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.2736892013
Short name	T1642
Test name
Test status
Simulation time	560751181 ps
CPU time	24.77 seconds
Started	Jul 24 07:33:29 PM PDT 24
Finished	Jul 24 07:33:54 PM PDT 24
Peak memory	576992 kb
Host	smart-bf7835d3-e229-4684-8d77-827b61887a68
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736892013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2736892013
Directory	/workspace/4.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_access_same_device.1503417367
Short name	T2438
Test name
Test status
Simulation time	217609615 ps
CPU time	10.6 seconds
Started	Jul 24 07:40:00 PM PDT 24
Finished	Jul 24 07:40:11 PM PDT 24
Peak memory	574908 kb
Host	smart-f65e2728-4af1-4794-b127-a2f41cf7f6a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503417367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .1503417367
Directory	/workspace/40.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1518106902
Short name	T930
Test name
Test status
Simulation time	55592141901 ps
CPU time	997.01 seconds
Started	Jul 24 07:40:00 PM PDT 24
Finished	Jul 24 07:56:37 PM PDT 24
Peak memory	577204 kb
Host	smart-be71b3ab-97a8-4579-b777-d14fdc573f6b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518106902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.1518106902
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.2771675590
Short name	T2559
Test name
Test status
Simulation time	1175603468 ps
CPU time	48.32 seconds
Started	Jul 24 07:39:56 PM PDT 24
Finished	Jul 24 07:40:45 PM PDT 24
Peak memory	577008 kb
Host	smart-a451737a-53fa-43cd-8151-ddfae6859e7a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771675590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.2771675590
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_error_random.2018977302
Short name	T2736
Test name
Test status
Simulation time	827322491 ps
CPU time	28.15 seconds
Started	Jul 24 07:40:00 PM PDT 24
Finished	Jul 24 07:40:29 PM PDT 24
Peak memory	576152 kb
Host	smart-158f3187-758e-4feb-9b54-8cb30ed159c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018977302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2018977302
Directory	/workspace/40.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_random.2788038320
Short name	T671
Test name
Test status
Simulation time	375682185 ps
CPU time	33.85 seconds
Started	Jul 24 07:39:56 PM PDT 24
Finished	Jul 24 07:40:30 PM PDT 24
Peak memory	577032 kb
Host	smart-3f6d5aed-84f7-410b-b899-f461a168908b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788038320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.2788038320
Directory	/workspace/40.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3620168944
Short name	T1622
Test name
Test status
Simulation time	14369521737 ps
CPU time	159.53 seconds
Started	Jul 24 07:39:57 PM PDT 24
Finished	Jul 24 07:42:37 PM PDT 24
Peak memory	576248 kb
Host	smart-b1216616-6cb0-44e8-8698-547b254b1071
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620168944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3620168944
Directory	/workspace/40.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.2797455177
Short name	T2612
Test name
Test status
Simulation time	69789143532 ps
CPU time	1315.59 seconds
Started	Jul 24 07:39:56 PM PDT 24
Finished	Jul 24 08:01:52 PM PDT 24
Peak memory	577092 kb
Host	smart-03516c5e-82f0-4104-a4e4-a418621d3582
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797455177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2797455177
Directory	/workspace/40.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2857788971
Short name	T2781
Test name
Test status
Simulation time	38548535 ps
CPU time	5.95 seconds
Started	Jul 24 07:39:57 PM PDT 24
Finished	Jul 24 07:40:03 PM PDT 24
Peak memory	574932 kb
Host	smart-34492e51-919d-425c-aed0-0798ca83c1f1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857788971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.2857788971
Directory	/workspace/40.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_same_source.4003049084
Short name	T1991
Test name
Test status
Simulation time	2672687731 ps
CPU time	94 seconds
Started	Jul 24 07:39:57 PM PDT 24
Finished	Jul 24 07:41:31 PM PDT 24
Peak memory	576264 kb
Host	smart-8cae8310-b180-4bbc-97e0-52da7fe92f77
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003049084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.4003049084
Directory	/workspace/40.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke.3384218945
Short name	T2243
Test name
Test status
Simulation time	189983549 ps
CPU time	8.4 seconds
Started	Jul 24 07:39:55 PM PDT 24
Finished	Jul 24 07:40:04 PM PDT 24
Peak memory	576156 kb
Host	smart-bd3ae274-4213-4eab-bdd8-e29e5333a453
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384218945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3384218945
Directory	/workspace/40.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2575832056
Short name	T2880
Test name
Test status
Simulation time	6196146206 ps
CPU time	62.37 seconds
Started	Jul 24 07:39:58 PM PDT 24
Finished	Jul 24 07:41:01 PM PDT 24
Peak memory	574972 kb
Host	smart-c1aefd22-edac-4b9c-b5ee-ebde3b94ba50
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575832056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2575832056
Directory	/workspace/40.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.823473632
Short name	T1959
Test name
Test status
Simulation time	4312298584 ps
CPU time	71.21 seconds
Started	Jul 24 07:39:58 PM PDT 24
Finished	Jul 24 07:41:10 PM PDT 24
Peak memory	574948 kb
Host	smart-4bd4ed9b-283b-4867-8677-305f19c67ebf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823473632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.823473632
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.4131413135
Short name	T2664
Test name
Test status
Simulation time	44464253 ps
CPU time	6.52 seconds
Started	Jul 24 07:39:58 PM PDT 24
Finished	Jul 24 07:40:04 PM PDT 24
Peak memory	574852 kb
Host	smart-b0dba4fa-9bde-4596-85f4-8f7f5dea30c3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131413135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.4131413135
Directory	/workspace/40.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all.1099321182
Short name	T2396
Test name
Test status
Simulation time	2322445402 ps
CPU time	87.02 seconds
Started	Jul 24 07:40:06 PM PDT 24
Finished	Jul 24 07:41:33 PM PDT 24
Peak memory	576340 kb
Host	smart-93c43c59-84b7-4d0c-9db3-d12fc061d839
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099321182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1099321182
Directory	/workspace/40.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.4055203439
Short name	T1446
Test name
Test status
Simulation time	62924957 ps
CPU time	8.76 seconds
Started	Jul 24 07:40:08 PM PDT 24
Finished	Jul 24 07:40:17 PM PDT 24
Peak memory	577036 kb
Host	smart-e1714641-d63d-466e-b7ba-125e4c2949cd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055203439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.4055203439
Directory	/workspace/40.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2206538778
Short name	T2762
Test name
Test status
Simulation time	189307662 ps
CPU time	152.98 seconds
Started	Jul 24 07:40:05 PM PDT 24
Finished	Jul 24 07:42:39 PM PDT 24
Peak memory	577160 kb
Host	smart-63eae13d-ff30-4c7c-a1c7-f9031fb2d3f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206538778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.2206538778
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2250926008
Short name	T2672
Test name
Test status
Simulation time	2349346402 ps
CPU time	231.51 seconds
Started	Jul 24 07:40:04 PM PDT 24
Finished	Jul 24 07:43:55 PM PDT 24
Peak memory	577172 kb
Host	smart-768433a9-6336-415a-b6f7-0d0734d7180f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250926008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.2250926008
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3988076032
Short name	T2836
Test name
Test status
Simulation time	140459223 ps
CPU time	9.06 seconds
Started	Jul 24 07:39:56 PM PDT 24
Finished	Jul 24 07:40:05 PM PDT 24
Peak memory	574964 kb
Host	smart-fd7b0afc-8f15-4946-b80c-15d2d2fa96ae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988076032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3988076032
Directory	/workspace/40.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_access_same_device.1733518927
Short name	T2504
Test name
Test status
Simulation time	15288201 ps
CPU time	5.85 seconds
Started	Jul 24 07:40:06 PM PDT 24
Finished	Jul 24 07:40:12 PM PDT 24
Peak memory	574940 kb
Host	smart-f16a5975-ae9a-49fa-9295-21bd1c68b159
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733518927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .1733518927
Directory	/workspace/41.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1863675613
Short name	T2685
Test name
Test status
Simulation time	18753500695 ps
CPU time	319.5 seconds
Started	Jul 24 07:40:09 PM PDT 24
Finished	Jul 24 07:45:28 PM PDT 24
Peak memory	577056 kb
Host	smart-e1fe51ed-e466-491a-931e-4a220f5b2069
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863675613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.1863675613
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3544509874
Short name	T1500
Test name
Test status
Simulation time	168403934 ps
CPU time	9.48 seconds
Started	Jul 24 07:40:10 PM PDT 24
Finished	Jul 24 07:40:19 PM PDT 24
Peak memory	574868 kb
Host	smart-6fb55e75-4c45-417a-8b8e-5173208c7f6b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544509874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.3544509874
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_error_random.2554897071
Short name	T2879
Test name
Test status
Simulation time	189673885 ps
CPU time	16.26 seconds
Started	Jul 24 07:40:06 PM PDT 24
Finished	Jul 24 07:40:23 PM PDT 24
Peak memory	576992 kb
Host	smart-2eaa4330-2fb6-4884-ac15-3b6eae2a0095
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554897071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2554897071
Directory	/workspace/41.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_random.1779720006
Short name	T681
Test name
Test status
Simulation time	2011250727 ps
CPU time	62.7 seconds
Started	Jul 24 07:40:05 PM PDT 24
Finished	Jul 24 07:41:08 PM PDT 24
Peak memory	576964 kb
Host	smart-e1573158-8398-46c3-a8a8-9782c7331445
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779720006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.1779720006
Directory	/workspace/41.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_random_large_delays.2981573085
Short name	T2091
Test name
Test status
Simulation time	59072987448 ps
CPU time	628.23 seconds
Started	Jul 24 07:40:03 PM PDT 24
Finished	Jul 24 07:50:32 PM PDT 24
Peak memory	576280 kb
Host	smart-1ad21471-ca18-4219-ae31-c26e4ab19ce5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981573085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2981573085
Directory	/workspace/41.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.1355807467
Short name	T2719
Test name
Test status
Simulation time	29292563763 ps
CPU time	509.95 seconds
Started	Jul 24 07:40:05 PM PDT 24
Finished	Jul 24 07:48:35 PM PDT 24
Peak memory	576308 kb
Host	smart-5dc037b3-c818-46e1-9a10-adade6a65245
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355807467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1355807467
Directory	/workspace/41.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2975085611
Short name	T1741
Test name
Test status
Simulation time	415902677 ps
CPU time	34.13 seconds
Started	Jul 24 07:40:06 PM PDT 24
Finished	Jul 24 07:40:40 PM PDT 24
Peak memory	577040 kb
Host	smart-caabdc50-c9e0-4200-a3a2-a1bb4489c0eb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975085611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.2975085611
Directory	/workspace/41.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_same_source.1632421154
Short name	T2886
Test name
Test status
Simulation time	1448417362 ps
CPU time	41.65 seconds
Started	Jul 24 07:40:05 PM PDT 24
Finished	Jul 24 07:40:47 PM PDT 24
Peak memory	576176 kb
Host	smart-80a088ed-c579-4235-b06b-8cb8aaf0c468
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632421154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1632421154
Directory	/workspace/41.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke.1343180775
Short name	T2441
Test name
Test status
Simulation time	55679455 ps
CPU time	6.43 seconds
Started	Jul 24 07:40:07 PM PDT 24
Finished	Jul 24 07:40:13 PM PDT 24
Peak memory	574968 kb
Host	smart-8bd7c623-d6bf-4e83-af65-31e02dca18a7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343180775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1343180775
Directory	/workspace/41.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.3605525241
Short name	T1935
Test name
Test status
Simulation time	8032532422 ps
CPU time	81.33 seconds
Started	Jul 24 07:40:10 PM PDT 24
Finished	Jul 24 07:41:31 PM PDT 24
Peak memory	574920 kb
Host	smart-51f11ccc-a229-4da6-a8d8-08be4b342208
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605525241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3605525241
Directory	/workspace/41.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1894404441
Short name	T2629
Test name
Test status
Simulation time	6657097442 ps
CPU time	114.74 seconds
Started	Jul 24 07:40:07 PM PDT 24
Finished	Jul 24 07:42:01 PM PDT 24
Peak memory	575116 kb
Host	smart-f23f0ca0-e84d-48e2-9194-9d76ecdb6465
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894404441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1894404441
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3695191414
Short name	T1612
Test name
Test status
Simulation time	38691373 ps
CPU time	6.01 seconds
Started	Jul 24 07:40:05 PM PDT 24
Finished	Jul 24 07:40:11 PM PDT 24
Peak memory	576228 kb
Host	smart-c9c988f4-bde9-44a4-8f08-54866238e47e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695191414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.3695191414
Directory	/workspace/41.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all.1279803993
Short name	T2484
Test name
Test status
Simulation time	402385969 ps
CPU time	19.8 seconds
Started	Jul 24 07:40:04 PM PDT 24
Finished	Jul 24 07:40:24 PM PDT 24
Peak memory	576228 kb
Host	smart-ddd8f11f-507d-4093-8dc9-c5164ba88707
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279803993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1279803993
Directory	/workspace/41.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.1938051825
Short name	T1987
Test name
Test status
Simulation time	18101451538 ps
CPU time	678.62 seconds
Started	Jul 24 07:40:04 PM PDT 24
Finished	Jul 24 07:51:23 PM PDT 24
Peak memory	577228 kb
Host	smart-b8b1efe5-09ea-4cea-8a9f-7202dae8d866
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938051825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1938051825
Directory	/workspace/41.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.161707072
Short name	T656
Test name
Test status
Simulation time	130978472 ps
CPU time	41.71 seconds
Started	Jul 24 07:40:10 PM PDT 24
Finished	Jul 24 07:40:51 PM PDT 24
Peak memory	576280 kb
Host	smart-5c24e778-05d1-483e-9af4-d38a9e3d702a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161707072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_ with_rand_reset.161707072
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1245034550
Short name	T964
Test name
Test status
Simulation time	904969391 ps
CPU time	248.38 seconds
Started	Jul 24 07:40:15 PM PDT 24
Finished	Jul 24 07:44:23 PM PDT 24
Peak memory	577112 kb
Host	smart-a5c75884-db79-4951-ab3a-e5564319a1ab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245034550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.1245034550
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.3722715381
Short name	T1908
Test name
Test status
Simulation time	1143409839 ps
CPU time	45.73 seconds
Started	Jul 24 07:40:06 PM PDT 24
Finished	Jul 24 07:40:52 PM PDT 24
Peak memory	577036 kb
Host	smart-348d8e29-f1e5-4ba2-b4af-ce9c11e69e13
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722715381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3722715381
Directory	/workspace/41.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_access_same_device.2716042037
Short name	T2447
Test name
Test status
Simulation time	1844108965 ps
CPU time	76.65 seconds
Started	Jul 24 07:40:15 PM PDT 24
Finished	Jul 24 07:41:32 PM PDT 24
Peak memory	577048 kb
Host	smart-f3526ade-bac9-4532-af8e-1c6f2d1d4ba0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716042037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .2716042037
Directory	/workspace/42.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.2291567933
Short name	T2801
Test name
Test status
Simulation time	51916237710 ps
CPU time	967.63 seconds
Started	Jul 24 07:40:19 PM PDT 24
Finished	Jul 24 07:56:27 PM PDT 24
Peak memory	577228 kb
Host	smart-499a7a4f-293c-460a-951f-cf4408a8e27b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291567933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.2291567933
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.748492643
Short name	T2912
Test name
Test status
Simulation time	652817210 ps
CPU time	28.98 seconds
Started	Jul 24 07:40:25 PM PDT 24
Finished	Jul 24 07:40:54 PM PDT 24
Peak memory	576952 kb
Host	smart-d22cb313-7f7a-49a7-b51a-045e68d9234f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748492643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr .748492643
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_error_random.825669696
Short name	T2847
Test name
Test status
Simulation time	1767127298 ps
CPU time	55.47 seconds
Started	Jul 24 07:40:14 PM PDT 24
Finished	Jul 24 07:41:09 PM PDT 24
Peak memory	577020 kb
Host	smart-d3565a1e-aa68-4a14-9c05-a484826a6e69
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825669696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.825669696
Directory	/workspace/42.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_random.4071641836
Short name	T531
Test name
Test status
Simulation time	356503341 ps
CPU time	32.39 seconds
Started	Jul 24 07:40:26 PM PDT 24
Finished	Jul 24 07:40:58 PM PDT 24
Peak memory	576956 kb
Host	smart-332a6fee-c28b-48da-b40c-70ec5ed47f7c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071641836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.4071641836
Directory	/workspace/42.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3181214273
Short name	T2587
Test name
Test status
Simulation time	97397269101 ps
CPU time	1048.01 seconds
Started	Jul 24 07:40:14 PM PDT 24
Finished	Jul 24 07:57:42 PM PDT 24
Peak memory	577100 kb
Host	smart-51c07ddf-4d67-4793-86d7-fb6742001df1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181214273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3181214273
Directory	/workspace/42.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.1181433923
Short name	T2458
Test name
Test status
Simulation time	47676561092 ps
CPU time	800.1 seconds
Started	Jul 24 07:40:13 PM PDT 24
Finished	Jul 24 07:53:33 PM PDT 24
Peak memory	576280 kb
Host	smart-161d4565-fbf5-4415-a806-0d2a1aa19da8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181433923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1181433923
Directory	/workspace/42.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.2413735549
Short name	T2452
Test name
Test status
Simulation time	575082257 ps
CPU time	48.82 seconds
Started	Jul 24 07:40:18 PM PDT 24
Finished	Jul 24 07:41:07 PM PDT 24
Peak memory	576204 kb
Host	smart-e14a7680-b9d1-443f-85b1-c8f9312ebba8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413735549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.2413735549
Directory	/workspace/42.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_same_source.4081085238
Short name	T1815
Test name
Test status
Simulation time	2051288685 ps
CPU time	62.59 seconds
Started	Jul 24 07:40:15 PM PDT 24
Finished	Jul 24 07:41:18 PM PDT 24
Peak memory	576972 kb
Host	smart-15d7dbe2-6807-4850-b4ec-c4d79b4662ab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081085238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.4081085238
Directory	/workspace/42.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke.2273889871
Short name	T1774
Test name
Test status
Simulation time	40865018 ps
CPU time	6.55 seconds
Started	Jul 24 07:40:15 PM PDT 24
Finished	Jul 24 07:40:21 PM PDT 24
Peak memory	574876 kb
Host	smart-bdd6142c-b88a-46e5-8442-3786ffef914d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273889871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2273889871
Directory	/workspace/42.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.4187788370
Short name	T2027
Test name
Test status
Simulation time	7720119310 ps
CPU time	73.98 seconds
Started	Jul 24 07:40:13 PM PDT 24
Finished	Jul 24 07:41:27 PM PDT 24
Peak memory	574996 kb
Host	smart-cc8eb652-43d0-4496-b576-4e430d364e8f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187788370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.4187788370
Directory	/workspace/42.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.2469907717
Short name	T1848
Test name
Test status
Simulation time	3866925610 ps
CPU time	62.83 seconds
Started	Jul 24 07:40:14 PM PDT 24
Finished	Jul 24 07:41:17 PM PDT 24
Peak memory	576276 kb
Host	smart-e5c8f6e1-a0ad-4f7b-a724-90c9a1f12658
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469907717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2469907717
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1887364721
Short name	T1822
Test name
Test status
Simulation time	55827217 ps
CPU time	7.11 seconds
Started	Jul 24 07:40:14 PM PDT 24
Finished	Jul 24 07:40:22 PM PDT 24
Peak memory	574852 kb
Host	smart-122228a3-c844-4e7e-b7a6-cdb66d1ab4ce
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887364721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.1887364721
Directory	/workspace/42.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all.3948662713
Short name	T628
Test name
Test status
Simulation time	3613845089 ps
CPU time	136.95 seconds
Started	Jul 24 07:40:24 PM PDT 24
Finished	Jul 24 07:42:41 PM PDT 24
Peak memory	577164 kb
Host	smart-8147d011-5e56-4269-9385-a318b2416f2b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948662713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3948662713
Directory	/workspace/42.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.4291932682
Short name	T637
Test name
Test status
Simulation time	8014849405 ps
CPU time	304.04 seconds
Started	Jul 24 07:40:22 PM PDT 24
Finished	Jul 24 07:45:26 PM PDT 24
Peak memory	577228 kb
Host	smart-829004fa-7013-4559-b43e-94831b0bb849
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291932682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.4291932682
Directory	/workspace/42.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3739089899
Short name	T661
Test name
Test status
Simulation time	450612937 ps
CPU time	178.41 seconds
Started	Jul 24 07:40:21 PM PDT 24
Finished	Jul 24 07:43:20 PM PDT 24
Peak memory	577108 kb
Host	smart-556e4e97-1cca-4f84-b3ad-0e9fbc047292
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739089899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.3739089899
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.2732501686
Short name	T2177
Test name
Test status
Simulation time	7891984355 ps
CPU time	481.64 seconds
Started	Jul 24 07:40:25 PM PDT 24
Finished	Jul 24 07:48:27 PM PDT 24
Peak memory	576112 kb
Host	smart-ab87a459-8567-46e7-ace2-b047b027830b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732501686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.2732501686
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.1882107774
Short name	T692
Test name
Test status
Simulation time	348240354 ps
CPU time	42.94 seconds
Started	Jul 24 07:40:14 PM PDT 24
Finished	Jul 24 07:40:57 PM PDT 24
Peak memory	577036 kb
Host	smart-4655e82d-ed9b-4665-bd63-59f47dffaf22
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882107774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1882107774
Directory	/workspace/42.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_access_same_device.3355290651
Short name	T2473
Test name
Test status
Simulation time	1992259892 ps
CPU time	75.67 seconds
Started	Jul 24 07:40:30 PM PDT 24
Finished	Jul 24 07:41:45 PM PDT 24
Peak memory	576128 kb
Host	smart-f6d81ddb-ebcf-44cb-adf5-9d1586112947
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355290651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .3355290651
Directory	/workspace/43.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.129662189
Short name	T944
Test name
Test status
Simulation time	75898234860 ps
CPU time	1374.11 seconds
Started	Jul 24 07:40:31 PM PDT 24
Finished	Jul 24 08:03:26 PM PDT 24
Peak memory	576316 kb
Host	smart-b412ba50-3882-401a-bf36-75ff87d39f1e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129662189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_d evice_slow_rsp.129662189
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.861177645
Short name	T1881
Test name
Test status
Simulation time	67057575 ps
CPU time	6.08 seconds
Started	Jul 24 07:40:32 PM PDT 24
Finished	Jul 24 07:40:39 PM PDT 24
Peak memory	574960 kb
Host	smart-f7ea1e1b-1c16-4218-9bef-0d36f28eaedf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861177645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr .861177645
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_error_random.3009178494
Short name	T2763
Test name
Test status
Simulation time	70664158 ps
CPU time	7.88 seconds
Started	Jul 24 07:40:34 PM PDT 24
Finished	Jul 24 07:40:42 PM PDT 24
Peak memory	574968 kb
Host	smart-aa189a81-7014-4b16-b4de-fad2280f9ce0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009178494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3009178494
Directory	/workspace/43.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_random.2277942707
Short name	T576
Test name
Test status
Simulation time	1955382848 ps
CPU time	76.48 seconds
Started	Jul 24 07:40:23 PM PDT 24
Finished	Jul 24 07:41:39 PM PDT 24
Peak memory	576168 kb
Host	smart-c87ad719-e077-4ccf-9ae2-90abb5dd822a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277942707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.2277942707
Directory	/workspace/43.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_random_large_delays.767863512
Short name	T2721
Test name
Test status
Simulation time	21155309407 ps
CPU time	214.82 seconds
Started	Jul 24 07:40:22 PM PDT 24
Finished	Jul 24 07:43:57 PM PDT 24
Peak memory	576332 kb
Host	smart-b92c3969-56fe-41a1-8ba9-935acf021b40
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767863512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.767863512
Directory	/workspace/43.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.1833205440
Short name	T726
Test name
Test status
Simulation time	23833765678 ps
CPU time	420.72 seconds
Started	Jul 24 07:40:22 PM PDT 24
Finished	Jul 24 07:47:23 PM PDT 24
Peak memory	577144 kb
Host	smart-3b8fc93c-3d7f-4143-9fde-e18deb0afd71
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833205440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1833205440
Directory	/workspace/43.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3254861855
Short name	T1472
Test name
Test status
Simulation time	37581230 ps
CPU time	5.85 seconds
Started	Jul 24 07:40:23 PM PDT 24
Finished	Jul 24 07:40:29 PM PDT 24
Peak memory	576168 kb
Host	smart-13ef35ab-a1cd-44c6-8263-6b689fcd1136
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254861855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.3254861855
Directory	/workspace/43.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_same_source.3160172130
Short name	T2771
Test name
Test status
Simulation time	2079917690 ps
CPU time	58.49 seconds
Started	Jul 24 07:40:33 PM PDT 24
Finished	Jul 24 07:41:32 PM PDT 24
Peak memory	576172 kb
Host	smart-33d7481b-e934-4f6d-a966-1860b8de9ccb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160172130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3160172130
Directory	/workspace/43.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke.1863381377
Short name	T1718
Test name
Test status
Simulation time	175269447 ps
CPU time	8.39 seconds
Started	Jul 24 07:40:23 PM PDT 24
Finished	Jul 24 07:40:32 PM PDT 24
Peak memory	574868 kb
Host	smart-ec2ad58b-5853-4530-8f85-3f44076772d5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863381377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1863381377
Directory	/workspace/43.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.2195464797
Short name	T1483
Test name
Test status
Simulation time	7564532004 ps
CPU time	77.9 seconds
Started	Jul 24 07:40:24 PM PDT 24
Finished	Jul 24 07:41:42 PM PDT 24
Peak memory	574996 kb
Host	smart-6dbcb15e-f789-45f8-aeed-d7499b9a370b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195464797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2195464797
Directory	/workspace/43.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.571756677
Short name	T2546
Test name
Test status
Simulation time	4093709731 ps
CPU time	69.26 seconds
Started	Jul 24 07:40:24 PM PDT 24
Finished	Jul 24 07:41:34 PM PDT 24
Peak memory	574968 kb
Host	smart-60fa6d4f-9d13-4b94-bfe8-32ca10b2a480
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571756677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.571756677
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3737163219
Short name	T1475
Test name
Test status
Simulation time	43335745 ps
CPU time	5.73 seconds
Started	Jul 24 07:40:23 PM PDT 24
Finished	Jul 24 07:40:28 PM PDT 24
Peak memory	574876 kb
Host	smart-25ad8aee-1094-4bec-bd42-ee34c8179aac
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737163219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.3737163219
Directory	/workspace/43.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all.2852660200
Short name	T2161
Test name
Test status
Simulation time	13717602861 ps
CPU time	543.81 seconds
Started	Jul 24 07:40:32 PM PDT 24
Finished	Jul 24 07:49:36 PM PDT 24
Peak memory	576444 kb
Host	smart-baddc048-f75f-4970-ae82-087a1fe47d49
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852660200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2852660200
Directory	/workspace/43.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.434178432
Short name	T2728
Test name
Test status
Simulation time	14350701565 ps
CPU time	510.42 seconds
Started	Jul 24 07:40:32 PM PDT 24
Finished	Jul 24 07:49:02 PM PDT 24
Peak memory	577188 kb
Host	smart-a2d712bf-fffe-4009-8006-61444730b5fd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434178432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.434178432
Directory	/workspace/43.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2668954974
Short name	T2765
Test name
Test status
Simulation time	2851740111 ps
CPU time	277.89 seconds
Started	Jul 24 07:40:31 PM PDT 24
Finished	Jul 24 07:45:09 PM PDT 24
Peak memory	577384 kb
Host	smart-43107e04-1c07-4d3d-8e24-3224c9e296dd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668954974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.2668954974
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1454054308
Short name	T2039
Test name
Test status
Simulation time	353636296 ps
CPU time	112.29 seconds
Started	Jul 24 07:40:30 PM PDT 24
Finished	Jul 24 07:42:23 PM PDT 24
Peak memory	577096 kb
Host	smart-249732b6-3353-45cb-8642-3ae60e7aed0d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454054308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.1454054308
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.1140965330
Short name	T1685
Test name
Test status
Simulation time	608143632 ps
CPU time	27.24 seconds
Started	Jul 24 07:40:32 PM PDT 24
Finished	Jul 24 07:40:59 PM PDT 24
Peak memory	576196 kb
Host	smart-788e4929-9163-4c91-8e95-24c3751e3039
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140965330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1140965330
Directory	/workspace/43.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_access_same_device.2086554685
Short name	T2326
Test name
Test status
Simulation time	2865580855 ps
CPU time	128.16 seconds
Started	Jul 24 07:40:44 PM PDT 24
Finished	Jul 24 07:42:53 PM PDT 24
Peak memory	577152 kb
Host	smart-1d6fcd1d-580b-41c8-a28a-d5ceeb496052
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086554685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .2086554685
Directory	/workspace/44.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.143784916
Short name	T2338
Test name
Test status
Simulation time	279777928 ps
CPU time	31.49 seconds
Started	Jul 24 07:40:40 PM PDT 24
Finished	Jul 24 07:41:12 PM PDT 24
Peak memory	576924 kb
Host	smart-8531f68f-282f-44a6-b2ac-25531e56517b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143784916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr .143784916
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_error_random.2553821332
Short name	T1783
Test name
Test status
Simulation time	1892982286 ps
CPU time	64.53 seconds
Started	Jul 24 07:40:43 PM PDT 24
Finished	Jul 24 07:41:48 PM PDT 24
Peak memory	577076 kb
Host	smart-76d412c9-8e66-4bad-8da5-c42d3da4811a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553821332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2553821332
Directory	/workspace/44.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_random.1490742308
Short name	T1456
Test name
Test status
Simulation time	113781727 ps
CPU time	13.58 seconds
Started	Jul 24 07:40:30 PM PDT 24
Finished	Jul 24 07:40:44 PM PDT 24
Peak memory	576188 kb
Host	smart-64f6302f-abd9-44a5-96a7-e25a208b8dff
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490742308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.1490742308
Directory	/workspace/44.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_random_large_delays.1620653507
Short name	T1808
Test name
Test status
Simulation time	23449721966 ps
CPU time	234.87 seconds
Started	Jul 24 07:40:31 PM PDT 24
Finished	Jul 24 07:44:26 PM PDT 24
Peak memory	577144 kb
Host	smart-f383b77e-21d2-408f-96df-6735ffe01c0c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620653507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1620653507
Directory	/workspace/44.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.352111451
Short name	T1942
Test name
Test status
Simulation time	53735151321 ps
CPU time	1003.32 seconds
Started	Jul 24 07:40:42 PM PDT 24
Finished	Jul 24 07:57:26 PM PDT 24
Peak memory	576324 kb
Host	smart-36e84ecb-f065-429e-9b8b-97b722cb654f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352111451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.352111451
Directory	/workspace/44.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3447237979
Short name	T2077
Test name
Test status
Simulation time	47778475 ps
CPU time	6.5 seconds
Started	Jul 24 07:40:32 PM PDT 24
Finished	Jul 24 07:40:39 PM PDT 24
Peak memory	574928 kb
Host	smart-50d08906-61db-4a6a-a34c-59cfbbdd3be4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447237979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.3447237979
Directory	/workspace/44.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_same_source.290342320
Short name	T1921
Test name
Test status
Simulation time	579001496 ps
CPU time	41.73 seconds
Started	Jul 24 07:40:42 PM PDT 24
Finished	Jul 24 07:41:24 PM PDT 24
Peak memory	576164 kb
Host	smart-f24b44be-6836-45c3-9618-498e23cbeb54
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290342320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.290342320
Directory	/workspace/44.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke.4048758439
Short name	T644
Test name
Test status
Simulation time	167341885 ps
CPU time	8.25 seconds
Started	Jul 24 07:40:31 PM PDT 24
Finished	Jul 24 07:40:40 PM PDT 24
Peak memory	576204 kb
Host	smart-87189491-173d-49dd-a2fb-cb414e1169cf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048758439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.4048758439
Directory	/workspace/44.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.2694088923
Short name	T2712
Test name
Test status
Simulation time	7143706559 ps
CPU time	79.01 seconds
Started	Jul 24 07:40:30 PM PDT 24
Finished	Jul 24 07:41:50 PM PDT 24
Peak memory	574912 kb
Host	smart-633fdd8a-5824-45b4-bdaf-e4cf2df76325
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694088923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2694088923
Directory	/workspace/44.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2779903774
Short name	T1735
Test name
Test status
Simulation time	3117094103 ps
CPU time	54.29 seconds
Started	Jul 24 07:40:31 PM PDT 24
Finished	Jul 24 07:41:25 PM PDT 24
Peak memory	575016 kb
Host	smart-8abb9b26-5ebf-40f8-a2d0-46683f3b15aa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779903774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2779903774
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1661972490
Short name	T2846
Test name
Test status
Simulation time	33431175 ps
CPU time	5.83 seconds
Started	Jul 24 07:40:32 PM PDT 24
Finished	Jul 24 07:40:38 PM PDT 24
Peak memory	574944 kb
Host	smart-4cc6a889-8d93-43a6-bbef-866b0649b6e1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661972490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.1661972490
Directory	/workspace/44.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all.1680908611
Short name	T536
Test name
Test status
Simulation time	3176333195 ps
CPU time	295.52 seconds
Started	Jul 24 07:40:41 PM PDT 24
Finished	Jul 24 07:45:37 PM PDT 24
Peak memory	576400 kb
Host	smart-661f90e7-0171-4281-bad8-fa623e69a1b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680908611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1680908611
Directory	/workspace/44.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1346401377
Short name	T1910
Test name
Test status
Simulation time	2144746109 ps
CPU time	76.29 seconds
Started	Jul 24 07:40:41 PM PDT 24
Finished	Jul 24 07:41:58 PM PDT 24
Peak memory	576028 kb
Host	smart-b25547b2-4103-444e-88f8-059295f69553
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346401377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1346401377
Directory	/workspace/44.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1742712385
Short name	T497
Test name
Test status
Simulation time	3846031393 ps
CPU time	419.87 seconds
Started	Jul 24 07:40:41 PM PDT 24
Finished	Jul 24 07:47:41 PM PDT 24
Peak memory	577248 kb
Host	smart-46483d7f-e6cf-47bd-b831-55916d0e1153
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742712385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.1742712385
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2769751786
Short name	T2673
Test name
Test status
Simulation time	289794369 ps
CPU time	137.94 seconds
Started	Jul 24 07:40:41 PM PDT 24
Finished	Jul 24 07:42:59 PM PDT 24
Peak memory	577128 kb
Host	smart-d426d26c-61f1-4d2b-bcf4-2a7039b3b751
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769751786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.2769751786
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2916405715
Short name	T461
Test name
Test status
Simulation time	949628907 ps
CPU time	42.31 seconds
Started	Jul 24 07:40:43 PM PDT 24
Finished	Jul 24 07:41:26 PM PDT 24
Peak memory	576304 kb
Host	smart-e96cbf40-943b-4818-a477-801b4c41036f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916405715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2916405715
Directory	/workspace/44.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_access_same_device.2512431152
Short name	T1929
Test name
Test status
Simulation time	55157514 ps
CPU time	16.07 seconds
Started	Jul 24 07:40:41 PM PDT 24
Finished	Jul 24 07:40:57 PM PDT 24
Peak memory	577080 kb
Host	smart-240bce26-81f8-40ca-a7b9-87c938a4c1c0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512431152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .2512431152
Directory	/workspace/45.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.2214796631
Short name	T2293
Test name
Test status
Simulation time	19162391135 ps
CPU time	330.4 seconds
Started	Jul 24 07:41:15 PM PDT 24
Finished	Jul 24 07:46:46 PM PDT 24
Peak memory	576404 kb
Host	smart-73482e54-5663-4af3-8517-d66850e8a616
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214796631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.2214796631
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.961815477
Short name	T2615
Test name
Test status
Simulation time	18202308 ps
CPU time	4.94 seconds
Started	Jul 24 07:41:14 PM PDT 24
Finished	Jul 24 07:41:19 PM PDT 24
Peak memory	574812 kb
Host	smart-a9ac056d-befa-43c6-b2bb-1d1c3dd9b175
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961815477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr .961815477
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_error_random.2568086802
Short name	T548
Test name
Test status
Simulation time	2265120169 ps
CPU time	75.12 seconds
Started	Jul 24 07:41:14 PM PDT 24
Finished	Jul 24 07:42:29 PM PDT 24
Peak memory	577128 kb
Host	smart-a2ea127b-d1c1-4550-9978-846db4543f18
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568086802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2568086802
Directory	/workspace/45.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_random.2188983893
Short name	T687
Test name
Test status
Simulation time	713950327 ps
CPU time	26.9 seconds
Started	Jul 24 07:40:41 PM PDT 24
Finished	Jul 24 07:41:08 PM PDT 24
Peak memory	576996 kb
Host	smart-f16e0f86-a117-45be-80a9-a1ced3b6b7e3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188983893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.2188983893
Directory	/workspace/45.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_random_large_delays.3912336190
Short name	T650
Test name
Test status
Simulation time	26336321960 ps
CPU time	282.46 seconds
Started	Jul 24 07:40:42 PM PDT 24
Finished	Jul 24 07:45:25 PM PDT 24
Peak memory	576368 kb
Host	smart-07c5ef66-1fc4-41d7-95a8-d78dd4432d05
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912336190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3912336190
Directory	/workspace/45.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3587831446
Short name	T2496
Test name
Test status
Simulation time	39200095933 ps
CPU time	683.59 seconds
Started	Jul 24 07:40:45 PM PDT 24
Finished	Jul 24 07:52:08 PM PDT 24
Peak memory	577084 kb
Host	smart-441c7de9-3a8a-4405-8225-4a6c9ab184fe
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587831446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3587831446
Directory	/workspace/45.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.2884361078
Short name	T2590
Test name
Test status
Simulation time	269352260 ps
CPU time	23.55 seconds
Started	Jul 24 07:40:39 PM PDT 24
Finished	Jul 24 07:41:02 PM PDT 24
Peak memory	576228 kb
Host	smart-f7cde397-0c5c-40b3-8dce-9d310068b4dd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884361078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.2884361078
Directory	/workspace/45.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_same_source.301241975
Short name	T2495
Test name
Test status
Simulation time	1129473308 ps
CPU time	33.14 seconds
Started	Jul 24 07:41:18 PM PDT 24
Finished	Jul 24 07:41:51 PM PDT 24
Peak memory	576156 kb
Host	smart-15d69551-05c6-4ec1-99fb-07c7df6b847e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301241975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.301241975
Directory	/workspace/45.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke.556375061
Short name	T1478
Test name
Test status
Simulation time	158564518 ps
CPU time	8.18 seconds
Started	Jul 24 07:40:40 PM PDT 24
Finished	Jul 24 07:40:48 PM PDT 24
Peak memory	574892 kb
Host	smart-3266c1cc-8797-4a02-8dc4-d841b6647d62
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556375061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.556375061
Directory	/workspace/45.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.3332878968
Short name	T2726
Test name
Test status
Simulation time	8844404283 ps
CPU time	89.42 seconds
Started	Jul 24 07:40:43 PM PDT 24
Finished	Jul 24 07:42:12 PM PDT 24
Peak memory	576200 kb
Host	smart-2baf7779-1bb3-42a9-87f1-5af83f524684
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332878968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3332878968
Directory	/workspace/45.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2782596362
Short name	T2220
Test name
Test status
Simulation time	4843953524 ps
CPU time	77.99 seconds
Started	Jul 24 07:40:42 PM PDT 24
Finished	Jul 24 07:42:00 PM PDT 24
Peak memory	574916 kb
Host	smart-c2a8f6fe-5af9-417c-8524-6330a1a21b37
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782596362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2782596362
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.1396347171
Short name	T2656
Test name
Test status
Simulation time	55240414 ps
CPU time	6.54 seconds
Started	Jul 24 07:40:43 PM PDT 24
Finished	Jul 24 07:40:49 PM PDT 24
Peak memory	574840 kb
Host	smart-04344413-b053-4f37-90ec-595249a65b0f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396347171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.1396347171
Directory	/workspace/45.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all.658284222
Short name	T2622
Test name
Test status
Simulation time	2871797872 ps
CPU time	94.94 seconds
Started	Jul 24 07:41:12 PM PDT 24
Finished	Jul 24 07:42:47 PM PDT 24
Peak memory	576356 kb
Host	smart-ce51cfe2-6eaa-4f7c-9665-d15132796f73
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658284222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.658284222
Directory	/workspace/45.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.4100593347
Short name	T2793
Test name
Test status
Simulation time	1484063693 ps
CPU time	138.94 seconds
Started	Jul 24 07:41:11 PM PDT 24
Finished	Jul 24 07:43:30 PM PDT 24
Peak memory	577160 kb
Host	smart-bc70b34d-1802-431d-92ff-d1cadb5ef15b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100593347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.4100593347
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2667224206
Short name	T956
Test name
Test status
Simulation time	390815798 ps
CPU time	44.72 seconds
Started	Jul 24 07:41:13 PM PDT 24
Finished	Jul 24 07:41:58 PM PDT 24
Peak memory	577164 kb
Host	smart-a87c191e-9264-493d-b28d-f246e32578f6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667224206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.2667224206
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.2815821478
Short name	T2799
Test name
Test status
Simulation time	74490628 ps
CPU time	6.61 seconds
Started	Jul 24 07:41:14 PM PDT 24
Finished	Jul 24 07:41:21 PM PDT 24
Peak memory	574808 kb
Host	smart-e267fe51-99e5-463e-b6a0-556212d3e7fc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815821478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2815821478
Directory	/workspace/45.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_access_same_device.1079670263
Short name	T2839
Test name
Test status
Simulation time	1738541769 ps
CPU time	73.89 seconds
Started	Jul 24 07:41:18 PM PDT 24
Finished	Jul 24 07:42:32 PM PDT 24
Peak memory	576108 kb
Host	smart-f65d981e-f444-455f-bd28-f884838cd711
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079670263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .1079670263
Directory	/workspace/46.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2467634507
Short name	T2657
Test name
Test status
Simulation time	107497161382 ps
CPU time	1986.41 seconds
Started	Jul 24 07:41:23 PM PDT 24
Finished	Jul 24 08:14:30 PM PDT 24
Peak memory	576364 kb
Host	smart-e036cb20-28db-4bff-b08a-8c7c22956a64
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467634507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.2467634507
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.3624349915
Short name	T2498
Test name
Test status
Simulation time	1034178429 ps
CPU time	37.44 seconds
Started	Jul 24 07:41:21 PM PDT 24
Finished	Jul 24 07:41:59 PM PDT 24
Peak memory	576160 kb
Host	smart-70f0c14d-1ac4-48a4-bf58-cdbfcc74dcae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624349915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.3624349915
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_error_random.811253442
Short name	T2040
Test name
Test status
Simulation time	436240805 ps
CPU time	18.35 seconds
Started	Jul 24 07:41:20 PM PDT 24
Finished	Jul 24 07:41:38 PM PDT 24
Peak memory	576096 kb
Host	smart-b6b2e487-c32e-4253-a47d-5d98381f80bd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811253442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.811253442
Directory	/workspace/46.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_random.1969742747
Short name	T1490
Test name
Test status
Simulation time	270537845 ps
CPU time	12.71 seconds
Started	Jul 24 07:41:21 PM PDT 24
Finished	Jul 24 07:41:34 PM PDT 24
Peak memory	576148 kb
Host	smart-0b9a2114-5e6a-4104-8f24-7430f4ce4a32
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969742747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1969742747
Directory	/workspace/46.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_random_large_delays.4255090072
Short name	T2684
Test name
Test status
Simulation time	27180481895 ps
CPU time	296.79 seconds
Started	Jul 24 07:41:25 PM PDT 24
Finished	Jul 24 07:46:22 PM PDT 24
Peak memory	576268 kb
Host	smart-85b7b007-56e2-4831-9820-3e117465d1d4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255090072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.4255090072
Directory	/workspace/46.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1721988097
Short name	T2900
Test name
Test status
Simulation time	61087092177 ps
CPU time	1151.55 seconds
Started	Jul 24 07:41:21 PM PDT 24
Finished	Jul 24 08:00:33 PM PDT 24
Peak memory	576376 kb
Host	smart-ff0a601f-dc2c-49e5-8f45-8bb958476d94
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721988097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1721988097
Directory	/workspace/46.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.613921313
Short name	T1832
Test name
Test status
Simulation time	40617704 ps
CPU time	5.93 seconds
Started	Jul 24 07:41:19 PM PDT 24
Finished	Jul 24 07:41:25 PM PDT 24
Peak memory	574888 kb
Host	smart-698f705b-6039-498f-a505-6519232718ab
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613921313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_dela ys.613921313
Directory	/workspace/46.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_same_source.525015825
Short name	T721
Test name
Test status
Simulation time	1756669194 ps
CPU time	47.47 seconds
Started	Jul 24 07:41:25 PM PDT 24
Finished	Jul 24 07:42:13 PM PDT 24
Peak memory	576168 kb
Host	smart-58904508-c408-4efa-880b-185c05c33002
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525015825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.525015825
Directory	/workspace/46.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke.2257647978
Short name	T1536
Test name
Test status
Simulation time	43856616 ps
CPU time	6.15 seconds
Started	Jul 24 07:41:14 PM PDT 24
Finished	Jul 24 07:41:20 PM PDT 24
Peak memory	574916 kb
Host	smart-44358ad2-f2b4-4b78-ad22-5b59c98f98b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257647978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2257647978
Directory	/workspace/46.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.2516819447
Short name	T1705
Test name
Test status
Simulation time	8667295708 ps
CPU time	91.01 seconds
Started	Jul 24 07:41:23 PM PDT 24
Finished	Jul 24 07:42:54 PM PDT 24
Peak memory	575040 kb
Host	smart-28e1abe3-b1ca-48a3-a45d-2f14701052d7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516819447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2516819447
Directory	/workspace/46.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.3954216922
Short name	T2158
Test name
Test status
Simulation time	6629087273 ps
CPU time	110.05 seconds
Started	Jul 24 07:41:24 PM PDT 24
Finished	Jul 24 07:43:14 PM PDT 24
Peak memory	575100 kb
Host	smart-ff20ee5c-6cf7-422f-bf16-5ebd157d54c7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954216922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3954216922
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.708836047
Short name	T1594
Test name
Test status
Simulation time	49881566 ps
CPU time	6.46 seconds
Started	Jul 24 07:41:12 PM PDT 24
Finished	Jul 24 07:41:19 PM PDT 24
Peak memory	574888 kb
Host	smart-554e0226-1b94-4762-b1ea-c9f85d2f5aef
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708836047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays .708836047
Directory	/workspace/46.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all.672282607
Short name	T483
Test name
Test status
Simulation time	10939235253 ps
CPU time	357 seconds
Started	Jul 24 07:41:24 PM PDT 24
Finished	Jul 24 07:47:21 PM PDT 24
Peak memory	576428 kb
Host	smart-8429951e-1b6f-4740-8975-bcaa5fb3d453
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672282607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.672282607
Directory	/workspace/46.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.883769246
Short name	T2395
Test name
Test status
Simulation time	2174024024 ps
CPU time	186.12 seconds
Started	Jul 24 07:41:25 PM PDT 24
Finished	Jul 24 07:44:32 PM PDT 24
Peak memory	577168 kb
Host	smart-3ddca2bd-ef62-4bb8-916b-5dcb1f8ccde3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883769246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.883769246
Directory	/workspace/46.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3870275847
Short name	T1615
Test name
Test status
Simulation time	390462770 ps
CPU time	123.22 seconds
Started	Jul 24 07:41:22 PM PDT 24
Finished	Jul 24 07:43:26 PM PDT 24
Peak memory	576320 kb
Host	smart-0a42ad48-41bf-4d52-92f1-fac1fba07c79
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870275847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.3870275847
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1462329155
Short name	T2923
Test name
Test status
Simulation time	272253912 ps
CPU time	97.36 seconds
Started	Jul 24 07:41:26 PM PDT 24
Finished	Jul 24 07:43:04 PM PDT 24
Peak memory	577144 kb
Host	smart-b53cd629-4f97-4844-bb38-5a13a3ac812c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462329155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.1462329155
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.2443026566
Short name	T1886
Test name
Test status
Simulation time	322758416 ps
CPU time	35.23 seconds
Started	Jul 24 07:41:25 PM PDT 24
Finished	Jul 24 07:42:01 PM PDT 24
Peak memory	576296 kb
Host	smart-a09722a8-37d4-4330-a59d-a69505669522
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443026566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2443026566
Directory	/workspace/46.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_access_same_device.4099111426
Short name	T758
Test name
Test status
Simulation time	591742342 ps
CPU time	45.11 seconds
Started	Jul 24 07:41:24 PM PDT 24
Finished	Jul 24 07:42:09 PM PDT 24
Peak memory	576924 kb
Host	smart-ae981a39-2a95-4ac1-b624-4fc068f45ad2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099111426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .4099111426
Directory	/workspace/47.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1545918819
Short name	T1868
Test name
Test status
Simulation time	109049722257 ps
CPU time	2004.95 seconds
Started	Jul 24 07:41:24 PM PDT 24
Finished	Jul 24 08:14:49 PM PDT 24
Peak memory	577248 kb
Host	smart-07b118d9-c5aa-4312-9da7-c10b29e989cd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545918819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.1545918819
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.4095844413
Short name	T2294
Test name
Test status
Simulation time	233375785 ps
CPU time	26.56 seconds
Started	Jul 24 07:41:22 PM PDT 24
Finished	Jul 24 07:41:49 PM PDT 24
Peak memory	576980 kb
Host	smart-71b9ed84-e2a3-4de7-97d6-3cec6e70c303
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095844413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.4095844413
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_error_random.3067855924
Short name	T2520
Test name
Test status
Simulation time	131248167 ps
CPU time	8.01 seconds
Started	Jul 24 07:41:22 PM PDT 24
Finished	Jul 24 07:41:30 PM PDT 24
Peak memory	574900 kb
Host	smart-4bdf8994-20e6-4319-8502-97143f0944f4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067855924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3067855924
Directory	/workspace/47.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_random.3329618681
Short name	T607
Test name
Test status
Simulation time	622337864 ps
CPU time	50.61 seconds
Started	Jul 24 07:41:21 PM PDT 24
Finished	Jul 24 07:42:12 PM PDT 24
Peak memory	577048 kb
Host	smart-f553c4f0-8432-4d31-bc93-dee6c9e409b5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329618681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.3329618681
Directory	/workspace/47.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_random_large_delays.3544603884
Short name	T1872
Test name
Test status
Simulation time	45906840533 ps
CPU time	453.99 seconds
Started	Jul 24 07:41:21 PM PDT 24
Finished	Jul 24 07:48:55 PM PDT 24
Peak memory	576372 kb
Host	smart-7847d839-f9c8-425f-a2a6-3c2938777ace
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544603884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3544603884
Directory	/workspace/47.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.64341021
Short name	T2690
Test name
Test status
Simulation time	29723036291 ps
CPU time	525.36 seconds
Started	Jul 24 07:41:25 PM PDT 24
Finished	Jul 24 07:50:10 PM PDT 24
Peak memory	577032 kb
Host	smart-5b6dde6b-f1e7-4e79-9e30-3c3f0807eb86
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64341021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.64341021
Directory	/workspace/47.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.2705494430
Short name	T703
Test name
Test status
Simulation time	64148461 ps
CPU time	8.58 seconds
Started	Jul 24 07:41:24 PM PDT 24
Finished	Jul 24 07:41:33 PM PDT 24
Peak memory	574956 kb
Host	smart-4f1fad06-16b8-431d-b412-292dfd556b5d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705494430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.2705494430
Directory	/workspace/47.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_same_source.2055908166
Short name	T2738
Test name
Test status
Simulation time	2538229463 ps
CPU time	78.81 seconds
Started	Jul 24 07:41:22 PM PDT 24
Finished	Jul 24 07:42:41 PM PDT 24
Peak memory	577024 kb
Host	smart-d675f0b8-7aa6-4cae-8c9c-c900efa496f3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055908166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2055908166
Directory	/workspace/47.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke.564127567
Short name	T2680
Test name
Test status
Simulation time	52814711 ps
CPU time	6.64 seconds
Started	Jul 24 07:41:21 PM PDT 24
Finished	Jul 24 07:41:28 PM PDT 24
Peak memory	574892 kb
Host	smart-c2b70589-134f-4820-b53c-5d060f4170e8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564127567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.564127567
Directory	/workspace/47.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.3128589709
Short name	T2162
Test name
Test status
Simulation time	10740255171 ps
CPU time	114.41 seconds
Started	Jul 24 07:41:23 PM PDT 24
Finished	Jul 24 07:43:18 PM PDT 24
Peak memory	575012 kb
Host	smart-b25cd752-1f20-4860-b7ac-677dd05d21fc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128589709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3128589709
Directory	/workspace/47.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3243882229
Short name	T487
Test name
Test status
Simulation time	6352335569 ps
CPU time	98.55 seconds
Started	Jul 24 07:41:21 PM PDT 24
Finished	Jul 24 07:42:59 PM PDT 24
Peak memory	574920 kb
Host	smart-1268b075-604d-4780-a7d1-42c3cb626a1d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243882229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3243882229
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1384884530
Short name	T2359
Test name
Test status
Simulation time	43078281 ps
CPU time	6.19 seconds
Started	Jul 24 07:41:23 PM PDT 24
Finished	Jul 24 07:41:29 PM PDT 24
Peak memory	574876 kb
Host	smart-5ae65d40-a6bd-4f9c-aa31-de718360d23d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384884530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.1384884530
Directory	/workspace/47.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all.4256815916
Short name	T1863
Test name
Test status
Simulation time	7542243961 ps
CPU time	282.46 seconds
Started	Jul 24 07:41:22 PM PDT 24
Finished	Jul 24 07:46:05 PM PDT 24
Peak memory	576368 kb
Host	smart-236a65b0-2b25-42b4-9243-7db80717064e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256815916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.4256815916
Directory	/workspace/47.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.968965058
Short name	T922
Test name
Test status
Simulation time	2376713430 ps
CPU time	167.68 seconds
Started	Jul 24 07:41:21 PM PDT 24
Finished	Jul 24 07:44:09 PM PDT 24
Peak memory	577176 kb
Host	smart-8d4627c4-5286-4aa3-b8b4-03df2aed6e47
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968965058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.968965058
Directory	/workspace/47.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2728369103
Short name	T465
Test name
Test status
Simulation time	5032732101 ps
CPU time	369.56 seconds
Started	Jul 24 07:41:19 PM PDT 24
Finished	Jul 24 07:47:29 PM PDT 24
Peak memory	577280 kb
Host	smart-0be6f51d-b04b-4c2f-96be-32282633c152
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728369103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.2728369103
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.680762861
Short name	T1842
Test name
Test status
Simulation time	1303248259 ps
CPU time	200.22 seconds
Started	Jul 24 07:41:23 PM PDT 24
Finished	Jul 24 07:44:43 PM PDT 24
Peak memory	577132 kb
Host	smart-9b02e83a-e4ad-46be-8e1b-cc8314dad231
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680762861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_reset_error.680762861
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.3348338779
Short name	T1909
Test name
Test status
Simulation time	1356201746 ps
CPU time	52.98 seconds
Started	Jul 24 07:41:25 PM PDT 24
Finished	Jul 24 07:42:18 PM PDT 24
Peak memory	576952 kb
Host	smart-4df43cd8-6262-4b02-ab03-fd63f2e67b3f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348338779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3348338779
Directory	/workspace/47.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_access_same_device.1748648261
Short name	T924
Test name
Test status
Simulation time	899377042 ps
CPU time	76.5 seconds
Started	Jul 24 07:41:37 PM PDT 24
Finished	Jul 24 07:42:54 PM PDT 24
Peak memory	576164 kb
Host	smart-77f28e75-a0a6-4353-a97f-342c25fecc61
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748648261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .1748648261
Directory	/workspace/48.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2868168496
Short name	T2120
Test name
Test status
Simulation time	13170883996 ps
CPU time	223.08 seconds
Started	Jul 24 07:41:29 PM PDT 24
Finished	Jul 24 07:45:13 PM PDT 24
Peak memory	576288 kb
Host	smart-0bc047ce-df67-4c9f-8a65-a6660aee9b38
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868168496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.2868168496
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2317077887
Short name	T2436
Test name
Test status
Simulation time	1381420299 ps
CPU time	57.38 seconds
Started	Jul 24 07:41:36 PM PDT 24
Finished	Jul 24 07:42:34 PM PDT 24
Peak memory	576996 kb
Host	smart-8c3a83c1-528e-4ea9-941d-442ef076f3d3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317077887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.2317077887
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_error_random.831242664
Short name	T1618
Test name
Test status
Simulation time	60877319 ps
CPU time	7.27 seconds
Started	Jul 24 07:41:32 PM PDT 24
Finished	Jul 24 07:41:39 PM PDT 24
Peak memory	574984 kb
Host	smart-92f9445c-2fce-4e54-bf70-97cc7e3f79d7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831242664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.831242664
Directory	/workspace/48.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_random.2299419549
Short name	T2866
Test name
Test status
Simulation time	898346994 ps
CPU time	34.41 seconds
Started	Jul 24 07:41:31 PM PDT 24
Finished	Jul 24 07:42:06 PM PDT 24
Peak memory	576192 kb
Host	smart-5802b61a-4c82-49f2-8cda-b524a9e01f8a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299419549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2299419549
Directory	/workspace/48.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3368987261
Short name	T2823
Test name
Test status
Simulation time	50409585900 ps
CPU time	539.66 seconds
Started	Jul 24 07:41:37 PM PDT 24
Finished	Jul 24 07:50:37 PM PDT 24
Peak memory	576348 kb
Host	smart-3a79b35d-bd9e-46f4-8b40-084175da2601
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368987261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3368987261
Directory	/workspace/48.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.189286887
Short name	T1813
Test name
Test status
Simulation time	3533239329 ps
CPU time	57.52 seconds
Started	Jul 24 07:41:40 PM PDT 24
Finished	Jul 24 07:42:37 PM PDT 24
Peak memory	576336 kb
Host	smart-edd975eb-c6da-4128-beac-5a3d3d96dae2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189286887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.189286887
Directory	/workspace/48.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1424013735
Short name	T2037
Test name
Test status
Simulation time	358550659 ps
CPU time	30.02 seconds
Started	Jul 24 07:41:30 PM PDT 24
Finished	Jul 24 07:42:01 PM PDT 24
Peak memory	576208 kb
Host	smart-29bcf3b0-b80f-421b-8838-c1830c0d720b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424013735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.1424013735
Directory	/workspace/48.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_same_source.3242482251
Short name	T2090
Test name
Test status
Simulation time	252343378 ps
CPU time	20.09 seconds
Started	Jul 24 07:41:36 PM PDT 24
Finished	Jul 24 07:41:56 PM PDT 24
Peak memory	576204 kb
Host	smart-2eb86b50-a51c-4eb7-beba-069855c20311
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242482251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3242482251
Directory	/workspace/48.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke.3573461088
Short name	T2493
Test name
Test status
Simulation time	249534822 ps
CPU time	9.71 seconds
Started	Jul 24 07:41:25 PM PDT 24
Finished	Jul 24 07:41:35 PM PDT 24
Peak memory	575048 kb
Host	smart-05e790ef-f30d-4bd7-a84c-8908a8947562
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573461088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3573461088
Directory	/workspace/48.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.287530578
Short name	T2105
Test name
Test status
Simulation time	8931783067 ps
CPU time	91.74 seconds
Started	Jul 24 07:41:24 PM PDT 24
Finished	Jul 24 07:42:56 PM PDT 24
Peak memory	575052 kb
Host	smart-f00f06c3-b2b8-46da-a608-b105094677b0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287530578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.287530578
Directory	/workspace/48.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1525323177
Short name	T2870
Test name
Test status
Simulation time	5765580510 ps
CPU time	97.77 seconds
Started	Jul 24 07:41:39 PM PDT 24
Finished	Jul 24 07:43:17 PM PDT 24
Peak memory	575024 kb
Host	smart-ebc49ef4-105e-4a7b-9a82-7a4827812a46
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525323177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1525323177
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.547004938
Short name	T1621
Test name
Test status
Simulation time	37130529 ps
CPU time	5.69 seconds
Started	Jul 24 07:41:25 PM PDT 24
Finished	Jul 24 07:41:31 PM PDT 24
Peak memory	576104 kb
Host	smart-9f18a0f6-f99c-4f22-980c-ae1bec54ddb3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547004938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays .547004938
Directory	/workspace/48.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all.2434474911
Short name	T2237
Test name
Test status
Simulation time	12964271065 ps
CPU time	514.24 seconds
Started	Jul 24 07:41:30 PM PDT 24
Finished	Jul 24 07:50:04 PM PDT 24
Peak memory	577292 kb
Host	smart-2dcb4aa6-3c0f-47e1-9faa-d75cba94cb88
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434474911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2434474911
Directory	/workspace/48.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.121980339
Short name	T714
Test name
Test status
Simulation time	1873164751 ps
CPU time	155.55 seconds
Started	Jul 24 07:41:31 PM PDT 24
Finished	Jul 24 07:44:07 PM PDT 24
Peak memory	576188 kb
Host	smart-4682c6fb-c8d9-4f2c-962e-01d11becfb7f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121980339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.121980339
Directory	/workspace/48.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3104717544
Short name	T957
Test name
Test status
Simulation time	415152861 ps
CPU time	164.18 seconds
Started	Jul 24 07:41:30 PM PDT 24
Finished	Jul 24 07:44:15 PM PDT 24
Peak memory	577060 kb
Host	smart-e42a434a-7d9a-4897-ba0b-9dfedd7480b8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104717544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.3104717544
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2656831139
Short name	T975
Test name
Test status
Simulation time	476773469 ps
CPU time	176.78 seconds
Started	Jul 24 07:41:30 PM PDT 24
Finished	Jul 24 07:44:27 PM PDT 24
Peak memory	576244 kb
Host	smart-53611059-dbe5-4691-b36a-ad5422ebd7ae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656831139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.2656831139
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.2020096742
Short name	T1946
Test name
Test status
Simulation time	259763223 ps
CPU time	30.31 seconds
Started	Jul 24 07:41:36 PM PDT 24
Finished	Jul 24 07:42:06 PM PDT 24
Peak memory	576260 kb
Host	smart-c98df533-99f3-484a-b9f6-df698621e215
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020096742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2020096742
Directory	/workspace/48.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_access_same_device.20745727
Short name	T514
Test name
Test status
Simulation time	1395791458 ps
CPU time	57.12 seconds
Started	Jul 24 07:41:38 PM PDT 24
Finished	Jul 24 07:42:36 PM PDT 24
Peak memory	576180 kb
Host	smart-d2b4a391-4b8b-44c1-a622-9a562dd11d2f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20745727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.20745727
Directory	/workspace/49.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.2518796399
Short name	T2229
Test name
Test status
Simulation time	447438299 ps
CPU time	20.06 seconds
Started	Jul 24 07:41:39 PM PDT 24
Finished	Jul 24 07:41:59 PM PDT 24
Peak memory	577012 kb
Host	smart-3e94ae8b-38fd-4521-9612-5e15c20a6147
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518796399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.2518796399
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_error_random.685036859
Short name	T2640
Test name
Test status
Simulation time	644331567 ps
CPU time	22.54 seconds
Started	Jul 24 07:41:40 PM PDT 24
Finished	Jul 24 07:42:02 PM PDT 24
Peak memory	577020 kb
Host	smart-7c35c149-f874-4de5-abf9-e33447dd61a1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685036859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.685036859
Directory	/workspace/49.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_random.46537741
Short name	T2171
Test name
Test status
Simulation time	489045390 ps
CPU time	36.06 seconds
Started	Jul 24 07:41:31 PM PDT 24
Finished	Jul 24 07:42:07 PM PDT 24
Peak memory	576192 kb
Host	smart-0665598e-38e3-4a03-a648-77ae9e19c6b0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46537741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.46537741
Directory	/workspace/49.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_random_large_delays.67105288
Short name	T1595
Test name
Test status
Simulation time	60098112492 ps
CPU time	619.54 seconds
Started	Jul 24 07:41:32 PM PDT 24
Finished	Jul 24 07:51:51 PM PDT 24
Peak memory	576376 kb
Host	smart-6ec0b727-0afc-4207-a5a2-7a79c0119a2d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67105288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.67105288
Directory	/workspace/49.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.3787670768
Short name	T1494
Test name
Test status
Simulation time	24013862862 ps
CPU time	385.28 seconds
Started	Jul 24 07:41:37 PM PDT 24
Finished	Jul 24 07:48:03 PM PDT 24
Peak memory	577144 kb
Host	smart-43596512-1d8b-4afa-9dea-8be08d682e80
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787670768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3787670768
Directory	/workspace/49.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.216162579
Short name	T481
Test name
Test status
Simulation time	161211481 ps
CPU time	17.5 seconds
Started	Jul 24 07:41:39 PM PDT 24
Finished	Jul 24 07:41:56 PM PDT 24
Peak memory	576248 kb
Host	smart-043ac19e-a6ad-4e58-be1e-821ab1a7d08c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216162579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_dela ys.216162579
Directory	/workspace/49.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_same_source.1420479340
Short name	T2388
Test name
Test status
Simulation time	87785493 ps
CPU time	9 seconds
Started	Jul 24 07:41:32 PM PDT 24
Finished	Jul 24 07:41:41 PM PDT 24
Peak memory	576964 kb
Host	smart-9a323dd5-5bac-4064-bc65-68aef2900505
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420479340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1420479340
Directory	/workspace/49.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke.3128713536
Short name	T558
Test name
Test status
Simulation time	219417607 ps
CPU time	9.21 seconds
Started	Jul 24 07:41:29 PM PDT 24
Finished	Jul 24 07:41:39 PM PDT 24
Peak memory	574868 kb
Host	smart-c75fefb8-19d9-4e42-95e9-f439e88b27af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128713536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3128713536
Directory	/workspace/49.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1575296823
Short name	T2904
Test name
Test status
Simulation time	8489775221 ps
CPU time	87.19 seconds
Started	Jul 24 07:41:32 PM PDT 24
Finished	Jul 24 07:42:59 PM PDT 24
Peak memory	576284 kb
Host	smart-234db31a-04ab-454b-bdcb-f278a01cadf1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575296823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1575296823
Directory	/workspace/49.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.610131421
Short name	T2930
Test name
Test status
Simulation time	4048612710 ps
CPU time	67.04 seconds
Started	Jul 24 07:41:36 PM PDT 24
Finished	Jul 24 07:42:43 PM PDT 24
Peak memory	575008 kb
Host	smart-c4814cc5-ea53-4903-a121-128245332dba
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610131421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.610131421
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1736260905
Short name	T2555
Test name
Test status
Simulation time	49081769 ps
CPU time	6.72 seconds
Started	Jul 24 07:41:32 PM PDT 24
Finished	Jul 24 07:41:39 PM PDT 24
Peak memory	574888 kb
Host	smart-9ebc5669-157f-472c-9581-4fa9ed9f1f9c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736260905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1736260905
Directory	/workspace/49.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all.3052860920
Short name	T2703
Test name
Test status
Simulation time	1765333957 ps
CPU time	117.8 seconds
Started	Jul 24 07:41:32 PM PDT 24
Finished	Jul 24 07:43:30 PM PDT 24
Peak memory	577044 kb
Host	smart-cc167bcc-07a6-4eb6-96c4-e6a69656b69b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052860920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3052860920
Directory	/workspace/49.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.3028793666
Short name	T1587
Test name
Test status
Simulation time	7035278634 ps
CPU time	245.07 seconds
Started	Jul 24 07:41:31 PM PDT 24
Finished	Jul 24 07:45:36 PM PDT 24
Peak memory	577272 kb
Host	smart-78770b6a-5519-4daa-8a0f-95bccffccba6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028793666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3028793666
Directory	/workspace/49.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.807782011
Short name	T2008
Test name
Test status
Simulation time	198543564 ps
CPU time	72.76 seconds
Started	Jul 24 07:41:32 PM PDT 24
Finished	Jul 24 07:42:45 PM PDT 24
Peak memory	576324 kb
Host	smart-a0eff25d-d8dc-411f-ae6c-9f5f29c8239e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807782011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_ with_rand_reset.807782011
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.782094678
Short name	T1825
Test name
Test status
Simulation time	90871352 ps
CPU time	17.71 seconds
Started	Jul 24 07:41:36 PM PDT 24
Finished	Jul 24 07:41:54 PM PDT 24
Peak memory	575076 kb
Host	smart-271a68ec-58e1-46ad-bd73-1c39b600c134
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782094678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_reset_error.782094678
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.1443302211
Short name	T696
Test name
Test status
Simulation time	220833796 ps
CPU time	26.61 seconds
Started	Jul 24 07:41:30 PM PDT 24
Finished	Jul 24 07:41:57 PM PDT 24
Peak memory	576968 kb
Host	smart-20559a33-9cbb-47e5-8cfe-4448a7b720e3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443302211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1443302211
Directory	/workspace/49.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.3189131211
Short name	T1828
Test name
Test status
Simulation time	7167187900 ps
CPU time	474.41 seconds
Started	Jul 24 07:33:28 PM PDT 24
Finished	Jul 24 07:41:23 PM PDT 24
Peak memory	643528 kb
Host	smart-7faf9d28-e47e-4b8b-a7b5-95cd737519ad
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189131211 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.3189131211
Directory	/workspace/5.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/5.chip_csr_rw.367483914
Short name	T1817
Test name
Test status
Simulation time	6280219447 ps
CPU time	562.1 seconds
Started	Jul 24 07:33:40 PM PDT 24
Finished	Jul 24 07:43:02 PM PDT 24
Peak memory	599436 kb
Host	smart-91938a30-57ab-443f-9ae7-4625d1a8779c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367483914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.367483914
Directory	/workspace/5.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2204400499
Short name	T2364
Test name
Test status
Simulation time	29946480865 ps
CPU time	3878.07 seconds
Started	Jul 24 07:33:23 PM PDT 24
Finished	Jul 24 08:38:01 PM PDT 24
Peak memory	594380 kb
Host	smart-62c27f09-7938-47dd-a6d5-c9320558085e
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204400499 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.2204400499
Directory	/workspace/5.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/5.chip_tl_errors.639938256
Short name	T572
Test name
Test status
Simulation time	3990046424 ps
CPU time	207.44 seconds
Started	Jul 24 07:33:18 PM PDT 24
Finished	Jul 24 07:36:45 PM PDT 24
Peak memory	600476 kb
Host	smart-a73f8481-5e00-48ea-a14d-f9f576445d52
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639938256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.639938256
Directory	/workspace/5.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_access_same_device.1826265081
Short name	T2193
Test name
Test status
Simulation time	788395514 ps
CPU time	67.85 seconds
Started	Jul 24 07:33:29 PM PDT 24
Finished	Jul 24 07:34:37 PM PDT 24
Peak memory	576276 kb
Host	smart-29fbdfa9-9c78-4bae-b17e-7a6255a413f1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826265081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 1826265081
Directory	/workspace/5.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.470056129
Short name	T945
Test name
Test status
Simulation time	22958376668 ps
CPU time	369.98 seconds
Started	Jul 24 07:33:40 PM PDT 24
Finished	Jul 24 07:39:50 PM PDT 24
Peak memory	577048 kb
Host	smart-3aac18ee-7532-4953-9acd-b0743317131a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470056129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_de vice_slow_rsp.470056129
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.591079173
Short name	T1922
Test name
Test status
Simulation time	328488445 ps
CPU time	16.52 seconds
Started	Jul 24 07:33:29 PM PDT 24
Finished	Jul 24 07:33:45 PM PDT 24
Peak memory	577008 kb
Host	smart-f8972d56-929a-4b6d-86a1-41251cfe2d9f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591079173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr. 591079173
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_error_random.623428911
Short name	T1459
Test name
Test status
Simulation time	843994910 ps
CPU time	24.3 seconds
Started	Jul 24 07:33:28 PM PDT 24
Finished	Jul 24 07:33:52 PM PDT 24
Peak memory	577056 kb
Host	smart-8d48e014-efc6-42f3-9d0b-80c4a91c543b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623428911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.623428911
Directory	/workspace/5.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_random.1889556883
Short name	T2422
Test name
Test status
Simulation time	522688620 ps
CPU time	45.96 seconds
Started	Jul 24 07:33:28 PM PDT 24
Finished	Jul 24 07:34:14 PM PDT 24
Peak memory	576104 kb
Host	smart-1e80dde7-4b68-4be3-9e72-a3de548186ac
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889556883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.1889556883
Directory	/workspace/5.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1497245289
Short name	T1796
Test name
Test status
Simulation time	69031076168 ps
CPU time	716.24 seconds
Started	Jul 24 07:33:28 PM PDT 24
Finished	Jul 24 07:45:25 PM PDT 24
Peak memory	577112 kb
Host	smart-8fabb697-4559-423e-a81c-a581e45ea2e3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497245289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1497245289
Directory	/workspace/5.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.100344832
Short name	T668
Test name
Test status
Simulation time	11119247557 ps
CPU time	201.17 seconds
Started	Jul 24 07:33:28 PM PDT 24
Finished	Jul 24 07:36:49 PM PDT 24
Peak memory	577076 kb
Host	smart-ff29010a-7464-4eb6-b9bd-318479f876fb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100344832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.100344832
Directory	/workspace/5.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.4068159897
Short name	T2062
Test name
Test status
Simulation time	604824581 ps
CPU time	49.19 seconds
Started	Jul 24 07:33:41 PM PDT 24
Finished	Jul 24 07:34:30 PM PDT 24
Peak memory	576224 kb
Host	smart-a28e2aab-2efe-4548-bab9-08b4cc38a202
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068159897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.4068159897
Directory	/workspace/5.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_same_source.2476113169
Short name	T646
Test name
Test status
Simulation time	573323125 ps
CPU time	41.23 seconds
Started	Jul 24 07:33:27 PM PDT 24
Finished	Jul 24 07:34:09 PM PDT 24
Peak memory	577004 kb
Host	smart-24e8b5e9-1479-416e-aab7-b258ad1abdc1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476113169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2476113169
Directory	/workspace/5.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke.1143199621
Short name	T2675
Test name
Test status
Simulation time	195880373 ps
CPU time	9.07 seconds
Started	Jul 24 07:33:24 PM PDT 24
Finished	Jul 24 07:33:33 PM PDT 24
Peak memory	574856 kb
Host	smart-72250568-81ea-4cbf-a114-4ab769006444
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143199621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1143199621
Directory	/workspace/5.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.757820878
Short name	T1450
Test name
Test status
Simulation time	9570909312 ps
CPU time	98.72 seconds
Started	Jul 24 07:33:17 PM PDT 24
Finished	Jul 24 07:34:56 PM PDT 24
Peak memory	574948 kb
Host	smart-525caafd-815b-48fc-bd29-3530b1b3e22c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757820878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.757820878
Directory	/workspace/5.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2296253440
Short name	T938
Test name
Test status
Simulation time	5836298543 ps
CPU time	97 seconds
Started	Jul 24 07:33:24 PM PDT 24
Finished	Jul 24 07:35:01 PM PDT 24
Peak memory	576264 kb
Host	smart-5f96c82e-e39c-484e-90fe-638548f10be1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296253440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2296253440
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.1714895563
Short name	T2826
Test name
Test status
Simulation time	41609717 ps
CPU time	6.4 seconds
Started	Jul 24 07:33:18 PM PDT 24
Finished	Jul 24 07:33:25 PM PDT 24
Peak memory	576188 kb
Host	smart-ad767e3b-b620-4526-85e9-535023b75727
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714895563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .1714895563
Directory	/workspace/5.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all.2504396347
Short name	T1769
Test name
Test status
Simulation time	2828490490 ps
CPU time	105.8 seconds
Started	Jul 24 07:33:41 PM PDT 24
Finished	Jul 24 07:35:27 PM PDT 24
Peak memory	576364 kb
Host	smart-ed5ff535-62a6-4fb1-a04a-24a63b5d3d7c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504396347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2504396347
Directory	/workspace/5.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.2787507961
Short name	T1535
Test name
Test status
Simulation time	1939024306 ps
CPU time	158.76 seconds
Started	Jul 24 07:33:28 PM PDT 24
Finished	Jul 24 07:36:07 PM PDT 24
Peak memory	577152 kb
Host	smart-e22a46c8-c062-45de-9c41-4c4df4b4e07f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787507961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2787507961
Directory	/workspace/5.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1119759043
Short name	T683
Test name
Test status
Simulation time	3323374879 ps
CPU time	442.83 seconds
Started	Jul 24 07:33:41 PM PDT 24
Finished	Jul 24 07:41:04 PM PDT 24
Peak memory	577292 kb
Host	smart-f2f25185-093a-4f06-beca-d7eb1e03e503
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119759043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.1119759043
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.1644956890
Short name	T2643
Test name
Test status
Simulation time	200948953 ps
CPU time	22.36 seconds
Started	Jul 24 07:33:41 PM PDT 24
Finished	Jul 24 07:34:03 PM PDT 24
Peak memory	576200 kb
Host	smart-e87eb481-a8e7-4497-b678-eedc60071382
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644956890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1644956890
Directory	/workspace/5.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_access_same_device.1820820338
Short name	T1992
Test name
Test status
Simulation time	1157153723 ps
CPU time	86.24 seconds
Started	Jul 24 07:41:42 PM PDT 24
Finished	Jul 24 07:43:08 PM PDT 24
Peak memory	576168 kb
Host	smart-1cbeb69f-b1d5-4651-87f3-dc9967fa4d67
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820820338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1820820338
Directory	/workspace/50.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1817435028
Short name	T903
Test name
Test status
Simulation time	74709247436 ps
CPU time	1349.97 seconds
Started	Jul 24 07:41:41 PM PDT 24
Finished	Jul 24 08:04:12 PM PDT 24
Peak memory	576308 kb
Host	smart-efb9293c-9598-40c6-aa5d-c2a5df6a48d9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817435028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.1817435028
Directory	/workspace/50.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.460179386
Short name	T1773
Test name
Test status
Simulation time	162276068 ps
CPU time	17.78 seconds
Started	Jul 24 07:41:45 PM PDT 24
Finished	Jul 24 07:42:03 PM PDT 24
Peak memory	576164 kb
Host	smart-dfe21b5d-78fd-41d7-8104-455b98228189
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460179386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr .460179386
Directory	/workspace/50.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_error_random.715636639
Short name	T560
Test name
Test status
Simulation time	156006019 ps
CPU time	16.2 seconds
Started	Jul 24 07:41:48 PM PDT 24
Finished	Jul 24 07:42:04 PM PDT 24
Peak memory	576132 kb
Host	smart-5d18550b-9f44-4ba0-9631-fbcd7bd3c261
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715636639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.715636639
Directory	/workspace/50.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_random.3808081621
Short name	T473
Test name
Test status
Simulation time	548084039 ps
CPU time	49.37 seconds
Started	Jul 24 07:41:51 PM PDT 24
Finished	Jul 24 07:42:41 PM PDT 24
Peak memory	576176 kb
Host	smart-63ccb952-4ebd-4d48-8bc3-3963b0580a26
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808081621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.3808081621
Directory	/workspace/50.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_random_large_delays.955422881
Short name	T2634
Test name
Test status
Simulation time	16925441323 ps
CPU time	172.69 seconds
Started	Jul 24 07:41:42 PM PDT 24
Finished	Jul 24 07:44:35 PM PDT 24
Peak memory	576296 kb
Host	smart-90a989f2-38ea-494f-93da-fb3cc99c02d9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955422881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.955422881
Directory	/workspace/50.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.4002715872
Short name	T2701
Test name
Test status
Simulation time	1425963912 ps
CPU time	23.61 seconds
Started	Jul 24 07:41:44 PM PDT 24
Finished	Jul 24 07:42:07 PM PDT 24
Peak memory	574996 kb
Host	smart-c5004740-9409-42c5-b9c2-6e3cef81d7e6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002715872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.4002715872
Directory	/workspace/50.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.3329726882
Short name	T2386
Test name
Test status
Simulation time	349640232 ps
CPU time	31.97 seconds
Started	Jul 24 07:41:44 PM PDT 24
Finished	Jul 24 07:42:16 PM PDT 24
Peak memory	577008 kb
Host	smart-0382a95b-5e6a-4930-ab8c-78377252e8e6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329726882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.3329726882
Directory	/workspace/50.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_same_source.3200116999
Short name	T2050
Test name
Test status
Simulation time	390055522 ps
CPU time	28.72 seconds
Started	Jul 24 07:41:42 PM PDT 24
Finished	Jul 24 07:42:10 PM PDT 24
Peak memory	576136 kb
Host	smart-25f82d63-4c2e-46bd-92b7-f22b01165488
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200116999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.3200116999
Directory	/workspace/50.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke.2737529574
Short name	T1740
Test name
Test status
Simulation time	191263167 ps
CPU time	8.93 seconds
Started	Jul 24 07:41:48 PM PDT 24
Finished	Jul 24 07:41:57 PM PDT 24
Peak memory	574872 kb
Host	smart-812d41c3-0ed1-4c3a-b123-761fe916b642
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737529574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.2737529574
Directory	/workspace/50.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.1247078142
Short name	T2682
Test name
Test status
Simulation time	8591029257 ps
CPU time	91.62 seconds
Started	Jul 24 07:41:52 PM PDT 24
Finished	Jul 24 07:43:23 PM PDT 24
Peak memory	575012 kb
Host	smart-ddfaccdb-d1ce-47f7-b088-662817b3482d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247078142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.1247078142
Directory	/workspace/50.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.904641079
Short name	T2132
Test name
Test status
Simulation time	4867316638 ps
CPU time	84.18 seconds
Started	Jul 24 07:41:48 PM PDT 24
Finished	Jul 24 07:43:12 PM PDT 24
Peak memory	574988 kb
Host	smart-5a52ec2b-14e5-4cd6-81dd-9636220dc624
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904641079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.904641079
Directory	/workspace/50.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.478968131
Short name	T1932
Test name
Test status
Simulation time	45530365 ps
CPU time	6.31 seconds
Started	Jul 24 07:41:42 PM PDT 24
Finished	Jul 24 07:41:49 PM PDT 24
Peak memory	574908 kb
Host	smart-21a07db6-9cd6-4dcf-9585-caf06acf5961
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478968131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays .478968131
Directory	/workspace/50.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.84042028
Short name	T2802
Test name
Test status
Simulation time	662467351 ps
CPU time	54.68 seconds
Started	Jul 24 07:41:43 PM PDT 24
Finished	Jul 24 07:42:38 PM PDT 24
Peak memory	576080 kb
Host	smart-ba9e87ac-6f15-441c-aaa1-a981ef8defe9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84042028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.84042028
Directory	/workspace/50.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3703198068
Short name	T476
Test name
Test status
Simulation time	2830934023 ps
CPU time	139.06 seconds
Started	Jul 24 07:41:45 PM PDT 24
Finished	Jul 24 07:44:04 PM PDT 24
Peak memory	576516 kb
Host	smart-1f9debe4-5806-4082-a681-726582af18da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703198068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.3703198068
Directory	/workspace/50.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.4050997215
Short name	T2858
Test name
Test status
Simulation time	22477994 ps
CPU time	18.54 seconds
Started	Jul 24 07:41:43 PM PDT 24
Finished	Jul 24 07:42:02 PM PDT 24
Peak memory	575084 kb
Host	smart-ea4eb059-9c9c-4461-a479-ce5e77fa79c4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050997215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.4050997215
Directory	/workspace/50.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2852924238
Short name	T2250
Test name
Test status
Simulation time	199876670 ps
CPU time	27.26 seconds
Started	Jul 24 07:41:42 PM PDT 24
Finished	Jul 24 07:42:09 PM PDT 24
Peak memory	576980 kb
Host	smart-c87462e9-6575-4f2a-a175-b373f2739af8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852924238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.2852924238
Directory	/workspace/50.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_access_same_device.776044906
Short name	T620
Test name
Test status
Simulation time	2940388607 ps
CPU time	127.84 seconds
Started	Jul 24 07:41:44 PM PDT 24
Finished	Jul 24 07:43:52 PM PDT 24
Peak memory	576272 kb
Host	smart-df8be211-9a61-4e56-b39b-44c01e29d315
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776044906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device. 776044906
Directory	/workspace/51.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.1700352413
Short name	T904
Test name
Test status
Simulation time	38515194051 ps
CPU time	628.85 seconds
Started	Jul 24 07:41:51 PM PDT 24
Finished	Jul 24 07:52:20 PM PDT 24
Peak memory	576348 kb
Host	smart-85638ca6-460c-4e7d-95d3-1e87db0673d8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700352413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.1700352413
Directory	/workspace/51.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.3376496020
Short name	T1649
Test name
Test status
Simulation time	1264373086 ps
CPU time	49.74 seconds
Started	Jul 24 07:42:07 PM PDT 24
Finished	Jul 24 07:42:57 PM PDT 24
Peak memory	576256 kb
Host	smart-956e3d93-5c53-4098-9297-f60fd86b5581
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376496020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.3376496020
Directory	/workspace/51.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_error_random.1452820395
Short name	T1468
Test name
Test status
Simulation time	382365989 ps
CPU time	31.8 seconds
Started	Jul 24 07:41:54 PM PDT 24
Finished	Jul 24 07:42:26 PM PDT 24
Peak memory	576992 kb
Host	smart-31787b9a-24d2-4662-b2b6-f74e6a1b7d41
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452820395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.1452820395
Directory	/workspace/51.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_random.2964353044
Short name	T631
Test name
Test status
Simulation time	2614728680 ps
CPU time	92.72 seconds
Started	Jul 24 07:41:44 PM PDT 24
Finished	Jul 24 07:43:17 PM PDT 24
Peak memory	577092 kb
Host	smart-9d288d0d-0db4-434f-95c2-64e8d0b658aa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964353044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.2964353044
Directory	/workspace/51.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_random_large_delays.2450396394
Short name	T1889
Test name
Test status
Simulation time	23944389279 ps
CPU time	267.15 seconds
Started	Jul 24 07:41:44 PM PDT 24
Finished	Jul 24 07:46:11 PM PDT 24
Peak memory	576228 kb
Host	smart-65c7e476-bab7-4c4c-909b-f0e1937d795f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450396394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.2450396394
Directory	/workspace/51.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.3809657304
Short name	T635
Test name
Test status
Simulation time	16420626391 ps
CPU time	285.13 seconds
Started	Jul 24 07:41:45 PM PDT 24
Finished	Jul 24 07:46:30 PM PDT 24
Peak memory	577136 kb
Host	smart-43921419-9465-4612-8353-eeab3887d434
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809657304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.3809657304
Directory	/workspace/51.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.3497762611
Short name	T2325
Test name
Test status
Simulation time	36758302 ps
CPU time	6.21 seconds
Started	Jul 24 07:41:51 PM PDT 24
Finished	Jul 24 07:41:57 PM PDT 24
Peak memory	574960 kb
Host	smart-d9ad23ac-0e02-4fac-b45d-126aafdf85fd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497762611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.3497762611
Directory	/workspace/51.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_same_source.17721627
Short name	T466
Test name
Test status
Simulation time	589495534 ps
CPU time	44.66 seconds
Started	Jul 24 07:41:54 PM PDT 24
Finished	Jul 24 07:42:39 PM PDT 24
Peak memory	576224 kb
Host	smart-9b3031c0-0402-4313-aacd-b9503dbdcfa1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17721627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.17721627
Directory	/workspace/51.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke.3511770782
Short name	T2048
Test name
Test status
Simulation time	200860909 ps
CPU time	8.61 seconds
Started	Jul 24 07:41:43 PM PDT 24
Finished	Jul 24 07:41:52 PM PDT 24
Peak memory	576108 kb
Host	smart-3335158b-1e4b-4392-98d7-7d3355bf691f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511770782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.3511770782
Directory	/workspace/51.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.2953174080
Short name	T1709
Test name
Test status
Simulation time	6722861314 ps
CPU time	69.42 seconds
Started	Jul 24 07:41:43 PM PDT 24
Finished	Jul 24 07:42:52 PM PDT 24
Peak memory	575056 kb
Host	smart-cbd33c82-d470-47ea-a568-7ef3023161f9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953174080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.2953174080
Directory	/workspace/51.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.753249782
Short name	T2766
Test name
Test status
Simulation time	3654735785 ps
CPU time	60.96 seconds
Started	Jul 24 07:41:43 PM PDT 24
Finished	Jul 24 07:42:45 PM PDT 24
Peak memory	576232 kb
Host	smart-c40a59f9-c475-44ba-a848-651be1fc3217
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753249782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.753249782
Directory	/workspace/51.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3950018503
Short name	T2301
Test name
Test status
Simulation time	34105755 ps
CPU time	5.55 seconds
Started	Jul 24 07:41:45 PM PDT 24
Finished	Jul 24 07:41:51 PM PDT 24
Peak memory	574912 kb
Host	smart-635e7ffa-1392-4f75-80e4-95db5fe9676f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950018503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.3950018503
Directory	/workspace/51.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all.1524563021
Short name	T502
Test name
Test status
Simulation time	14263302475 ps
CPU time	582.28 seconds
Started	Jul 24 07:41:51 PM PDT 24
Finished	Jul 24 07:51:33 PM PDT 24
Peak memory	577272 kb
Host	smart-e7d7be76-19c6-447d-bcd3-c1dfdb0de40b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524563021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1524563021
Directory	/workspace/51.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.1072953495
Short name	T2570
Test name
Test status
Simulation time	17103180491 ps
CPU time	635.02 seconds
Started	Jul 24 07:41:54 PM PDT 24
Finished	Jul 24 07:52:29 PM PDT 24
Peak memory	576416 kb
Host	smart-d478477f-1449-48bc-aea8-fdb5a6cf03a0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072953495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.1072953495
Directory	/workspace/51.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.4065110326
Short name	T2016
Test name
Test status
Simulation time	2268440801 ps
CPU time	181.84 seconds
Started	Jul 24 07:41:57 PM PDT 24
Finished	Jul 24 07:44:59 PM PDT 24
Peak memory	576460 kb
Host	smart-03b7bc79-5827-405d-8497-ef0196a5ea71
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065110326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.4065110326
Directory	/workspace/51.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.150639085
Short name	T675
Test name
Test status
Simulation time	10562173615 ps
CPU time	567.2 seconds
Started	Jul 24 07:42:07 PM PDT 24
Finished	Jul 24 07:51:34 PM PDT 24
Peak memory	577368 kb
Host	smart-7bb419da-f500-4cf0-a0c4-7d16f8aa0112
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150639085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_reset_error.150639085
Directory	/workspace/51.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2190407037
Short name	T2466
Test name
Test status
Simulation time	821175884 ps
CPU time	33.79 seconds
Started	Jul 24 07:42:07 PM PDT 24
Finished	Jul 24 07:42:41 PM PDT 24
Peak memory	576272 kb
Host	smart-89275589-267a-4a14-afec-f42715375386
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190407037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2190407037
Directory	/workspace/51.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_access_same_device.1218963159
Short name	T1743
Test name
Test status
Simulation time	2233070938 ps
CPU time	92.2 seconds
Started	Jul 24 07:42:06 PM PDT 24
Finished	Jul 24 07:43:38 PM PDT 24
Peak memory	577232 kb
Host	smart-f1ab71a9-ede7-4cc6-ba68-a9b4c16e1e26
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218963159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .1218963159
Directory	/workspace/52.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2762291022
Short name	T2424
Test name
Test status
Simulation time	77888373626 ps
CPU time	1389.54 seconds
Started	Jul 24 07:41:50 PM PDT 24
Finished	Jul 24 08:04:59 PM PDT 24
Peak memory	576340 kb
Host	smart-8d63bc9e-d942-43f6-a1d6-743ed7b9be78
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762291022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.2762291022
Directory	/workspace/52.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.916846810
Short name	T557
Test name
Test status
Simulation time	65703751 ps
CPU time	6.15 seconds
Started	Jul 24 07:41:55 PM PDT 24
Finished	Jul 24 07:42:02 PM PDT 24
Peak memory	574924 kb
Host	smart-a41cf843-e92a-4c41-ab41-2468abac56f5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916846810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_addr .916846810
Directory	/workspace/52.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_error_random.1135518737
Short name	T1755
Test name
Test status
Simulation time	1608977499 ps
CPU time	59.44 seconds
Started	Jul 24 07:42:07 PM PDT 24
Finished	Jul 24 07:43:06 PM PDT 24
Peak memory	576240 kb
Host	smart-e2393275-bbcd-4b96-999b-28e7177c95c8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135518737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.1135518737
Directory	/workspace/52.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_random.3813933408
Short name	T1780
Test name
Test status
Simulation time	117194181 ps
CPU time	13.52 seconds
Started	Jul 24 07:41:56 PM PDT 24
Finished	Jul 24 07:42:09 PM PDT 24
Peak memory	576312 kb
Host	smart-97afe7fd-36d7-42f3-8bc9-ca3b439eedf1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813933408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.3813933408
Directory	/workspace/52.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_random_large_delays.2492396410
Short name	T736
Test name
Test status
Simulation time	46943588779 ps
CPU time	520.63 seconds
Started	Jul 24 07:41:50 PM PDT 24
Finished	Jul 24 07:50:31 PM PDT 24
Peak memory	577112 kb
Host	smart-4552292a-4d7b-43bd-8be8-aa595100bf88
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492396410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.2492396410
Directory	/workspace/52.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.3473962621
Short name	T1933
Test name
Test status
Simulation time	4044884752 ps
CPU time	67.91 seconds
Started	Jul 24 07:41:56 PM PDT 24
Finished	Jul 24 07:43:04 PM PDT 24
Peak memory	575020 kb
Host	smart-21049eed-d634-4dc3-8416-291890aca11b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473962621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.3473962621
Directory	/workspace/52.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.79643411
Short name	T611
Test name
Test status
Simulation time	554846028 ps
CPU time	49.56 seconds
Started	Jul 24 07:41:54 PM PDT 24
Finished	Jul 24 07:42:44 PM PDT 24
Peak memory	576248 kb
Host	smart-4bf2e112-9941-4852-a085-a483b7c226c0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79643411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_delay s.79643411
Directory	/workspace/52.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_same_source.1784382594
Short name	T2041
Test name
Test status
Simulation time	396423949 ps
CPU time	14.52 seconds
Started	Jul 24 07:41:49 PM PDT 24
Finished	Jul 24 07:42:04 PM PDT 24
Peak memory	576180 kb
Host	smart-0e1ce0dd-7069-4023-a89a-fa30be195b1f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784382594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.1784382594
Directory	/workspace/52.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke.2192697446
Short name	T1680
Test name
Test status
Simulation time	237164298 ps
CPU time	8.64 seconds
Started	Jul 24 07:41:57 PM PDT 24
Finished	Jul 24 07:42:06 PM PDT 24
Peak memory	574868 kb
Host	smart-5f9beb82-278b-47c6-a7c4-a2855272a275
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192697446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.2192697446
Directory	/workspace/52.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.3528354665
Short name	T1509
Test name
Test status
Simulation time	7895522967 ps
CPU time	78.57 seconds
Started	Jul 24 07:41:50 PM PDT 24
Finished	Jul 24 07:43:09 PM PDT 24
Peak memory	575040 kb
Host	smart-b2a8e073-5dfe-4369-a08a-21e7609cd29c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528354665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.3528354665
Directory	/workspace/52.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.2156844663
Short name	T2221
Test name
Test status
Simulation time	5157838026 ps
CPU time	93.25 seconds
Started	Jul 24 07:41:51 PM PDT 24
Finished	Jul 24 07:43:24 PM PDT 24
Peak memory	576288 kb
Host	smart-4fc0dcc8-0620-4e41-b593-35988a1fb76d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156844663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.2156844663
Directory	/workspace/52.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.794540474
Short name	T2742
Test name
Test status
Simulation time	42329401 ps
CPU time	5.7 seconds
Started	Jul 24 07:41:55 PM PDT 24
Finished	Jul 24 07:42:01 PM PDT 24
Peak memory	575008 kb
Host	smart-737d9545-5648-4cb0-9691-32b3baa31edc
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794540474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays .794540474
Directory	/workspace/52.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all.2742933990
Short name	T1900
Test name
Test status
Simulation time	1115134516 ps
CPU time	45.54 seconds
Started	Jul 24 07:41:52 PM PDT 24
Finished	Jul 24 07:42:37 PM PDT 24
Peak memory	577128 kb
Host	smart-36ea8456-d756-4347-8279-f002936c881a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742933990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.2742933990
Directory	/workspace/52.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.4155790889
Short name	T1695
Test name
Test status
Simulation time	4877888244 ps
CPU time	166.42 seconds
Started	Jul 24 07:42:00 PM PDT 24
Finished	Jul 24 07:44:47 PM PDT 24
Peak memory	577128 kb
Host	smart-bb3ad72b-4a0e-4fbf-835c-e98077078a5c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155790889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.4155790889
Directory	/workspace/52.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.217466685
Short name	T959
Test name
Test status
Simulation time	1722667323 ps
CPU time	295.76 seconds
Started	Jul 24 07:41:56 PM PDT 24
Finished	Jul 24 07:46:52 PM PDT 24
Peak memory	577264 kb
Host	smart-f9291de4-8555-49b5-b668-0ffbb12fa4f3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217466685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_ with_rand_reset.217466685
Directory	/workspace/52.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.4081388260
Short name	T965
Test name
Test status
Simulation time	430743331 ps
CPU time	152.69 seconds
Started	Jul 24 07:42:00 PM PDT 24
Finished	Jul 24 07:44:33 PM PDT 24
Peak memory	577072 kb
Host	smart-a8656b4a-dd4e-4aab-ac84-52ac0ceafa8b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081388260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.4081388260
Directory	/workspace/52.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2496064592
Short name	T1798
Test name
Test status
Simulation time	233219683 ps
CPU time	26.97 seconds
Started	Jul 24 07:41:52 PM PDT 24
Finished	Jul 24 07:42:19 PM PDT 24
Peak memory	576152 kb
Host	smart-29fc97af-7ec2-4f87-9b11-f95e2e902c93
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496064592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2496064592
Directory	/workspace/52.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_access_same_device.3236351291
Short name	T2505
Test name
Test status
Simulation time	2069721056 ps
CPU time	86.25 seconds
Started	Jul 24 07:42:01 PM PDT 24
Finished	Jul 24 07:43:28 PM PDT 24
Peak memory	577012 kb
Host	smart-53a8bd74-e111-4fb5-a9a0-ee97984d2499
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236351291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .3236351291
Directory	/workspace/53.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1045483732
Short name	T936
Test name
Test status
Simulation time	24227711671 ps
CPU time	391.14 seconds
Started	Jul 24 07:42:01 PM PDT 24
Finished	Jul 24 07:48:32 PM PDT 24
Peak memory	577212 kb
Host	smart-96411700-9825-458d-a153-cce33bce6e97
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045483732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.1045483732
Directory	/workspace/53.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3608294645
Short name	T1702
Test name
Test status
Simulation time	74449101 ps
CPU time	5.88 seconds
Started	Jul 24 07:42:21 PM PDT 24
Finished	Jul 24 07:42:27 PM PDT 24
Peak memory	574896 kb
Host	smart-4a067795-cb54-4499-b094-33e18df9ea40
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608294645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.3608294645
Directory	/workspace/53.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_error_random.1908504835
Short name	T2348
Test name
Test status
Simulation time	492349223 ps
CPU time	36.89 seconds
Started	Jul 24 07:41:58 PM PDT 24
Finished	Jul 24 07:42:35 PM PDT 24
Peak memory	576940 kb
Host	smart-5d15bbeb-475e-4f43-b171-948a63792a66
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908504835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.1908504835
Directory	/workspace/53.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_random.3840690661
Short name	T471
Test name
Test status
Simulation time	1031523173 ps
CPU time	39.47 seconds
Started	Jul 24 07:41:59 PM PDT 24
Finished	Jul 24 07:42:39 PM PDT 24
Peak memory	576128 kb
Host	smart-11e23d27-e426-45cd-b814-26811f8a3403
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840690661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.3840690661
Directory	/workspace/53.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_random_large_delays.4291091004
Short name	T1590
Test name
Test status
Simulation time	29003504744 ps
CPU time	301.4 seconds
Started	Jul 24 07:42:01 PM PDT 24
Finished	Jul 24 07:47:02 PM PDT 24
Peak memory	576332 kb
Host	smart-3fbcb6b7-3318-4074-98b8-93c46794c26b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291091004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.4291091004
Directory	/workspace/53.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.4218204713
Short name	T2164
Test name
Test status
Simulation time	42966578218 ps
CPU time	758.54 seconds
Started	Jul 24 07:41:59 PM PDT 24
Finished	Jul 24 07:54:38 PM PDT 24
Peak memory	576272 kb
Host	smart-b302f74a-662f-411d-9c34-0990447a5496
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218204713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.4218204713
Directory	/workspace/53.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.990124948
Short name	T2538
Test name
Test status
Simulation time	97603229 ps
CPU time	11.26 seconds
Started	Jul 24 07:42:01 PM PDT 24
Finished	Jul 24 07:42:12 PM PDT 24
Peak memory	577088 kb
Host	smart-a2720834-3896-4357-9bce-c9e52b9df7ab
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990124948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_dela ys.990124948
Directory	/workspace/53.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_same_source.3335172930
Short name	T2581
Test name
Test status
Simulation time	2575499600 ps
CPU time	66.66 seconds
Started	Jul 24 07:41:58 PM PDT 24
Finished	Jul 24 07:43:05 PM PDT 24
Peak memory	577044 kb
Host	smart-733abb55-77cc-4884-bfce-50da43861c06
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335172930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.3335172930
Directory	/workspace/53.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke.1287353201
Short name	T1699
Test name
Test status
Simulation time	242420619 ps
CPU time	9.88 seconds
Started	Jul 24 07:42:08 PM PDT 24
Finished	Jul 24 07:42:17 PM PDT 24
Peak memory	574956 kb
Host	smart-a3a24266-148b-4a3b-ab94-229ccbc3fe33
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287353201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1287353201
Directory	/workspace/53.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.2571771272
Short name	T2181
Test name
Test status
Simulation time	6666623851 ps
CPU time	66.84 seconds
Started	Jul 24 07:42:00 PM PDT 24
Finished	Jul 24 07:43:07 PM PDT 24
Peak memory	574976 kb
Host	smart-55c84688-73e9-40fb-9ea6-feffa7065ed7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571771272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.2571771272
Directory	/workspace/53.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1179340136
Short name	T617
Test name
Test status
Simulation time	5244443728 ps
CPU time	84.22 seconds
Started	Jul 24 07:41:59 PM PDT 24
Finished	Jul 24 07:43:23 PM PDT 24
Peak memory	574988 kb
Host	smart-035411f8-f370-4e7c-8fed-e821507a3bb6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179340136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1179340136
Directory	/workspace/53.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1422765822
Short name	T1840
Test name
Test status
Simulation time	51639934 ps
CPU time	6.51 seconds
Started	Jul 24 07:42:00 PM PDT 24
Finished	Jul 24 07:42:07 PM PDT 24
Peak memory	574904 kb
Host	smart-3d1075cb-41db-4505-8769-b9a23f024eb2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422765822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.1422765822
Directory	/workspace/53.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all.2971215780
Short name	T2148
Test name
Test status
Simulation time	1371101305 ps
CPU time	120.65 seconds
Started	Jul 24 07:42:22 PM PDT 24
Finished	Jul 24 07:44:22 PM PDT 24
Peak memory	576388 kb
Host	smart-5d27747f-7c8f-4c0e-b8fa-4fb229ae5830
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971215780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.2971215780
Directory	/workspace/53.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.3889633478
Short name	T2168
Test name
Test status
Simulation time	15045180276 ps
CPU time	461.62 seconds
Started	Jul 24 07:42:22 PM PDT 24
Finished	Jul 24 07:50:04 PM PDT 24
Peak memory	576428 kb
Host	smart-9d103f27-38a9-46b2-ad20-d2943138032c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889633478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.3889633478
Directory	/workspace/53.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3801047339
Short name	T1698
Test name
Test status
Simulation time	3396607801 ps
CPU time	222.58 seconds
Started	Jul 24 07:42:23 PM PDT 24
Finished	Jul 24 07:46:05 PM PDT 24
Peak memory	576504 kb
Host	smart-3b785434-75b0-42c1-8309-b03744b02b6f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801047339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.3801047339
Directory	/workspace/53.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.3490221562
Short name	T2239
Test name
Test status
Simulation time	329085304 ps
CPU time	35.75 seconds
Started	Jul 24 07:41:59 PM PDT 24
Finished	Jul 24 07:42:35 PM PDT 24
Peak memory	576140 kb
Host	smart-5bf54f71-2a56-4eb5-9663-b105614be1c1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490221562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.3490221562
Directory	/workspace/53.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_access_same_device.369581023
Short name	T2573
Test name
Test status
Simulation time	405856565 ps
CPU time	24.75 seconds
Started	Jul 24 07:42:22 PM PDT 24
Finished	Jul 24 07:42:46 PM PDT 24
Peak memory	576120 kb
Host	smart-bee66bef-58e2-4cc8-a0b3-593968b52d24
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369581023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device. 369581023
Directory	/workspace/54.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.311394011
Short name	T254
Test name
Test status
Simulation time	11458227779 ps
CPU time	194.59 seconds
Started	Jul 24 07:42:22 PM PDT 24
Finished	Jul 24 07:45:37 PM PDT 24
Peak memory	574964 kb
Host	smart-94dbe6cb-e93c-4f40-b4d4-5d9d9ba72e5b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311394011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_d evice_slow_rsp.311394011
Directory	/workspace/54.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1266464016
Short name	T1866
Test name
Test status
Simulation time	144800917 ps
CPU time	18.03 seconds
Started	Jul 24 07:42:24 PM PDT 24
Finished	Jul 24 07:42:42 PM PDT 24
Peak memory	576980 kb
Host	smart-5840f952-f412-4ed4-8f45-bcb3233775da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266464016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.1266464016
Directory	/workspace/54.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_error_random.2489456825
Short name	T1719
Test name
Test status
Simulation time	596842704 ps
CPU time	40.09 seconds
Started	Jul 24 07:42:24 PM PDT 24
Finished	Jul 24 07:43:04 PM PDT 24
Peak memory	576124 kb
Host	smart-7b832046-7505-42e6-9f27-c03915e37d82
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489456825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2489456825
Directory	/workspace/54.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_random.3019488440
Short name	T2916
Test name
Test status
Simulation time	1804238271 ps
CPU time	72.43 seconds
Started	Jul 24 07:42:25 PM PDT 24
Finished	Jul 24 07:43:38 PM PDT 24
Peak memory	576180 kb
Host	smart-abdc967b-bf43-49fa-b49f-f6e75bdabf18
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019488440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3019488440
Directory	/workspace/54.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_random_large_delays.794649982
Short name	T516
Test name
Test status
Simulation time	80311453868 ps
CPU time	897.14 seconds
Started	Jul 24 07:42:22 PM PDT 24
Finished	Jul 24 07:57:20 PM PDT 24
Peak memory	576352 kb
Host	smart-0809b435-fa4f-4886-b9cb-df7e302c95ca
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794649982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.794649982
Directory	/workspace/54.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.1761844896
Short name	T2861
Test name
Test status
Simulation time	26806668195 ps
CPU time	453.21 seconds
Started	Jul 24 07:42:24 PM PDT 24
Finished	Jul 24 07:49:57 PM PDT 24
Peak memory	577116 kb
Host	smart-171cb9b0-8278-468b-9882-f0f9b3aa9698
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761844896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.1761844896
Directory	/workspace/54.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.1740504081
Short name	T2191
Test name
Test status
Simulation time	274158990 ps
CPU time	28.39 seconds
Started	Jul 24 07:42:20 PM PDT 24
Finished	Jul 24 07:42:49 PM PDT 24
Peak memory	577060 kb
Host	smart-02a84db4-3816-4c07-a259-c3bede43120e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740504081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.1740504081
Directory	/workspace/54.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_same_source.2603529717
Short name	T2855
Test name
Test status
Simulation time	75383808 ps
CPU time	9.57 seconds
Started	Jul 24 07:42:22 PM PDT 24
Finished	Jul 24 07:42:32 PM PDT 24
Peak memory	576984 kb
Host	smart-be01a142-e35a-419c-9ac9-c514b4361bd2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603529717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.2603529717
Directory	/workspace/54.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke.884689815
Short name	T1451
Test name
Test status
Simulation time	163770635 ps
CPU time	7.82 seconds
Started	Jul 24 07:42:23 PM PDT 24
Finished	Jul 24 07:42:31 PM PDT 24
Peak memory	574912 kb
Host	smart-cedf2a4f-a56b-4096-a940-800b4090af42
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884689815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.884689815
Directory	/workspace/54.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.2857753650
Short name	T1860
Test name
Test status
Simulation time	9392226253 ps
CPU time	95.49 seconds
Started	Jul 24 07:42:20 PM PDT 24
Finished	Jul 24 07:43:56 PM PDT 24
Peak memory	574972 kb
Host	smart-0fbcbb14-4a2a-4a3e-b8ac-38805459f5c2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857753650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.2857753650
Directory	/workspace/54.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1997743034
Short name	T2207
Test name
Test status
Simulation time	4421161856 ps
CPU time	75.52 seconds
Started	Jul 24 07:42:22 PM PDT 24
Finished	Jul 24 07:43:38 PM PDT 24
Peak memory	574980 kb
Host	smart-bfa81b97-d2b7-4ad1-8334-8820e219767d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997743034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.1997743034
Directory	/workspace/54.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1473203528
Short name	T2124
Test name
Test status
Simulation time	52604369 ps
CPU time	6.78 seconds
Started	Jul 24 07:42:24 PM PDT 24
Finished	Jul 24 07:42:31 PM PDT 24
Peak memory	574804 kb
Host	smart-3d31ffae-3cbf-45f4-a7b7-6042a96dbaef
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473203528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1473203528
Directory	/workspace/54.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all.1297854199
Short name	T2624
Test name
Test status
Simulation time	1956817280 ps
CPU time	166.29 seconds
Started	Jul 24 07:42:21 PM PDT 24
Finished	Jul 24 07:45:07 PM PDT 24
Peak memory	577176 kb
Host	smart-96bcfe25-f767-4b99-a01c-71045913b64e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297854199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.1297854199
Directory	/workspace/54.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2894304885
Short name	T1812
Test name
Test status
Simulation time	355232848 ps
CPU time	177.36 seconds
Started	Jul 24 07:42:33 PM PDT 24
Finished	Jul 24 07:45:31 PM PDT 24
Peak memory	576332 kb
Host	smart-ea0a69b7-0c4e-471a-b2cb-5734b0798f00
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894304885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.2894304885
Directory	/workspace/54.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.132316868
Short name	T2066
Test name
Test status
Simulation time	7306151 ps
CPU time	4.53 seconds
Started	Jul 24 07:42:32 PM PDT 24
Finished	Jul 24 07:42:37 PM PDT 24
Peak memory	574068 kb
Host	smart-19e3a5a7-70fd-472b-8d2c-81e8d182b4bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132316868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_reset_error.132316868
Directory	/workspace/54.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.2698713853
Short name	T1605
Test name
Test status
Simulation time	864363867 ps
CPU time	37.7 seconds
Started	Jul 24 07:42:23 PM PDT 24
Finished	Jul 24 07:43:01 PM PDT 24
Peak memory	576952 kb
Host	smart-925c46b8-1067-474e-9bff-32ee5fda8134
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698713853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.2698713853
Directory	/workspace/54.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_access_same_device.2999038141
Short name	T923
Test name
Test status
Simulation time	713716860 ps
CPU time	29.82 seconds
Started	Jul 24 07:42:30 PM PDT 24
Finished	Jul 24 07:43:00 PM PDT 24
Peak memory	576136 kb
Host	smart-16e728dc-9d0d-420d-9081-c0584f327dd3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999038141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .2999038141
Directory	/workspace/55.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3963435966
Short name	T929
Test name
Test status
Simulation time	139504557952 ps
CPU time	2626.25 seconds
Started	Jul 24 07:42:29 PM PDT 24
Finished	Jul 24 08:26:15 PM PDT 24
Peak memory	577088 kb
Host	smart-15db1ede-3a71-4107-9864-09e9293ced01
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963435966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.3963435966
Directory	/workspace/55.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.795916509
Short name	T2106
Test name
Test status
Simulation time	235661449 ps
CPU time	22.85 seconds
Started	Jul 24 07:42:29 PM PDT 24
Finished	Jul 24 07:42:52 PM PDT 24
Peak memory	576972 kb
Host	smart-3e977ba6-4eb8-4dbd-abbd-b89adaaaee7a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795916509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr .795916509
Directory	/workspace/55.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_error_random.330809516
Short name	T2344
Test name
Test status
Simulation time	1980527415 ps
CPU time	69.22 seconds
Started	Jul 24 07:42:28 PM PDT 24
Finished	Jul 24 07:43:38 PM PDT 24
Peak memory	576160 kb
Host	smart-2df6fb0f-fc13-4826-8bde-43771e551a5b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330809516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.330809516
Directory	/workspace/55.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_random.2294442778
Short name	T2064
Test name
Test status
Simulation time	2086762877 ps
CPU time	81.46 seconds
Started	Jul 24 07:42:27 PM PDT 24
Finished	Jul 24 07:43:49 PM PDT 24
Peak memory	577000 kb
Host	smart-4f073d0f-afdd-4c3a-9fac-6b428dbdf257
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294442778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.2294442778
Directory	/workspace/55.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_random_large_delays.3235794382
Short name	T2545
Test name
Test status
Simulation time	44175966524 ps
CPU time	455.33 seconds
Started	Jul 24 07:42:36 PM PDT 24
Finished	Jul 24 07:50:11 PM PDT 24
Peak memory	577072 kb
Host	smart-cbf20643-51a3-4aaa-84e5-8f916f1cc389
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235794382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.3235794382
Directory	/workspace/55.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.3602507803
Short name	T1870
Test name
Test status
Simulation time	47871352235 ps
CPU time	804.22 seconds
Started	Jul 24 07:42:29 PM PDT 24
Finished	Jul 24 07:55:53 PM PDT 24
Peak memory	577092 kb
Host	smart-42967ffd-1b21-43dd-9c4a-68212d3f1dda
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602507803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.3602507803
Directory	/workspace/55.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1148885233
Short name	T2666
Test name
Test status
Simulation time	232884309 ps
CPU time	20.93 seconds
Started	Jul 24 07:42:30 PM PDT 24
Finished	Jul 24 07:42:51 PM PDT 24
Peak memory	577024 kb
Host	smart-2e8fca4e-75b2-427f-bb64-72c27f193c1e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148885233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.1148885233
Directory	/workspace/55.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_same_source.2118313397
Short name	T2921
Test name
Test status
Simulation time	1232391216 ps
CPU time	38.51 seconds
Started	Jul 24 07:42:32 PM PDT 24
Finished	Jul 24 07:43:11 PM PDT 24
Peak memory	576924 kb
Host	smart-240041ae-7257-4791-94ff-c6c8cb7bcf44
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118313397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.2118313397
Directory	/workspace/55.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke.1194789451
Short name	T1512
Test name
Test status
Simulation time	232131364 ps
CPU time	8.83 seconds
Started	Jul 24 07:42:31 PM PDT 24
Finished	Jul 24 07:42:40 PM PDT 24
Peak memory	574900 kb
Host	smart-61c4c219-1eb4-4874-9f9c-c80cd4477d75
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194789451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1194789451
Directory	/workspace/55.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2054685973
Short name	T2019
Test name
Test status
Simulation time	9773329028 ps
CPU time	107.22 seconds
Started	Jul 24 07:42:31 PM PDT 24
Finished	Jul 24 07:44:18 PM PDT 24
Peak memory	574972 kb
Host	smart-e6efa138-b4f6-4da7-81cd-db3b20e4d14a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054685973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.2054685973
Directory	/workspace/55.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.318556396
Short name	T2455
Test name
Test status
Simulation time	3529802974 ps
CPU time	58.84 seconds
Started	Jul 24 07:42:31 PM PDT 24
Finished	Jul 24 07:43:30 PM PDT 24
Peak memory	575032 kb
Host	smart-6d9da182-bf9c-44ff-9272-ea553c881fa9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318556396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.318556396
Directory	/workspace/55.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3362623802
Short name	T2407
Test name
Test status
Simulation time	42799368 ps
CPU time	6.03 seconds
Started	Jul 24 07:42:29 PM PDT 24
Finished	Jul 24 07:42:35 PM PDT 24
Peak memory	574892 kb
Host	smart-b9ec966f-5b4e-4c9d-9a3a-386db3395103
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362623802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.3362623802
Directory	/workspace/55.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all.3768903265
Short name	T581
Test name
Test status
Simulation time	1399161161 ps
CPU time	90.54 seconds
Started	Jul 24 07:42:33 PM PDT 24
Finished	Jul 24 07:44:04 PM PDT 24
Peak memory	577160 kb
Host	smart-b478a976-18bc-4f66-9630-17a10185797b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768903265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3768903265
Directory	/workspace/55.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2686645884
Short name	T484
Test name
Test status
Simulation time	763412028 ps
CPU time	291.65 seconds
Started	Jul 24 07:42:30 PM PDT 24
Finished	Jul 24 07:47:21 PM PDT 24
Peak memory	577132 kb
Host	smart-bacd6ee6-6f44-4193-ab5b-0ac105c08965
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686645884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.2686645884
Directory	/workspace/55.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3051555379
Short name	T2566
Test name
Test status
Simulation time	468098942 ps
CPU time	159.61 seconds
Started	Jul 24 07:42:32 PM PDT 24
Finished	Jul 24 07:45:12 PM PDT 24
Peak memory	577104 kb
Host	smart-689e048e-25b9-4fe8-8305-34b93df40481
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051555379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.3051555379
Directory	/workspace/55.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3890135175
Short name	T1777
Test name
Test status
Simulation time	608556922 ps
CPU time	28.85 seconds
Started	Jul 24 07:42:34 PM PDT 24
Finished	Jul 24 07:43:03 PM PDT 24
Peak memory	576196 kb
Host	smart-66455fbd-0a7c-46ba-98c6-dea2b8fb83bd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890135175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3890135175
Directory	/workspace/55.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_access_same_device.777851640
Short name	T1882
Test name
Test status
Simulation time	2112226474 ps
CPU time	94.33 seconds
Started	Jul 24 07:42:35 PM PDT 24
Finished	Jul 24 07:44:09 PM PDT 24
Peak memory	576992 kb
Host	smart-827cfe37-b4e0-42c6-bfdf-482c09f972f6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777851640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device. 777851640
Directory	/workspace/56.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2912909777
Short name	T909
Test name
Test status
Simulation time	62697188303 ps
CPU time	1151.81 seconds
Started	Jul 24 07:42:30 PM PDT 24
Finished	Jul 24 08:01:43 PM PDT 24
Peak memory	576404 kb
Host	smart-083062ed-86b8-4f5e-9250-8a8c3b72543c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912909777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.2912909777
Directory	/workspace/56.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.5023311
Short name	T2343
Test name
Test status
Simulation time	1000300276 ps
CPU time	42.45 seconds
Started	Jul 24 07:42:40 PM PDT 24
Finished	Jul 24 07:43:22 PM PDT 24
Peak memory	576104 kb
Host	smart-016c8e5c-eb6a-4442-ace8-8d6c7be23a2d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5023311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr.5023311
Directory	/workspace/56.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_error_random.3905912968
Short name	T1488
Test name
Test status
Simulation time	627985523 ps
CPU time	50.98 seconds
Started	Jul 24 07:42:39 PM PDT 24
Finished	Jul 24 07:43:30 PM PDT 24
Peak memory	576988 kb
Host	smart-484d736b-3684-4705-9cf0-ffd775686780
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905912968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.3905912968
Directory	/workspace/56.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_random.487007998
Short name	T2739
Test name
Test status
Simulation time	1049719277 ps
CPU time	32.3 seconds
Started	Jul 24 07:42:32 PM PDT 24
Finished	Jul 24 07:43:04 PM PDT 24
Peak memory	576180 kb
Host	smart-766590e0-78fd-411c-a0d6-3585b7cbf344
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487007998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.487007998
Directory	/workspace/56.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_random_large_delays.2404460655
Short name	T1657
Test name
Test status
Simulation time	59618189416 ps
CPU time	583.72 seconds
Started	Jul 24 07:42:31 PM PDT 24
Finished	Jul 24 07:52:15 PM PDT 24
Peak memory	577180 kb
Host	smart-1c66e929-2ff2-4681-babf-4efb1e6dec0c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404460655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.2404460655
Directory	/workspace/56.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.1381072497
Short name	T685
Test name
Test status
Simulation time	47060489933 ps
CPU time	783.33 seconds
Started	Jul 24 07:42:27 PM PDT 24
Finished	Jul 24 07:55:31 PM PDT 24
Peak memory	577048 kb
Host	smart-8d45e136-b7cf-432e-ab7b-a1281f3b1d8c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381072497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.1381072497
Directory	/workspace/56.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.2721822131
Short name	T1613
Test name
Test status
Simulation time	537068503 ps
CPU time	39.3 seconds
Started	Jul 24 07:42:29 PM PDT 24
Finished	Jul 24 07:43:08 PM PDT 24
Peak memory	576276 kb
Host	smart-cb548801-d064-4536-a737-6269e7fac308
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721822131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.2721822131
Directory	/workspace/56.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_same_source.2782799691
Short name	T634
Test name
Test status
Simulation time	121171171 ps
CPU time	13.04 seconds
Started	Jul 24 07:42:41 PM PDT 24
Finished	Jul 24 07:42:54 PM PDT 24
Peak memory	576204 kb
Host	smart-0425453f-f49e-4b34-948c-d90bc06fd250
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782799691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.2782799691
Directory	/workspace/56.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke.4167022142
Short name	T2282
Test name
Test status
Simulation time	51793715 ps
CPU time	6.66 seconds
Started	Jul 24 07:42:31 PM PDT 24
Finished	Jul 24 07:42:38 PM PDT 24
Peak memory	574892 kb
Host	smart-e64ffb09-992e-4200-a2a5-4a788e559efc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167022142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.4167022142
Directory	/workspace/56.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.7660962
Short name	T2512
Test name
Test status
Simulation time	11064148824 ps
CPU time	108.41 seconds
Started	Jul 24 07:42:29 PM PDT 24
Finished	Jul 24 07:44:18 PM PDT 24
Peak memory	574992 kb
Host	smart-d9e1405a-1c6b-42d6-9c3a-8c743410dce0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7660962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.7660962
Directory	/workspace/56.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2619506702
Short name	T2535
Test name
Test status
Simulation time	4494746120 ps
CPU time	76.83 seconds
Started	Jul 24 07:42:28 PM PDT 24
Finished	Jul 24 07:43:45 PM PDT 24
Peak memory	575120 kb
Host	smart-b2f20f63-e957-4213-be2f-17cdcffc3a4b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619506702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.2619506702
Directory	/workspace/56.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.1442896609
Short name	T2054
Test name
Test status
Simulation time	41149171 ps
CPU time	6.02 seconds
Started	Jul 24 07:42:28 PM PDT 24
Finished	Jul 24 07:42:34 PM PDT 24
Peak memory	576136 kb
Host	smart-21c1b0ce-1723-4dad-9f39-0a53dfca1d7f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442896609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.1442896609
Directory	/workspace/56.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all.3002562348
Short name	T2476
Test name
Test status
Simulation time	4450448981 ps
CPU time	368.75 seconds
Started	Jul 24 07:42:41 PM PDT 24
Finished	Jul 24 07:48:50 PM PDT 24
Peak memory	577228 kb
Host	smart-fdb69e8a-9b27-4770-aa10-c74b03346ef9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002562348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3002562348
Directory	/workspace/56.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.3868727839
Short name	T2238
Test name
Test status
Simulation time	3497333457 ps
CPU time	267.83 seconds
Started	Jul 24 07:42:36 PM PDT 24
Finished	Jul 24 07:47:04 PM PDT 24
Peak memory	576444 kb
Host	smart-d64dc81d-60d3-4191-b44b-7d9c56af1de1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868727839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.3868727839
Directory	/workspace/56.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2355810882
Short name	T2752
Test name
Test status
Simulation time	1670196999 ps
CPU time	217.59 seconds
Started	Jul 24 07:42:40 PM PDT 24
Finished	Jul 24 07:46:17 PM PDT 24
Peak memory	577112 kb
Host	smart-b38a5869-c2cf-4651-9a75-9e996482f3b0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355810882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.2355810882
Directory	/workspace/56.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2663733626
Short name	T2461
Test name
Test status
Simulation time	425681657 ps
CPU time	117.3 seconds
Started	Jul 24 07:42:40 PM PDT 24
Finished	Jul 24 07:44:38 PM PDT 24
Peak memory	577220 kb
Host	smart-0619bac1-bd17-4d6c-ad54-24f654f6015a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663733626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.2663733626
Directory	/workspace/56.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.395132810
Short name	T2070
Test name
Test status
Simulation time	1391291343 ps
CPU time	53.94 seconds
Started	Jul 24 07:42:39 PM PDT 24
Finished	Jul 24 07:43:33 PM PDT 24
Peak memory	577036 kb
Host	smart-a18551f0-50cf-4bbf-a22b-2d868385f61a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395132810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.395132810
Directory	/workspace/56.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_access_same_device.17229204
Short name	T1619
Test name
Test status
Simulation time	827806409 ps
CPU time	64.63 seconds
Started	Jul 24 07:42:40 PM PDT 24
Finished	Jul 24 07:43:45 PM PDT 24
Peak memory	577148 kb
Host	smart-fca3e520-7e27-4ded-8a94-0e0a4d176d29
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17229204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device.17229204
Directory	/workspace/57.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.324563328
Short name	T920
Test name
Test status
Simulation time	88446893093 ps
CPU time	1664.17 seconds
Started	Jul 24 07:42:42 PM PDT 24
Finished	Jul 24 08:10:26 PM PDT 24
Peak memory	576356 kb
Host	smart-17dd17f5-0c7a-4b67-814c-8353f2518cfb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324563328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_d evice_slow_rsp.324563328
Directory	/workspace/57.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1222074542
Short name	T2383
Test name
Test status
Simulation time	1157400704 ps
CPU time	47.06 seconds
Started	Jul 24 07:42:40 PM PDT 24
Finished	Jul 24 07:43:27 PM PDT 24
Peak memory	576956 kb
Host	smart-34ee8d1b-939c-4571-a165-c559c2b5aa32
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222074542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.1222074542
Directory	/workspace/57.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_error_random.2945172290
Short name	T1571
Test name
Test status
Simulation time	2535576034 ps
CPU time	91.91 seconds
Started	Jul 24 07:42:41 PM PDT 24
Finished	Jul 24 07:44:13 PM PDT 24
Peak memory	577172 kb
Host	smart-cba85759-c914-42d1-a8fd-b882ca6cb4e6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945172290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.2945172290
Directory	/workspace/57.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_random.3483766658
Short name	T2746
Test name
Test status
Simulation time	2133895147 ps
CPU time	74.67 seconds
Started	Jul 24 07:42:40 PM PDT 24
Finished	Jul 24 07:43:54 PM PDT 24
Peak memory	576080 kb
Host	smart-c71eea77-da82-4efd-b93e-f15aece24c88
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483766658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.3483766658
Directory	/workspace/57.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_random_large_delays.938753183
Short name	T1639
Test name
Test status
Simulation time	41795975604 ps
CPU time	444.05 seconds
Started	Jul 24 07:42:41 PM PDT 24
Finished	Jul 24 07:50:05 PM PDT 24
Peak memory	576216 kb
Host	smart-c1ffa3f7-c4c4-4b02-9281-a60524444777
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938753183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.938753183
Directory	/workspace/57.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.286105145
Short name	T2143
Test name
Test status
Simulation time	29490045247 ps
CPU time	522.79 seconds
Started	Jul 24 07:42:39 PM PDT 24
Finished	Jul 24 07:51:22 PM PDT 24
Peak memory	577072 kb
Host	smart-dd268d62-1685-4aad-91b5-217646799700
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286105145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.286105145
Directory	/workspace/57.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.913476417
Short name	T2014
Test name
Test status
Simulation time	320825148 ps
CPU time	26.37 seconds
Started	Jul 24 07:43:26 PM PDT 24
Finished	Jul 24 07:43:52 PM PDT 24
Peak memory	577016 kb
Host	smart-95c3cce2-0486-46f5-b32b-08763a281f0b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913476417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_dela ys.913476417
Directory	/workspace/57.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_same_source.4208794081
Short name	T2655
Test name
Test status
Simulation time	487500777 ps
CPU time	39.57 seconds
Started	Jul 24 07:42:39 PM PDT 24
Finished	Jul 24 07:43:18 PM PDT 24
Peak memory	576180 kb
Host	smart-ea04bd7a-b01b-4bf6-ac6d-5e4dcd1956da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208794081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.4208794081
Directory	/workspace/57.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke.837769841
Short name	T2506
Test name
Test status
Simulation time	250103930 ps
CPU time	10.24 seconds
Started	Jul 24 07:42:41 PM PDT 24
Finished	Jul 24 07:42:52 PM PDT 24
Peak memory	576164 kb
Host	smart-37849e5f-e219-4d2e-a06c-72d5b4f6a2e6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837769841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.837769841
Directory	/workspace/57.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.2857148800
Short name	T1614
Test name
Test status
Simulation time	8833103966 ps
CPU time	86.49 seconds
Started	Jul 24 07:42:40 PM PDT 24
Finished	Jul 24 07:44:07 PM PDT 24
Peak memory	576236 kb
Host	smart-ea0f824b-8dd9-4e28-aa3d-95dc75ee5738
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857148800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.2857148800
Directory	/workspace/57.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.758232653
Short name	T2092
Test name
Test status
Simulation time	5130280960 ps
CPU time	89.3 seconds
Started	Jul 24 07:42:39 PM PDT 24
Finished	Jul 24 07:44:09 PM PDT 24
Peak memory	575028 kb
Host	smart-cb7e4fee-744a-4bdf-bcad-63bbd16a72db
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758232653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.758232653
Directory	/workspace/57.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.503501701
Short name	T1918
Test name
Test status
Simulation time	51525869 ps
CPU time	6.24 seconds
Started	Jul 24 07:42:41 PM PDT 24
Finished	Jul 24 07:42:47 PM PDT 24
Peak memory	574908 kb
Host	smart-6d7996ce-fe16-4637-bb3d-8aa797e8a0bd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503501701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays .503501701
Directory	/workspace/57.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all.1046304398
Short name	T475
Test name
Test status
Simulation time	3798140946 ps
CPU time	300.09 seconds
Started	Jul 24 07:42:49 PM PDT 24
Finished	Jul 24 07:47:49 PM PDT 24
Peak memory	576500 kb
Host	smart-ca8602f2-4fc4-4a39-a519-df9d5db24da0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046304398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.1046304398
Directory	/workspace/57.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.3405950355
Short name	T1473
Test name
Test status
Simulation time	11343622121 ps
CPU time	439.53 seconds
Started	Jul 24 07:42:52 PM PDT 24
Finished	Jul 24 07:50:12 PM PDT 24
Peak memory	576452 kb
Host	smart-91da6ce8-7c25-4173-a19f-ed7e067c55de
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405950355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.3405950355
Directory	/workspace/57.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1299401198
Short name	T973
Test name
Test status
Simulation time	527442190 ps
CPU time	171.36 seconds
Started	Jul 24 07:42:49 PM PDT 24
Finished	Jul 24 07:45:41 PM PDT 24
Peak memory	576292 kb
Host	smart-9469b12c-8daf-4f93-902c-a97ff17e433a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299401198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.1299401198
Directory	/workspace/57.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1949489919
Short name	T916
Test name
Test status
Simulation time	3726635145 ps
CPU time	217.92 seconds
Started	Jul 24 07:42:48 PM PDT 24
Finished	Jul 24 07:46:26 PM PDT 24
Peak memory	576436 kb
Host	smart-da144795-106d-461b-a249-85676e63ca54
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949489919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.1949489919
Directory	/workspace/57.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.3081142423
Short name	T2692
Test name
Test status
Simulation time	58806160 ps
CPU time	6.04 seconds
Started	Jul 24 07:42:39 PM PDT 24
Finished	Jul 24 07:42:46 PM PDT 24
Peak memory	574896 kb
Host	smart-cc4c52f5-c971-4570-913c-21422e11ee77
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081142423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.3081142423
Directory	/workspace/57.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_access_same_device.2187293629
Short name	T564
Test name
Test status
Simulation time	1528598435 ps
CPU time	66.65 seconds
Started	Jul 24 07:42:56 PM PDT 24
Finished	Jul 24 07:44:03 PM PDT 24
Peak memory	577008 kb
Host	smart-120acc1b-0fe1-468d-ae3a-c22a6f84cc03
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187293629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .2187293629
Directory	/workspace/58.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2207463930
Short name	T2274
Test name
Test status
Simulation time	77961849890 ps
CPU time	1415.62 seconds
Started	Jul 24 07:43:03 PM PDT 24
Finished	Jul 24 08:06:39 PM PDT 24
Peak memory	576420 kb
Host	smart-472bce11-a0cd-48cc-8f00-a317c15d96c8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207463930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.2207463930
Directory	/workspace/58.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2046710494
Short name	T2128
Test name
Test status
Simulation time	55394229 ps
CPU time	8.64 seconds
Started	Jul 24 07:42:58 PM PDT 24
Finished	Jul 24 07:43:07 PM PDT 24
Peak memory	577016 kb
Host	smart-53198637-3230-4a02-aae4-06e836f3735d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046710494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.2046710494
Directory	/workspace/58.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_error_random.2345513706
Short name	T1632
Test name
Test status
Simulation time	2396395750 ps
CPU time	87.16 seconds
Started	Jul 24 07:42:57 PM PDT 24
Finished	Jul 24 07:44:25 PM PDT 24
Peak memory	577056 kb
Host	smart-3e059eb7-a882-4bf1-a7b0-1ce73bf11c83
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345513706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.2345513706
Directory	/workspace/58.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_random.1423070828
Short name	T2589
Test name
Test status
Simulation time	1031966857 ps
CPU time	39.78 seconds
Started	Jul 24 07:42:52 PM PDT 24
Finished	Jul 24 07:43:32 PM PDT 24
Peak memory	576168 kb
Host	smart-f5020a01-b5a3-49c2-b5ab-25a9e35ee988
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423070828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1423070828
Directory	/workspace/58.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_random_large_delays.485151054
Short name	T641
Test name
Test status
Simulation time	60709673024 ps
CPU time	593.92 seconds
Started	Jul 24 07:43:41 PM PDT 24
Finished	Jul 24 07:53:36 PM PDT 24
Peak memory	576284 kb
Host	smart-ff8de146-c283-4e74-b0ee-9222845f54f7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485151054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.485151054
Directory	/workspace/58.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.3190756009
Short name	T2475
Test name
Test status
Simulation time	41719292379 ps
CPU time	765.63 seconds
Started	Jul 24 07:42:56 PM PDT 24
Finished	Jul 24 07:55:42 PM PDT 24
Peak memory	576240 kb
Host	smart-fe078e8b-c4cf-4104-8800-6652e9fcb03c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190756009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.3190756009
Directory	/workspace/58.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.1364206342
Short name	T2929
Test name
Test status
Simulation time	57504348 ps
CPU time	8.38 seconds
Started	Jul 24 07:43:00 PM PDT 24
Finished	Jul 24 07:43:09 PM PDT 24
Peak memory	574996 kb
Host	smart-cb67a674-4dcd-4109-8d94-5001a54a38a0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364206342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.1364206342
Directory	/workspace/58.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_same_source.2756439641
Short name	T588
Test name
Test status
Simulation time	377633478 ps
CPU time	24.56 seconds
Started	Jul 24 07:42:57 PM PDT 24
Finished	Jul 24 07:43:21 PM PDT 24
Peak memory	576992 kb
Host	smart-22ca7294-b4ad-4a9f-ab09-03e2fa99b341
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756439641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.2756439641
Directory	/workspace/58.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke.191268120
Short name	T1589
Test name
Test status
Simulation time	191331563 ps
CPU time	8.07 seconds
Started	Jul 24 07:43:12 PM PDT 24
Finished	Jul 24 07:43:21 PM PDT 24
Peak memory	574928 kb
Host	smart-67c8a94a-d248-4002-9c53-3258b9a1ec35
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191268120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.191268120
Directory	/workspace/58.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2691700435
Short name	T686
Test name
Test status
Simulation time	8042564412 ps
CPU time	82.31 seconds
Started	Jul 24 07:42:53 PM PDT 24
Finished	Jul 24 07:44:15 PM PDT 24
Peak memory	574996 kb
Host	smart-b059d8bc-e432-4224-9c46-8fddf79ea1a9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691700435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.2691700435
Directory	/workspace/58.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2168000562
Short name	T1630
Test name
Test status
Simulation time	5728229991 ps
CPU time	94.56 seconds
Started	Jul 24 07:42:52 PM PDT 24
Finished	Jul 24 07:44:27 PM PDT 24
Peak memory	576208 kb
Host	smart-74f358cb-87c4-400f-a357-fae150a0169a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168000562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.2168000562
Directory	/workspace/58.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2584170637
Short name	T2596
Test name
Test status
Simulation time	47418365 ps
CPU time	6.48 seconds
Started	Jul 24 07:42:52 PM PDT 24
Finished	Jul 24 07:42:59 PM PDT 24
Peak memory	574888 kb
Host	smart-51b40771-691d-4176-a592-ed7f6a35f70a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584170637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.2584170637
Directory	/workspace/58.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all.636114462
Short name	T2568
Test name
Test status
Simulation time	7216151589 ps
CPU time	261.71 seconds
Started	Jul 24 07:42:58 PM PDT 24
Finished	Jul 24 07:47:20 PM PDT 24
Peak memory	577300 kb
Host	smart-5ce39143-cbff-450b-80e8-a47bee2e1652
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636114462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.636114462
Directory	/workspace/58.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.4134919733
Short name	T2174
Test name
Test status
Simulation time	3324992813 ps
CPU time	255.08 seconds
Started	Jul 24 07:43:03 PM PDT 24
Finished	Jul 24 07:47:19 PM PDT 24
Peak memory	576436 kb
Host	smart-a8259da6-b696-48f4-99d4-68be38b7b949
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134919733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.4134919733
Directory	/workspace/58.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.304610889
Short name	T2485
Test name
Test status
Simulation time	291758564 ps
CPU time	124.95 seconds
Started	Jul 24 07:42:58 PM PDT 24
Finished	Jul 24 07:45:04 PM PDT 24
Peak memory	577160 kb
Host	smart-799b7ca3-ad4c-4228-b4c2-f4ab5a0ed31f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304610889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_ with_rand_reset.304610889
Directory	/workspace/58.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2088765688
Short name	T961
Test name
Test status
Simulation time	8494168392 ps
CPU time	448.81 seconds
Started	Jul 24 07:42:58 PM PDT 24
Finished	Jul 24 07:50:28 PM PDT 24
Peak memory	577364 kb
Host	smart-4ddb4591-b762-4ee6-924d-d654c719b06f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088765688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.2088765688
Directory	/workspace/58.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.4071358971
Short name	T701
Test name
Test status
Simulation time	219853667 ps
CPU time	24.76 seconds
Started	Jul 24 07:42:59 PM PDT 24
Finished	Jul 24 07:43:24 PM PDT 24
Peak memory	577136 kb
Host	smart-c8c57cde-1a9c-472d-9faa-d52ad97bddae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071358971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.4071358971
Directory	/workspace/58.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_access_same_device.3828040545
Short name	T2460
Test name
Test status
Simulation time	2313428245 ps
CPU time	94.24 seconds
Started	Jul 24 07:43:06 PM PDT 24
Finished	Jul 24 07:44:41 PM PDT 24
Peak memory	577152 kb
Host	smart-77031c75-6ae4-48e9-9217-6b1442452c34
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828040545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .3828040545
Directory	/workspace/59.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3988134102
Short name	T2575
Test name
Test status
Simulation time	131126232058 ps
CPU time	2447.1 seconds
Started	Jul 24 07:43:07 PM PDT 24
Finished	Jul 24 08:23:55 PM PDT 24
Peak memory	576452 kb
Host	smart-d1937b27-4fbe-46c0-bcc9-d5217561b687
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988134102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.3988134102
Directory	/workspace/59.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.2865749503
Short name	T1539
Test name
Test status
Simulation time	270308152 ps
CPU time	29.95 seconds
Started	Jul 24 07:43:06 PM PDT 24
Finished	Jul 24 07:43:36 PM PDT 24
Peak memory	576908 kb
Host	smart-279daa15-75c6-40d3-925f-18b6fef927df
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865749503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.2865749503
Directory	/workspace/59.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_error_random.477145215
Short name	T2329
Test name
Test status
Simulation time	475551518 ps
CPU time	35.92 seconds
Started	Jul 24 07:43:10 PM PDT 24
Finished	Jul 24 07:43:47 PM PDT 24
Peak memory	577108 kb
Host	smart-336cb3da-6098-411d-bece-ced4fc999a97
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477145215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.477145215
Directory	/workspace/59.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_random.2484268387
Short name	T2351
Test name
Test status
Simulation time	2248284242 ps
CPU time	89.45 seconds
Started	Jul 24 07:43:09 PM PDT 24
Finished	Jul 24 07:44:38 PM PDT 24
Peak memory	576332 kb
Host	smart-a5a3842e-69f0-4566-96e1-8075d273afc6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484268387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.2484268387
Directory	/workspace/59.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_random_large_delays.3876582857
Short name	T1855
Test name
Test status
Simulation time	28255685151 ps
CPU time	276.06 seconds
Started	Jul 24 07:43:07 PM PDT 24
Finished	Jul 24 07:47:44 PM PDT 24
Peak memory	577140 kb
Host	smart-b950970e-b354-4fab-b7e1-e39f9385de2b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876582857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.3876582857
Directory	/workspace/59.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1130767571
Short name	T615
Test name
Test status
Simulation time	41282040729 ps
CPU time	675.54 seconds
Started	Jul 24 07:43:12 PM PDT 24
Finished	Jul 24 07:54:28 PM PDT 24
Peak memory	577240 kb
Host	smart-e0e07962-2e34-4c1a-b259-1641693132e6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130767571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.1130767571
Directory	/workspace/59.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.884745288
Short name	T590
Test name
Test status
Simulation time	511505127 ps
CPU time	39.97 seconds
Started	Jul 24 07:43:06 PM PDT 24
Finished	Jul 24 07:43:46 PM PDT 24
Peak memory	577016 kb
Host	smart-7f190f68-70d7-4305-872b-0b19975c606a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884745288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_dela ys.884745288
Directory	/workspace/59.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_same_source.2535051781
Short name	T670
Test name
Test status
Simulation time	1944368712 ps
CPU time	59.15 seconds
Started	Jul 24 07:43:08 PM PDT 24
Finished	Jul 24 07:44:07 PM PDT 24
Peak memory	576968 kb
Host	smart-32d2a937-c640-4ecd-9ee1-12283c8c3d69
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535051781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.2535051781
Directory	/workspace/59.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke.3066281791
Short name	T737
Test name
Test status
Simulation time	217726369 ps
CPU time	9.43 seconds
Started	Jul 24 07:42:58 PM PDT 24
Finished	Jul 24 07:43:08 PM PDT 24
Peak memory	576092 kb
Host	smart-0102da0e-4063-4fe4-9ea6-df1a4c33a0e0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066281791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.3066281791
Directory	/workspace/59.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.696121007
Short name	T1497
Test name
Test status
Simulation time	8210328322 ps
CPU time	83.46 seconds
Started	Jul 24 07:43:02 PM PDT 24
Finished	Jul 24 07:44:26 PM PDT 24
Peak memory	575020 kb
Host	smart-303ffe2a-9601-4a23-9d2c-1d528d71e86e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696121007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.696121007
Directory	/workspace/59.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3498342835
Short name	T2769
Test name
Test status
Simulation time	5639757237 ps
CPU time	96.39 seconds
Started	Jul 24 07:43:06 PM PDT 24
Finished	Jul 24 07:44:43 PM PDT 24
Peak memory	575024 kb
Host	smart-ae76dcc4-d9e7-472a-a253-cc02f32da0fc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498342835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.3498342835
Directory	/workspace/59.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1422510745
Short name	T2699
Test name
Test status
Simulation time	54790576 ps
CPU time	6.74 seconds
Started	Jul 24 07:42:58 PM PDT 24
Finished	Jul 24 07:43:06 PM PDT 24
Peak memory	574860 kb
Host	smart-05763254-875f-447a-abca-fbf7b532d5cd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422510745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.1422510745
Directory	/workspace/59.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all.3864401128
Short name	T2862
Test name
Test status
Simulation time	2547798029 ps
CPU time	222.13 seconds
Started	Jul 24 07:43:10 PM PDT 24
Finished	Jul 24 07:46:53 PM PDT 24
Peak memory	576380 kb
Host	smart-4cf221cb-4c31-48e5-977c-6f268d54cd16
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864401128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.3864401128
Directory	/workspace/59.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.523356555
Short name	T2104
Test name
Test status
Simulation time	3768021874 ps
CPU time	142.76 seconds
Started	Jul 24 07:43:08 PM PDT 24
Finished	Jul 24 07:45:31 PM PDT 24
Peak memory	576332 kb
Host	smart-37f08bf3-ef52-4d49-9dfb-764736c30ea0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523356555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.523356555
Directory	/workspace/59.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.1162166484
Short name	T1722
Test name
Test status
Simulation time	134550241 ps
CPU time	70.85 seconds
Started	Jul 24 07:43:06 PM PDT 24
Finished	Jul 24 07:44:17 PM PDT 24
Peak memory	576288 kb
Host	smart-4a6cd73e-ea7c-418e-8238-8f26765147ca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162166484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.1162166484
Directory	/workspace/59.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1430418498
Short name	T1638
Test name
Test status
Simulation time	1262114140 ps
CPU time	119.48 seconds
Started	Jul 24 07:43:07 PM PDT 24
Finished	Jul 24 07:45:07 PM PDT 24
Peak memory	577148 kb
Host	smart-45740524-0971-445b-a521-879846793045
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430418498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.1430418498
Directory	/workspace/59.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.2979428065
Short name	T2796
Test name
Test status
Simulation time	305838495 ps
CPU time	36.13 seconds
Started	Jul 24 07:43:09 PM PDT 24
Finished	Jul 24 07:43:45 PM PDT 24
Peak memory	576260 kb
Host	smart-da2d56ed-86c5-46ab-8a10-4d474db0d99d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979428065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.2979428065
Directory	/workspace/59.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1793380767
Short name	T1620
Test name
Test status
Simulation time	8063737895 ps
CPU time	539.92 seconds
Started	Jul 24 07:33:56 PM PDT 24
Finished	Jul 24 07:42:56 PM PDT 24
Peak memory	642676 kb
Host	smart-86cb74ab-58a6-44ee-9003-ce3845568d41
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793380767 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.1793380767
Directory	/workspace/6.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/6.chip_csr_rw.1011857640
Short name	T1905
Test name
Test status
Simulation time	4280892252 ps
CPU time	422.15 seconds
Started	Jul 24 07:33:56 PM PDT 24
Finished	Jul 24 07:40:58 PM PDT 24
Peak memory	599672 kb
Host	smart-ba4e3d01-eda1-48e0-a7a8-c57bd7119285
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011857640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.1011857640
Directory	/workspace/6.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/6.chip_tl_errors.1459413442
Short name	T648
Test name
Test status
Simulation time	3195531314 ps
CPU time	180.38 seconds
Started	Jul 24 07:33:41 PM PDT 24
Finished	Jul 24 07:36:41 PM PDT 24
Peak memory	600500 kb
Host	smart-e12cae31-87e8-4838-8b18-867a10f1578b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459413442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1459413442
Directory	/workspace/6.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_access_same_device.2591801333
Short name	T1648
Test name
Test status
Simulation time	1059709360 ps
CPU time	40.99 seconds
Started	Jul 24 07:33:56 PM PDT 24
Finished	Jul 24 07:34:38 PM PDT 24
Peak memory	576264 kb
Host	smart-6974b1c4-11c3-45b2-8a10-c2077351c5c1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591801333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 2591801333
Directory	/workspace/6.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2833505214
Short name	T2123
Test name
Test status
Simulation time	110644731325 ps
CPU time	1899 seconds
Started	Jul 24 07:33:36 PM PDT 24
Finished	Jul 24 08:05:15 PM PDT 24
Peak memory	576356 kb
Host	smart-71e560f8-e209-4530-b963-0da4ac8f4b76
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833505214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.2833505214
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3277446070
Short name	T2620
Test name
Test status
Simulation time	240782047 ps
CPU time	26.61 seconds
Started	Jul 24 07:33:58 PM PDT 24
Finished	Jul 24 07:34:25 PM PDT 24
Peak memory	576204 kb
Host	smart-d616f082-a8c7-4bfb-8c61-a7a65ccf745e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277446070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .3277446070
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_error_random.1041935544
Short name	T2626
Test name
Test status
Simulation time	1501704683 ps
CPU time	50.95 seconds
Started	Jul 24 07:33:53 PM PDT 24
Finished	Jul 24 07:34:44 PM PDT 24
Peak memory	576136 kb
Host	smart-5f41943a-6d77-492d-89b7-f4c00d8466a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041935544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1041935544
Directory	/workspace/6.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_random.664777823
Short name	T1823
Test name
Test status
Simulation time	2546686961 ps
CPU time	93.89 seconds
Started	Jul 24 07:33:30 PM PDT 24
Finished	Jul 24 07:35:04 PM PDT 24
Peak memory	576232 kb
Host	smart-7b838072-bdb9-47cd-8a52-dd90eb6b4a7d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664777823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.664777823
Directory	/workspace/6.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_random_large_delays.2436485838
Short name	T1857
Test name
Test status
Simulation time	43387219777 ps
CPU time	451.19 seconds
Started	Jul 24 07:33:35 PM PDT 24
Finished	Jul 24 07:41:07 PM PDT 24
Peak memory	577136 kb
Host	smart-752382eb-4f5b-45ea-80ae-586b9e1ccedc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436485838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2436485838
Directory	/workspace/6.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.205236674
Short name	T2093
Test name
Test status
Simulation time	7661345981 ps
CPU time	127.29 seconds
Started	Jul 24 07:33:56 PM PDT 24
Finished	Jul 24 07:36:04 PM PDT 24
Peak memory	577116 kb
Host	smart-e627db59-b3a9-49b2-a960-55476996753f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205236674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.205236674
Directory	/workspace/6.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.3118018154
Short name	T669
Test name
Test status
Simulation time	217501929 ps
CPU time	20.29 seconds
Started	Jul 24 07:33:41 PM PDT 24
Finished	Jul 24 07:34:01 PM PDT 24
Peak memory	577008 kb
Host	smart-9c47854c-c8c7-4f94-8b9c-f075d0a310ef
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118018154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.3118018154
Directory	/workspace/6.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_same_source.3337799648
Short name	T1980
Test name
Test status
Simulation time	1478164763 ps
CPU time	47.31 seconds
Started	Jul 24 07:33:35 PM PDT 24
Finished	Jul 24 07:34:23 PM PDT 24
Peak memory	577028 kb
Host	smart-d4dcdcea-9c25-4acd-8838-d79ad6270cd9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337799648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3337799648
Directory	/workspace/6.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke.1452753955
Short name	T1530
Test name
Test status
Simulation time	56536207 ps
CPU time	6.27 seconds
Started	Jul 24 07:33:37 PM PDT 24
Finished	Jul 24 07:33:43 PM PDT 24
Peak memory	574952 kb
Host	smart-064b38bb-b9a4-4d13-85fd-f7b889f3fb83
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452753955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1452753955
Directory	/workspace/6.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3967948982
Short name	T2805
Test name
Test status
Simulation time	8001940847 ps
CPU time	78.51 seconds
Started	Jul 24 07:33:41 PM PDT 24
Finished	Jul 24 07:34:59 PM PDT 24
Peak memory	574932 kb
Host	smart-099cad06-b885-4a7a-93ee-f85ebbe1836e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967948982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3967948982
Directory	/workspace/6.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.799437903
Short name	T2434
Test name
Test status
Simulation time	5699858950 ps
CPU time	100.37 seconds
Started	Jul 24 07:33:26 PM PDT 24
Finished	Jul 24 07:35:07 PM PDT 24
Peak memory	576272 kb
Host	smart-bc9ce408-7aef-41fd-b1a9-89c84c995e95
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799437903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.799437903
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3897035550
Short name	T1831
Test name
Test status
Simulation time	34083116 ps
CPU time	5.6 seconds
Started	Jul 24 07:33:41 PM PDT 24
Finished	Jul 24 07:33:47 PM PDT 24
Peak memory	576196 kb
Host	smart-afdb2350-760e-4fbf-801d-6bbc2eda45e2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897035550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .3897035550
Directory	/workspace/6.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all.1775407372
Short name	T519
Test name
Test status
Simulation time	11439209716 ps
CPU time	385.19 seconds
Started	Jul 24 07:33:58 PM PDT 24
Finished	Jul 24 07:40:23 PM PDT 24
Peak memory	576520 kb
Host	smart-c7028f12-d128-40f4-9062-ef24e7ba6ade
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775407372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1775407372
Directory	/workspace/6.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.1018794919
Short name	T1691
Test name
Test status
Simulation time	1303842165 ps
CPU time	110.48 seconds
Started	Jul 24 07:33:58 PM PDT 24
Finished	Jul 24 07:35:49 PM PDT 24
Peak memory	576360 kb
Host	smart-9afd0f8c-03a7-4b21-8328-d843df2ac59b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018794919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1018794919
Directory	/workspace/6.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1004111036
Short name	T2218
Test name
Test status
Simulation time	6552707074 ps
CPU time	730.79 seconds
Started	Jul 24 07:33:54 PM PDT 24
Finished	Jul 24 07:46:05 PM PDT 24
Peak memory	576460 kb
Host	smart-ea4736ba-d552-4547-932d-398a59724b57
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004111036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.1004111036
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3946302098
Short name	T949
Test name
Test status
Simulation time	381004200 ps
CPU time	109 seconds
Started	Jul 24 07:33:37 PM PDT 24
Finished	Jul 24 07:35:26 PM PDT 24
Peak memory	577176 kb
Host	smart-f2f58997-4c8f-4e59-83aa-d4c948bef084
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946302098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.3946302098
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.3359058029
Short name	T1746
Test name
Test status
Simulation time	1223148389 ps
CPU time	48.42 seconds
Started	Jul 24 07:33:52 PM PDT 24
Finished	Jul 24 07:34:41 PM PDT 24
Peak memory	576200 kb
Host	smart-a99b8dba-b668-4cef-90f4-35fe7b5b9e3d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359058029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3359058029
Directory	/workspace/6.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_access_same_device.1261068177
Short name	T757
Test name
Test status
Simulation time	2386903140 ps
CPU time	94.87 seconds
Started	Jul 24 07:43:09 PM PDT 24
Finished	Jul 24 07:44:44 PM PDT 24
Peak memory	576196 kb
Host	smart-c1826278-18e5-49a5-9891-0af8bbe52cd6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261068177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .1261068177
Directory	/workspace/60.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.439599746
Short name	T926
Test name
Test status
Simulation time	132049785957 ps
CPU time	2331.21 seconds
Started	Jul 24 07:43:10 PM PDT 24
Finished	Jul 24 08:22:01 PM PDT 24
Peak memory	576324 kb
Host	smart-61a70904-fd33-4565-a281-23c0ecabd39f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439599746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_d evice_slow_rsp.439599746
Directory	/workspace/60.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1657244147
Short name	T1566
Test name
Test status
Simulation time	252090974 ps
CPU time	11.92 seconds
Started	Jul 24 07:43:17 PM PDT 24
Finished	Jul 24 07:43:29 PM PDT 24
Peak memory	577004 kb
Host	smart-88d7f310-de3f-4a47-9ff5-e93b2be9c4fe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657244147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.1657244147
Directory	/workspace/60.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_error_random.1347038398
Short name	T1765
Test name
Test status
Simulation time	98692386 ps
CPU time	11.51 seconds
Started	Jul 24 07:43:15 PM PDT 24
Finished	Jul 24 07:43:27 PM PDT 24
Peak memory	576968 kb
Host	smart-2b00c2c9-03d7-4044-a016-567add33c827
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347038398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.1347038398
Directory	/workspace/60.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_random.3367470306
Short name	T1806
Test name
Test status
Simulation time	101720371 ps
CPU time	12.2 seconds
Started	Jul 24 07:43:06 PM PDT 24
Finished	Jul 24 07:43:19 PM PDT 24
Peak memory	576208 kb
Host	smart-bd4b107d-ca15-4f6c-9525-6f73ae00051f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367470306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.3367470306
Directory	/workspace/60.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_random_large_delays.3587861207
Short name	T2425
Test name
Test status
Simulation time	42734095070 ps
CPU time	450.62 seconds
Started	Jul 24 07:43:07 PM PDT 24
Finished	Jul 24 07:50:38 PM PDT 24
Peak memory	576336 kb
Host	smart-6b7c0b83-cf18-4b86-8573-9e74da54099b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587861207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.3587861207
Directory	/workspace/60.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.577190620
Short name	T1474
Test name
Test status
Simulation time	7954960921 ps
CPU time	125.03 seconds
Started	Jul 24 07:43:08 PM PDT 24
Finished	Jul 24 07:45:14 PM PDT 24
Peak memory	577080 kb
Host	smart-c61dd04c-a9d5-4d35-a2b3-677bedd929fa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577190620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.577190620
Directory	/workspace/60.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.2194785978
Short name	T1841
Test name
Test status
Simulation time	390745046 ps
CPU time	34.64 seconds
Started	Jul 24 07:43:08 PM PDT 24
Finished	Jul 24 07:43:43 PM PDT 24
Peak memory	577008 kb
Host	smart-5ab1e5d9-ab2b-4b8b-b3f7-96e373ab63a9
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194785978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.2194785978
Directory	/workspace/60.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_same_source.3081125847
Short name	T2287
Test name
Test status
Simulation time	533881517 ps
CPU time	39.14 seconds
Started	Jul 24 07:43:14 PM PDT 24
Finished	Jul 24 07:43:54 PM PDT 24
Peak memory	576216 kb
Host	smart-7921dbd8-edf0-4d34-8dd5-6dd5fcc8d40b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081125847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.3081125847
Directory	/workspace/60.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke.3247248907
Short name	T2582
Test name
Test status
Simulation time	45510970 ps
CPU time	6 seconds
Started	Jul 24 07:43:07 PM PDT 24
Finished	Jul 24 07:43:13 PM PDT 24
Peak memory	574976 kb
Host	smart-e8e18518-12bb-41d5-89a7-d8316b2b5a9a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247248907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.3247248907
Directory	/workspace/60.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.1922470855
Short name	T2792
Test name
Test status
Simulation time	7137175956 ps
CPU time	78.17 seconds
Started	Jul 24 07:43:09 PM PDT 24
Finished	Jul 24 07:44:27 PM PDT 24
Peak memory	576264 kb
Host	smart-591dd56b-6ecc-4a9d-b47c-6d6cc8b1e992
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922470855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.1922470855
Directory	/workspace/60.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3215834493
Short name	T1558
Test name
Test status
Simulation time	4258950463 ps
CPU time	73.85 seconds
Started	Jul 24 07:43:06 PM PDT 24
Finished	Jul 24 07:44:20 PM PDT 24
Peak memory	575092 kb
Host	smart-0d21b58e-8a61-4448-9440-f58114dff559
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215834493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.3215834493
Directory	/workspace/60.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3971507439
Short name	T2281
Test name
Test status
Simulation time	52816568 ps
CPU time	7.07 seconds
Started	Jul 24 07:43:10 PM PDT 24
Finished	Jul 24 07:43:18 PM PDT 24
Peak memory	574932 kb
Host	smart-109df01e-fa1a-482d-9d40-0b66a88f71d0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971507439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.3971507439
Directory	/workspace/60.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all.894741654
Short name	T1862
Test name
Test status
Simulation time	2509392705 ps
CPU time	81.65 seconds
Started	Jul 24 07:43:16 PM PDT 24
Finished	Jul 24 07:44:37 PM PDT 24
Peak memory	577084 kb
Host	smart-5475f438-a2e9-4043-8b5e-ee5ee7ffba94
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894741654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.894741654
Directory	/workspace/60.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.1035204424
Short name	T2257
Test name
Test status
Simulation time	2322362415 ps
CPU time	65.42 seconds
Started	Jul 24 07:43:16 PM PDT 24
Finished	Jul 24 07:44:22 PM PDT 24
Peak memory	576144 kb
Host	smart-24aa30a6-e5a3-471a-a103-8795c9369e21
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035204424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.1035204424
Directory	/workspace/60.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.4142491877
Short name	T2529
Test name
Test status
Simulation time	934456114 ps
CPU time	280.84 seconds
Started	Jul 24 07:43:33 PM PDT 24
Finished	Jul 24 07:48:14 PM PDT 24
Peak memory	577156 kb
Host	smart-8505d15b-9d40-435a-bc8f-365e9470c24a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142491877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.4142491877
Directory	/workspace/60.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2096294314
Short name	T2602
Test name
Test status
Simulation time	9421587077 ps
CPU time	528.05 seconds
Started	Jul 24 07:43:17 PM PDT 24
Finished	Jul 24 07:52:05 PM PDT 24
Peak memory	578396 kb
Host	smart-dca2f985-3e58-419e-a017-6c41fd543c35
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096294314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.2096294314
Directory	/workspace/60.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2126309043
Short name	T1529
Test name
Test status
Simulation time	321825028 ps
CPU time	16.82 seconds
Started	Jul 24 07:43:15 PM PDT 24
Finished	Jul 24 07:43:32 PM PDT 24
Peak memory	576176 kb
Host	smart-bb6ce5cf-a15c-472d-8bb3-049311f18247
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126309043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2126309043
Directory	/workspace/60.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_access_same_device.820424837
Short name	T2190
Test name
Test status
Simulation time	579971221 ps
CPU time	42.62 seconds
Started	Jul 24 07:43:14 PM PDT 24
Finished	Jul 24 07:43:56 PM PDT 24
Peak memory	576976 kb
Host	smart-535210fe-cd1a-4fc9-bd2d-a3850ac4f5a0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820424837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device. 820424837
Directory	/workspace/61.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.880597769
Short name	T2100
Test name
Test status
Simulation time	39958214854 ps
CPU time	653.54 seconds
Started	Jul 24 07:43:34 PM PDT 24
Finished	Jul 24 07:54:28 PM PDT 24
Peak memory	577132 kb
Host	smart-8ca9f5db-0a9f-4b91-bb37-36794e11484e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880597769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_d evice_slow_rsp.880597769
Directory	/workspace/61.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2388564464
Short name	T2156
Test name
Test status
Simulation time	614276533 ps
CPU time	30.15 seconds
Started	Jul 24 07:43:26 PM PDT 24
Finished	Jul 24 07:43:57 PM PDT 24
Peak memory	577008 kb
Host	smart-1f9a96ae-a834-4490-818d-04206766a9a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388564464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.2388564464
Directory	/workspace/61.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_error_random.1078003353
Short name	T1550
Test name
Test status
Simulation time	2113454170 ps
CPU time	64.75 seconds
Started	Jul 24 07:43:29 PM PDT 24
Finished	Jul 24 07:44:34 PM PDT 24
Peak memory	577036 kb
Host	smart-0e092232-af7c-4be4-9113-4877ce2ec7d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078003353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.1078003353
Directory	/workspace/61.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_random.2151258999
Short name	T562
Test name
Test status
Simulation time	420713868 ps
CPU time	35.1 seconds
Started	Jul 24 07:43:15 PM PDT 24
Finished	Jul 24 07:43:50 PM PDT 24
Peak memory	576140 kb
Host	smart-70d75417-346f-44d6-9888-c778a2ca3937
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151258999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.2151258999
Directory	/workspace/61.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_random_large_delays.565717337
Short name	T2854
Test name
Test status
Simulation time	46173294555 ps
CPU time	475.36 seconds
Started	Jul 24 07:43:14 PM PDT 24
Finished	Jul 24 07:51:10 PM PDT 24
Peak memory	576344 kb
Host	smart-601f3f0c-6f85-4ccb-bdd9-163bc5fd979e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565717337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.565717337
Directory	/workspace/61.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.364679706
Short name	T1898
Test name
Test status
Simulation time	52652070020 ps
CPU time	920.79 seconds
Started	Jul 24 07:43:34 PM PDT 24
Finished	Jul 24 07:58:55 PM PDT 24
Peak memory	576312 kb
Host	smart-b2818489-d678-45fb-8682-d815162cd223
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364679706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.364679706
Directory	/workspace/61.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.2325519014
Short name	T739
Test name
Test status
Simulation time	366489895 ps
CPU time	34.26 seconds
Started	Jul 24 07:43:14 PM PDT 24
Finished	Jul 24 07:43:49 PM PDT 24
Peak memory	576236 kb
Host	smart-327f33a9-2d8e-45e7-83b2-0a9bae86580f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325519014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.2325519014
Directory	/workspace/61.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_same_source.1996946871
Short name	T1711
Test name
Test status
Simulation time	1290654974 ps
CPU time	34.15 seconds
Started	Jul 24 07:43:35 PM PDT 24
Finished	Jul 24 07:44:09 PM PDT 24
Peak memory	576160 kb
Host	smart-c6e8b150-bfc5-49d8-ac37-ab0fa6691089
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996946871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.1996946871
Directory	/workspace/61.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke.3927348417
Short name	T2902
Test name
Test status
Simulation time	54714762 ps
CPU time	6.21 seconds
Started	Jul 24 07:43:14 PM PDT 24
Finished	Jul 24 07:43:20 PM PDT 24
Peak memory	574848 kb
Host	smart-2fa24ffb-9473-4b54-8ac6-c189b9fc076e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927348417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3927348417
Directory	/workspace/61.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.1183300840
Short name	T2528
Test name
Test status
Simulation time	6055489067 ps
CPU time	62.52 seconds
Started	Jul 24 07:43:34 PM PDT 24
Finished	Jul 24 07:44:37 PM PDT 24
Peak memory	575000 kb
Host	smart-78b9a87b-d56b-414f-80d8-7cda624dddb7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183300840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.1183300840
Directory	/workspace/61.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.667510898
Short name	T2212
Test name
Test status
Simulation time	4150137651 ps
CPU time	70.23 seconds
Started	Jul 24 07:43:35 PM PDT 24
Finished	Jul 24 07:44:46 PM PDT 24
Peak memory	574996 kb
Host	smart-67bf5196-856a-46b1-9ea4-7e3e78803989
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667510898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.667510898
Directory	/workspace/61.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2960330981
Short name	T2182
Test name
Test status
Simulation time	44646961 ps
CPU time	5.9 seconds
Started	Jul 24 07:43:16 PM PDT 24
Finished	Jul 24 07:43:22 PM PDT 24
Peak memory	574904 kb
Host	smart-1be08fdc-e976-48c3-b4e7-e5a333586a9a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960330981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.2960330981
Directory	/workspace/61.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all.3430265668
Short name	T691
Test name
Test status
Simulation time	543553840 ps
CPU time	38.31 seconds
Started	Jul 24 07:43:24 PM PDT 24
Finished	Jul 24 07:44:03 PM PDT 24
Peak memory	576220 kb
Host	smart-4d8a9768-5712-40a5-8bce-8a08aea43753
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430265668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.3430265668
Directory	/workspace/61.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.1599821878
Short name	T2339
Test name
Test status
Simulation time	12048482193 ps
CPU time	465.77 seconds
Started	Jul 24 07:43:23 PM PDT 24
Finished	Jul 24 07:51:09 PM PDT 24
Peak memory	576424 kb
Host	smart-6bfc3fa0-1a30-468b-90d5-bad0797aec05
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599821878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.1599821878
Directory	/workspace/61.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2735166053
Short name	T1720
Test name
Test status
Simulation time	303953868 ps
CPU time	110.38 seconds
Started	Jul 24 07:43:23 PM PDT 24
Finished	Jul 24 07:45:14 PM PDT 24
Peak memory	577156 kb
Host	smart-4fd4a38e-8975-4c63-9ebc-57cb1e8aec53
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735166053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.2735166053
Directory	/workspace/61.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.4108452275
Short name	T1895
Test name
Test status
Simulation time	662979284 ps
CPU time	29.81 seconds
Started	Jul 24 07:43:25 PM PDT 24
Finished	Jul 24 07:43:55 PM PDT 24
Peak memory	577032 kb
Host	smart-085ccbba-596b-4c4c-9d16-fe7447a1f30f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108452275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.4108452275
Directory	/workspace/61.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_access_same_device.2960975543
Short name	T2210
Test name
Test status
Simulation time	499726596 ps
CPU time	38.89 seconds
Started	Jul 24 07:43:32 PM PDT 24
Finished	Jul 24 07:44:10 PM PDT 24
Peak memory	576096 kb
Host	smart-eb4272c5-b77f-4ad0-b4eb-da4bf1004995
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960975543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .2960975543
Directory	/workspace/62.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.515681196
Short name	T2099
Test name
Test status
Simulation time	107473551937 ps
CPU time	2061.17 seconds
Started	Jul 24 07:43:34 PM PDT 24
Finished	Jul 24 08:17:56 PM PDT 24
Peak memory	577128 kb
Host	smart-2c77a3d0-4993-4fda-bd78-0fdd2e5ef06e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515681196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_d evice_slow_rsp.515681196
Directory	/workspace/62.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2125744231
Short name	T2517
Test name
Test status
Simulation time	516979815 ps
CPU time	23.78 seconds
Started	Jul 24 07:43:39 PM PDT 24
Finished	Jul 24 07:44:03 PM PDT 24
Peak memory	576176 kb
Host	smart-0635bdb8-0c8b-45eb-8055-4e2fe7816f24
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125744231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.2125744231
Directory	/workspace/62.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_error_random.1904449
Short name	T1499
Test name
Test status
Simulation time	558024893 ps
CPU time	44.41 seconds
Started	Jul 24 07:43:32 PM PDT 24
Finished	Jul 24 07:44:16 PM PDT 24
Peak memory	576188 kb
Host	smart-96db9f27-0848-49db-be7b-ee2460c70548
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1904449
Directory	/workspace/62.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_random.341812626
Short name	T2853
Test name
Test status
Simulation time	2350119383 ps
CPU time	81.65 seconds
Started	Jul 24 07:43:34 PM PDT 24
Finished	Jul 24 07:44:56 PM PDT 24
Peak memory	577164 kb
Host	smart-2f6dd038-6930-4231-a3db-595b17512b57
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341812626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.341812626
Directory	/workspace/62.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_random_large_delays.1272568364
Short name	T1707
Test name
Test status
Simulation time	81062612783 ps
CPU time	908.2 seconds
Started	Jul 24 07:43:31 PM PDT 24
Finished	Jul 24 07:58:39 PM PDT 24
Peak memory	576376 kb
Host	smart-9208c88e-6295-4f23-8f9d-a23d5b826a73
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272568364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.1272568364
Directory	/workspace/62.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.1181012999
Short name	T2258
Test name
Test status
Simulation time	176510940 ps
CPU time	16.99 seconds
Started	Jul 24 07:43:35 PM PDT 24
Finished	Jul 24 07:43:52 PM PDT 24
Peak memory	576236 kb
Host	smart-dbb720f7-8bcf-4e44-9297-590150226913
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181012999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.1181012999
Directory	/workspace/62.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_same_source.4028226203
Short name	T1884
Test name
Test status
Simulation time	498081317 ps
CPU time	17.37 seconds
Started	Jul 24 07:43:37 PM PDT 24
Finished	Jul 24 07:43:54 PM PDT 24
Peak memory	576200 kb
Host	smart-eade7c06-890c-48c3-b8f0-17e255acdbb8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028226203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.4028226203
Directory	/workspace/62.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke.2158643129
Short name	T2515
Test name
Test status
Simulation time	180075188 ps
CPU time	7.82 seconds
Started	Jul 24 07:43:29 PM PDT 24
Finished	Jul 24 07:43:37 PM PDT 24
Peak memory	574928 kb
Host	smart-9f42e589-3527-4a49-8722-5c596e7410f5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158643129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.2158643129
Directory	/workspace/62.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.2429945938
Short name	T2734
Test name
Test status
Simulation time	9853243999 ps
CPU time	97.51 seconds
Started	Jul 24 07:43:26 PM PDT 24
Finished	Jul 24 07:45:03 PM PDT 24
Peak memory	574956 kb
Host	smart-b58ac07e-9d2c-4725-b332-ad80413f6bea
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429945938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.2429945938
Directory	/workspace/62.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.502228080
Short name	T2051
Test name
Test status
Simulation time	3377553602 ps
CPU time	58.47 seconds
Started	Jul 24 07:43:25 PM PDT 24
Finished	Jul 24 07:44:24 PM PDT 24
Peak memory	575068 kb
Host	smart-9bbb3372-bd99-4ecf-9795-9e00c5d97d39
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502228080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.502228080
Directory	/workspace/62.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2124702923
Short name	T1557
Test name
Test status
Simulation time	49239009 ps
CPU time	6.02 seconds
Started	Jul 24 07:43:26 PM PDT 24
Finished	Jul 24 07:43:32 PM PDT 24
Peak memory	574972 kb
Host	smart-4e740476-893f-4e64-98d7-fc7b027c03ed
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124702923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.2124702923
Directory	/workspace/62.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all.2333575492
Short name	T2932
Test name
Test status
Simulation time	197578333 ps
CPU time	14.89 seconds
Started	Jul 24 07:43:41 PM PDT 24
Finished	Jul 24 07:43:56 PM PDT 24
Peak memory	577004 kb
Host	smart-e2ff05b8-8e81-43e3-aba6-d516eaf84f64
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333575492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.2333575492
Directory	/workspace/62.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3119957532
Short name	T941
Test name
Test status
Simulation time	2902064906 ps
CPU time	226.47 seconds
Started	Jul 24 07:43:42 PM PDT 24
Finished	Jul 24 07:47:28 PM PDT 24
Peak memory	577328 kb
Host	smart-cf622fb6-bca1-4b78-8106-2929f14c7274
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119957532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.3119957532
Directory	/workspace/62.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3960934988
Short name	T967
Test name
Test status
Simulation time	2124107294 ps
CPU time	162.73 seconds
Started	Jul 24 07:43:44 PM PDT 24
Finished	Jul 24 07:46:27 PM PDT 24
Peak memory	576256 kb
Host	smart-2c1ff908-6f47-4f17-a455-4745609b5c00
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960934988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.3960934988
Directory	/workspace/62.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.244747686
Short name	T496
Test name
Test status
Simulation time	260349895 ps
CPU time	28.95 seconds
Started	Jul 24 07:43:33 PM PDT 24
Finished	Jul 24 07:44:02 PM PDT 24
Peak memory	577056 kb
Host	smart-62e17cfd-7f0e-4ea9-bacc-71020abe4ba1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244747686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.244747686
Directory	/workspace/62.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_access_same_device.2655462496
Short name	T2028
Test name
Test status
Simulation time	2925562196 ps
CPU time	129.07 seconds
Started	Jul 24 07:43:42 PM PDT 24
Finished	Jul 24 07:45:52 PM PDT 24
Peak memory	577168 kb
Host	smart-0435d0ba-1fb4-4b57-b99f-9c53fc7f2d86
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655462496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .2655462496
Directory	/workspace/63.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2078022474
Short name	T2235
Test name
Test status
Simulation time	36536208228 ps
CPU time	636.51 seconds
Started	Jul 24 07:43:44 PM PDT 24
Finished	Jul 24 07:54:20 PM PDT 24
Peak memory	576292 kb
Host	smart-4b45af26-e423-4042-b238-da269298b897
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078022474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.2078022474
Directory	/workspace/63.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.184850012
Short name	T1966
Test name
Test status
Simulation time	23877642 ps
CPU time	5.58 seconds
Started	Jul 24 07:43:42 PM PDT 24
Finished	Jul 24 07:43:47 PM PDT 24
Peak memory	574836 kb
Host	smart-4c08aeb3-a002-4335-836a-cc824ecb0a50
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184850012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr .184850012
Directory	/workspace/63.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_error_random.3991780811
Short name	T1713
Test name
Test status
Simulation time	111512338 ps
CPU time	11.93 seconds
Started	Jul 24 07:43:40 PM PDT 24
Finished	Jul 24 07:43:52 PM PDT 24
Peak memory	576988 kb
Host	smart-62136828-b7a4-4c69-9677-a9d2d090f1eb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991780811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.3991780811
Directory	/workspace/63.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_random.1827752741
Short name	T612
Test name
Test status
Simulation time	2351724674 ps
CPU time	77.82 seconds
Started	Jul 24 07:43:40 PM PDT 24
Finished	Jul 24 07:44:58 PM PDT 24
Peak memory	576296 kb
Host	smart-e18eb974-bcd9-4440-ba58-889d72837670
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827752741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.1827752741
Directory	/workspace/63.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_random_large_delays.2023041129
Short name	T1811
Test name
Test status
Simulation time	95057197569 ps
CPU time	1037.43 seconds
Started	Jul 24 07:43:41 PM PDT 24
Finished	Jul 24 08:00:59 PM PDT 24
Peak memory	576376 kb
Host	smart-19a1f524-1a6c-41bd-b555-ba3fcff7ecc3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023041129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.2023041129
Directory	/workspace/63.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.2456634598
Short name	T621
Test name
Test status
Simulation time	68224109009 ps
CPU time	1211.83 seconds
Started	Jul 24 07:43:49 PM PDT 24
Finished	Jul 24 08:04:01 PM PDT 24
Peak memory	577100 kb
Host	smart-664c29e0-d1de-4063-a1d3-d6e789bb03e5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456634598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.2456634598
Directory	/workspace/63.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.963003870
Short name	T1487
Test name
Test status
Simulation time	26111358 ps
CPU time	5.47 seconds
Started	Jul 24 07:43:40 PM PDT 24
Finished	Jul 24 07:43:46 PM PDT 24
Peak memory	574936 kb
Host	smart-7d8919e1-65f2-4ead-ab3a-d10400a1045f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963003870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_dela ys.963003870
Directory	/workspace/63.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_same_source.3938512004
Short name	T629
Test name
Test status
Simulation time	366431872 ps
CPU time	28.05 seconds
Started	Jul 24 07:43:40 PM PDT 24
Finished	Jul 24 07:44:09 PM PDT 24
Peak memory	577036 kb
Host	smart-cd36713b-072a-436a-b655-7f3caf05683e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938512004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.3938512004
Directory	/workspace/63.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke.535285183
Short name	T2812
Test name
Test status
Simulation time	45493373 ps
CPU time	6.32 seconds
Started	Jul 24 07:43:41 PM PDT 24
Finished	Jul 24 07:43:47 PM PDT 24
Peak memory	576040 kb
Host	smart-c3137b15-ef26-4990-929f-a8efd7ec7190
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535285183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.535285183
Directory	/workspace/63.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.3443250078
Short name	T2272
Test name
Test status
Simulation time	9610659608 ps
CPU time	100.45 seconds
Started	Jul 24 07:43:40 PM PDT 24
Finished	Jul 24 07:45:20 PM PDT 24
Peak memory	575092 kb
Host	smart-bb39e803-6980-466d-bd54-6aa76d581053
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443250078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.3443250078
Directory	/workspace/63.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3107332460
Short name	T2373
Test name
Test status
Simulation time	5717788923 ps
CPU time	92.76 seconds
Started	Jul 24 07:43:44 PM PDT 24
Finished	Jul 24 07:45:17 PM PDT 24
Peak memory	574920 kb
Host	smart-9c5ae1d2-88a1-4256-83e4-9e9943707862
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107332460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.3107332460
Directory	/workspace/63.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.136917964
Short name	T1887
Test name
Test status
Simulation time	49119857 ps
CPU time	7.01 seconds
Started	Jul 24 07:43:41 PM PDT 24
Finished	Jul 24 07:43:48 PM PDT 24
Peak memory	576100 kb
Host	smart-480f1e97-9790-4fb0-9c8c-5ea3b3f86202
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136917964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays .136917964
Directory	/workspace/63.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all.1843328201
Short name	T2107
Test name
Test status
Simulation time	468378526 ps
CPU time	18.12 seconds
Started	Jul 24 07:43:50 PM PDT 24
Finished	Jul 24 07:44:08 PM PDT 24
Peak memory	576996 kb
Host	smart-58e5878d-3106-4b4d-a203-644642c0a6da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843328201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.1843328201
Directory	/workspace/63.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.597783878
Short name	T2687
Test name
Test status
Simulation time	1123794313 ps
CPU time	91.89 seconds
Started	Jul 24 07:43:45 PM PDT 24
Finished	Jul 24 07:45:17 PM PDT 24
Peak memory	577056 kb
Host	smart-e595dbbc-b5a2-440e-8e2d-a68bda654837
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597783878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.597783878
Directory	/workspace/63.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2626245002
Short name	T2189
Test name
Test status
Simulation time	600728067 ps
CPU time	217.4 seconds
Started	Jul 24 07:43:40 PM PDT 24
Finished	Jul 24 07:47:18 PM PDT 24
Peak memory	576372 kb
Host	smart-ae9177ae-5497-4830-b29b-8e791320242b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626245002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.2626245002
Directory	/workspace/63.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1364278340
Short name	T2324
Test name
Test status
Simulation time	175153923 ps
CPU time	61.37 seconds
Started	Jul 24 07:43:50 PM PDT 24
Finished	Jul 24 07:44:51 PM PDT 24
Peak memory	577020 kb
Host	smart-e0aa1fa0-c4fd-41bc-9589-8294d61585d9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364278340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.1364278340
Directory	/workspace/63.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.2313432952
Short name	T2819
Test name
Test status
Simulation time	183743973 ps
CPU time	20.09 seconds
Started	Jul 24 07:43:45 PM PDT 24
Finished	Jul 24 07:44:05 PM PDT 24
Peak memory	576216 kb
Host	smart-e3787569-90ca-4a6f-9fb7-a07360858031
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313432952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.2313432952
Directory	/workspace/63.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_access_same_device.2676426532
Short name	T907
Test name
Test status
Simulation time	1270735193 ps
CPU time	54.56 seconds
Started	Jul 24 07:43:55 PM PDT 24
Finished	Jul 24 07:44:50 PM PDT 24
Peak memory	576972 kb
Host	smart-8e2e036d-fd75-4b91-9e99-65429ccdc153
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676426532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .2676426532
Directory	/workspace/64.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.652383386
Short name	T1727
Test name
Test status
Simulation time	100824542385 ps
CPU time	1767.02 seconds
Started	Jul 24 07:43:53 PM PDT 24
Finished	Jul 24 08:13:20 PM PDT 24
Peak memory	577164 kb
Host	smart-df46845d-9b1b-4ddc-8723-69659e6ac48c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652383386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_d evice_slow_rsp.652383386
Directory	/workspace/64.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.548160653
Short name	T2400
Test name
Test status
Simulation time	376716263 ps
CPU time	18.66 seconds
Started	Jul 24 07:43:55 PM PDT 24
Finished	Jul 24 07:44:14 PM PDT 24
Peak memory	577084 kb
Host	smart-22572a48-4971-45c4-b190-15fab556841d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548160653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr .548160653
Directory	/workspace/64.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_error_random.230298824
Short name	T2881
Test name
Test status
Simulation time	613975323 ps
CPU time	48.37 seconds
Started	Jul 24 07:43:52 PM PDT 24
Finished	Jul 24 07:44:41 PM PDT 24
Peak memory	577084 kb
Host	smart-6cba4187-04fb-47d3-a2aa-af99a4657ccb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230298824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.230298824
Directory	/workspace/64.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_random.1609390999
Short name	T2368
Test name
Test status
Simulation time	1143131790 ps
CPU time	40.49 seconds
Started	Jul 24 07:43:53 PM PDT 24
Finished	Jul 24 07:44:34 PM PDT 24
Peak memory	576992 kb
Host	smart-9b488279-6dff-4eed-8a9a-35a66c4f0ef1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609390999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.1609390999
Directory	/workspace/64.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_random_large_delays.3359124387
Short name	T2184
Test name
Test status
Simulation time	62287944368 ps
CPU time	642.9 seconds
Started	Jul 24 07:43:53 PM PDT 24
Finished	Jul 24 07:54:37 PM PDT 24
Peak memory	577192 kb
Host	smart-e9302117-994c-445f-a746-0a22d6237419
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359124387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.3359124387
Directory	/workspace/64.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1834578231
Short name	T2810
Test name
Test status
Simulation time	29270373878 ps
CPU time	466.53 seconds
Started	Jul 24 07:43:57 PM PDT 24
Finished	Jul 24 07:51:44 PM PDT 24
Peak memory	577112 kb
Host	smart-19372010-9381-4dba-89ec-4e7a4eab2c4b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834578231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.1834578231
Directory	/workspace/64.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.3798939094
Short name	T636
Test name
Test status
Simulation time	442250448 ps
CPU time	40.31 seconds
Started	Jul 24 07:43:54 PM PDT 24
Finished	Jul 24 07:44:35 PM PDT 24
Peak memory	576216 kb
Host	smart-6bd3572a-afe9-4f30-9404-98f6616c8707
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798939094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.3798939094
Directory	/workspace/64.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_same_source.2899266090
Short name	T489
Test name
Test status
Simulation time	524098605 ps
CPU time	37.91 seconds
Started	Jul 24 07:43:52 PM PDT 24
Finished	Jul 24 07:44:30 PM PDT 24
Peak memory	576180 kb
Host	smart-66ab5520-f261-4cf2-9084-76014db298df
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899266090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2899266090
Directory	/workspace/64.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke.1714566922
Short name	T2468
Test name
Test status
Simulation time	37629755 ps
CPU time	5.61 seconds
Started	Jul 24 07:43:55 PM PDT 24
Finished	Jul 24 07:44:01 PM PDT 24
Peak memory	574808 kb
Host	smart-427a2b79-56df-4670-9446-92855b253e62
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714566922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.1714566922
Directory	/workspace/64.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.1627423581
Short name	T2913
Test name
Test status
Simulation time	8588602348 ps
CPU time	82.29 seconds
Started	Jul 24 07:43:54 PM PDT 24
Finished	Jul 24 07:45:16 PM PDT 24
Peak memory	574996 kb
Host	smart-94c61048-8cc3-4a3a-988c-b1fa916260a8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627423581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.1627423581
Directory	/workspace/64.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3126269311
Short name	T718
Test name
Test status
Simulation time	5808322975 ps
CPU time	97.49 seconds
Started	Jul 24 07:43:54 PM PDT 24
Finished	Jul 24 07:45:31 PM PDT 24
Peak memory	574972 kb
Host	smart-2415600c-0744-4643-90c6-82abd201b562
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126269311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.3126269311
Directory	/workspace/64.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.3674359243
Short name	T2134
Test name
Test status
Simulation time	53058666 ps
CPU time	7.07 seconds
Started	Jul 24 07:43:52 PM PDT 24
Finished	Jul 24 07:43:59 PM PDT 24
Peak memory	576192 kb
Host	smart-1a247632-e70f-4e53-ab7d-345326114327
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674359243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.3674359243
Directory	/workspace/64.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all.252454210
Short name	T2121
Test name
Test status
Simulation time	14252773578 ps
CPU time	594.12 seconds
Started	Jul 24 07:43:53 PM PDT 24
Finished	Jul 24 07:53:47 PM PDT 24
Peak memory	576540 kb
Host	smart-c342d5a2-ff63-4c28-bae8-427af5a71c30
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252454210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.252454210
Directory	/workspace/64.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.415592299
Short name	T2045
Test name
Test status
Simulation time	7714198479 ps
CPU time	242.54 seconds
Started	Jul 24 07:43:53 PM PDT 24
Finished	Jul 24 07:47:55 PM PDT 24
Peak memory	576120 kb
Host	smart-7f367f62-b87e-4f35-88e3-40f844a6d43a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415592299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.415592299
Directory	/workspace/64.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.4144189682
Short name	T960
Test name
Test status
Simulation time	364415618 ps
CPU time	137.88 seconds
Started	Jul 24 07:43:53 PM PDT 24
Finished	Jul 24 07:46:11 PM PDT 24
Peak memory	577152 kb
Host	smart-3a0afee7-08fa-4954-912b-dcf897f492f2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144189682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.4144189682
Directory	/workspace/64.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.4179541158
Short name	T1943
Test name
Test status
Simulation time	1343283603 ps
CPU time	68.96 seconds
Started	Jul 24 07:43:52 PM PDT 24
Finished	Jul 24 07:45:01 PM PDT 24
Peak memory	577124 kb
Host	smart-e9a4eaeb-4ffb-45d6-999a-ece6fa33d192
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179541158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.4179541158
Directory	/workspace/64.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.4072769037
Short name	T2737
Test name
Test status
Simulation time	286663043 ps
CPU time	30.26 seconds
Started	Jul 24 07:43:54 PM PDT 24
Finished	Jul 24 07:44:25 PM PDT 24
Peak memory	577012 kb
Host	smart-6529c176-36e8-4904-a089-4d94b54d078c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072769037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.4072769037
Directory	/workspace/64.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_access_same_device.2944939588
Short name	T2231
Test name
Test status
Simulation time	457698369 ps
CPU time	43.89 seconds
Started	Jul 24 07:44:01 PM PDT 24
Finished	Jul 24 07:44:45 PM PDT 24
Peak memory	576952 kb
Host	smart-1d0953d6-dc9a-401d-b27f-27ea9e0fc2a0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944939588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .2944939588
Directory	/workspace/65.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2539338394
Short name	T2572
Test name
Test status
Simulation time	87764086786 ps
CPU time	1681.39 seconds
Started	Jul 24 07:44:03 PM PDT 24
Finished	Jul 24 08:12:04 PM PDT 24
Peak memory	576368 kb
Host	smart-7f625825-dc8a-445e-88ef-649b7e653bdf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539338394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.2539338394
Directory	/workspace/65.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3347714137
Short name	T1930
Test name
Test status
Simulation time	260973834 ps
CPU time	13.7 seconds
Started	Jul 24 07:44:00 PM PDT 24
Finished	Jul 24 07:44:14 PM PDT 24
Peak memory	577008 kb
Host	smart-5ae28596-9af6-445d-befe-7d5289943a16
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347714137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.3347714137
Directory	/workspace/65.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_error_random.1496942509
Short name	T1757
Test name
Test status
Simulation time	584152048 ps
CPU time	42.93 seconds
Started	Jul 24 07:44:01 PM PDT 24
Finished	Jul 24 07:44:44 PM PDT 24
Peak memory	576984 kb
Host	smart-b810b33d-badd-4de7-96c6-c7b2099189cb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496942509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.1496942509
Directory	/workspace/65.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_random.2950978827
Short name	T526
Test name
Test status
Simulation time	2097017314 ps
CPU time	76.67 seconds
Started	Jul 24 07:43:59 PM PDT 24
Finished	Jul 24 07:45:16 PM PDT 24
Peak memory	576152 kb
Host	smart-d379d26a-2705-4ebd-9b83-e7356e60cd01
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950978827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2950978827
Directory	/workspace/65.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_random_large_delays.427913641
Short name	T595
Test name
Test status
Simulation time	44039532393 ps
CPU time	457.8 seconds
Started	Jul 24 07:44:02 PM PDT 24
Finished	Jul 24 07:51:40 PM PDT 24
Peak memory	576300 kb
Host	smart-70cfb8eb-bbd3-4741-b7ff-57be10a4a17f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427913641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.427913641
Directory	/workspace/65.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.1358308601
Short name	T2413
Test name
Test status
Simulation time	6712860731 ps
CPU time	118.55 seconds
Started	Jul 24 07:44:02 PM PDT 24
Finished	Jul 24 07:46:00 PM PDT 24
Peak memory	576228 kb
Host	smart-60b08e94-a423-4b17-b483-e0a890485bf3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358308601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.1358308601
Directory	/workspace/65.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.222324906
Short name	T680
Test name
Test status
Simulation time	480460567 ps
CPU time	46.82 seconds
Started	Jul 24 07:44:03 PM PDT 24
Finished	Jul 24 07:44:50 PM PDT 24
Peak memory	576304 kb
Host	smart-5b253827-4973-44c9-98d8-bbe84dc506b8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222324906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_dela ys.222324906
Directory	/workspace/65.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_same_source.745817784
Short name	T2252
Test name
Test status
Simulation time	367349507 ps
CPU time	29.97 seconds
Started	Jul 24 07:44:03 PM PDT 24
Finished	Jul 24 07:44:33 PM PDT 24
Peak memory	576196 kb
Host	smart-f64906d4-28d5-4b24-a0b7-75bba694b922
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745817784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.745817784
Directory	/workspace/65.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke.3324533047
Short name	T2175
Test name
Test status
Simulation time	45549001 ps
CPU time	6.47 seconds
Started	Jul 24 07:44:01 PM PDT 24
Finished	Jul 24 07:44:08 PM PDT 24
Peak memory	576192 kb
Host	smart-ddff6412-dac0-4296-b26e-723e41fd7a03
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324533047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.3324533047
Directory	/workspace/65.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.4020413538
Short name	T626
Test name
Test status
Simulation time	8398252451 ps
CPU time	92.17 seconds
Started	Jul 24 07:44:03 PM PDT 24
Finished	Jul 24 07:45:35 PM PDT 24
Peak memory	576172 kb
Host	smart-9f4f9af8-683b-4953-ad7b-7fd2e6851a6a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020413538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.4020413538
Directory	/workspace/65.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.926969820
Short name	T2309
Test name
Test status
Simulation time	3241775091 ps
CPU time	54.91 seconds
Started	Jul 24 07:44:04 PM PDT 24
Finished	Jul 24 07:45:00 PM PDT 24
Peak memory	574964 kb
Host	smart-436ef175-b5de-4617-b127-f8ef79f8773f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926969820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.926969820
Directory	/workspace/65.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2593505255
Short name	T2453
Test name
Test status
Simulation time	42785116 ps
CPU time	6.11 seconds
Started	Jul 24 07:44:04 PM PDT 24
Finished	Jul 24 07:44:10 PM PDT 24
Peak memory	574900 kb
Host	smart-adb820ed-cbd6-4552-986e-f58f398a4596
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593505255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.2593505255
Directory	/workspace/65.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all.3202884236
Short name	T647
Test name
Test status
Simulation time	1683588841 ps
CPU time	141.76 seconds
Started	Jul 24 07:44:01 PM PDT 24
Finished	Jul 24 07:46:23 PM PDT 24
Peak memory	577128 kb
Host	smart-064096b4-5a14-4a09-9ef4-213000546128
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202884236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.3202884236
Directory	/workspace/65.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.4174866697
Short name	T1800
Test name
Test status
Simulation time	3488658647 ps
CPU time	291.91 seconds
Started	Jul 24 07:44:06 PM PDT 24
Finished	Jul 24 07:48:59 PM PDT 24
Peak memory	577284 kb
Host	smart-997de5c4-61b0-438c-b67e-8390a0e8a523
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174866697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.4174866697
Directory	/workspace/65.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2400504461
Short name	T2532
Test name
Test status
Simulation time	1013197241 ps
CPU time	117.93 seconds
Started	Jul 24 07:44:05 PM PDT 24
Finished	Jul 24 07:46:03 PM PDT 24
Peak memory	576328 kb
Host	smart-8734b318-89ec-466c-bd98-a87dc2631791
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400504461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.2400504461
Directory	/workspace/65.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.4046255277
Short name	T963
Test name
Test status
Simulation time	2779164943 ps
CPU time	263.03 seconds
Started	Jul 24 07:44:05 PM PDT 24
Finished	Jul 24 07:48:29 PM PDT 24
Peak memory	577232 kb
Host	smart-d75d7830-f746-4bf6-8983-a28095c20e5c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046255277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.4046255277
Directory	/workspace/65.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.3382699738
Short name	T640
Test name
Test status
Simulation time	262588614 ps
CPU time	14.47 seconds
Started	Jul 24 07:44:04 PM PDT 24
Finished	Jul 24 07:44:19 PM PDT 24
Peak memory	576992 kb
Host	smart-3caf7b9d-38c7-48b6-98bb-4b09215572db
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382699738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.3382699738
Directory	/workspace/65.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2043169861
Short name	T2159
Test name
Test status
Simulation time	3003720285 ps
CPU time	52.06 seconds
Started	Jul 24 07:44:12 PM PDT 24
Finished	Jul 24 07:45:04 PM PDT 24
Peak memory	574964 kb
Host	smart-ee93a1b2-59da-47da-952a-b3b12b76e418
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043169861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.2043169861
Directory	/workspace/66.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.395521489
Short name	T1523
Test name
Test status
Simulation time	804516326 ps
CPU time	31.6 seconds
Started	Jul 24 07:44:11 PM PDT 24
Finished	Jul 24 07:44:43 PM PDT 24
Peak memory	577000 kb
Host	smart-4f9c635c-4af5-4972-95ea-ff42dc5cda5b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395521489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr .395521489
Directory	/workspace/66.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_error_random.3625126443
Short name	T2649
Test name
Test status
Simulation time	1111486618 ps
CPU time	35.06 seconds
Started	Jul 24 07:44:10 PM PDT 24
Finished	Jul 24 07:44:45 PM PDT 24
Peak memory	576992 kb
Host	smart-7ff5af47-c842-4e92-a231-6ae6d544a5d1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625126443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.3625126443
Directory	/workspace/66.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_random.89665753
Short name	T1953
Test name
Test status
Simulation time	919909309 ps
CPU time	31.77 seconds
Started	Jul 24 07:44:01 PM PDT 24
Finished	Jul 24 07:44:33 PM PDT 24
Peak memory	576124 kb
Host	smart-2b7aa4a1-0cb1-4a7b-9595-a07b778e5706
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89665753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.89665753
Directory	/workspace/66.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_random_large_delays.99809890
Short name	T1748
Test name
Test status
Simulation time	57714328786 ps
CPU time	574.39 seconds
Started	Jul 24 07:44:01 PM PDT 24
Finished	Jul 24 07:53:35 PM PDT 24
Peak memory	576324 kb
Host	smart-bf6f5269-0b71-4cb9-82b5-862baedc4c8c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99809890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.99809890
Directory	/workspace/66.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.4149468386
Short name	T1645
Test name
Test status
Simulation time	41161401114 ps
CPU time	717.95 seconds
Started	Jul 24 07:44:00 PM PDT 24
Finished	Jul 24 07:55:58 PM PDT 24
Peak memory	577088 kb
Host	smart-1c1e2edc-7e84-4a2c-bf1d-dd2a9353dcfb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149468386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.4149468386
Directory	/workspace/66.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.2719522001
Short name	T1732
Test name
Test status
Simulation time	31807165 ps
CPU time	6.03 seconds
Started	Jul 24 07:44:03 PM PDT 24
Finished	Jul 24 07:44:09 PM PDT 24
Peak memory	574960 kb
Host	smart-4c23246c-4877-40f6-b057-bced10deea14
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719522001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.2719522001
Directory	/workspace/66.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_same_source.1425675080
Short name	T2909
Test name
Test status
Simulation time	150041508 ps
CPU time	11.95 seconds
Started	Jul 24 07:44:10 PM PDT 24
Finished	Jul 24 07:44:22 PM PDT 24
Peak memory	576160 kb
Host	smart-d69e5ca0-edfc-4caa-a86c-74cddf094387
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425675080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.1425675080
Directory	/workspace/66.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke.1138848453
Short name	T2242
Test name
Test status
Simulation time	53919902 ps
CPU time	6.92 seconds
Started	Jul 24 07:44:06 PM PDT 24
Finished	Jul 24 07:44:13 PM PDT 24
Peak memory	574944 kb
Host	smart-7bb20b4c-7fcd-42f7-82ab-18d664e636d7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138848453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1138848453
Directory	/workspace/66.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.2149719704
Short name	T2276
Test name
Test status
Simulation time	7648224091 ps
CPU time	72.09 seconds
Started	Jul 24 07:44:00 PM PDT 24
Finished	Jul 24 07:45:13 PM PDT 24
Peak memory	576348 kb
Host	smart-ae1710fa-871c-467e-8ff9-2a82eb66e71f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149719704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2149719704
Directory	/workspace/66.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.4255684083
Short name	T2065
Test name
Test status
Simulation time	6479676128 ps
CPU time	107.41 seconds
Started	Jul 24 07:44:02 PM PDT 24
Finished	Jul 24 07:45:49 PM PDT 24
Peak memory	575036 kb
Host	smart-f1a70ab5-9a63-4003-9ad1-9ba48b21d567
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255684083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.4255684083
Directory	/workspace/66.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.3768133220
Short name	T1637
Test name
Test status
Simulation time	52727090 ps
CPU time	6.92 seconds
Started	Jul 24 07:44:05 PM PDT 24
Finished	Jul 24 07:44:12 PM PDT 24
Peak memory	574852 kb
Host	smart-295d272d-fa19-4d98-a9d2-87f7c778e866
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768133220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.3768133220
Directory	/workspace/66.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all.371115411
Short name	T2391
Test name
Test status
Simulation time	2282098561 ps
CPU time	188.22 seconds
Started	Jul 24 07:44:10 PM PDT 24
Finished	Jul 24 07:47:18 PM PDT 24
Peak memory	577268 kb
Host	smart-294cd650-ca81-4c56-b0a1-2a05939cbf61
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371115411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.371115411
Directory	/workspace/66.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.4145158826
Short name	T803
Test name
Test status
Simulation time	745434657 ps
CPU time	61.37 seconds
Started	Jul 24 07:44:12 PM PDT 24
Finished	Jul 24 07:45:13 PM PDT 24
Peak memory	576304 kb
Host	smart-18773681-fc37-4698-bf53-b8b97566ea71
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145158826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.4145158826
Directory	/workspace/66.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3021548739
Short name	T627
Test name
Test status
Simulation time	2453937000 ps
CPU time	482.13 seconds
Started	Jul 24 07:44:14 PM PDT 24
Finished	Jul 24 07:52:16 PM PDT 24
Peak memory	576380 kb
Host	smart-c06a41b8-ff63-42d0-b78a-6c4b3239c44f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021548739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.3021548739
Directory	/workspace/66.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.4102279564
Short name	T547
Test name
Test status
Simulation time	1032321404 ps
CPU time	164.07 seconds
Started	Jul 24 07:44:11 PM PDT 24
Finished	Jul 24 07:46:55 PM PDT 24
Peak memory	577080 kb
Host	smart-323ee068-7f7b-4679-bc00-d7663985c92c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102279564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.4102279564
Directory	/workspace/66.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.430446236
Short name	T2110
Test name
Test status
Simulation time	85994497 ps
CPU time	6.55 seconds
Started	Jul 24 07:44:10 PM PDT 24
Finished	Jul 24 07:44:16 PM PDT 24
Peak memory	574900 kb
Host	smart-9e7fdb87-0abe-4ba4-b50c-b429d79a86e9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430446236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.430446236
Directory	/workspace/66.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_access_same_device.4086660966
Short name	T2511
Test name
Test status
Simulation time	3922760272 ps
CPU time	170.19 seconds
Started	Jul 24 07:44:10 PM PDT 24
Finished	Jul 24 07:47:00 PM PDT 24
Peak memory	576384 kb
Host	smart-08aedddd-5365-44bb-bb65-af21cffc0732
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086660966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .4086660966
Directory	/workspace/67.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.1355276925
Short name	T596
Test name
Test status
Simulation time	157444356135 ps
CPU time	2666.78 seconds
Started	Jul 24 07:44:10 PM PDT 24
Finished	Jul 24 08:28:37 PM PDT 24
Peak memory	576360 kb
Host	smart-ad87b301-61cc-4021-b867-fbe2a7a535da
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355276925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.1355276925
Directory	/workspace/67.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.4271042246
Short name	T1726
Test name
Test status
Simulation time	785781186 ps
CPU time	31.43 seconds
Started	Jul 24 07:44:25 PM PDT 24
Finished	Jul 24 07:44:57 PM PDT 24
Peak memory	576120 kb
Host	smart-3963c657-ce3d-4758-b9e8-2472d3258b83
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271042246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.4271042246
Directory	/workspace/67.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_error_random.2059591829
Short name	T2660
Test name
Test status
Simulation time	1685236828 ps
CPU time	61.54 seconds
Started	Jul 24 07:44:13 PM PDT 24
Finished	Jul 24 07:45:15 PM PDT 24
Peak memory	576992 kb
Host	smart-11dc675e-59b4-460e-8c2f-7c8964c4689b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059591829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2059591829
Directory	/workspace/67.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_random.2332723721
Short name	T2544
Test name
Test status
Simulation time	412047066 ps
CPU time	15.58 seconds
Started	Jul 24 07:44:12 PM PDT 24
Finished	Jul 24 07:44:28 PM PDT 24
Peak memory	577088 kb
Host	smart-2d2b75a0-7b07-4e5d-b338-86a65c8d0edf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332723721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.2332723721
Directory	/workspace/67.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_random_large_delays.1017858596
Short name	T2874
Test name
Test status
Simulation time	30441939860 ps
CPU time	317.73 seconds
Started	Jul 24 07:44:13 PM PDT 24
Finished	Jul 24 07:49:31 PM PDT 24
Peak memory	576348 kb
Host	smart-0426cfe9-038a-45cb-8ac9-a85b4ae53e4c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017858596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.1017858596
Directory	/workspace/67.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.2847909682
Short name	T2756
Test name
Test status
Simulation time	54423813593 ps
CPU time	944.49 seconds
Started	Jul 24 07:44:14 PM PDT 24
Finished	Jul 24 07:59:59 PM PDT 24
Peak memory	576292 kb
Host	smart-2d521676-cddc-49ab-b473-10fcc82fda7f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847909682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.2847909682
Directory	/workspace/67.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3042657917
Short name	T511
Test name
Test status
Simulation time	213742199 ps
CPU time	20.57 seconds
Started	Jul 24 07:44:15 PM PDT 24
Finished	Jul 24 07:44:36 PM PDT 24
Peak memory	576216 kb
Host	smart-5dea4bac-8801-4102-b3ea-bb068b832f81
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042657917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.3042657917
Directory	/workspace/67.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_same_source.3092755032
Short name	T638
Test name
Test status
Simulation time	2627274405 ps
CPU time	80.38 seconds
Started	Jul 24 07:44:09 PM PDT 24
Finished	Jul 24 07:45:30 PM PDT 24
Peak memory	577108 kb
Host	smart-ae24ee27-28ce-49b6-a0a4-0e5232aa1d12
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092755032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.3092755032
Directory	/workspace/67.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke.1127187204
Short name	T2354
Test name
Test status
Simulation time	257053509 ps
CPU time	10.6 seconds
Started	Jul 24 07:44:09 PM PDT 24
Finished	Jul 24 07:44:20 PM PDT 24
Peak memory	574912 kb
Host	smart-2bfc37ad-712f-49ca-888a-c78404773035
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127187204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.1127187204
Directory	/workspace/67.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.2337905664
Short name	T2095
Test name
Test status
Simulation time	6610159038 ps
CPU time	66.85 seconds
Started	Jul 24 07:44:14 PM PDT 24
Finished	Jul 24 07:45:21 PM PDT 24
Peak memory	575016 kb
Host	smart-aa5f816d-50ab-43df-83d1-ca22b59fc018
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337905664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.2337905664
Directory	/workspace/67.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.567534886
Short name	T2556
Test name
Test status
Simulation time	6672852403 ps
CPU time	115.65 seconds
Started	Jul 24 07:44:12 PM PDT 24
Finished	Jul 24 07:46:08 PM PDT 24
Peak memory	575116 kb
Host	smart-139c00bd-a503-4ea3-b660-1334b86de1a1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567534886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.567534886
Directory	/workspace/67.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1023011409
Short name	T2550
Test name
Test status
Simulation time	45385242 ps
CPU time	6.2 seconds
Started	Jul 24 07:44:14 PM PDT 24
Finished	Jul 24 07:44:20 PM PDT 24
Peak memory	574840 kb
Host	smart-f397743a-ffe0-4d7c-b011-a4f42db84197
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023011409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.1023011409
Directory	/workspace/67.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all.1188698673
Short name	T2346
Test name
Test status
Simulation time	7217045241 ps
CPU time	249.42 seconds
Started	Jul 24 07:44:19 PM PDT 24
Finished	Jul 24 07:48:29 PM PDT 24
Peak memory	576384 kb
Host	smart-e46be736-2519-4103-8a1d-5b08e71bcde5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188698673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1188698673
Directory	/workspace/67.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.724661905
Short name	T925
Test name
Test status
Simulation time	10500409598 ps
CPU time	377.49 seconds
Started	Jul 24 07:44:18 PM PDT 24
Finished	Jul 24 07:50:36 PM PDT 24
Peak memory	577248 kb
Host	smart-945f5cd9-e4ef-4eee-b806-a8301543f082
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724661905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.724661905
Directory	/workspace/67.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1193613635
Short name	T2788
Test name
Test status
Simulation time	3301073831 ps
CPU time	295.54 seconds
Started	Jul 24 07:44:18 PM PDT 24
Finished	Jul 24 07:49:14 PM PDT 24
Peak memory	577288 kb
Host	smart-a62c4533-556f-42e7-b327-392c1fe8d456
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193613635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.1193613635
Directory	/workspace/67.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1058443041
Short name	T953
Test name
Test status
Simulation time	3221029191 ps
CPU time	201.33 seconds
Started	Jul 24 07:44:16 PM PDT 24
Finished	Jul 24 07:47:38 PM PDT 24
Peak memory	577268 kb
Host	smart-f1f31d71-bb43-43ba-a464-aa914355fd56
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058443041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.1058443041
Directory	/workspace/67.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.2380158456
Short name	T1915
Test name
Test status
Simulation time	229250646 ps
CPU time	28.87 seconds
Started	Jul 24 07:44:21 PM PDT 24
Finished	Jul 24 07:44:50 PM PDT 24
Peak memory	577100 kb
Host	smart-55b190fb-e813-418a-a7a9-765ae5f0353d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380158456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.2380158456
Directory	/workspace/67.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_access_same_device.2577314760
Short name	T918
Test name
Test status
Simulation time	1418578100 ps
CPU time	51.65 seconds
Started	Jul 24 07:44:26 PM PDT 24
Finished	Jul 24 07:45:18 PM PDT 24
Peak memory	577024 kb
Host	smart-1eacd07b-2639-4121-bcc1-dad6ac8ec1fa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577314760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .2577314760
Directory	/workspace/68.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1033105831
Short name	T2116
Test name
Test status
Simulation time	20732599934 ps
CPU time	379.83 seconds
Started	Jul 24 07:44:25 PM PDT 24
Finished	Jul 24 07:50:46 PM PDT 24
Peak memory	576280 kb
Host	smart-89b34b13-6dab-40e1-ad0f-a06f64158db7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033105831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.1033105831
Directory	/workspace/68.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.105003432
Short name	T2022
Test name
Test status
Simulation time	358677950 ps
CPU time	33.17 seconds
Started	Jul 24 07:44:26 PM PDT 24
Finished	Jul 24 07:44:59 PM PDT 24
Peak memory	576980 kb
Host	smart-79cd5e7d-9434-4c51-a525-82c2a84fd48e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105003432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr .105003432
Directory	/workspace/68.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_error_random.221639680
Short name	T2385
Test name
Test status
Simulation time	2377926523 ps
CPU time	66.5 seconds
Started	Jul 24 07:44:24 PM PDT 24
Finished	Jul 24 07:45:31 PM PDT 24
Peak memory	576184 kb
Host	smart-c528d0b9-cf50-479f-bee5-36d7255ffcb1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221639680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.221639680
Directory	/workspace/68.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_random.2752432306
Short name	T1669
Test name
Test status
Simulation time	2207552810 ps
CPU time	78.15 seconds
Started	Jul 24 07:44:25 PM PDT 24
Finished	Jul 24 07:45:43 PM PDT 24
Peak memory	577108 kb
Host	smart-40e0764f-c75c-4846-9313-232579b66ff7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752432306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.2752432306
Directory	/workspace/68.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_random_large_delays.4268795251
Short name	T480
Test name
Test status
Simulation time	84763055341 ps
CPU time	895.86 seconds
Started	Jul 24 07:44:26 PM PDT 24
Finished	Jul 24 07:59:22 PM PDT 24
Peak memory	577104 kb
Host	smart-3d401033-efa8-4e38-98cd-3aa2c976fc08
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268795251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.4268795251
Directory	/workspace/68.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.99470492
Short name	T2725
Test name
Test status
Simulation time	51707967130 ps
CPU time	931.48 seconds
Started	Jul 24 07:44:36 PM PDT 24
Finished	Jul 24 08:00:08 PM PDT 24
Peak memory	576280 kb
Host	smart-9fd00bd3-b23f-4191-922b-e229d9051126
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99470492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.99470492
Directory	/workspace/68.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.1004996124
Short name	T2408
Test name
Test status
Simulation time	253583723 ps
CPU time	25.78 seconds
Started	Jul 24 07:44:26 PM PDT 24
Finished	Jul 24 07:44:52 PM PDT 24
Peak memory	576092 kb
Host	smart-b3cb0f21-2a89-4186-a60a-d2b8aec98077
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004996124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.1004996124
Directory	/workspace/68.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_same_source.2267163427
Short name	T1627
Test name
Test status
Simulation time	314824046 ps
CPU time	25.59 seconds
Started	Jul 24 07:44:27 PM PDT 24
Finished	Jul 24 07:44:52 PM PDT 24
Peak memory	576932 kb
Host	smart-b36ae59e-fcd2-4364-98a1-a78239cc928d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267163427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.2267163427
Directory	/workspace/68.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke.3581360043
Short name	T1830
Test name
Test status
Simulation time	41167819 ps
CPU time	6.31 seconds
Started	Jul 24 07:44:20 PM PDT 24
Finished	Jul 24 07:44:26 PM PDT 24
Peak memory	574928 kb
Host	smart-3fcb0a16-851e-4912-b9d6-d158d1bf97b6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581360043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.3581360043
Directory	/workspace/68.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.1182012438
Short name	T551
Test name
Test status
Simulation time	6221916370 ps
CPU time	65.98 seconds
Started	Jul 24 07:44:18 PM PDT 24
Finished	Jul 24 07:45:24 PM PDT 24
Peak memory	575032 kb
Host	smart-bd68bae0-2685-4572-82f2-956716015442
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182012438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.1182012438
Directory	/workspace/68.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3817421603
Short name	T2006
Test name
Test status
Simulation time	4381594903 ps
CPU time	71.63 seconds
Started	Jul 24 07:44:20 PM PDT 24
Finished	Jul 24 07:45:32 PM PDT 24
Peak memory	574960 kb
Host	smart-41078eba-d207-4695-bec7-0c3caa0b211f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817421603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3817421603
Directory	/workspace/68.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.219348441
Short name	T2446
Test name
Test status
Simulation time	40250071 ps
CPU time	5.56 seconds
Started	Jul 24 07:44:20 PM PDT 24
Finished	Jul 24 07:44:26 PM PDT 24
Peak memory	574812 kb
Host	smart-7e9ec4f3-183e-4b50-845c-cd63aff73b89
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219348441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays .219348441
Directory	/workspace/68.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all.409040940
Short name	T2689
Test name
Test status
Simulation time	2883245113 ps
CPU time	232.4 seconds
Started	Jul 24 07:44:37 PM PDT 24
Finished	Jul 24 07:48:29 PM PDT 24
Peak memory	576448 kb
Host	smart-9e72276b-1eb3-419b-a285-c59d9be7392b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409040940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.409040940
Directory	/workspace/68.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.347444693
Short name	T2875
Test name
Test status
Simulation time	15325958224 ps
CPU time	576.41 seconds
Started	Jul 24 07:44:25 PM PDT 24
Finished	Jul 24 07:54:01 PM PDT 24
Peak memory	577220 kb
Host	smart-d28f4414-cb49-4c0d-b92d-1f2d8c07df31
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347444693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.347444693
Directory	/workspace/68.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3782945347
Short name	T2279
Test name
Test status
Simulation time	186787363 ps
CPU time	45.92 seconds
Started	Jul 24 07:44:25 PM PDT 24
Finished	Jul 24 07:45:11 PM PDT 24
Peak memory	576308 kb
Host	smart-b5915f8c-d533-4f03-af57-5aefee86064e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782945347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.3782945347
Directory	/workspace/68.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3013848059
Short name	T2135
Test name
Test status
Simulation time	121239403 ps
CPU time	41.47 seconds
Started	Jul 24 07:44:25 PM PDT 24
Finished	Jul 24 07:45:06 PM PDT 24
Peak memory	577152 kb
Host	smart-a0f69f56-a963-42ed-a412-9c30e1f5b70b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013848059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3013848059
Directory	/workspace/68.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.4140174388
Short name	T1771
Test name
Test status
Simulation time	86450634 ps
CPU time	6.35 seconds
Started	Jul 24 07:44:26 PM PDT 24
Finished	Jul 24 07:44:33 PM PDT 24
Peak memory	575020 kb
Host	smart-fa898fcc-2f1c-4f89-9bd5-d38ae6227fa4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140174388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.4140174388
Directory	/workspace/68.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_access_same_device.1364337315
Short name	T2576
Test name
Test status
Simulation time	1158129797 ps
CPU time	50.85 seconds
Started	Jul 24 07:44:33 PM PDT 24
Finished	Jul 24 07:45:24 PM PDT 24
Peak memory	576936 kb
Host	smart-88b5ce69-6d29-4cd8-ad90-b10fb3eeb83c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364337315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .1364337315
Directory	/workspace/69.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2214098761
Short name	T2261
Test name
Test status
Simulation time	115943693322 ps
CPU time	2123.39 seconds
Started	Jul 24 07:44:33 PM PDT 24
Finished	Jul 24 08:19:57 PM PDT 24
Peak memory	576300 kb
Host	smart-355a2ab8-7bd3-490b-b5aa-c9e4b3b951b1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214098761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.2214098761
Directory	/workspace/69.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3630973449
Short name	T2192
Test name
Test status
Simulation time	285583905 ps
CPU time	29.73 seconds
Started	Jul 24 07:44:36 PM PDT 24
Finished	Jul 24 07:45:06 PM PDT 24
Peak memory	577020 kb
Host	smart-99acd27e-8a5e-4854-bca2-e5114ecd59e8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630973449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.3630973449
Directory	/workspace/69.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_error_random.645732211
Short name	T2748
Test name
Test status
Simulation time	552033237 ps
CPU time	41.33 seconds
Started	Jul 24 07:44:38 PM PDT 24
Finished	Jul 24 07:45:19 PM PDT 24
Peak memory	576964 kb
Host	smart-5509d852-3d90-4711-b595-a82c7f9f1a97
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645732211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.645732211
Directory	/workspace/69.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_random.2929390381
Short name	T678
Test name
Test status
Simulation time	310092572 ps
CPU time	25.27 seconds
Started	Jul 24 07:44:26 PM PDT 24
Finished	Jul 24 07:44:51 PM PDT 24
Peak memory	577000 kb
Host	smart-e1bac13c-22a7-4392-bb87-581372e57067
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929390381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2929390381
Directory	/workspace/69.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_random_large_delays.1980300380
Short name	T1717
Test name
Test status
Simulation time	36714998402 ps
CPU time	383.15 seconds
Started	Jul 24 07:44:32 PM PDT 24
Finished	Jul 24 07:50:56 PM PDT 24
Peak memory	577152 kb
Host	smart-b546eaa0-1915-48ee-b54c-b9daf9f7459d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980300380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.1980300380
Directory	/workspace/69.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.4166844655
Short name	T2230
Test name
Test status
Simulation time	8664173656 ps
CPU time	146.03 seconds
Started	Jul 24 07:44:35 PM PDT 24
Finished	Jul 24 07:47:01 PM PDT 24
Peak memory	577120 kb
Host	smart-653ba637-4ee8-47e8-b122-8a74385f286a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166844655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.4166844655
Directory	/workspace/69.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.1731986032
Short name	T1531
Test name
Test status
Simulation time	126564164 ps
CPU time	14.73 seconds
Started	Jul 24 07:44:25 PM PDT 24
Finished	Jul 24 07:44:40 PM PDT 24
Peak memory	577008 kb
Host	smart-ce3e6dad-73eb-4ac9-aabf-e2793801fd4c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731986032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.1731986032
Directory	/workspace/69.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_same_source.2740015947
Short name	T1486
Test name
Test status
Simulation time	235506109 ps
CPU time	10.18 seconds
Started	Jul 24 07:44:33 PM PDT 24
Finished	Jul 24 07:44:44 PM PDT 24
Peak memory	574792 kb
Host	smart-8b603994-7c79-41c8-a814-83498a4a3927
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740015947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.2740015947
Directory	/workspace/69.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke.3347915096
Short name	T1676
Test name
Test status
Simulation time	165599966 ps
CPU time	8.07 seconds
Started	Jul 24 07:44:36 PM PDT 24
Finished	Jul 24 07:44:44 PM PDT 24
Peak memory	574848 kb
Host	smart-103fb067-4976-4571-a464-fa7b2310523a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347915096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3347915096
Directory	/workspace/69.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.4239503121
Short name	T2129
Test name
Test status
Simulation time	6497361556 ps
CPU time	66.35 seconds
Started	Jul 24 07:44:35 PM PDT 24
Finished	Jul 24 07:45:42 PM PDT 24
Peak memory	575016 kb
Host	smart-15618903-8194-4812-8057-8bf4a34085af
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239503121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.4239503121
Directory	/workspace/69.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3609332159
Short name	T1572
Test name
Test status
Simulation time	5373821847 ps
CPU time	92.11 seconds
Started	Jul 24 07:44:25 PM PDT 24
Finished	Jul 24 07:45:57 PM PDT 24
Peak memory	575032 kb
Host	smart-0539a280-2c89-4b10-9ebb-6755a9af28e9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609332159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.3609332159
Directory	/workspace/69.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.276228401
Short name	T1826
Test name
Test status
Simulation time	49078877 ps
CPU time	6.44 seconds
Started	Jul 24 07:44:25 PM PDT 24
Finished	Jul 24 07:44:32 PM PDT 24
Peak memory	574892 kb
Host	smart-4e4ab11d-715c-41b0-9100-e1581557dd3d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276228401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays .276228401
Directory	/workspace/69.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all.4276737886
Short name	T2406
Test name
Test status
Simulation time	2516915626 ps
CPU time	97.35 seconds
Started	Jul 24 07:44:35 PM PDT 24
Finished	Jul 24 07:46:12 PM PDT 24
Peak memory	577200 kb
Host	smart-326d9dee-398f-4f7f-9a4f-38bd92c2748e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276737886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.4276737886
Directory	/workspace/69.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.881163552
Short name	T932
Test name
Test status
Simulation time	3779818461 ps
CPU time	146.43 seconds
Started	Jul 24 07:44:32 PM PDT 24
Finished	Jul 24 07:46:59 PM PDT 24
Peak memory	577196 kb
Host	smart-ff575f2f-315b-4f7c-a29f-87a8441c4fb9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881163552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.881163552
Directory	/workspace/69.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.150003210
Short name	T1579
Test name
Test status
Simulation time	152830993 ps
CPU time	17.77 seconds
Started	Jul 24 07:44:36 PM PDT 24
Finished	Jul 24 07:44:54 PM PDT 24
Peak memory	576224 kb
Host	smart-a17d72fb-d5e9-4eb2-8cd2-ea4a01d98ae1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150003210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_reset_error.150003210
Directory	/workspace/69.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.1893688325
Short name	T2079
Test name
Test status
Simulation time	659182552 ps
CPU time	29.97 seconds
Started	Jul 24 07:44:35 PM PDT 24
Finished	Jul 24 07:45:05 PM PDT 24
Peak memory	576336 kb
Host	smart-ecf49c2a-263e-4e5f-83e6-42a89f411164
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893688325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.1893688325
Directory	/workspace/69.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.361890632
Short name	T1871
Test name
Test status
Simulation time	6148769964 ps
CPU time	422.32 seconds
Started	Jul 24 07:33:59 PM PDT 24
Finished	Jul 24 07:41:01 PM PDT 24
Peak memory	641728 kb
Host	smart-54b630b9-ef2e-4ff6-9582-8da9f4cf56f7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361890632 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.361890632
Directory	/workspace/7.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/7.chip_csr_rw.1899526806
Short name	T1672
Test name
Test status
Simulation time	4299028725 ps
CPU time	300.19 seconds
Started	Jul 24 07:34:03 PM PDT 24
Finished	Jul 24 07:39:03 PM PDT 24
Peak memory	598600 kb
Host	smart-83d475db-0c83-4321-8461-89db6c00f218
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899526806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.1899526806
Directory	/workspace/7.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.1903270306
Short name	T1581
Test name
Test status
Simulation time	29381486498 ps
CPU time	3930.54 seconds
Started	Jul 24 07:33:55 PM PDT 24
Finished	Jul 24 08:39:26 PM PDT 24
Peak memory	593992 kb
Host	smart-73a0a10f-e55e-4d1d-83f4-5439c73151a3
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903270306 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.1903270306
Directory	/workspace/7.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/7.chip_tl_errors.1549713849
Short name	T796
Test name
Test status
Simulation time	3955687296 ps
CPU time	301.96 seconds
Started	Jul 24 07:33:58 PM PDT 24
Finished	Jul 24 07:39:00 PM PDT 24
Peak memory	600896 kb
Host	smart-d9a78ed2-f10a-4105-b75f-143607b15278
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549713849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.1549713849
Directory	/workspace/7.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_access_same_device.162932582
Short name	T2382
Test name
Test status
Simulation time	1715995277 ps
CPU time	74 seconds
Started	Jul 24 07:33:46 PM PDT 24
Finished	Jul 24 07:35:00 PM PDT 24
Peak memory	576140 kb
Host	smart-e1f26f86-b75c-4900-9dfc-c3044c41dd02
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162932582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.162932582
Directory	/workspace/7.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2116613326
Short name	T1934
Test name
Test status
Simulation time	47859201422 ps
CPU time	826.86 seconds
Started	Jul 24 07:33:46 PM PDT 24
Finished	Jul 24 07:47:33 PM PDT 24
Peak memory	576280 kb
Host	smart-448755e4-9b28-413f-af9a-cff5edec7307
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116613326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.2116613326
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.816953542
Short name	T2593
Test name
Test status
Simulation time	1337664689 ps
CPU time	54.76 seconds
Started	Jul 24 07:33:46 PM PDT 24
Finished	Jul 24 07:34:41 PM PDT 24
Peak memory	576916 kb
Host	smart-c2f6c634-3bd2-42fb-b485-b26c11268300
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816953542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr. 816953542
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_error_random.3983038346
Short name	T1770
Test name
Test status
Simulation time	272251630 ps
CPU time	11.36 seconds
Started	Jul 24 07:34:05 PM PDT 24
Finished	Jul 24 07:34:17 PM PDT 24
Peak memory	576984 kb
Host	smart-31cbff8d-d93f-4c19-8393-47ea938434c3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983038346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3983038346
Directory	/workspace/7.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_random.2270622182
Short name	T1651
Test name
Test status
Simulation time	261149436 ps
CPU time	10.95 seconds
Started	Jul 24 07:33:55 PM PDT 24
Finished	Jul 24 07:34:06 PM PDT 24
Peak memory	576144 kb
Host	smart-5b1c1abc-2b78-4648-ba4d-9b187be5d057
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270622182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.2270622182
Directory	/workspace/7.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_random_large_delays.4078698219
Short name	T2610
Test name
Test status
Simulation time	95280674503 ps
CPU time	929.6 seconds
Started	Jul 24 07:33:54 PM PDT 24
Finished	Jul 24 07:49:24 PM PDT 24
Peak memory	576268 kb
Host	smart-d22816a3-4473-4360-8b6a-1c9a8d9f981b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078698219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.4078698219
Directory	/workspace/7.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1926511733
Short name	T2523
Test name
Test status
Simulation time	50868791382 ps
CPU time	810.74 seconds
Started	Jul 24 07:33:52 PM PDT 24
Finished	Jul 24 07:47:23 PM PDT 24
Peak memory	576292 kb
Host	smart-7408aeb2-cc72-4927-9aa7-e1c5a1085855
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926511733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1926511733
Directory	/workspace/7.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3372171415
Short name	T1641
Test name
Test status
Simulation time	61090400 ps
CPU time	8.37 seconds
Started	Jul 24 07:33:57 PM PDT 24
Finished	Jul 24 07:34:06 PM PDT 24
Peak memory	574956 kb
Host	smart-77e471fc-386b-4a3c-8aca-620408568e21
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372171415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.3372171415
Directory	/workspace/7.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_same_source.2765295475
Short name	T506
Test name
Test status
Simulation time	1942152419 ps
CPU time	57.47 seconds
Started	Jul 24 07:34:05 PM PDT 24
Finished	Jul 24 07:35:03 PM PDT 24
Peak memory	576160 kb
Host	smart-1916617f-584a-4fdd-a377-a9bc3b5902a9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765295475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2765295475
Directory	/workspace/7.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke.45296022
Short name	T799
Test name
Test status
Simulation time	47690604 ps
CPU time	6.22 seconds
Started	Jul 24 07:33:56 PM PDT 24
Finished	Jul 24 07:34:02 PM PDT 24
Peak memory	574940 kb
Host	smart-f21ce3c4-1b95-48d0-9443-2c884d5e62ac
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45296022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.45296022
Directory	/workspace/7.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.284329615
Short name	T2696
Test name
Test status
Simulation time	8306603305 ps
CPU time	84.61 seconds
Started	Jul 24 07:33:58 PM PDT 24
Finished	Jul 24 07:35:23 PM PDT 24
Peak memory	575104 kb
Host	smart-1f20973f-a8c0-4a6d-8b67-f2b13645d598
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284329615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.284329615
Directory	/workspace/7.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.2702526942
Short name	T643
Test name
Test status
Simulation time	4996831911 ps
CPU time	86.79 seconds
Started	Jul 24 07:33:36 PM PDT 24
Finished	Jul 24 07:35:03 PM PDT 24
Peak memory	576280 kb
Host	smart-79683a64-1cf4-4d9f-9857-3c495ba6034e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702526942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2702526942
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.809738771
Short name	T2600
Test name
Test status
Simulation time	53478724 ps
CPU time	6.19 seconds
Started	Jul 24 07:33:41 PM PDT 24
Finished	Jul 24 07:33:47 PM PDT 24
Peak memory	574900 kb
Host	smart-8461c0c9-665f-45c7-af1a-c27b656734e4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809738771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays. 809738771
Directory	/workspace/7.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all.3128241124
Short name	T2265
Test name
Test status
Simulation time	1395905008 ps
CPU time	107.07 seconds
Started	Jul 24 07:33:48 PM PDT 24
Finished	Jul 24 07:35:35 PM PDT 24
Peak memory	576320 kb
Host	smart-6552fb71-0105-4faa-8009-ca98888d57c5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128241124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3128241124
Directory	/workspace/7.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.3766574211
Short name	T942
Test name
Test status
Simulation time	13542914394 ps
CPU time	494.29 seconds
Started	Jul 24 07:33:51 PM PDT 24
Finished	Jul 24 07:42:05 PM PDT 24
Peak memory	577236 kb
Host	smart-f581a1d9-b607-4ec9-985d-4e3d8786a8ae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766574211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3766574211
Directory	/workspace/7.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.896690957
Short name	T518
Test name
Test status
Simulation time	9001933886 ps
CPU time	553.25 seconds
Started	Jul 24 07:33:47 PM PDT 24
Finished	Jul 24 07:43:01 PM PDT 24
Peak memory	577360 kb
Host	smart-9250318c-a8e3-4949-b47d-485017456a39
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896690957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_w ith_rand_reset.896690957
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.4055956793
Short name	T752
Test name
Test status
Simulation time	3280383965 ps
CPU time	365.41 seconds
Started	Jul 24 07:34:01 PM PDT 24
Finished	Jul 24 07:40:07 PM PDT 24
Peak memory	576440 kb
Host	smart-2853abca-4270-4bf2-8202-67d2d75f5807
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055956793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.4055956793
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.753977776
Short name	T2729
Test name
Test status
Simulation time	204337288 ps
CPU time	24.38 seconds
Started	Jul 24 07:34:03 PM PDT 24
Finished	Jul 24 07:34:27 PM PDT 24
Peak memory	576220 kb
Host	smart-bf3ffa0f-a26a-4762-8ddd-13013c18bf79
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753977776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.753977776
Directory	/workspace/7.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_access_same_device.187051503
Short name	T1728
Test name
Test status
Simulation time	203894956 ps
CPU time	18.24 seconds
Started	Jul 24 07:44:42 PM PDT 24
Finished	Jul 24 07:45:01 PM PDT 24
Peak memory	576160 kb
Host	smart-5fc2af74-b85a-4506-90f9-2def8d2c6e5f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187051503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device. 187051503
Directory	/workspace/70.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3478032812
Short name	T2832
Test name
Test status
Simulation time	100581389348 ps
CPU time	1860.7 seconds
Started	Jul 24 07:44:46 PM PDT 24
Finished	Jul 24 08:15:47 PM PDT 24
Peak memory	576364 kb
Host	smart-99c21fc4-b5ab-4077-9b87-5c367dae36de
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478032812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.3478032812
Directory	/workspace/70.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2036690284
Short name	T2813
Test name
Test status
Simulation time	75058229 ps
CPU time	10.9 seconds
Started	Jul 24 07:44:42 PM PDT 24
Finished	Jul 24 07:44:53 PM PDT 24
Peak memory	576952 kb
Host	smart-f8993faf-ac93-4cf7-8bd8-f68694bfa265
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036690284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.2036690284
Directory	/workspace/70.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_error_random.2707345508
Short name	T2360
Test name
Test status
Simulation time	349503315 ps
CPU time	30.08 seconds
Started	Jul 24 07:44:44 PM PDT 24
Finished	Jul 24 07:45:14 PM PDT 24
Peak memory	576904 kb
Host	smart-a9d5d112-3fae-4837-8fb4-c1ad70fddb97
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707345508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2707345508
Directory	/workspace/70.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_random.4097366263
Short name	T2140
Test name
Test status
Simulation time	498594947 ps
CPU time	19.66 seconds
Started	Jul 24 07:44:32 PM PDT 24
Finished	Jul 24 07:44:52 PM PDT 24
Peak memory	577036 kb
Host	smart-73e2380b-2639-4c87-8978-fc445bfc26c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097366263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.4097366263
Directory	/workspace/70.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_random_large_delays.4160477757
Short name	T1729
Test name
Test status
Simulation time	57910091455 ps
CPU time	647.31 seconds
Started	Jul 24 07:44:43 PM PDT 24
Finished	Jul 24 07:55:31 PM PDT 24
Peak memory	576324 kb
Host	smart-61479578-1572-4e97-b39e-4872fcb67a84
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160477757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.4160477757
Directory	/workspace/70.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.3459679660
Short name	T1522
Test name
Test status
Simulation time	1684369911 ps
CPU time	30.02 seconds
Started	Jul 24 07:44:45 PM PDT 24
Finished	Jul 24 07:45:16 PM PDT 24
Peak memory	574960 kb
Host	smart-aa912656-6f6c-47a4-8902-09d5bfd73872
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459679660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.3459679660
Directory	/workspace/70.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.3043478975
Short name	T2142
Test name
Test status
Simulation time	63905032 ps
CPU time	7.84 seconds
Started	Jul 24 07:44:46 PM PDT 24
Finished	Jul 24 07:44:54 PM PDT 24
Peak memory	574964 kb
Host	smart-4dad2c15-b3d1-46b7-aff8-9b1348741ce5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043478975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.3043478975
Directory	/workspace/70.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_same_source.1442066311
Short name	T2372
Test name
Test status
Simulation time	1357079406 ps
CPU time	39.13 seconds
Started	Jul 24 07:44:45 PM PDT 24
Finished	Jul 24 07:45:24 PM PDT 24
Peak memory	576284 kb
Host	smart-e8ef263e-4985-4a70-b428-109773b7a48f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442066311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.1442066311
Directory	/workspace/70.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke.620383462
Short name	T2917
Test name
Test status
Simulation time	52156392 ps
CPU time	6.94 seconds
Started	Jul 24 07:44:34 PM PDT 24
Finished	Jul 24 07:44:41 PM PDT 24
Peak memory	574944 kb
Host	smart-a2eda552-0082-4028-ad11-4a9ab0c81c09
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620383462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.620383462
Directory	/workspace/70.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.2190928138
Short name	T1736
Test name
Test status
Simulation time	5019762147 ps
CPU time	51.96 seconds
Started	Jul 24 07:44:35 PM PDT 24
Finished	Jul 24 07:45:27 PM PDT 24
Peak memory	574976 kb
Host	smart-976fa55e-7413-411e-8e2c-74c90fcf2a16
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190928138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.2190928138
Directory	/workspace/70.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1756870577
Short name	T2816
Test name
Test status
Simulation time	4979751591 ps
CPU time	87.8 seconds
Started	Jul 24 07:44:33 PM PDT 24
Finished	Jul 24 07:46:01 PM PDT 24
Peak memory	574988 kb
Host	smart-661524b6-16d0-46be-ac71-07e2cc76a618
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756870577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.1756870577
Directory	/workspace/70.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.542285668
Short name	T1890
Test name
Test status
Simulation time	46779862 ps
CPU time	6.63 seconds
Started	Jul 24 07:44:32 PM PDT 24
Finished	Jul 24 07:44:39 PM PDT 24
Peak memory	574844 kb
Host	smart-7cfcd0ac-02aa-47f0-a2c6-a3ddad0d8aac
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542285668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays .542285668
Directory	/workspace/70.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all.1446328602
Short name	T2828
Test name
Test status
Simulation time	6450924351 ps
CPU time	213.87 seconds
Started	Jul 24 07:44:45 PM PDT 24
Finished	Jul 24 07:48:19 PM PDT 24
Peak memory	576484 kb
Host	smart-6d7b0feb-9a5a-4b62-b587-f27dc2fdbc14
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446328602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.1446328602
Directory	/workspace/70.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.638968726
Short name	T2648
Test name
Test status
Simulation time	113834248 ps
CPU time	13.79 seconds
Started	Jul 24 07:44:43 PM PDT 24
Finished	Jul 24 07:44:57 PM PDT 24
Peak memory	577008 kb
Host	smart-324d242b-c368-47a5-9c36-5dac1b457285
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638968726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.638968726
Directory	/workspace/70.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.970125537
Short name	T2195
Test name
Test status
Simulation time	8411492134 ps
CPU time	517.89 seconds
Started	Jul 24 07:44:43 PM PDT 24
Finished	Jul 24 07:53:21 PM PDT 24
Peak memory	577292 kb
Host	smart-a1360038-4e97-4c9d-b656-eaf86475bd81
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970125537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_ with_rand_reset.970125537
Directory	/workspace/70.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3568814010
Short name	T2577
Test name
Test status
Simulation time	11830930892 ps
CPU time	647.61 seconds
Started	Jul 24 07:44:51 PM PDT 24
Finished	Jul 24 07:55:39 PM PDT 24
Peak memory	577264 kb
Host	smart-b0610177-8646-4c50-b577-324aca485ef2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568814010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.3568814010
Directory	/workspace/70.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2941491508
Short name	T1517
Test name
Test status
Simulation time	288240218 ps
CPU time	12.77 seconds
Started	Jul 24 07:44:40 PM PDT 24
Finished	Jul 24 07:44:53 PM PDT 24
Peak memory	577100 kb
Host	smart-6565bcd3-2530-4dd5-930c-668a5a4cd396
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941491508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2941491508
Directory	/workspace/70.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_access_same_device.2033298791
Short name	T1679
Test name
Test status
Simulation time	2397880851 ps
CPU time	96.17 seconds
Started	Jul 24 07:44:49 PM PDT 24
Finished	Jul 24 07:46:25 PM PDT 24
Peak memory	577092 kb
Host	smart-c0dfd26e-c761-4926-b7f9-a524d37d67ec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033298791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .2033298791
Directory	/workspace/71.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2942973417
Short name	T1896
Test name
Test status
Simulation time	3084761814 ps
CPU time	55.99 seconds
Started	Jul 24 07:44:51 PM PDT 24
Finished	Jul 24 07:45:47 PM PDT 24
Peak memory	574960 kb
Host	smart-46cc534a-f9e5-459f-bc10-4b341a8967b2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942973417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.2942973417
Directory	/workspace/71.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.1230765204
Short name	T2347
Test name
Test status
Simulation time	542797650 ps
CPU time	23.4 seconds
Started	Jul 24 07:44:50 PM PDT 24
Finished	Jul 24 07:45:14 PM PDT 24
Peak memory	575892 kb
Host	smart-e21e8f1b-7c45-4a31-ac28-b18fdc6a02ab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230765204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.1230765204
Directory	/workspace/71.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_error_random.2029347872
Short name	T1482
Test name
Test status
Simulation time	1439018841 ps
CPU time	49.12 seconds
Started	Jul 24 07:44:49 PM PDT 24
Finished	Jul 24 07:45:38 PM PDT 24
Peak memory	577080 kb
Host	smart-5cdace94-182f-407d-a625-3a3aa5845346
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029347872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.2029347872
Directory	/workspace/71.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_random.1758417024
Short name	T517
Test name
Test status
Simulation time	2354732396 ps
CPU time	92.66 seconds
Started	Jul 24 07:44:49 PM PDT 24
Finished	Jul 24 07:46:22 PM PDT 24
Peak memory	577132 kb
Host	smart-58d6f695-6391-44e3-b9fe-d8e7bfeb1152
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758417024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1758417024
Directory	/workspace/71.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_random_large_delays.3920174291
Short name	T2428
Test name
Test status
Simulation time	93627411255 ps
CPU time	1059.36 seconds
Started	Jul 24 07:44:49 PM PDT 24
Finished	Jul 24 08:02:29 PM PDT 24
Peak memory	576428 kb
Host	smart-bc9f75fd-4096-4c3e-b690-6f84266d8e52
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920174291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.3920174291
Directory	/workspace/71.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.3132468970
Short name	T2717
Test name
Test status
Simulation time	51089553584 ps
CPU time	877.32 seconds
Started	Jul 24 07:44:53 PM PDT 24
Finished	Jul 24 07:59:30 PM PDT 24
Peak memory	576344 kb
Host	smart-79ffd175-09cd-40fb-87e7-24d357d472d1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132468970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.3132468970
Directory	/workspace/71.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.1317079472
Short name	T1764
Test name
Test status
Simulation time	537951322 ps
CPU time	46.39 seconds
Started	Jul 24 07:44:51 PM PDT 24
Finished	Jul 24 07:45:38 PM PDT 24
Peak memory	577004 kb
Host	smart-a8e55da7-5699-4b25-94cf-792199f93dda
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317079472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.1317079472
Directory	/workspace/71.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_same_source.1940318383
Short name	T552
Test name
Test status
Simulation time	160527011 ps
CPU time	14.04 seconds
Started	Jul 24 07:44:50 PM PDT 24
Finished	Jul 24 07:45:04 PM PDT 24
Peak memory	576304 kb
Host	smart-2c9c69e8-82c7-46cc-8c3d-88d603663923
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940318383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.1940318383
Directory	/workspace/71.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke.519851834
Short name	T2138
Test name
Test status
Simulation time	214685500 ps
CPU time	10.03 seconds
Started	Jul 24 07:44:50 PM PDT 24
Finished	Jul 24 07:45:00 PM PDT 24
Peak memory	576164 kb
Host	smart-fcd58b9f-3447-4a3f-ab0a-6d30365e27ae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519851834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.519851834
Directory	/workspace/71.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.1911010133
Short name	T2539
Test name
Test status
Simulation time	9726726143 ps
CPU time	102.56 seconds
Started	Jul 24 07:44:51 PM PDT 24
Finished	Jul 24 07:46:34 PM PDT 24
Peak memory	574984 kb
Host	smart-75580649-cb7a-4b5f-a302-6c965957ccd0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911010133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.1911010133
Directory	/workspace/71.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.149798482
Short name	T2580
Test name
Test status
Simulation time	3435296774 ps
CPU time	60.51 seconds
Started	Jul 24 07:44:51 PM PDT 24
Finished	Jul 24 07:45:52 PM PDT 24
Peak memory	575060 kb
Host	smart-0d07bc2f-efcd-4b2d-92c6-bfff1675847d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149798482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.149798482
Directory	/workspace/71.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3905595937
Short name	T2797
Test name
Test status
Simulation time	48424559 ps
CPU time	6.52 seconds
Started	Jul 24 07:44:50 PM PDT 24
Finished	Jul 24 07:44:57 PM PDT 24
Peak memory	574860 kb
Host	smart-380e7432-f938-411d-bf9b-54ae592edbde
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905595937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.3905595937
Directory	/workspace/71.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all.451802270
Short name	T2608
Test name
Test status
Simulation time	669826622 ps
CPU time	49.92 seconds
Started	Jul 24 07:44:50 PM PDT 24
Finished	Jul 24 07:45:40 PM PDT 24
Peak memory	576304 kb
Host	smart-4dd962fd-e13d-4853-a889-f174fa8cd84b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451802270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.451802270
Directory	/workspace/71.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.2109197427
Short name	T2661
Test name
Test status
Simulation time	828167205 ps
CPU time	65.58 seconds
Started	Jul 24 07:45:00 PM PDT 24
Finished	Jul 24 07:46:05 PM PDT 24
Peak memory	577044 kb
Host	smart-8ca97f8a-d858-4ca9-9598-367997cd52bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109197427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.2109197427
Directory	/workspace/71.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1937848333
Short name	T2334
Test name
Test status
Simulation time	298910950 ps
CPU time	175.74 seconds
Started	Jul 24 07:44:58 PM PDT 24
Finished	Jul 24 07:47:54 PM PDT 24
Peak memory	576328 kb
Host	smart-6f7878e1-cebf-423b-a643-3cb934d64e93
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937848333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.1937848333
Directory	/workspace/71.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.158871384
Short name	T711
Test name
Test status
Simulation time	551755363 ps
CPU time	188.84 seconds
Started	Jul 24 07:44:59 PM PDT 24
Finished	Jul 24 07:48:08 PM PDT 24
Peak memory	576320 kb
Host	smart-df0ba928-d56d-4f0a-9248-1e54c2fd341d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158871384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_reset_error.158871384
Directory	/workspace/71.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.1622834816
Short name	T2387
Test name
Test status
Simulation time	1447183271 ps
CPU time	59.55 seconds
Started	Jul 24 07:44:53 PM PDT 24
Finished	Jul 24 07:45:52 PM PDT 24
Peak memory	576196 kb
Host	smart-110a71d7-0175-4b82-9909-70d1967e900a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622834816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.1622834816
Directory	/workspace/71.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_access_same_device.2357854752
Short name	T1977
Test name
Test status
Simulation time	623481866 ps
CPU time	66.42 seconds
Started	Jul 24 07:44:59 PM PDT 24
Finished	Jul 24 07:46:05 PM PDT 24
Peak memory	576220 kb
Host	smart-654d5e85-949f-4963-81cc-4a2199fb019f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357854752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .2357854752
Directory	/workspace/72.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1706286958
Short name	T2691
Test name
Test status
Simulation time	61490413878 ps
CPU time	1186.11 seconds
Started	Jul 24 07:44:58 PM PDT 24
Finished	Jul 24 08:04:45 PM PDT 24
Peak memory	576308 kb
Host	smart-2e01db88-5c64-4aef-8811-6384addbad85
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706286958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.1706286958
Directory	/workspace/72.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3570736453
Short name	T2509
Test name
Test status
Simulation time	182384406 ps
CPU time	10.56 seconds
Started	Jul 24 07:45:01 PM PDT 24
Finished	Jul 24 07:45:11 PM PDT 24
Peak memory	574952 kb
Host	smart-9a2ab34c-21fc-409e-9f70-0059f531dfd2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570736453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.3570736453
Directory	/workspace/72.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_error_random.3554660072
Short name	T1899
Test name
Test status
Simulation time	414338468 ps
CPU time	34.55 seconds
Started	Jul 24 07:45:02 PM PDT 24
Finished	Jul 24 07:45:37 PM PDT 24
Peak memory	576908 kb
Host	smart-6c62028d-d878-4b70-9469-451eb3ac0fe2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554660072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.3554660072
Directory	/workspace/72.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_random.228604463
Short name	T2522
Test name
Test status
Simulation time	2302483800 ps
CPU time	87.86 seconds
Started	Jul 24 07:45:01 PM PDT 24
Finished	Jul 24 07:46:29 PM PDT 24
Peak memory	576308 kb
Host	smart-d0caf387-5e22-4633-aa20-f000e6338efb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228604463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.228604463
Directory	/workspace/72.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_random_large_delays.2035910633
Short name	T1603
Test name
Test status
Simulation time	5093708764 ps
CPU time	54.34 seconds
Started	Jul 24 07:45:01 PM PDT 24
Finished	Jul 24 07:45:55 PM PDT 24
Peak memory	575064 kb
Host	smart-a3d2a077-5af3-4342-a81a-acbdd2a382a4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035910633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.2035910633
Directory	/workspace/72.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.1005377659
Short name	T459
Test name
Test status
Simulation time	67381196416 ps
CPU time	1229.46 seconds
Started	Jul 24 07:44:59 PM PDT 24
Finished	Jul 24 08:05:28 PM PDT 24
Peak memory	577136 kb
Host	smart-1fa5a599-6fce-4266-a3a5-a689bd86b905
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005377659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.1005377659
Directory	/workspace/72.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1473156562
Short name	T1847
Test name
Test status
Simulation time	123547131 ps
CPU time	12.13 seconds
Started	Jul 24 07:44:59 PM PDT 24
Finished	Jul 24 07:45:12 PM PDT 24
Peak memory	577008 kb
Host	smart-2d3f9ece-e99f-41e4-95c5-7163b1166d7b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473156562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.1473156562
Directory	/workspace/72.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_same_source.2056968979
Short name	T734
Test name
Test status
Simulation time	2294115472 ps
CPU time	71.78 seconds
Started	Jul 24 07:45:01 PM PDT 24
Finished	Jul 24 07:46:13 PM PDT 24
Peak memory	577192 kb
Host	smart-e16b03bf-800d-4ebf-84ab-0b753844b74a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056968979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.2056968979
Directory	/workspace/72.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke.1700171268
Short name	T1837
Test name
Test status
Simulation time	162461625 ps
CPU time	7.68 seconds
Started	Jul 24 07:44:59 PM PDT 24
Finished	Jul 24 07:45:06 PM PDT 24
Peak memory	574932 kb
Host	smart-d067899c-62fc-42a3-bbf9-15088f74fba0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700171268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1700171268
Directory	/workspace/72.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.1224341516
Short name	T1839
Test name
Test status
Simulation time	8162993316 ps
CPU time	83.63 seconds
Started	Jul 24 07:45:04 PM PDT 24
Finished	Jul 24 07:46:28 PM PDT 24
Peak memory	574948 kb
Host	smart-c36129a9-cc58-44a4-bb70-8144d0a0c0b6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224341516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.1224341516
Directory	/workspace/72.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1044514998
Short name	T1670
Test name
Test status
Simulation time	5857193337 ps
CPU time	95.15 seconds
Started	Jul 24 07:44:58 PM PDT 24
Finished	Jul 24 07:46:33 PM PDT 24
Peak memory	576284 kb
Host	smart-0301bd31-7285-4538-809e-0d98b3d8745a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044514998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.1044514998
Directory	/workspace/72.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1321640060
Short name	T1577
Test name
Test status
Simulation time	42532056 ps
CPU time	6.23 seconds
Started	Jul 24 07:44:57 PM PDT 24
Finished	Jul 24 07:45:04 PM PDT 24
Peak memory	574956 kb
Host	smart-a3a3f566-554e-4e31-90ff-825747545160
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321640060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.1321640060
Directory	/workspace/72.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all.1528311256
Short name	T529
Test name
Test status
Simulation time	2332141562 ps
CPU time	195.6 seconds
Started	Jul 24 07:45:01 PM PDT 24
Finished	Jul 24 07:48:17 PM PDT 24
Peak memory	576400 kb
Host	smart-d7d82d9b-c9db-46fc-91cd-b83998478c55
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528311256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.1528311256
Directory	/workspace/72.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3638934857
Short name	T802
Test name
Test status
Simulation time	10644737923 ps
CPU time	357.7 seconds
Started	Jul 24 07:45:04 PM PDT 24
Finished	Jul 24 07:51:02 PM PDT 24
Peak memory	577136 kb
Host	smart-c8debc9b-7cb1-4cef-83c8-e8c12c77ba06
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638934857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3638934857
Directory	/workspace/72.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2145916906
Short name	T1471
Test name
Test status
Simulation time	8240029 ps
CPU time	14.87 seconds
Started	Jul 24 07:45:00 PM PDT 24
Finished	Jul 24 07:45:15 PM PDT 24
Peak memory	576908 kb
Host	smart-8ba37729-62c9-4b0d-8239-e9f6337a82bc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145916906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.2145916906
Directory	/workspace/72.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1514431026
Short name	T2208
Test name
Test status
Simulation time	129451096 ps
CPU time	43.26 seconds
Started	Jul 24 07:44:59 PM PDT 24
Finished	Jul 24 07:45:43 PM PDT 24
Peak memory	576356 kb
Host	smart-189e84c6-7626-4d88-aba9-cfd28c2997a2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514431026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.1514431026
Directory	/workspace/72.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.781605033
Short name	T2280
Test name
Test status
Simulation time	1243091410 ps
CPU time	50.3 seconds
Started	Jul 24 07:45:01 PM PDT 24
Finished	Jul 24 07:45:51 PM PDT 24
Peak memory	577132 kb
Host	smart-13e92afa-42a0-4a9c-81b1-eab5947a718a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781605033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.781605033
Directory	/workspace/72.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_access_same_device.3898573337
Short name	T2845
Test name
Test status
Simulation time	579040349 ps
CPU time	45.95 seconds
Started	Jul 24 07:45:06 PM PDT 24
Finished	Jul 24 07:45:52 PM PDT 24
Peak memory	576152 kb
Host	smart-2b6fad33-7436-4edf-8c9b-10c3920b846e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898573337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .3898573337
Directory	/workspace/73.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.673463613
Short name	T2623
Test name
Test status
Simulation time	142493619626 ps
CPU time	2638.05 seconds
Started	Jul 24 07:45:07 PM PDT 24
Finished	Jul 24 08:29:05 PM PDT 24
Peak memory	577156 kb
Host	smart-a891e8ad-8333-4d09-9288-19793cb06c3d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673463613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_d evice_slow_rsp.673463613
Directory	/workspace/73.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.496150709
Short name	T2638
Test name
Test status
Simulation time	58192729 ps
CPU time	8.69 seconds
Started	Jul 24 07:45:14 PM PDT 24
Finished	Jul 24 07:45:23 PM PDT 24
Peak memory	576972 kb
Host	smart-651f2db6-e5f6-4631-a7eb-d1c3d8ddbe7b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496150709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr .496150709
Directory	/workspace/73.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_error_random.3182860645
Short name	T2450
Test name
Test status
Simulation time	182041268 ps
CPU time	15.97 seconds
Started	Jul 24 07:45:19 PM PDT 24
Finished	Jul 24 07:45:35 PM PDT 24
Peak memory	576984 kb
Host	smart-70057716-4dbc-4b54-9e81-b56c16a7156f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182860645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.3182860645
Directory	/workspace/73.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_random.994551435
Short name	T2606
Test name
Test status
Simulation time	1018800048 ps
CPU time	38.17 seconds
Started	Jul 24 07:45:05 PM PDT 24
Finished	Jul 24 07:45:43 PM PDT 24
Peak memory	577012 kb
Host	smart-2fff5085-73c2-435f-be77-844f3107215b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994551435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.994551435
Directory	/workspace/73.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_random_large_delays.3181787787
Short name	T1462
Test name
Test status
Simulation time	10451929041 ps
CPU time	108.02 seconds
Started	Jul 24 07:45:06 PM PDT 24
Finished	Jul 24 07:46:54 PM PDT 24
Peak memory	575104 kb
Host	smart-1619c635-8587-4be5-a3ca-c11da02924d7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181787787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.3181787787
Directory	/workspace/73.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.869281191
Short name	T2778
Test name
Test status
Simulation time	18595750673 ps
CPU time	320.88 seconds
Started	Jul 24 07:45:08 PM PDT 24
Finished	Jul 24 07:50:29 PM PDT 24
Peak memory	577216 kb
Host	smart-69d6651d-a674-4b19-9f4c-91d683840a79
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869281191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.869281191
Directory	/workspace/73.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.251754435
Short name	T583
Test name
Test status
Simulation time	513011203 ps
CPU time	43.03 seconds
Started	Jul 24 07:45:09 PM PDT 24
Finished	Jul 24 07:45:52 PM PDT 24
Peak memory	576224 kb
Host	smart-e2a7e661-ae92-49a3-a0b5-37d2da28f851
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251754435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_dela ys.251754435
Directory	/workspace/73.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_same_source.2998807828
Short name	T1961
Test name
Test status
Simulation time	778978781 ps
CPU time	24.65 seconds
Started	Jul 24 07:45:09 PM PDT 24
Finished	Jul 24 07:45:33 PM PDT 24
Peak memory	576252 kb
Host	smart-0d0c3338-04ca-4b37-9b41-a873f4d04de2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998807828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2998807828
Directory	/workspace/73.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke.1967667685
Short name	T2240
Test name
Test status
Simulation time	164513198 ps
CPU time	8.34 seconds
Started	Jul 24 07:44:59 PM PDT 24
Finished	Jul 24 07:45:07 PM PDT 24
Peak memory	574928 kb
Host	smart-f8205efd-e95d-4226-a6e3-9624e7d51f16
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967667685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.1967667685
Directory	/workspace/73.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.3911561808
Short name	T2818
Test name
Test status
Simulation time	8171433134 ps
CPU time	90.11 seconds
Started	Jul 24 07:45:07 PM PDT 24
Finished	Jul 24 07:46:37 PM PDT 24
Peak memory	574928 kb
Host	smart-25b9ee56-eac0-452a-8bf2-e43fd4fb5623
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911561808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.3911561808
Directory	/workspace/73.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.3785980974
Short name	T1449
Test name
Test status
Simulation time	4464291529 ps
CPU time	74.09 seconds
Started	Jul 24 07:45:06 PM PDT 24
Finished	Jul 24 07:46:20 PM PDT 24
Peak memory	576228 kb
Host	smart-a1a93d52-c578-4404-a1ae-5799d92ff65c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785980974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.3785980974
Directory	/workspace/73.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1636506693
Short name	T2314
Test name
Test status
Simulation time	46015780 ps
CPU time	6.51 seconds
Started	Jul 24 07:45:07 PM PDT 24
Finished	Jul 24 07:45:14 PM PDT 24
Peak memory	574936 kb
Host	smart-5fa8eaaa-f200-4edb-babb-5a74902810c8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636506693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.1636506693
Directory	/workspace/73.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all.2772528814
Short name	T2209
Test name
Test status
Simulation time	8617409233 ps
CPU time	282.48 seconds
Started	Jul 24 07:45:20 PM PDT 24
Finished	Jul 24 07:50:03 PM PDT 24
Peak memory	576420 kb
Host	smart-0482b2e5-91ea-43af-9170-b3a9fc04f0f5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772528814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.2772528814
Directory	/workspace/73.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.358568400
Short name	T2267
Test name
Test status
Simulation time	2569280023 ps
CPU time	79.8 seconds
Started	Jul 24 07:45:17 PM PDT 24
Finished	Jul 24 07:46:37 PM PDT 24
Peak memory	577160 kb
Host	smart-fcc4d898-894f-4ba3-83a1-ece41d972ecf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358568400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.358568400
Directory	/workspace/73.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.767229908
Short name	T665
Test name
Test status
Simulation time	226465761 ps
CPU time	59.91 seconds
Started	Jul 24 07:45:21 PM PDT 24
Finished	Jul 24 07:46:21 PM PDT 24
Peak memory	576304 kb
Host	smart-6e56c5a3-3608-4945-a1ae-9a4651eac2dd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767229908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_ with_rand_reset.767229908
Directory	/workspace/73.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3978244193
Short name	T1807
Test name
Test status
Simulation time	7720836164 ps
CPU time	424.02 seconds
Started	Jul 24 07:45:14 PM PDT 24
Finished	Jul 24 07:52:18 PM PDT 24
Peak memory	577292 kb
Host	smart-0e2f8d2f-83ac-4b70-9dfd-2704512d716f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978244193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.3978244193
Directory	/workspace/73.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.770848498
Short name	T1982
Test name
Test status
Simulation time	285293409 ps
CPU time	15.62 seconds
Started	Jul 24 07:45:20 PM PDT 24
Finished	Jul 24 07:45:36 PM PDT 24
Peak memory	576148 kb
Host	smart-5715a70c-949f-4f0e-8c00-664ef1bf0f34
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770848498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.770848498
Directory	/workspace/73.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_access_same_device.426747076
Short name	T2047
Test name
Test status
Simulation time	3343284417 ps
CPU time	136.57 seconds
Started	Jul 24 07:45:17 PM PDT 24
Finished	Jul 24 07:47:34 PM PDT 24
Peak memory	576404 kb
Host	smart-6a23f581-7e67-4d95-adf1-7a333abe933c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426747076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device. 426747076
Directory	/workspace/74.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2066940640
Short name	T910
Test name
Test status
Simulation time	34288057526 ps
CPU time	641.61 seconds
Started	Jul 24 07:45:15 PM PDT 24
Finished	Jul 24 07:55:58 PM PDT 24
Peak memory	576292 kb
Host	smart-53541fba-4c2c-46a1-91ec-0156a54806bc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066940640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.2066940640
Directory	/workspace/74.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2867642204
Short name	T1604
Test name
Test status
Simulation time	174407028 ps
CPU time	19.47 seconds
Started	Jul 24 07:45:17 PM PDT 24
Finished	Jul 24 07:45:37 PM PDT 24
Peak memory	576908 kb
Host	smart-71e8a070-05e6-45bd-9318-02db8dabd5c0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867642204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.2867642204
Directory	/workspace/74.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_error_random.3873009857
Short name	T2109
Test name
Test status
Simulation time	1544200539 ps
CPU time	51.41 seconds
Started	Jul 24 07:45:16 PM PDT 24
Finished	Jul 24 07:46:07 PM PDT 24
Peak memory	577024 kb
Host	smart-413b37bd-3b30-4f13-81cd-16260fac6946
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873009857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.3873009857
Directory	/workspace/74.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_random.3818451782
Short name	T2004
Test name
Test status
Simulation time	575492920 ps
CPU time	40.55 seconds
Started	Jul 24 07:45:18 PM PDT 24
Finished	Jul 24 07:45:58 PM PDT 24
Peak memory	576168 kb
Host	smart-ef1091c4-58ff-4759-a6d3-3358ab5b2e70
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818451782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.3818451782
Directory	/workspace/74.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_random_large_delays.3863019942
Short name	T666
Test name
Test status
Simulation time	21567972078 ps
CPU time	217.92 seconds
Started	Jul 24 07:45:18 PM PDT 24
Finished	Jul 24 07:48:56 PM PDT 24
Peak memory	577120 kb
Host	smart-a0f78597-88d7-428b-b386-c83e0174f8d1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863019942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.3863019942
Directory	/workspace/74.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.4016310215
Short name	T688
Test name
Test status
Simulation time	18924674962 ps
CPU time	322.18 seconds
Started	Jul 24 07:45:16 PM PDT 24
Finished	Jul 24 07:50:38 PM PDT 24
Peak memory	576224 kb
Host	smart-720d61f2-db9f-4bfa-aebd-6994f07179a5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016310215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.4016310215
Directory	/workspace/74.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.2436919286
Short name	T2583
Test name
Test status
Simulation time	513408665 ps
CPU time	40.4 seconds
Started	Jul 24 07:45:16 PM PDT 24
Finished	Jul 24 07:45:57 PM PDT 24
Peak memory	577024 kb
Host	smart-66facfb9-4d04-4ef0-b837-589a6301cd06
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436919286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.2436919286
Directory	/workspace/74.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_same_source.3729510098
Short name	T2767
Test name
Test status
Simulation time	353559657 ps
CPU time	25.95 seconds
Started	Jul 24 07:45:16 PM PDT 24
Finished	Jul 24 07:45:42 PM PDT 24
Peak memory	576984 kb
Host	smart-f67f51de-caae-44c9-89dc-4f4866541067
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729510098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.3729510098
Directory	/workspace/74.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke.835050934
Short name	T2023
Test name
Test status
Simulation time	209394783 ps
CPU time	8.95 seconds
Started	Jul 24 07:45:15 PM PDT 24
Finished	Jul 24 07:45:24 PM PDT 24
Peak memory	574844 kb
Host	smart-4807096d-084d-4eb6-b6e4-4fbc824fc0a3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835050934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.835050934
Directory	/workspace/74.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.1536181196
Short name	T2753
Test name
Test status
Simulation time	7156138321 ps
CPU time	74.8 seconds
Started	Jul 24 07:45:20 PM PDT 24
Finished	Jul 24 07:46:35 PM PDT 24
Peak memory	574984 kb
Host	smart-6ffb89c2-b6fa-4dc5-b29f-e54fefb7432d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536181196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.1536181196
Directory	/workspace/74.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1628776225
Short name	T2318
Test name
Test status
Simulation time	5705207797 ps
CPU time	98.44 seconds
Started	Jul 24 07:45:16 PM PDT 24
Finished	Jul 24 07:46:55 PM PDT 24
Peak memory	574996 kb
Host	smart-a544f582-4464-4cfd-a1dc-78cbfc4798cf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628776225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.1628776225
Directory	/workspace/74.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.2193581309
Short name	T2176
Test name
Test status
Simulation time	46642808 ps
CPU time	6.48 seconds
Started	Jul 24 07:45:14 PM PDT 24
Finished	Jul 24 07:45:21 PM PDT 24
Peak memory	574908 kb
Host	smart-2d81a8e2-3cac-4a47-bd13-9b1d0979f8c2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193581309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.2193581309
Directory	/workspace/74.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all.787713079
Short name	T604
Test name
Test status
Simulation time	3301376050 ps
CPU time	237.35 seconds
Started	Jul 24 07:45:16 PM PDT 24
Finished	Jul 24 07:49:13 PM PDT 24
Peak memory	577288 kb
Host	smart-f409ce58-2377-4c28-97c9-24ddf869c388
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787713079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.787713079
Directory	/workspace/74.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.2424988409
Short name	T2319
Test name
Test status
Simulation time	2267549145 ps
CPU time	71.99 seconds
Started	Jul 24 07:45:38 PM PDT 24
Finished	Jul 24 07:46:50 PM PDT 24
Peak memory	577132 kb
Host	smart-77532d65-985c-4cb0-816d-00004d79b065
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424988409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.2424988409
Directory	/workspace/74.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.895306171
Short name	T2842
Test name
Test status
Simulation time	4180808323 ps
CPU time	196.02 seconds
Started	Jul 24 07:45:35 PM PDT 24
Finished	Jul 24 07:48:52 PM PDT 24
Peak memory	576420 kb
Host	smart-e3670eea-ade4-4a15-87ea-c05342cf3c47
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895306171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_reset_error.895306171
Directory	/workspace/74.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1046326704
Short name	T1877
Test name
Test status
Simulation time	932538572 ps
CPU time	40.79 seconds
Started	Jul 24 07:45:16 PM PDT 24
Finished	Jul 24 07:45:57 PM PDT 24
Peak memory	576156 kb
Host	smart-56f3f1ab-497f-46e4-a068-6282b76134d8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046326704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1046326704
Directory	/workspace/74.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_access_same_device.3419521083
Short name	T915
Test name
Test status
Simulation time	515744999 ps
CPU time	22.82 seconds
Started	Jul 24 07:45:38 PM PDT 24
Finished	Jul 24 07:46:01 PM PDT 24
Peak memory	576172 kb
Host	smart-e8308702-ada7-4ad6-9781-491ce1dd9bbe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419521083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .3419521083
Directory	/workspace/75.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.90683292
Short name	T717
Test name
Test status
Simulation time	144143146097 ps
CPU time	2616.3 seconds
Started	Jul 24 07:45:38 PM PDT 24
Finished	Jul 24 08:29:15 PM PDT 24
Peak memory	576416 kb
Host	smart-c420c87c-3c72-4b98-aac6-25d47e3411a2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90683292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_de vice_slow_rsp.90683292
Directory	/workspace/75.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2111272972
Short name	T2273
Test name
Test status
Simulation time	1013516863 ps
CPU time	40.58 seconds
Started	Jul 24 07:45:35 PM PDT 24
Finished	Jul 24 07:46:16 PM PDT 24
Peak memory	576036 kb
Host	smart-bc96df03-65d8-476d-83df-be959caebbe9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111272972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.2111272972
Directory	/workspace/75.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_error_random.2906975831
Short name	T2083
Test name
Test status
Simulation time	2043881204 ps
CPU time	60.4 seconds
Started	Jul 24 07:45:35 PM PDT 24
Finished	Jul 24 07:46:36 PM PDT 24
Peak memory	576956 kb
Host	smart-e0931b94-0e80-462e-bdd8-a1b2a4a106ed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906975831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2906975831
Directory	/workspace/75.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_random.2452123828
Short name	T1923
Test name
Test status
Simulation time	462718233 ps
CPU time	17.53 seconds
Started	Jul 24 07:45:35 PM PDT 24
Finished	Jul 24 07:45:53 PM PDT 24
Peak memory	576904 kb
Host	smart-b505e5b4-52e4-4828-96cd-09cea22a59fa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452123828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.2452123828
Directory	/workspace/75.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3466395125
Short name	T2773
Test name
Test status
Simulation time	32586292348 ps
CPU time	326.66 seconds
Started	Jul 24 07:45:36 PM PDT 24
Finished	Jul 24 07:51:03 PM PDT 24
Peak memory	576280 kb
Host	smart-9ea397ae-7446-43b2-be2d-e5b44a142be7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466395125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.3466395125
Directory	/workspace/75.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.671648585
Short name	T1917
Test name
Test status
Simulation time	59523001522 ps
CPU time	1026.46 seconds
Started	Jul 24 07:45:36 PM PDT 24
Finished	Jul 24 08:02:42 PM PDT 24
Peak memory	576304 kb
Host	smart-593bd6ff-e898-48cb-a2f2-c6b6dbecb885
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671648585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.671648585
Directory	/workspace/75.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.4290188956
Short name	T2597
Test name
Test status
Simulation time	312951105 ps
CPU time	30.14 seconds
Started	Jul 24 07:45:36 PM PDT 24
Finished	Jul 24 07:46:07 PM PDT 24
Peak memory	576980 kb
Host	smart-825fb655-95bb-437d-82df-69b72d897239
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290188956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.4290188956
Directory	/workspace/75.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_same_source.229879899
Short name	T2369
Test name
Test status
Simulation time	277079915 ps
CPU time	11.31 seconds
Started	Jul 24 07:45:35 PM PDT 24
Finished	Jul 24 07:45:47 PM PDT 24
Peak memory	577000 kb
Host	smart-4d0130cd-a934-4c8e-a290-a7d72ad85f8f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229879899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.229879899
Directory	/workspace/75.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke.2288838448
Short name	T1460
Test name
Test status
Simulation time	197171223 ps
CPU time	8.97 seconds
Started	Jul 24 07:45:38 PM PDT 24
Finished	Jul 24 07:45:47 PM PDT 24
Peak memory	574872 kb
Host	smart-8376ea0d-d4d4-4e6f-849d-034b6a3f1816
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288838448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.2288838448
Directory	/workspace/75.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.1897287937
Short name	T2807
Test name
Test status
Simulation time	10030606394 ps
CPU time	96.82 seconds
Started	Jul 24 07:45:36 PM PDT 24
Finished	Jul 24 07:47:13 PM PDT 24
Peak memory	576216 kb
Host	smart-f86ad04a-ddec-462d-ab37-c3cc03cbe923
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897287937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.1897287937
Directory	/workspace/75.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3865444567
Short name	T2686
Test name
Test status
Simulation time	4695057356 ps
CPU time	79.36 seconds
Started	Jul 24 07:45:37 PM PDT 24
Finished	Jul 24 07:46:56 PM PDT 24
Peak memory	574988 kb
Host	smart-9fe4d72d-60ae-449f-954c-d605b6033885
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865444567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.3865444567
Directory	/workspace/75.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1374145341
Short name	T1532
Test name
Test status
Simulation time	44086097 ps
CPU time	5.77 seconds
Started	Jul 24 07:45:38 PM PDT 24
Finished	Jul 24 07:45:44 PM PDT 24
Peak memory	574808 kb
Host	smart-7a823877-7005-46a3-a880-9c5e7b015b83
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374145341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.1374145341
Directory	/workspace/75.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all.2970290332
Short name	T2322
Test name
Test status
Simulation time	1687164915 ps
CPU time	49.53 seconds
Started	Jul 24 07:45:37 PM PDT 24
Finished	Jul 24 07:46:27 PM PDT 24
Peak memory	577124 kb
Host	smart-f28d176b-29a0-49a6-9379-3e153189f37b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970290332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.2970290332
Directory	/workspace/75.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1984800797
Short name	T1879
Test name
Test status
Simulation time	426786425 ps
CPU time	39.88 seconds
Started	Jul 24 07:45:45 PM PDT 24
Finished	Jul 24 07:46:25 PM PDT 24
Peak memory	577020 kb
Host	smart-788b2467-983a-4a75-9aa7-7b8b96b7d3a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984800797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1984800797
Directory	/workspace/75.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1510713139
Short name	T605
Test name
Test status
Simulation time	2840184337 ps
CPU time	375.16 seconds
Started	Jul 24 07:45:37 PM PDT 24
Finished	Jul 24 07:51:52 PM PDT 24
Peak memory	576376 kb
Host	smart-272ee585-7570-4f00-a565-c188abee84b8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510713139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.1510713139
Directory	/workspace/75.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1222107118
Short name	T2586
Test name
Test status
Simulation time	103340292 ps
CPU time	34.64 seconds
Started	Jul 24 07:45:52 PM PDT 24
Finished	Jul 24 07:46:27 PM PDT 24
Peak memory	577132 kb
Host	smart-a001866d-410b-4db9-8922-00b7e0ea6762
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222107118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.1222107118
Directory	/workspace/75.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1117063773
Short name	T532
Test name
Test status
Simulation time	886660817 ps
CPU time	35.35 seconds
Started	Jul 24 07:45:40 PM PDT 24
Finished	Jul 24 07:46:15 PM PDT 24
Peak memory	577004 kb
Host	smart-64272df7-d387-46af-9cf2-fd66beeaf87b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117063773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.1117063773
Directory	/workspace/75.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_access_same_device.2181849410
Short name	T2477
Test name
Test status
Simulation time	68694719 ps
CPU time	7.36 seconds
Started	Jul 24 07:45:47 PM PDT 24
Finished	Jul 24 07:45:54 PM PDT 24
Peak memory	576088 kb
Host	smart-7075724d-9e38-44ed-a99b-d4c9e2948689
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181849410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .2181849410
Directory	/workspace/76.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3033419418
Short name	T2533
Test name
Test status
Simulation time	90074105625 ps
CPU time	1603.92 seconds
Started	Jul 24 07:45:45 PM PDT 24
Finished	Jul 24 08:12:29 PM PDT 24
Peak memory	576336 kb
Host	smart-93131b99-4786-46d8-aac9-ba556ffee991
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033419418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.3033419418
Directory	/workspace/76.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2045880530
Short name	T2167
Test name
Test status
Simulation time	49173680 ps
CPU time	8.13 seconds
Started	Jul 24 07:45:45 PM PDT 24
Finished	Jul 24 07:45:54 PM PDT 24
Peak memory	574856 kb
Host	smart-176dadb2-2bec-43ec-a4a1-84ab2e0d9dc1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045880530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.2045880530
Directory	/workspace/76.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_error_random.777117950
Short name	T1659
Test name
Test status
Simulation time	382957764 ps
CPU time	30.64 seconds
Started	Jul 24 07:45:50 PM PDT 24
Finished	Jul 24 07:46:21 PM PDT 24
Peak memory	576952 kb
Host	smart-733c0690-451e-4944-bdd7-00828d1fa9ff
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777117950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.777117950
Directory	/workspace/76.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_random.3066015081
Short name	T2119
Test name
Test status
Simulation time	356261929 ps
CPU time	15.68 seconds
Started	Jul 24 07:45:44 PM PDT 24
Finished	Jul 24 07:45:59 PM PDT 24
Peak memory	576224 kb
Host	smart-012b227d-a075-4327-b4c5-fed46f63a425
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066015081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.3066015081
Directory	/workspace/76.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_random_large_delays.1626131088
Short name	T76
Test name
Test status
Simulation time	15085431938 ps
CPU time	147.43 seconds
Started	Jul 24 07:45:52 PM PDT 24
Finished	Jul 24 07:48:19 PM PDT 24
Peak memory	576324 kb
Host	smart-a800d7a7-b33d-460d-9659-7a16ca4c3ed0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626131088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.1626131088
Directory	/workspace/76.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.3965541003
Short name	T1652
Test name
Test status
Simulation time	61347923228 ps
CPU time	1149.91 seconds
Started	Jul 24 07:45:48 PM PDT 24
Finished	Jul 24 08:04:59 PM PDT 24
Peak memory	577148 kb
Host	smart-1e804426-2979-4ac3-a2cd-f7d5fbd7267f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965541003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.3965541003
Directory	/workspace/76.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.463010710
Short name	T606
Test name
Test status
Simulation time	488884661 ps
CPU time	44.22 seconds
Started	Jul 24 07:45:58 PM PDT 24
Finished	Jul 24 07:46:42 PM PDT 24
Peak memory	576132 kb
Host	smart-7b83cc33-ae00-4ac7-8363-771b253e575c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463010710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_dela ys.463010710
Directory	/workspace/76.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_same_source.2357151196
Short name	T553
Test name
Test status
Simulation time	305457388 ps
CPU time	21.53 seconds
Started	Jul 24 07:45:50 PM PDT 24
Finished	Jul 24 07:46:11 PM PDT 24
Peak memory	576068 kb
Host	smart-ac6dd670-49d7-47a7-8b71-1bf1083e7dea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357151196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.2357151196
Directory	/workspace/76.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke.739172413
Short name	T2614
Test name
Test status
Simulation time	156861425 ps
CPU time	7.82 seconds
Started	Jul 24 07:45:44 PM PDT 24
Finished	Jul 24 07:45:52 PM PDT 24
Peak memory	574776 kb
Host	smart-99b573e9-fc43-4b50-b2a1-6322ed11487c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739172413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.739172413
Directory	/workspace/76.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.1111875345
Short name	T1903
Test name
Test status
Simulation time	8422550324 ps
CPU time	87.16 seconds
Started	Jul 24 07:45:45 PM PDT 24
Finished	Jul 24 07:47:13 PM PDT 24
Peak memory	576240 kb
Host	smart-85983214-613c-457e-a198-a3de6a66f309
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111875345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.1111875345
Directory	/workspace/76.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.1451625014
Short name	T2617
Test name
Test status
Simulation time	2415796866 ps
CPU time	42.53 seconds
Started	Jul 24 07:45:49 PM PDT 24
Finished	Jul 24 07:46:32 PM PDT 24
Peak memory	576304 kb
Host	smart-51507b1e-1f99-4da4-ae4d-31fc76422577
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451625014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.1451625014
Directory	/workspace/76.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.864995431
Short name	T1920
Test name
Test status
Simulation time	51485708 ps
CPU time	6.22 seconds
Started	Jul 24 07:45:43 PM PDT 24
Finished	Jul 24 07:45:50 PM PDT 24
Peak memory	574888 kb
Host	smart-eba44a17-25e5-4eca-8a0e-4610fae39e08
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864995431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays .864995431
Directory	/workspace/76.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all.156059221
Short name	T2233
Test name
Test status
Simulation time	2371015887 ps
CPU time	195.29 seconds
Started	Jul 24 07:45:52 PM PDT 24
Finished	Jul 24 07:49:07 PM PDT 24
Peak memory	576532 kb
Host	smart-bfb15249-487b-4688-a12b-5582be4a0897
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156059221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.156059221
Directory	/workspace/76.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.954647255
Short name	T2552
Test name
Test status
Simulation time	1323995232 ps
CPU time	49.61 seconds
Started	Jul 24 07:45:43 PM PDT 24
Finished	Jul 24 07:46:33 PM PDT 24
Peak memory	576232 kb
Host	smart-a7d30a29-2525-42ca-ac2b-1e6cf2432079
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954647255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.954647255
Directory	/workspace/76.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.971514247
Short name	T972
Test name
Test status
Simulation time	481463319 ps
CPU time	166.44 seconds
Started	Jul 24 07:45:49 PM PDT 24
Finished	Jul 24 07:48:35 PM PDT 24
Peak memory	577112 kb
Host	smart-a1f3148c-8e37-47db-b30e-a2b94a97c791
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971514247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_ with_rand_reset.971514247
Directory	/workspace/76.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2540820727
Short name	T971
Test name
Test status
Simulation time	1886367909 ps
CPU time	90.09 seconds
Started	Jul 24 07:45:46 PM PDT 24
Finished	Jul 24 07:47:16 PM PDT 24
Peak memory	577152 kb
Host	smart-3962d34a-94fe-4f37-b444-5b61328e46f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540820727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.2540820727
Directory	/workspace/76.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.2335375871
Short name	T2200
Test name
Test status
Simulation time	1116147694 ps
CPU time	48.84 seconds
Started	Jul 24 07:45:47 PM PDT 24
Finished	Jul 24 07:46:36 PM PDT 24
Peak memory	577028 kb
Host	smart-1d5dd878-e137-4a1c-a8fc-60f52cafbd98
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335375871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.2335375871
Directory	/workspace/76.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_access_same_device.2544485538
Short name	T2698
Test name
Test status
Simulation time	225912549 ps
CPU time	22.61 seconds
Started	Jul 24 07:45:52 PM PDT 24
Finished	Jul 24 07:46:15 PM PDT 24
Peak memory	576140 kb
Host	smart-bd5f4077-56b6-48e3-b86b-30fbe6a6f031
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544485538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .2544485538
Directory	/workspace/77.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.1384647675
Short name	T2075
Test name
Test status
Simulation time	291726881 ps
CPU time	13.81 seconds
Started	Jul 24 07:45:45 PM PDT 24
Finished	Jul 24 07:45:59 PM PDT 24
Peak memory	576976 kb
Host	smart-38476a18-4d5a-48a7-b079-ad0fd4ea1681
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384647675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.1384647675
Directory	/workspace/77.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_error_random.342165558
Short name	T1617
Test name
Test status
Simulation time	1863815307 ps
CPU time	66.48 seconds
Started	Jul 24 07:45:45 PM PDT 24
Finished	Jul 24 07:46:52 PM PDT 24
Peak memory	576084 kb
Host	smart-a24039b1-392e-4ddc-9ff6-366fcd920ab3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342165558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.342165558
Directory	/workspace/77.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_random.400347519
Short name	T2730
Test name
Test status
Simulation time	1255243998 ps
CPU time	37.45 seconds
Started	Jul 24 07:45:49 PM PDT 24
Finished	Jul 24 07:46:26 PM PDT 24
Peak memory	576932 kb
Host	smart-a37134bb-d676-4373-b8fe-f71876bd58bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400347519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.400347519
Directory	/workspace/77.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_random_large_delays.2745299883
Short name	T2144
Test name
Test status
Simulation time	92066449820 ps
CPU time	969.58 seconds
Started	Jul 24 07:45:51 PM PDT 24
Finished	Jul 24 08:02:01 PM PDT 24
Peak memory	577184 kb
Host	smart-110943b9-b661-4f1c-acab-b4ab0ca0562b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745299883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.2745299883
Directory	/workspace/77.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.4080563491
Short name	T1797
Test name
Test status
Simulation time	63785793743 ps
CPU time	1217.84 seconds
Started	Jul 24 07:45:49 PM PDT 24
Finished	Jul 24 08:06:07 PM PDT 24
Peak memory	576304 kb
Host	smart-60ec3eb9-c95c-41a9-ab86-868ec010cc27
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080563491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.4080563491
Directory	/workspace/77.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1976220135
Short name	T515
Test name
Test status
Simulation time	375108084 ps
CPU time	34.12 seconds
Started	Jul 24 07:45:47 PM PDT 24
Finished	Jul 24 07:46:21 PM PDT 24
Peak memory	577052 kb
Host	smart-a2d21a9f-53d8-4f73-8e16-67308dc64324
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976220135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.1976220135
Directory	/workspace/77.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_same_source.2237627701
Short name	T494
Test name
Test status
Simulation time	1741403855 ps
CPU time	54.11 seconds
Started	Jul 24 07:45:49 PM PDT 24
Finished	Jul 24 07:46:43 PM PDT 24
Peak memory	576960 kb
Host	smart-d1a73bcc-62b3-499d-9162-9a2c18f97f69
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237627701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.2237627701
Directory	/workspace/77.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke.1494879354
Short name	T2313
Test name
Test status
Simulation time	46883380 ps
CPU time	6.52 seconds
Started	Jul 24 07:45:46 PM PDT 24
Finished	Jul 24 07:45:53 PM PDT 24
Peak memory	574896 kb
Host	smart-168ad4dd-5090-4a7a-8ba4-0d5f31d9c1d9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494879354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.1494879354
Directory	/workspace/77.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.2749659459
Short name	T2679
Test name
Test status
Simulation time	6021078388 ps
CPU time	61.99 seconds
Started	Jul 24 07:45:49 PM PDT 24
Finished	Jul 24 07:46:51 PM PDT 24
Peak memory	576308 kb
Host	smart-e79ef961-4c2e-4f96-a220-dc7cfb5e93b5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749659459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.2749659459
Directory	/workspace/77.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1145602732
Short name	T623
Test name
Test status
Simulation time	3414943341 ps
CPU time	52.92 seconds
Started	Jul 24 07:45:44 PM PDT 24
Finished	Jul 24 07:46:37 PM PDT 24
Peak memory	574988 kb
Host	smart-caf9a9ac-3984-408f-8a7b-bf106739c305
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145602732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.1145602732
Directory	/workspace/77.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.1105456662
Short name	T2012
Test name
Test status
Simulation time	48363636 ps
CPU time	6.31 seconds
Started	Jul 24 07:45:46 PM PDT 24
Finished	Jul 24 07:45:52 PM PDT 24
Peak memory	576152 kb
Host	smart-a97c78bd-6af3-4e1a-a4e2-2c92f39196d5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105456662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.1105456662
Directory	/workspace/77.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all.3686801480
Short name	T2554
Test name
Test status
Simulation time	48759709 ps
CPU time	6.31 seconds
Started	Jul 24 07:45:47 PM PDT 24
Finished	Jul 24 07:45:53 PM PDT 24
Peak memory	574860 kb
Host	smart-5cce5583-aa98-45ed-a074-c3bd88ab6741
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686801480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.3686801480
Directory	/workspace/77.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.1109153298
Short name	T1665
Test name
Test status
Simulation time	2656475558 ps
CPU time	99.34 seconds
Started	Jul 24 07:45:47 PM PDT 24
Finished	Jul 24 07:47:26 PM PDT 24
Peak memory	576304 kb
Host	smart-a8b1af7a-65cf-49d6-acea-168b0840133b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109153298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.1109153298
Directory	/workspace/77.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2366237095
Short name	T2905
Test name
Test status
Simulation time	110667841 ps
CPU time	26.31 seconds
Started	Jul 24 07:45:45 PM PDT 24
Finished	Jul 24 07:46:12 PM PDT 24
Peak memory	577124 kb
Host	smart-31419d24-6bc8-4aa1-9caf-addaa297f69a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366237095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.2366237095
Directory	/workspace/77.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.4283656546
Short name	T952
Test name
Test status
Simulation time	272154030 ps
CPU time	99.6 seconds
Started	Jul 24 07:45:46 PM PDT 24
Finished	Jul 24 07:47:25 PM PDT 24
Peak memory	576412 kb
Host	smart-0365917c-66af-4aba-a92b-f882e1034b09
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283656546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.4283656546
Directory	/workspace/77.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.895592188
Short name	T1874
Test name
Test status
Simulation time	1264317296 ps
CPU time	51.35 seconds
Started	Jul 24 07:45:49 PM PDT 24
Finished	Jul 24 07:46:40 PM PDT 24
Peak memory	576176 kb
Host	smart-0f9ebc6f-ea31-4bcc-9748-23aec03b9dfd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895592188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.895592188
Directory	/workspace/77.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_access_same_device.1169549341
Short name	T900
Test name
Test status
Simulation time	3094784142 ps
CPU time	113.55 seconds
Started	Jul 24 07:45:44 PM PDT 24
Finished	Jul 24 07:47:38 PM PDT 24
Peak memory	577196 kb
Host	smart-cf06e6cd-3608-4f6c-a24b-19621543dc33
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169549341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .1169549341
Directory	/workspace/78.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3590103636
Short name	T1653
Test name
Test status
Simulation time	76682788905 ps
CPU time	1395.07 seconds
Started	Jul 24 07:45:47 PM PDT 24
Finished	Jul 24 08:09:03 PM PDT 24
Peak memory	577128 kb
Host	smart-1fbb1b6c-d629-46ea-b5d5-fc00400a6a30
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590103636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.3590103636
Directory	/workspace/78.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.71934142
Short name	T1947
Test name
Test status
Simulation time	192303155 ps
CPU time	10.28 seconds
Started	Jul 24 07:45:47 PM PDT 24
Finished	Jul 24 07:45:57 PM PDT 24
Peak memory	574856 kb
Host	smart-1edc5c40-830e-4ff7-b1c2-c52504eecfcb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71934142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr.71934142
Directory	/workspace/78.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_error_random.2494977541
Short name	T2860
Test name
Test status
Simulation time	1854305099 ps
CPU time	55.51 seconds
Started	Jul 24 07:45:50 PM PDT 24
Finished	Jul 24 07:46:46 PM PDT 24
Peak memory	577052 kb
Host	smart-9c7ff5df-98b2-494d-bb18-ffcd29aeec86
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494977541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.2494977541
Directory	/workspace/78.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_random.3936347669
Short name	T1849
Test name
Test status
Simulation time	1211772937 ps
CPU time	41.74 seconds
Started	Jul 24 07:45:46 PM PDT 24
Finished	Jul 24 07:46:28 PM PDT 24
Peak memory	576900 kb
Host	smart-79c50948-7aac-4ba8-b111-252a7a5a9cd9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936347669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.3936347669
Directory	/workspace/78.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_random_large_delays.1277304175
Short name	T2611
Test name
Test status
Simulation time	35467526110 ps
CPU time	389.11 seconds
Started	Jul 24 07:45:53 PM PDT 24
Finished	Jul 24 07:52:22 PM PDT 24
Peak memory	576252 kb
Host	smart-1f441fd5-0de5-4376-ac74-8711adb319ed
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277304175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.1277304175
Directory	/workspace/78.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.2980984781
Short name	T1858
Test name
Test status
Simulation time	63387210889 ps
CPU time	1186.32 seconds
Started	Jul 24 07:45:53 PM PDT 24
Finished	Jul 24 08:05:40 PM PDT 24
Peak memory	577124 kb
Host	smart-fec8d70a-8fb1-45fb-ab0e-8a1f29bb2022
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980984781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.2980984781
Directory	/workspace/78.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1241185469
Short name	T1706
Test name
Test status
Simulation time	162009912 ps
CPU time	18.25 seconds
Started	Jul 24 07:45:51 PM PDT 24
Finished	Jul 24 07:46:09 PM PDT 24
Peak memory	576904 kb
Host	smart-1da1a592-873a-4ae9-8c0e-6a172a61fdd7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241185469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.1241185469
Directory	/workspace/78.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_same_source.924547898
Short name	T2821
Test name
Test status
Simulation time	930849868 ps
CPU time	29.7 seconds
Started	Jul 24 07:45:46 PM PDT 24
Finished	Jul 24 07:46:16 PM PDT 24
Peak memory	577100 kb
Host	smart-d948af0e-a273-4268-a058-5e0382c11805
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924547898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.924547898
Directory	/workspace/78.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke.4120402099
Short name	T1768
Test name
Test status
Simulation time	44533047 ps
CPU time	6.08 seconds
Started	Jul 24 07:45:51 PM PDT 24
Finished	Jul 24 07:45:57 PM PDT 24
Peak memory	576096 kb
Host	smart-21984308-9b93-4d5c-94d3-7c6f39bc40b4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120402099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.4120402099
Directory	/workspace/78.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2094091963
Short name	T2786
Test name
Test status
Simulation time	8102555071 ps
CPU time	87.23 seconds
Started	Jul 24 07:45:52 PM PDT 24
Finished	Jul 24 07:47:19 PM PDT 24
Peak memory	575048 kb
Host	smart-75f0315f-aade-4b89-992e-4694b36d1a5f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094091963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.2094091963
Directory	/workspace/78.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3831640037
Short name	T2371
Test name
Test status
Simulation time	5116819099 ps
CPU time	87.07 seconds
Started	Jul 24 07:45:47 PM PDT 24
Finished	Jul 24 07:47:15 PM PDT 24
Peak memory	574916 kb
Host	smart-9348e2c1-d195-46c7-bc21-ea14faad557a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831640037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.3831640037
Directory	/workspace/78.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.3603331839
Short name	T1585
Test name
Test status
Simulation time	51011506 ps
CPU time	6.43 seconds
Started	Jul 24 07:45:47 PM PDT 24
Finished	Jul 24 07:45:54 PM PDT 24
Peak memory	576132 kb
Host	smart-77516d80-b3c2-4d85-853d-a5c8358a4549
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603331839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.3603331839
Directory	/workspace/78.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all.2347316248
Short name	T657
Test name
Test status
Simulation time	373410310 ps
CPU time	16.5 seconds
Started	Jul 24 07:45:54 PM PDT 24
Finished	Jul 24 07:46:10 PM PDT 24
Peak memory	577104 kb
Host	smart-d9588e0c-feda-496c-855c-b28e2f9d0b61
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347316248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2347316248
Directory	/workspace/78.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.2408544246
Short name	T2915
Test name
Test status
Simulation time	675609052 ps
CPU time	52.11 seconds
Started	Jul 24 07:45:54 PM PDT 24
Finished	Jul 24 07:46:46 PM PDT 24
Peak memory	576188 kb
Host	smart-1f0e7e49-e2ad-4498-9db6-aaaac96d250e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408544246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.2408544246
Directory	/workspace/78.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2262177740
Short name	T2269
Test name
Test status
Simulation time	45215956 ps
CPU time	60.56 seconds
Started	Jul 24 07:45:57 PM PDT 24
Finished	Jul 24 07:46:58 PM PDT 24
Peak memory	577100 kb
Host	smart-a71f12a9-d3e2-4c9a-b99f-40c786a46db2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262177740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.2262177740
Directory	/workspace/78.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.4135409852
Short name	T1725
Test name
Test status
Simulation time	192668757 ps
CPU time	81.04 seconds
Started	Jul 24 07:45:54 PM PDT 24
Finished	Jul 24 07:47:15 PM PDT 24
Peak memory	576432 kb
Host	smart-774dbc16-5426-4ff1-8c69-2a9b71881217
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135409852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.4135409852
Directory	/workspace/78.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.87931051
Short name	T2286
Test name
Test status
Simulation time	349462988 ps
CPU time	16.8 seconds
Started	Jul 24 07:45:46 PM PDT 24
Finished	Jul 24 07:46:03 PM PDT 24
Peak memory	577008 kb
Host	smart-fa59073f-31d1-40d9-8b13-d386e32ddf8a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87931051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.87931051
Directory	/workspace/78.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_access_same_device.2999764481
Short name	T1690
Test name
Test status
Simulation time	523782823 ps
CPU time	34.52 seconds
Started	Jul 24 07:45:58 PM PDT 24
Finished	Jul 24 07:46:32 PM PDT 24
Peak memory	577032 kb
Host	smart-92efa156-9207-442a-a35f-db5066aa674a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999764481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .2999764481
Directory	/workspace/79.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2268431600
Short name	T2145
Test name
Test status
Simulation time	29273179741 ps
CPU time	541.77 seconds
Started	Jul 24 07:45:55 PM PDT 24
Finished	Jul 24 07:54:57 PM PDT 24
Peak memory	577132 kb
Host	smart-172367bf-c244-4adf-b016-623ff3f192ad
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268431600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.2268431600
Directory	/workspace/79.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3237761579
Short name	T1454
Test name
Test status
Simulation time	110008459 ps
CPU time	6.94 seconds
Started	Jul 24 07:45:56 PM PDT 24
Finished	Jul 24 07:46:03 PM PDT 24
Peak memory	574756 kb
Host	smart-93a26c6a-2688-4c55-aafb-3efa6a7b96a5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237761579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.3237761579
Directory	/workspace/79.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_error_random.2865057551
Short name	T2787
Test name
Test status
Simulation time	1469372582 ps
CPU time	47.44 seconds
Started	Jul 24 07:45:57 PM PDT 24
Finished	Jul 24 07:46:44 PM PDT 24
Peak memory	576960 kb
Host	smart-5fce911b-19a3-4a4d-b4b2-601945f38465
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865057551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.2865057551
Directory	/workspace/79.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_random.2312394945
Short name	T468
Test name
Test status
Simulation time	596069405 ps
CPU time	46.27 seconds
Started	Jul 24 07:45:55 PM PDT 24
Finished	Jul 24 07:46:42 PM PDT 24
Peak memory	576244 kb
Host	smart-67549bc2-62e0-49e3-ada5-8b2abbaeb6aa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312394945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.2312394945
Directory	/workspace/79.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.422051876
Short name	T1708
Test name
Test status
Simulation time	54551961304 ps
CPU time	1096.69 seconds
Started	Jul 24 07:45:57 PM PDT 24
Finished	Jul 24 08:04:14 PM PDT 24
Peak memory	577232 kb
Host	smart-7935e1a2-a706-4a91-a6a5-f3c36a54953a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422051876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.422051876
Directory	/workspace/79.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.2347807527
Short name	T2549
Test name
Test status
Simulation time	78658933 ps
CPU time	9.29 seconds
Started	Jul 24 07:45:54 PM PDT 24
Finished	Jul 24 07:46:04 PM PDT 24
Peak memory	577004 kb
Host	smart-f90118f3-8a5e-4645-af32-000b14478a9e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347807527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.2347807527
Directory	/workspace/79.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_same_source.133444211
Short name	T549
Test name
Test status
Simulation time	1126633662 ps
CPU time	35.48 seconds
Started	Jul 24 07:45:56 PM PDT 24
Finished	Jul 24 07:46:31 PM PDT 24
Peak memory	576260 kb
Host	smart-9f7b148a-13bb-428c-836a-ebbd38ae5787
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133444211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.133444211
Directory	/workspace/79.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke.3164219520
Short name	T1878
Test name
Test status
Simulation time	195184298 ps
CPU time	9.03 seconds
Started	Jul 24 07:45:58 PM PDT 24
Finished	Jul 24 07:46:07 PM PDT 24
Peak memory	576232 kb
Host	smart-eda5ff2b-032e-49e8-82bc-5a1941a8a749
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164219520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.3164219520
Directory	/workspace/79.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.308420833
Short name	T1782
Test name
Test status
Simulation time	7739042127 ps
CPU time	79.32 seconds
Started	Jul 24 07:45:53 PM PDT 24
Finished	Jul 24 07:47:13 PM PDT 24
Peak memory	575040 kb
Host	smart-f4a66034-6ea4-44fd-b239-f00a180d0f61
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308420833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.308420833
Directory	/workspace/79.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.3381516516
Short name	T1972
Test name
Test status
Simulation time	4942074897 ps
CPU time	89.27 seconds
Started	Jul 24 07:45:53 PM PDT 24
Finished	Jul 24 07:47:23 PM PDT 24
Peak memory	575052 kb
Host	smart-b2ece824-47e7-415a-bd27-ee84ab4b7b09
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381516516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.3381516516
Directory	/workspace/79.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.200153739
Short name	T1880
Test name
Test status
Simulation time	54255643 ps
CPU time	6.83 seconds
Started	Jul 24 07:45:59 PM PDT 24
Finished	Jul 24 07:46:06 PM PDT 24
Peak memory	576164 kb
Host	smart-08a60ccb-e054-4624-a5c2-3c691657293d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200153739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays .200153739
Directory	/workspace/79.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all.270096948
Short name	T1940
Test name
Test status
Simulation time	1797054202 ps
CPU time	148.49 seconds
Started	Jul 24 07:45:59 PM PDT 24
Finished	Jul 24 07:48:28 PM PDT 24
Peak memory	577180 kb
Host	smart-bec36591-d793-4119-987e-b69a00451e58
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270096948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.270096948
Directory	/workspace/79.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.3221590077
Short name	T2072
Test name
Test status
Simulation time	736544546 ps
CPU time	277.17 seconds
Started	Jul 24 07:46:06 PM PDT 24
Finished	Jul 24 07:50:43 PM PDT 24
Peak memory	576412 kb
Host	smart-38b808b7-550a-4fa8-99e6-61faf4349323
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221590077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.3221590077
Directory	/workspace/79.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.185187574
Short name	T974
Test name
Test status
Simulation time	1393360620 ps
CPU time	152.68 seconds
Started	Jul 24 07:46:05 PM PDT 24
Finished	Jul 24 07:48:38 PM PDT 24
Peak memory	577116 kb
Host	smart-ad18e32f-ad02-41c1-bbdb-add0498ecabd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185187574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_reset_error.185187574
Directory	/workspace/79.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.4110905290
Short name	T2366
Test name
Test status
Simulation time	929562418 ps
CPU time	37.19 seconds
Started	Jul 24 07:45:56 PM PDT 24
Finished	Jul 24 07:46:33 PM PDT 24
Peak memory	577096 kb
Host	smart-15c2d0e0-d222-46af-9e34-1522a1ed94c6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110905290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.4110905290
Directory	/workspace/79.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.2649880230
Short name	T1591
Test name
Test status
Simulation time	10753070275 ps
CPU time	827.07 seconds
Started	Jul 24 07:33:56 PM PDT 24
Finished	Jul 24 07:47:43 PM PDT 24
Peak memory	653364 kb
Host	smart-25e700b9-73ce-4e22-9cff-2a150e40f907
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649880230 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.2649880230
Directory	/workspace/8.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/8.chip_csr_rw.3706377013
Short name	T2341
Test name
Test status
Simulation time	5836403515 ps
CPU time	524.12 seconds
Started	Jul 24 07:34:06 PM PDT 24
Finished	Jul 24 07:42:51 PM PDT 24
Peak memory	599736 kb
Host	smart-a9d353ed-4142-46e2-a1f0-bee4e8285f95
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706377013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.3706377013
Directory	/workspace/8.chip_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.4000051186
Short name	T405
Test name
Test status
Simulation time	27426828746 ps
CPU time	3512.78 seconds
Started	Jul 24 07:34:04 PM PDT 24
Finished	Jul 24 08:32:37 PM PDT 24
Peak memory	594036 kb
Host	smart-4be12bf4-347c-4659-b429-77f7407e8e42
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000051186 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.4000051186
Directory	/workspace/8.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/8.chip_tl_errors.6393498
Short name	T594
Test name
Test status
Simulation time	2782036641 ps
CPU time	115.75 seconds
Started	Jul 24 07:34:05 PM PDT 24
Finished	Jul 24 07:36:00 PM PDT 24
Peak memory	600464 kb
Host	smart-d68db3ab-96f3-4aaa-9e32-2ff96d2faa01
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6393498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.6393498
Directory	/workspace/8.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_access_same_device.3731345686
Short name	T1772
Test name
Test status
Simulation time	559003334 ps
CPU time	45.68 seconds
Started	Jul 24 07:34:01 PM PDT 24
Finished	Jul 24 07:34:47 PM PDT 24
Peak memory	576148 kb
Host	smart-51eec158-8f17-4e6d-95ca-a1e9184d86d7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731345686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 3731345686
Directory	/workspace/8.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1421943596
Short name	T2356
Test name
Test status
Simulation time	103144938483 ps
CPU time	1792.56 seconds
Started	Jul 24 07:33:58 PM PDT 24
Finished	Jul 24 08:03:51 PM PDT 24
Peak memory	576556 kb
Host	smart-3c7de46d-aeed-4601-ad22-ce8837e7b5b6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421943596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.1421943596
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3122297843
Short name	T2713
Test name
Test status
Simulation time	415369248 ps
CPU time	19.13 seconds
Started	Jul 24 07:34:00 PM PDT 24
Finished	Jul 24 07:34:19 PM PDT 24
Peak memory	576992 kb
Host	smart-f952bc4a-1ad5-403c-b0d0-8aa32b9003a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122297843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .3122297843
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_error_random.44226754
Short name	T2025
Test name
Test status
Simulation time	585111634 ps
CPU time	42.99 seconds
Started	Jul 24 07:34:22 PM PDT 24
Finished	Jul 24 07:35:05 PM PDT 24
Peak memory	576988 kb
Host	smart-4cddf56a-9ac6-4881-979b-3f35e3d090bd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44226754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.44226754
Directory	/workspace/8.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_random.3444623661
Short name	T513
Test name
Test status
Simulation time	402991500 ps
CPU time	38.28 seconds
Started	Jul 24 07:33:58 PM PDT 24
Finished	Jul 24 07:34:36 PM PDT 24
Peak memory	576180 kb
Host	smart-e52d448a-2198-4bdc-8ad3-bacaa7a5c1f1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444623661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3444623661
Directory	/workspace/8.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_random_large_delays.1181605027
Short name	T2848
Test name
Test status
Simulation time	50823064940 ps
CPU time	577.81 seconds
Started	Jul 24 07:34:16 PM PDT 24
Finished	Jul 24 07:43:54 PM PDT 24
Peak memory	576316 kb
Host	smart-97fc2b0f-b66a-49de-bc64-23164818a63d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181605027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1181605027
Directory	/workspace/8.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.2008597172
Short name	T2096
Test name
Test status
Simulation time	11959950635 ps
CPU time	200.29 seconds
Started	Jul 24 07:33:56 PM PDT 24
Finished	Jul 24 07:37:17 PM PDT 24
Peak memory	577132 kb
Host	smart-7d72cfa7-4248-4721-b875-e91c5e248a17
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008597172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2008597172
Directory	/workspace/8.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3632335932
Short name	T1902
Test name
Test status
Simulation time	585242909 ps
CPU time	49.59 seconds
Started	Jul 24 07:34:22 PM PDT 24
Finished	Jul 24 07:35:12 PM PDT 24
Peak memory	577064 kb
Host	smart-6bb830b0-7751-4411-874b-d5e0ccb44cf8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632335932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.3632335932
Directory	/workspace/8.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_same_source.3245780514
Short name	T2605
Test name
Test status
Simulation time	224733883 ps
CPU time	18.69 seconds
Started	Jul 24 07:34:22 PM PDT 24
Finished	Jul 24 07:34:41 PM PDT 24
Peak memory	577024 kb
Host	smart-4bb15f85-1d77-4c04-8007-127f2bc80f32
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245780514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3245780514
Directory	/workspace/8.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke.2870532627
Short name	T1525
Test name
Test status
Simulation time	45350394 ps
CPU time	6.13 seconds
Started	Jul 24 07:34:05 PM PDT 24
Finished	Jul 24 07:34:11 PM PDT 24
Peak memory	574872 kb
Host	smart-c04b90a2-e6bd-419b-95d0-fbb8d33a1076
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870532627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2870532627
Directory	/workspace/8.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.4260102033
Short name	T1495
Test name
Test status
Simulation time	8562064227 ps
CPU time	88.31 seconds
Started	Jul 24 07:34:05 PM PDT 24
Finished	Jul 24 07:35:33 PM PDT 24
Peak memory	574992 kb
Host	smart-66ea97b4-4545-4021-b633-304b478864a7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260102033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.4260102033
Directory	/workspace/8.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3524518924
Short name	T1504
Test name
Test status
Simulation time	3883518509 ps
CPU time	62.85 seconds
Started	Jul 24 07:34:04 PM PDT 24
Finished	Jul 24 07:35:07 PM PDT 24
Peak memory	575000 kb
Host	smart-a9ffea23-0c61-4ed9-9c8f-2d12f204c288
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524518924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3524518924
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.4244405657
Short name	T2201
Test name
Test status
Simulation time	47588605 ps
CPU time	6.62 seconds
Started	Jul 24 07:33:46 PM PDT 24
Finished	Jul 24 07:33:53 PM PDT 24
Peak memory	574948 kb
Host	smart-8b81c18a-8fbc-478b-9db1-233197d64e5d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244405657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .4244405657
Directory	/workspace/8.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all.3708930032
Short name	T2007
Test name
Test status
Simulation time	8489128599 ps
CPU time	279.2 seconds
Started	Jul 24 07:34:22 PM PDT 24
Finished	Jul 24 07:39:01 PM PDT 24
Peak memory	576464 kb
Host	smart-68f22517-7a07-47ae-a1fd-ecc2c23a391e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708930032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3708930032
Directory	/workspace/8.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3728739380
Short name	T1567
Test name
Test status
Simulation time	1569863530 ps
CPU time	124.62 seconds
Started	Jul 24 07:34:00 PM PDT 24
Finished	Jul 24 07:36:05 PM PDT 24
Peak memory	577100 kb
Host	smart-f39ce0ec-5a13-4e58-a1a1-58f584915296
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728739380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3728739380
Directory	/workspace/8.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3554102333
Short name	T2345
Test name
Test status
Simulation time	876343327 ps
CPU time	215.48 seconds
Started	Jul 24 07:34:00 PM PDT 24
Finished	Jul 24 07:37:35 PM PDT 24
Peak memory	576304 kb
Host	smart-967741cd-54a8-4081-83ef-fd22d377c9d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554102333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.3554102333
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.3804784447
Short name	T642
Test name
Test status
Simulation time	182978625 ps
CPU time	10.98 seconds
Started	Jul 24 07:33:57 PM PDT 24
Finished	Jul 24 07:34:08 PM PDT 24
Peak memory	576240 kb
Host	smart-497fe0a6-4e5f-427e-91f1-f1bc07549ca4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804784447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3804784447
Directory	/workspace/8.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_access_same_device.359459316
Short name	T2308
Test name
Test status
Simulation time	1445349374 ps
CPU time	58.88 seconds
Started	Jul 24 07:46:06 PM PDT 24
Finished	Jul 24 07:47:05 PM PDT 24
Peak memory	576944 kb
Host	smart-86e843c4-035b-42b9-a0fa-6583a1c7a86c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359459316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device. 359459316
Directory	/workspace/80.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2863687786
Short name	T2783
Test name
Test status
Simulation time	113418499235 ps
CPU time	2106.49 seconds
Started	Jul 24 07:46:59 PM PDT 24
Finished	Jul 24 08:22:06 PM PDT 24
Peak memory	576276 kb
Host	smart-7d986f1d-fff7-43a4-be49-ebe15aba322a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863687786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.2863687786
Directory	/workspace/80.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2929055138
Short name	T2213
Test name
Test status
Simulation time	1237932634 ps
CPU time	46.14 seconds
Started	Jul 24 07:46:13 PM PDT 24
Finished	Jul 24 07:46:59 PM PDT 24
Peak memory	576164 kb
Host	smart-3d6863bb-fc69-47b3-a36c-c7d3860dfa5d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929055138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.2929055138
Directory	/workspace/80.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_random.692049998
Short name	T2198
Test name
Test status
Simulation time	399269616 ps
CPU time	37.78 seconds
Started	Jul 24 07:46:18 PM PDT 24
Finished	Jul 24 07:46:56 PM PDT 24
Peak memory	576140 kb
Host	smart-22e8869e-7302-46b0-83a6-a3a379f67c8e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692049998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.692049998
Directory	/workspace/80.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2662390423
Short name	T2465
Test name
Test status
Simulation time	53326030903 ps
CPU time	562.03 seconds
Started	Jul 24 07:46:03 PM PDT 24
Finished	Jul 24 07:55:25 PM PDT 24
Peak memory	576332 kb
Host	smart-efd4b061-70f1-4920-a21e-a2043af42d9b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662390423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2662390423
Directory	/workspace/80.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.939219017
Short name	T522
Test name
Test status
Simulation time	63103268334 ps
CPU time	1030.48 seconds
Started	Jul 24 07:46:04 PM PDT 24
Finished	Jul 24 08:03:15 PM PDT 24
Peak memory	576280 kb
Host	smart-917f3133-cbad-4fcb-aa3e-9f63d8a11d27
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939219017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.939219017
Directory	/workspace/80.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.2159595679
Short name	T2637
Test name
Test status
Simulation time	463492253 ps
CPU time	38.13 seconds
Started	Jul 24 07:46:16 PM PDT 24
Finished	Jul 24 07:46:54 PM PDT 24
Peak memory	576972 kb
Host	smart-12906592-15c9-4bb3-9bab-6015fafe0009
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159595679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.2159595679
Directory	/workspace/80.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_same_source.2511982848
Short name	T2791
Test name
Test status
Simulation time	1772053796 ps
CPU time	51.53 seconds
Started	Jul 24 07:46:04 PM PDT 24
Finished	Jul 24 07:46:55 PM PDT 24
Peak memory	576192 kb
Host	smart-24ccc059-82bc-4e2d-b0ae-d0758bb7c8ee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511982848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.2511982848
Directory	/workspace/80.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke.646487999
Short name	T2379
Test name
Test status
Simulation time	151038181 ps
CPU time	8.34 seconds
Started	Jul 24 07:46:07 PM PDT 24
Finished	Jul 24 07:46:15 PM PDT 24
Peak memory	574848 kb
Host	smart-422253ff-53ef-4cd0-a8ab-8e0b7d787cda
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646487999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.646487999
Directory	/workspace/80.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1043282941
Short name	T2147
Test name
Test status
Simulation time	6255531843 ps
CPU time	66.22 seconds
Started	Jul 24 07:46:16 PM PDT 24
Finished	Jul 24 07:47:22 PM PDT 24
Peak memory	575028 kb
Host	smart-9fc6d33e-d820-4756-83d5-37deb827529a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043282941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1043282941
Directory	/workspace/80.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.190778333
Short name	T1650
Test name
Test status
Simulation time	4791243074 ps
CPU time	80.63 seconds
Started	Jul 24 07:46:18 PM PDT 24
Finished	Jul 24 07:47:39 PM PDT 24
Peak memory	574996 kb
Host	smart-ae841f15-05cd-423b-a4d5-8acf8ecdc110
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190778333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.190778333
Directory	/workspace/80.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3053595247
Short name	T1493
Test name
Test status
Simulation time	48008488 ps
CPU time	6.51 seconds
Started	Jul 24 07:46:05 PM PDT 24
Finished	Jul 24 07:46:12 PM PDT 24
Peak memory	574892 kb
Host	smart-7641bf46-4ee1-44d1-b4fb-ee7fc9f3b6fb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053595247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.3053595247
Directory	/workspace/80.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all.2941944539
Short name	T2653
Test name
Test status
Simulation time	10312471761 ps
CPU time	383.24 seconds
Started	Jul 24 07:46:17 PM PDT 24
Finished	Jul 24 07:52:40 PM PDT 24
Peak memory	576412 kb
Host	smart-32ccf044-10bc-4cf1-be43-52a14e235919
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941944539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.2941944539
Directory	/workspace/80.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.460575520
Short name	T2665
Test name
Test status
Simulation time	12025020342 ps
CPU time	383.35 seconds
Started	Jul 24 07:46:06 PM PDT 24
Finished	Jul 24 07:52:30 PM PDT 24
Peak memory	576404 kb
Host	smart-e7cd4629-fa22-4b86-b4c9-9baf5141ff3b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460575520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.460575520
Directory	/workspace/80.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2878670724
Short name	T947
Test name
Test status
Simulation time	211702847 ps
CPU time	58.75 seconds
Started	Jul 24 07:46:16 PM PDT 24
Finished	Jul 24 07:47:15 PM PDT 24
Peak memory	576344 kb
Host	smart-cd86bc27-59d6-4faf-8882-c3dcbd4b8885
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878670724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2878670724
Directory	/workspace/80.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1016150739
Short name	T968
Test name
Test status
Simulation time	9777005740 ps
CPU time	623.76 seconds
Started	Jul 24 07:46:18 PM PDT 24
Finished	Jul 24 07:56:43 PM PDT 24
Peak memory	577252 kb
Host	smart-da403b79-5e74-4f20-9a71-08b5a5ff834d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016150739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.1016150739
Directory	/workspace/80.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.504236295
Short name	T2652
Test name
Test status
Simulation time	301216401 ps
CPU time	30.51 seconds
Started	Jul 24 07:46:05 PM PDT 24
Finished	Jul 24 07:46:36 PM PDT 24
Peak memory	577192 kb
Host	smart-bc63a388-1954-42ab-b753-2b4bb24a2538
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504236295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.504236295
Directory	/workspace/80.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_access_same_device.245803484
Short name	T1598
Test name
Test status
Simulation time	1433578066 ps
CPU time	59.84 seconds
Started	Jul 24 07:46:12 PM PDT 24
Finished	Jul 24 07:47:11 PM PDT 24
Peak memory	577020 kb
Host	smart-bf22157e-891c-432b-8e90-7a679796d970
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245803484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device. 245803484
Directory	/workspace/81.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.2161465750
Short name	T2034
Test name
Test status
Simulation time	544939638 ps
CPU time	28.16 seconds
Started	Jul 24 07:46:18 PM PDT 24
Finished	Jul 24 07:46:47 PM PDT 24
Peak memory	576164 kb
Host	smart-6f34c1a2-1f91-49a3-b8d6-aa6f8b5f3784
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161465750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.2161465750
Directory	/workspace/81.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_error_random.2773579564
Short name	T2262
Test name
Test status
Simulation time	1561602245 ps
CPU time	59.75 seconds
Started	Jul 24 07:46:18 PM PDT 24
Finished	Jul 24 07:47:18 PM PDT 24
Peak memory	577008 kb
Host	smart-4708b276-83cb-4f09-85f9-bc5f87a28e6e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773579564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.2773579564
Directory	/workspace/81.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_random.1718760454
Short name	T2149
Test name
Test status
Simulation time	381527727 ps
CPU time	15.47 seconds
Started	Jul 24 07:46:32 PM PDT 24
Finished	Jul 24 07:46:48 PM PDT 24
Peak memory	576992 kb
Host	smart-ace6618c-039f-48d7-b8e5-d415839b60bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718760454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.1718760454
Directory	/workspace/81.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_random_large_delays.3504091613
Short name	T1761
Test name
Test status
Simulation time	71162734879 ps
CPU time	846.36 seconds
Started	Jul 24 07:46:32 PM PDT 24
Finished	Jul 24 08:00:39 PM PDT 24
Peak memory	576296 kb
Host	smart-013a7197-4dff-40aa-a26d-14269c7f1802
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504091613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.3504091613
Directory	/workspace/81.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.109609642
Short name	T1574
Test name
Test status
Simulation time	42793830063 ps
CPU time	735.46 seconds
Started	Jul 24 07:46:12 PM PDT 24
Finished	Jul 24 07:58:28 PM PDT 24
Peak memory	577100 kb
Host	smart-0225d066-4fab-4ccd-8ed8-e99ec79c325e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109609642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.109609642
Directory	/workspace/81.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.1112608903
Short name	T1873
Test name
Test status
Simulation time	406384032 ps
CPU time	33.7 seconds
Started	Jul 24 07:46:12 PM PDT 24
Finished	Jul 24 07:46:46 PM PDT 24
Peak memory	577016 kb
Host	smart-edae1fce-c496-4e94-ae61-e05156320cca
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112608903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.1112608903
Directory	/workspace/81.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_same_source.4220595051
Short name	T592
Test name
Test status
Simulation time	2321254102 ps
CPU time	61.28 seconds
Started	Jul 24 07:46:35 PM PDT 24
Finished	Jul 24 07:47:36 PM PDT 24
Peak memory	576280 kb
Host	smart-297a4fb7-819f-4059-b09e-d83ea61cb15d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220595051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.4220595051
Directory	/workspace/81.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke.628896164
Short name	T715
Test name
Test status
Simulation time	51790703 ps
CPU time	6.25 seconds
Started	Jul 24 07:46:05 PM PDT 24
Finished	Jul 24 07:46:12 PM PDT 24
Peak memory	574868 kb
Host	smart-923bbb30-0390-4c3b-a3b0-561b122f2b96
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628896164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.628896164
Directory	/workspace/81.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.470650251
Short name	T2674
Test name
Test status
Simulation time	6786995557 ps
CPU time	68.99 seconds
Started	Jul 24 07:46:31 PM PDT 24
Finished	Jul 24 07:47:40 PM PDT 24
Peak memory	574992 kb
Host	smart-ba462d33-e006-4f69-b39b-2173ce85ad48
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470650251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.470650251
Directory	/workspace/81.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2149326926
Short name	T2253
Test name
Test status
Simulation time	5691319874 ps
CPU time	94.39 seconds
Started	Jul 24 07:46:14 PM PDT 24
Finished	Jul 24 07:47:48 PM PDT 24
Peak memory	574976 kb
Host	smart-c8c05b87-4d7c-4868-abd9-7c0124857be5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149326926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2149326926
Directory	/workspace/81.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2042776589
Short name	T1507
Test name
Test status
Simulation time	53955554 ps
CPU time	6.47 seconds
Started	Jul 24 07:46:16 PM PDT 24
Finished	Jul 24 07:46:23 PM PDT 24
Peak memory	576124 kb
Host	smart-064f2348-dfda-40c8-b460-a1594f1b9f72
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042776589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.2042776589
Directory	/workspace/81.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all.3153406550
Short name	T2245
Test name
Test status
Simulation time	2785606450 ps
CPU time	257.32 seconds
Started	Jul 24 07:46:13 PM PDT 24
Finished	Jul 24 07:50:31 PM PDT 24
Peak memory	576428 kb
Host	smart-2d0653d3-834d-4f8d-b792-921fa196342b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153406550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.3153406550
Directory	/workspace/81.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.1748350194
Short name	T2427
Test name
Test status
Simulation time	2694788932 ps
CPU time	222.95 seconds
Started	Jul 24 07:46:14 PM PDT 24
Finished	Jul 24 07:49:57 PM PDT 24
Peak memory	577264 kb
Host	smart-1dd59e8b-5801-4fe5-8446-4e5a01d36384
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748350194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1748350194
Directory	/workspace/81.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.2248803343
Short name	T2112
Test name
Test status
Simulation time	210269389 ps
CPU time	130.26 seconds
Started	Jul 24 07:46:21 PM PDT 24
Finished	Jul 24 07:48:32 PM PDT 24
Peak memory	576356 kb
Host	smart-090cc222-3af3-45d4-993b-7f167ffc98be
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248803343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.2248803343
Directory	/workspace/81.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3719500200
Short name	T927
Test name
Test status
Simulation time	301589347 ps
CPU time	79.24 seconds
Started	Jul 24 07:46:32 PM PDT 24
Finished	Jul 24 07:47:51 PM PDT 24
Peak memory	576332 kb
Host	smart-d4110629-58ad-4b46-b834-7ab47b4e890a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719500200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.3719500200
Directory	/workspace/81.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.2105634757
Short name	T1960
Test name
Test status
Simulation time	199147770 ps
CPU time	27.14 seconds
Started	Jul 24 07:46:19 PM PDT 24
Finished	Jul 24 07:46:46 PM PDT 24
Peak memory	576204 kb
Host	smart-e5e0a1f0-d28d-4f48-8adf-2f6f5dfa7084
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105634757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.2105634757
Directory	/workspace/81.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_access_same_device.2148630955
Short name	T421
Test name
Test status
Simulation time	1689308393 ps
CPU time	66.23 seconds
Started	Jul 24 07:46:20 PM PDT 24
Finished	Jul 24 07:47:26 PM PDT 24
Peak memory	577060 kb
Host	smart-55eb6bf6-fd86-4750-b3a0-d1eab31e318c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148630955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .2148630955
Directory	/workspace/82.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.330447580
Short name	T2122
Test name
Test status
Simulation time	50676686096 ps
CPU time	866.83 seconds
Started	Jul 24 07:46:19 PM PDT 24
Finished	Jul 24 08:00:46 PM PDT 24
Peak memory	577148 kb
Host	smart-185f8397-3d48-466d-96a9-412e19ab13e6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330447580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_d evice_slow_rsp.330447580
Directory	/workspace/82.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.3191148566
Short name	T2298
Test name
Test status
Simulation time	1280648810 ps
CPU time	40.74 seconds
Started	Jul 24 07:46:23 PM PDT 24
Finished	Jul 24 07:47:04 PM PDT 24
Peak memory	577012 kb
Host	smart-6c1be167-7fd2-47d1-8445-8ebaedd2c784
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191148566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.3191148566
Directory	/workspace/82.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_error_random.729571087
Short name	T2443
Test name
Test status
Simulation time	1432311262 ps
CPU time	49.74 seconds
Started	Jul 24 07:46:23 PM PDT 24
Finished	Jul 24 07:47:13 PM PDT 24
Peak memory	576232 kb
Host	smart-9d945980-e609-4294-a339-e25f3f90aafb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729571087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.729571087
Directory	/workspace/82.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_random.3129380738
Short name	T533
Test name
Test status
Simulation time	516846991 ps
CPU time	53.25 seconds
Started	Jul 24 07:46:19 PM PDT 24
Finished	Jul 24 07:47:12 PM PDT 24
Peak memory	577032 kb
Host	smart-7ac20b2a-9a22-4e5e-bf81-fcfd0550b7ac
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129380738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.3129380738
Directory	/workspace/82.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_random_large_delays.1051477747
Short name	T2785
Test name
Test status
Simulation time	65640478038 ps
CPU time	663.78 seconds
Started	Jul 24 07:46:35 PM PDT 24
Finished	Jul 24 07:57:39 PM PDT 24
Peak memory	577112 kb
Host	smart-36709520-77fb-4214-88e5-a780e20f55cc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051477747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.1051477747
Directory	/workspace/82.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.1153253731
Short name	T2088
Test name
Test status
Simulation time	48556259611 ps
CPU time	799.14 seconds
Started	Jul 24 07:46:23 PM PDT 24
Finished	Jul 24 07:59:43 PM PDT 24
Peak memory	576280 kb
Host	smart-45cfe37a-79f5-4fab-add4-6fd2eb33e668
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153253731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.1153253731
Directory	/workspace/82.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.595181743
Short name	T602
Test name
Test status
Simulation time	602070043 ps
CPU time	49.4 seconds
Started	Jul 24 07:46:22 PM PDT 24
Finished	Jul 24 07:47:12 PM PDT 24
Peak memory	577036 kb
Host	smart-91b74957-94dc-4f36-bfd5-155ffe3bc12f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595181743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_dela ys.595181743
Directory	/workspace/82.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_same_source.2977880083
Short name	T1799
Test name
Test status
Simulation time	288409294 ps
CPU time	10.85 seconds
Started	Jul 24 07:46:20 PM PDT 24
Finished	Jul 24 07:46:31 PM PDT 24
Peak memory	576212 kb
Host	smart-2f3117ac-48bf-44f6-a6b9-64d342b751ec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977880083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.2977880083
Directory	/workspace/82.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke.1505034105
Short name	T1753
Test name
Test status
Simulation time	219338748 ps
CPU time	9.5 seconds
Started	Jul 24 07:46:13 PM PDT 24
Finished	Jul 24 07:46:22 PM PDT 24
Peak memory	576188 kb
Host	smart-9f417b97-aaa8-4d07-a79c-fb70912cd47e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505034105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.1505034105
Directory	/workspace/82.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.2516377399
Short name	T2415
Test name
Test status
Simulation time	9233391095 ps
CPU time	98.51 seconds
Started	Jul 24 07:46:32 PM PDT 24
Finished	Jul 24 07:48:10 PM PDT 24
Peak memory	575064 kb
Host	smart-6fc6b7ed-84ed-40c5-9603-a352bf38ab5a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516377399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.2516377399
Directory	/workspace/82.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.3618879228
Short name	T1692
Test name
Test status
Simulation time	5682460560 ps
CPU time	90.71 seconds
Started	Jul 24 07:46:33 PM PDT 24
Finished	Jul 24 07:48:03 PM PDT 24
Peak memory	576276 kb
Host	smart-5f6111e1-5b02-417a-876a-4ad3161e928b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618879228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.3618879228
Directory	/workspace/82.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.469541791
Short name	T2278
Test name
Test status
Simulation time	53142504 ps
CPU time	6.49 seconds
Started	Jul 24 07:46:13 PM PDT 24
Finished	Jul 24 07:46:20 PM PDT 24
Peak memory	574820 kb
Host	smart-bb0b8251-fab3-4ce6-8268-431f99f80bbe
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469541791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays .469541791
Directory	/workspace/82.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all.2906130078
Short name	T537
Test name
Test status
Simulation time	13510888647 ps
CPU time	520.5 seconds
Started	Jul 24 07:46:22 PM PDT 24
Finished	Jul 24 07:55:02 PM PDT 24
Peak memory	577284 kb
Host	smart-b7006e1c-734c-45fd-9302-0648535a7441
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906130078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.2906130078
Directory	/workspace/82.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.123070383
Short name	T2884
Test name
Test status
Simulation time	1596452551 ps
CPU time	60.63 seconds
Started	Jul 24 07:46:24 PM PDT 24
Finished	Jul 24 07:47:25 PM PDT 24
Peak memory	577016 kb
Host	smart-92fb9d48-923b-473f-aedf-43bf11662c81
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123070383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.123070383
Directory	/workspace/82.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2645220461
Short name	T2754
Test name
Test status
Simulation time	486368497 ps
CPU time	163.79 seconds
Started	Jul 24 07:46:35 PM PDT 24
Finished	Jul 24 07:49:19 PM PDT 24
Peak memory	577164 kb
Host	smart-ee1883d8-7252-4ae1-849e-74de695ebedc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645220461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.2645220461
Directory	/workspace/82.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.441486985
Short name	T2531
Test name
Test status
Simulation time	236746126 ps
CPU time	98.5 seconds
Started	Jul 24 07:46:28 PM PDT 24
Finished	Jul 24 07:48:07 PM PDT 24
Peak memory	576312 kb
Host	smart-0c7810e2-a7a6-449b-b03c-b6e637dc7b31
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441486985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_reset_error.441486985
Directory	/workspace/82.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.3062076690
Short name	T1756
Test name
Test status
Simulation time	992826153 ps
CPU time	38.15 seconds
Started	Jul 24 07:46:21 PM PDT 24
Finished	Jul 24 07:46:59 PM PDT 24
Peak memory	577076 kb
Host	smart-902b9304-09c6-4ab6-96f9-97bb335957a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062076690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.3062076690
Directory	/workspace/82.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_access_same_device.2090750252
Short name	T2724
Test name
Test status
Simulation time	2444527168 ps
CPU time	100.9 seconds
Started	Jul 24 07:46:20 PM PDT 24
Finished	Jul 24 07:48:01 PM PDT 24
Peak memory	577284 kb
Host	smart-c12a33cf-9d50-4d07-a1cf-e2834ba5916f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090750252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .2090750252
Directory	/workspace/83.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2329281556
Short name	T2584
Test name
Test status
Simulation time	122999289143 ps
CPU time	2143.33 seconds
Started	Jul 24 07:46:28 PM PDT 24
Finished	Jul 24 08:22:12 PM PDT 24
Peak memory	577208 kb
Host	smart-d315caf4-177c-43b2-90ca-a8a6a9a20280
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329281556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.2329281556
Directory	/workspace/83.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2383342325
Short name	T2331
Test name
Test status
Simulation time	775304068 ps
CPU time	31.42 seconds
Started	Jul 24 07:46:31 PM PDT 24
Finished	Jul 24 07:47:02 PM PDT 24
Peak memory	576972 kb
Host	smart-0c86bf9d-12fa-418f-bc3c-81417bc5e2c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383342325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.2383342325
Directory	/workspace/83.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_error_random.2920480153
Short name	T1524
Test name
Test status
Simulation time	224749500 ps
CPU time	21.05 seconds
Started	Jul 24 07:46:20 PM PDT 24
Finished	Jul 24 07:46:41 PM PDT 24
Peak memory	576156 kb
Host	smart-2e7ae81b-f376-42e5-b920-638993ec12ab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920480153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.2920480153
Directory	/workspace/83.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_random.3299545688
Short name	T569
Test name
Test status
Simulation time	176983107 ps
CPU time	9.34 seconds
Started	Jul 24 07:46:21 PM PDT 24
Finished	Jul 24 07:46:30 PM PDT 24
Peak memory	576124 kb
Host	smart-1e9ba4ac-b67a-499e-bf1c-584d5d789f3c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299545688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.3299545688
Directory	/workspace/83.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_random_large_delays.2401278330
Short name	T2859
Test name
Test status
Simulation time	47560103661 ps
CPU time	523.92 seconds
Started	Jul 24 07:46:20 PM PDT 24
Finished	Jul 24 07:55:05 PM PDT 24
Peak memory	577188 kb
Host	smart-31d049f1-e836-42e0-8675-674c6cc9580e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401278330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.2401278330
Directory	/workspace/83.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.2194451505
Short name	T2563
Test name
Test status
Simulation time	38315483680 ps
CPU time	749.63 seconds
Started	Jul 24 07:46:22 PM PDT 24
Finished	Jul 24 07:58:52 PM PDT 24
Peak memory	576316 kb
Host	smart-583f587f-3056-4eee-92e4-8eb7488ba000
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194451505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.2194451505
Directory	/workspace/83.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1133566757
Short name	T2534
Test name
Test status
Simulation time	636720747 ps
CPU time	50.7 seconds
Started	Jul 24 07:46:34 PM PDT 24
Finished	Jul 24 07:47:25 PM PDT 24
Peak memory	577024 kb
Host	smart-3b9d6e6e-bb04-40b2-bcd4-dd6bd79d57ac
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133566757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1133566757
Directory	/workspace/83.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_same_source.3020409676
Short name	T2565
Test name
Test status
Simulation time	170344245 ps
CPU time	7.84 seconds
Started	Jul 24 07:46:24 PM PDT 24
Finished	Jul 24 07:46:32 PM PDT 24
Peak memory	574880 kb
Host	smart-1061b64c-5c88-4880-b648-6cf3a1408c47
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020409676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.3020409676
Directory	/workspace/83.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke.1080077450
Short name	T2829
Test name
Test status
Simulation time	48364088 ps
CPU time	6.41 seconds
Started	Jul 24 07:46:24 PM PDT 24
Finished	Jul 24 07:46:31 PM PDT 24
Peak memory	574948 kb
Host	smart-b2217805-be19-4b9c-91f1-62bd87456899
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080077450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.1080077450
Directory	/workspace/83.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.476386580
Short name	T2211
Test name
Test status
Simulation time	8004255864 ps
CPU time	80.56 seconds
Started	Jul 24 07:46:24 PM PDT 24
Finished	Jul 24 07:47:44 PM PDT 24
Peak memory	575064 kb
Host	smart-e504e8ac-175c-4bd2-b103-c5478e7f30fd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476386580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.476386580
Directory	/workspace/83.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1296779269
Short name	T1739
Test name
Test status
Simulation time	5030695443 ps
CPU time	79.28 seconds
Started	Jul 24 07:46:20 PM PDT 24
Finished	Jul 24 07:47:39 PM PDT 24
Peak memory	574956 kb
Host	smart-f3112caa-21c7-4281-8b1b-8183f1b252c7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296779269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.1296779269
Directory	/workspace/83.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.2040278421
Short name	T2317
Test name
Test status
Simulation time	44824773 ps
CPU time	6.06 seconds
Started	Jul 24 07:46:25 PM PDT 24
Finished	Jul 24 07:46:31 PM PDT 24
Peak memory	576064 kb
Host	smart-1c82615d-0f62-4617-b710-3e886d6af71c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040278421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.2040278421
Directory	/workspace/83.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all.1689999259
Short name	T1816
Test name
Test status
Simulation time	7805762188 ps
CPU time	305.66 seconds
Started	Jul 24 07:46:29 PM PDT 24
Finished	Jul 24 07:51:35 PM PDT 24
Peak memory	576444 kb
Host	smart-241af8dd-3333-4707-9681-6282df388540
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689999259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.1689999259
Directory	/workspace/83.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.3444824602
Short name	T1681
Test name
Test status
Simulation time	1997504943 ps
CPU time	163.61 seconds
Started	Jul 24 07:46:30 PM PDT 24
Finished	Jul 24 07:49:13 PM PDT 24
Peak memory	577108 kb
Host	smart-1c5327a9-62c8-4374-995a-49873498b3f1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444824602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.3444824602
Directory	/workspace/83.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.472170997
Short name	T2049
Test name
Test status
Simulation time	399660671 ps
CPU time	129.06 seconds
Started	Jul 24 07:46:31 PM PDT 24
Finished	Jul 24 07:48:40 PM PDT 24
Peak memory	577176 kb
Host	smart-56d88083-a333-4484-9ce0-bcb1021d2158
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472170997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_ with_rand_reset.472170997
Directory	/workspace/83.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.1378185078
Short name	T955
Test name
Test status
Simulation time	26649688034 ps
CPU time	918.44 seconds
Started	Jul 24 07:46:30 PM PDT 24
Finished	Jul 24 08:01:49 PM PDT 24
Peak memory	583328 kb
Host	smart-326f232e-5870-437a-893a-1579a02eb3ce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378185078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.1378185078
Directory	/workspace/83.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.689576663
Short name	T1888
Test name
Test status
Simulation time	668193721 ps
CPU time	30.69 seconds
Started	Jul 24 07:46:20 PM PDT 24
Finished	Jul 24 07:46:51 PM PDT 24
Peak memory	576252 kb
Host	smart-7035c32a-299c-45b3-bcd5-27abfce88179
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689576663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.689576663
Directory	/workspace/83.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_access_same_device.3533604188
Short name	T2381
Test name
Test status
Simulation time	3609066614 ps
CPU time	137.93 seconds
Started	Jul 24 07:47:36 PM PDT 24
Finished	Jul 24 07:49:54 PM PDT 24
Peak memory	577132 kb
Host	smart-63a95410-5f8d-4e1d-8db4-da97d3075bfa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533604188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .3533604188
Directory	/workspace/84.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2089516675
Short name	T1664
Test name
Test status
Simulation time	82196685171 ps
CPU time	1364.75 seconds
Started	Jul 24 07:46:28 PM PDT 24
Finished	Jul 24 08:09:13 PM PDT 24
Peak memory	576408 kb
Host	smart-1e45172e-19b8-4180-85de-954448b86fae
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089516675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.2089516675
Directory	/workspace/84.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1997867419
Short name	T2058
Test name
Test status
Simulation time	1368980039 ps
CPU time	52.66 seconds
Started	Jul 24 07:46:41 PM PDT 24
Finished	Jul 24 07:47:33 PM PDT 24
Peak memory	576080 kb
Host	smart-c7fc31fe-2ca4-4448-92c9-3435f7a2bcf0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997867419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.1997867419
Directory	/workspace/84.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_error_random.2610026154
Short name	T1738
Test name
Test status
Simulation time	590754474 ps
CPU time	49.57 seconds
Started	Jul 24 07:47:33 PM PDT 24
Finished	Jul 24 07:48:23 PM PDT 24
Peak memory	576136 kb
Host	smart-85b92573-0f13-47fa-ba9d-93c76ba734df
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610026154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.2610026154
Directory	/workspace/84.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_random.1814867127
Short name	T655
Test name
Test status
Simulation time	1735184614 ps
CPU time	61.63 seconds
Started	Jul 24 07:46:31 PM PDT 24
Finished	Jul 24 07:47:32 PM PDT 24
Peak memory	577076 kb
Host	smart-c05284ef-4d4f-40d6-9f33-4a45cec15dba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814867127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.1814867127
Directory	/workspace/84.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_random_large_delays.2527097241
Short name	T652
Test name
Test status
Simulation time	70076179949 ps
CPU time	797.1 seconds
Started	Jul 24 07:46:34 PM PDT 24
Finished	Jul 24 07:59:51 PM PDT 24
Peak memory	576300 kb
Host	smart-73813029-335d-4120-9103-1d99aaf03d1b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527097241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.2527097241
Directory	/workspace/84.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.90220004
Short name	T1584
Test name
Test status
Simulation time	23236016757 ps
CPU time	405.96 seconds
Started	Jul 24 07:46:33 PM PDT 24
Finished	Jul 24 07:53:19 PM PDT 24
Peak memory	576316 kb
Host	smart-441c4d0c-0308-428c-8b7e-6e447aab238a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90220004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.90220004
Directory	/workspace/84.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.1096398151
Short name	T2223
Test name
Test status
Simulation time	424692842 ps
CPU time	39.15 seconds
Started	Jul 24 07:46:33 PM PDT 24
Finished	Jul 24 07:47:12 PM PDT 24
Peak memory	576976 kb
Host	smart-400812c1-2b04-4583-a982-c448bca8ad9c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096398151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.1096398151
Directory	/workspace/84.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_same_source.2990428113
Short name	T504
Test name
Test status
Simulation time	2561872394 ps
CPU time	81.63 seconds
Started	Jul 24 07:46:32 PM PDT 24
Finished	Jul 24 07:47:53 PM PDT 24
Peak memory	576300 kb
Host	smart-39bac896-e2fb-45ac-9691-b54f3dabdbb6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990428113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.2990428113
Directory	/workspace/84.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke.223865721
Short name	T570
Test name
Test status
Simulation time	56980803 ps
CPU time	6.64 seconds
Started	Jul 24 07:46:33 PM PDT 24
Finished	Jul 24 07:46:40 PM PDT 24
Peak memory	574940 kb
Host	smart-93ffc0e6-0c7a-4c3b-965d-18b93ae4b1ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223865721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.223865721
Directory	/workspace/84.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1867805816
Short name	T1697
Test name
Test status
Simulation time	8823068049 ps
CPU time	90.38 seconds
Started	Jul 24 07:46:30 PM PDT 24
Finished	Jul 24 07:48:00 PM PDT 24
Peak memory	574976 kb
Host	smart-a1782aa9-8815-4248-99a1-bdea073632ec
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867805816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1867805816
Directory	/workspace/84.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3445475043
Short name	T1492
Test name
Test status
Simulation time	3542747804 ps
CPU time	58.8 seconds
Started	Jul 24 07:46:28 PM PDT 24
Finished	Jul 24 07:47:27 PM PDT 24
Peak memory	575088 kb
Host	smart-9bce93bb-f88f-49cd-acfa-da38fe2136b6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445475043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.3445475043
Directory	/workspace/84.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1678936887
Short name	T2557
Test name
Test status
Simulation time	51434344 ps
CPU time	6.5 seconds
Started	Jul 24 07:46:30 PM PDT 24
Finished	Jul 24 07:46:37 PM PDT 24
Peak memory	576088 kb
Host	smart-aee9d3b0-7912-4e44-9883-6f0502a524c0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678936887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.1678936887
Directory	/workspace/84.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all.3366706356
Short name	T2571
Test name
Test status
Simulation time	8559524718 ps
CPU time	349.15 seconds
Started	Jul 24 07:46:42 PM PDT 24
Finished	Jul 24 07:52:31 PM PDT 24
Peak memory	577184 kb
Host	smart-ca29524f-beaa-4ed6-a06e-c855e3f649cb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366706356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.3366706356
Directory	/workspace/84.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.3429074707
Short name	T1731
Test name
Test status
Simulation time	3065456645 ps
CPU time	101.09 seconds
Started	Jul 24 07:46:39 PM PDT 24
Finished	Jul 24 07:48:20 PM PDT 24
Peak memory	576252 kb
Host	smart-03f3772b-dd3e-428b-ae3c-fb13c3423120
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429074707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.3429074707
Directory	/workspace/84.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.1022810850
Short name	T478
Test name
Test status
Simulation time	13546596619 ps
CPU time	657.45 seconds
Started	Jul 24 07:46:37 PM PDT 24
Finished	Jul 24 07:57:35 PM PDT 24
Peak memory	576488 kb
Host	smart-1eb6d878-9b7a-48d4-92a3-de72d8cf97e2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022810850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.1022810850
Directory	/workspace/84.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.3032427039
Short name	T2056
Test name
Test status
Simulation time	280370376 ps
CPU time	78.78 seconds
Started	Jul 24 07:46:42 PM PDT 24
Finished	Jul 24 07:48:01 PM PDT 24
Peak memory	577172 kb
Host	smart-03428828-8ed0-44e0-b0bf-344b93289343
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032427039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.3032427039
Directory	/workspace/84.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.654903588
Short name	T2302
Test name
Test status
Simulation time	682661792 ps
CPU time	28.59 seconds
Started	Jul 24 07:46:42 PM PDT 24
Finished	Jul 24 07:47:11 PM PDT 24
Peak memory	577076 kb
Host	smart-3087c4da-9551-438e-afc6-241882cc2661
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654903588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.654903588
Directory	/workspace/84.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_access_same_device.2592896717
Short name	T943
Test name
Test status
Simulation time	2476623703 ps
CPU time	96.23 seconds
Started	Jul 24 07:46:51 PM PDT 24
Finished	Jul 24 07:48:27 PM PDT 24
Peak memory	576360 kb
Host	smart-73e66a56-b247-4db9-8999-10ff873402de
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592896717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .2592896717
Directory	/workspace/85.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.2356527760
Short name	T2599
Test name
Test status
Simulation time	72242437941 ps
CPU time	1359.73 seconds
Started	Jul 24 07:46:46 PM PDT 24
Finished	Jul 24 08:09:26 PM PDT 24
Peak memory	576280 kb
Host	smart-9e6e6fde-512f-458d-991c-8fb2f10615b1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356527760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.2356527760
Directory	/workspace/85.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1660607935
Short name	T2270
Test name
Test status
Simulation time	1140868826 ps
CPU time	46.99 seconds
Started	Jul 24 07:46:53 PM PDT 24
Finished	Jul 24 07:47:41 PM PDT 24
Peak memory	575944 kb
Host	smart-0f3acbbe-48b9-4d86-8f62-bd71bd812500
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660607935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1660607935
Directory	/workspace/85.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_error_random.3799828716
Short name	T2432
Test name
Test status
Simulation time	2007337903 ps
CPU time	72.63 seconds
Started	Jul 24 07:46:49 PM PDT 24
Finished	Jul 24 07:48:02 PM PDT 24
Peak memory	576116 kb
Host	smart-f9a9c738-1d39-40ca-aacd-5b5d1b978007
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799828716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.3799828716
Directory	/workspace/85.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_random.367910812
Short name	T1962
Test name
Test status
Simulation time	171414594 ps
CPU time	9.82 seconds
Started	Jul 24 07:46:42 PM PDT 24
Finished	Jul 24 07:46:52 PM PDT 24
Peak memory	574856 kb
Host	smart-87843307-0e50-4a13-8ad4-21debe973999
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367910812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.367910812
Directory	/workspace/85.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_random_large_delays.3075500573
Short name	T492
Test name
Test status
Simulation time	109386961375 ps
CPU time	1271.23 seconds
Started	Jul 24 07:46:37 PM PDT 24
Finished	Jul 24 08:07:49 PM PDT 24
Peak memory	576316 kb
Host	smart-6883ecb9-446b-4b7c-90d9-962feae522f2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075500573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.3075500573
Directory	/workspace/85.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.1749149119
Short name	T441
Test name
Test status
Simulation time	65257800286 ps
CPU time	1181.62 seconds
Started	Jul 24 07:46:49 PM PDT 24
Finished	Jul 24 08:06:31 PM PDT 24
Peak memory	576424 kb
Host	smart-6498aa58-2fc7-49d9-9dc6-c167cde5e7ff
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749149119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.1749149119
Directory	/workspace/85.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.1973806759
Short name	T1752
Test name
Test status
Simulation time	30920111 ps
CPU time	5.93 seconds
Started	Jul 24 07:46:40 PM PDT 24
Finished	Jul 24 07:46:46 PM PDT 24
Peak memory	574996 kb
Host	smart-e6fa93ae-6fd9-40de-b0f9-ad28a8801ff3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973806759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.1973806759
Directory	/workspace/85.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_same_source.1496424811
Short name	T2431
Test name
Test status
Simulation time	421795253 ps
CPU time	15.24 seconds
Started	Jul 24 07:46:46 PM PDT 24
Finished	Jul 24 07:47:02 PM PDT 24
Peak memory	576968 kb
Host	smart-46df6b6d-088a-4263-bf42-0b53741c42bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496424811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1496424811
Directory	/workspace/85.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke.250576759
Short name	T1469
Test name
Test status
Simulation time	49797060 ps
CPU time	6.1 seconds
Started	Jul 24 07:46:38 PM PDT 24
Finished	Jul 24 07:46:44 PM PDT 24
Peak memory	574888 kb
Host	smart-0aaa66fc-9789-4ecb-b9a8-a98d2e0b792b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250576759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.250576759
Directory	/workspace/85.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2950273015
Short name	T1644
Test name
Test status
Simulation time	6687317688 ps
CPU time	68.99 seconds
Started	Jul 24 07:46:38 PM PDT 24
Finished	Jul 24 07:47:47 PM PDT 24
Peak memory	576264 kb
Host	smart-b89e82ce-65e1-4db6-9b7e-8721318a8a26
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950273015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2950273015
Directory	/workspace/85.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.3495647992
Short name	T2562
Test name
Test status
Simulation time	4582259111 ps
CPU time	78.76 seconds
Started	Jul 24 07:46:39 PM PDT 24
Finished	Jul 24 07:47:58 PM PDT 24
Peak memory	575092 kb
Host	smart-fa72a378-9bee-45f1-97db-4e9b645b8710
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495647992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.3495647992
Directory	/workspace/85.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.227096620
Short name	T2277
Test name
Test status
Simulation time	55724070 ps
CPU time	6.6 seconds
Started	Jul 24 07:46:40 PM PDT 24
Finished	Jul 24 07:46:47 PM PDT 24
Peak memory	574904 kb
Host	smart-78badc94-19cb-4e8a-9fee-14fa67a3dca9
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227096620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays .227096620
Directory	/workspace/85.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all.242016994
Short name	T505
Test name
Test status
Simulation time	11583430085 ps
CPU time	385.8 seconds
Started	Jul 24 07:46:48 PM PDT 24
Finished	Jul 24 07:53:14 PM PDT 24
Peak memory	577264 kb
Host	smart-9964bf00-f650-43fe-9042-098be4c49790
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242016994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.242016994
Directory	/workspace/85.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.269595914
Short name	T2808
Test name
Test status
Simulation time	15321773428 ps
CPU time	571.79 seconds
Started	Jul 24 07:46:50 PM PDT 24
Finished	Jul 24 07:56:22 PM PDT 24
Peak memory	576400 kb
Host	smart-8681d24d-369f-4094-bc34-0bab805ef83a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269595914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.269595914
Directory	/workspace/85.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1600348998
Short name	T1867
Test name
Test status
Simulation time	7442784803 ps
CPU time	517.18 seconds
Started	Jul 24 07:46:53 PM PDT 24
Finished	Jul 24 07:55:31 PM PDT 24
Peak memory	576496 kb
Host	smart-50d7069f-a31d-4c58-9cfd-c438631c0523
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600348998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.1600348998
Directory	/workspace/85.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.1671361053
Short name	T966
Test name
Test status
Simulation time	193524298 ps
CPU time	65.09 seconds
Started	Jul 24 07:46:51 PM PDT 24
Finished	Jul 24 07:47:56 PM PDT 24
Peak memory	577248 kb
Host	smart-7e23dfe4-d18d-42cb-924c-e1c30db82630
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671361053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.1671361053
Directory	/workspace/85.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3814196536
Short name	T1789
Test name
Test status
Simulation time	730731723 ps
CPU time	31.93 seconds
Started	Jul 24 07:46:51 PM PDT 24
Finished	Jul 24 07:47:23 PM PDT 24
Peak memory	576336 kb
Host	smart-583aa2b7-394c-47b1-901a-178678b2a4bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814196536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3814196536
Directory	/workspace/85.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_access_same_device.3072839498
Short name	T2052
Test name
Test status
Simulation time	1077067308 ps
CPU time	80.96 seconds
Started	Jul 24 07:46:59 PM PDT 24
Finished	Jul 24 07:48:20 PM PDT 24
Peak memory	577008 kb
Host	smart-e5d36da5-4ed0-404e-b924-22ac1b56cd13
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072839498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .3072839498
Directory	/workspace/86.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3861699162
Short name	T2321
Test name
Test status
Simulation time	67408193242 ps
CPU time	1358.59 seconds
Started	Jul 24 07:47:00 PM PDT 24
Finished	Jul 24 08:09:39 PM PDT 24
Peak memory	577084 kb
Host	smart-615d958c-cba5-4c3b-9919-77c03f796590
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861699162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.3861699162
Directory	/workspace/86.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2841374810
Short name	T2491
Test name
Test status
Simulation time	208755676 ps
CPU time	23.55 seconds
Started	Jul 24 07:46:56 PM PDT 24
Finished	Jul 24 07:47:19 PM PDT 24
Peak memory	576168 kb
Host	smart-2d27e4bd-fd67-45e9-9eec-f7bd39a57b32
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841374810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.2841374810
Directory	/workspace/86.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_error_random.4250920930
Short name	T2333
Test name
Test status
Simulation time	585572070 ps
CPU time	52.61 seconds
Started	Jul 24 07:46:58 PM PDT 24
Finished	Jul 24 07:47:50 PM PDT 24
Peak memory	576968 kb
Host	smart-55fa7c70-0bfa-4af3-b2d6-da8d99c74c5f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250920930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.4250920930
Directory	/workspace/86.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_random.1743055125
Short name	T2353
Test name
Test status
Simulation time	553802142 ps
CPU time	19.95 seconds
Started	Jul 24 07:46:51 PM PDT 24
Finished	Jul 24 07:47:11 PM PDT 24
Peak memory	576992 kb
Host	smart-6f7d460a-0487-493f-ab5c-9d008570f804
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743055125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.1743055125
Directory	/workspace/86.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_random_large_delays.3894539703
Short name	T2411
Test name
Test status
Simulation time	34287895470 ps
CPU time	344.64 seconds
Started	Jul 24 07:46:46 PM PDT 24
Finished	Jul 24 07:52:31 PM PDT 24
Peak memory	576368 kb
Host	smart-dbcb4cd1-3743-4e05-a83f-033473baf264
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894539703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3894539703
Directory	/workspace/86.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.3993986175
Short name	T1501
Test name
Test status
Simulation time	1857419697 ps
CPU time	29.83 seconds
Started	Jul 24 07:46:57 PM PDT 24
Finished	Jul 24 07:47:27 PM PDT 24
Peak memory	574856 kb
Host	smart-8ab72ffb-bba0-475e-a3a1-18bab1e0c7e1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993986175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.3993986175
Directory	/workspace/86.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.2412657055
Short name	T580
Test name
Test status
Simulation time	661688132 ps
CPU time	62.52 seconds
Started	Jul 24 07:46:46 PM PDT 24
Finished	Jul 24 07:47:49 PM PDT 24
Peak memory	577044 kb
Host	smart-bc6a58b2-3f3f-4527-987c-62381c381f94
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412657055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.2412657055
Directory	/workspace/86.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_same_source.2480452938
Short name	T2920
Test name
Test status
Simulation time	2220095199 ps
CPU time	63.57 seconds
Started	Jul 24 07:46:59 PM PDT 24
Finished	Jul 24 07:48:03 PM PDT 24
Peak memory	576308 kb
Host	smart-4f037024-3520-431d-9609-c1f6bc40b14c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480452938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.2480452938
Directory	/workspace/86.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke.1766206567
Short name	T2825
Test name
Test status
Simulation time	268790995 ps
CPU time	10.48 seconds
Started	Jul 24 07:46:52 PM PDT 24
Finished	Jul 24 07:47:03 PM PDT 24
Peak memory	574908 kb
Host	smart-037981e1-2b22-4018-a32b-d504835a0f0c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766206567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.1766206567
Directory	/workspace/86.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.3980721080
Short name	T2894
Test name
Test status
Simulation time	8973273495 ps
CPU time	93.57 seconds
Started	Jul 24 07:46:49 PM PDT 24
Finished	Jul 24 07:48:23 PM PDT 24
Peak memory	576364 kb
Host	smart-34125a33-795b-4b71-a815-d54082ff8d23
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980721080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.3980721080
Directory	/workspace/86.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2699735338
Short name	T2125
Test name
Test status
Simulation time	4557458530 ps
CPU time	77.26 seconds
Started	Jul 24 07:46:47 PM PDT 24
Finished	Jul 24 07:48:05 PM PDT 24
Peak memory	575040 kb
Host	smart-dcadd649-b167-44fb-8cdb-2530adcee8ca
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699735338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.2699735338
Directory	/workspace/86.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2993720511
Short name	T1833
Test name
Test status
Simulation time	45413947 ps
CPU time	6.73 seconds
Started	Jul 24 07:46:47 PM PDT 24
Finished	Jul 24 07:46:54 PM PDT 24
Peak memory	574940 kb
Host	smart-b68877c9-9681-425f-9c7f-097a1b951720
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993720511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.2993720511
Directory	/workspace/86.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all.3387423218
Short name	T2085
Test name
Test status
Simulation time	76223417 ps
CPU time	8.43 seconds
Started	Jul 24 07:46:56 PM PDT 24
Finished	Jul 24 07:47:05 PM PDT 24
Peak memory	576984 kb
Host	smart-6174521d-5843-4cf4-8075-58860d4db8dc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387423218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.3387423218
Directory	/workspace/86.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.4165862283
Short name	T1971
Test name
Test status
Simulation time	2045317036 ps
CPU time	158.93 seconds
Started	Jul 24 07:46:54 PM PDT 24
Finished	Jul 24 07:49:33 PM PDT 24
Peak memory	576304 kb
Host	smart-32c6788f-79c2-415e-9028-85cdc8adf1ad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165862283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.4165862283
Directory	/workspace/86.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.573147894
Short name	T660
Test name
Test status
Simulation time	4365077883 ps
CPU time	385.77 seconds
Started	Jul 24 07:46:58 PM PDT 24
Finished	Jul 24 07:53:24 PM PDT 24
Peak memory	577220 kb
Host	smart-000a7643-7ac0-48cb-b443-f08ea327536d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573147894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_ with_rand_reset.573147894
Directory	/workspace/86.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.2777912867
Short name	T2585
Test name
Test status
Simulation time	810439092 ps
CPU time	93.7 seconds
Started	Jul 24 07:46:57 PM PDT 24
Finished	Jul 24 07:48:31 PM PDT 24
Peak memory	576320 kb
Host	smart-8af25d16-40bc-4305-afef-5e41d1e1cfcf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777912867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.2777912867
Directory	/workspace/86.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.799072052
Short name	T1850
Test name
Test status
Simulation time	160602294 ps
CPU time	9.45 seconds
Started	Jul 24 07:46:59 PM PDT 24
Finished	Jul 24 07:47:09 PM PDT 24
Peak memory	574920 kb
Host	smart-6cd426a2-0083-4f99-acae-615ff4819f17
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799072052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.799072052
Directory	/workspace/86.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_access_same_device.675850104
Short name	T899
Test name
Test status
Simulation time	166121986 ps
CPU time	14.79 seconds
Started	Jul 24 07:46:56 PM PDT 24
Finished	Jul 24 07:47:11 PM PDT 24
Peak memory	576952 kb
Host	smart-cf5c07bf-f10f-4aa3-9f11-275528fa04bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675850104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device. 675850104
Directory	/workspace/87.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1254602168
Short name	T2487
Test name
Test status
Simulation time	42126685306 ps
CPU time	728.95 seconds
Started	Jul 24 07:47:04 PM PDT 24
Finished	Jul 24 07:59:13 PM PDT 24
Peak memory	577176 kb
Host	smart-e523761b-9fa6-4f64-b6bb-3fd5716f700e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254602168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.1254602168
Directory	/workspace/87.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1346921787
Short name	T2060
Test name
Test status
Simulation time	211098917 ps
CPU time	10.57 seconds
Started	Jul 24 07:47:07 PM PDT 24
Finished	Jul 24 07:47:17 PM PDT 24
Peak memory	574968 kb
Host	smart-8dd33635-02cc-49ae-8148-1bbf096af6ce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346921787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.1346921787
Directory	/workspace/87.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_error_random.2070040701
Short name	T2166
Test name
Test status
Simulation time	2551733048 ps
CPU time	77.61 seconds
Started	Jul 24 07:47:04 PM PDT 24
Finished	Jul 24 07:48:22 PM PDT 24
Peak memory	577068 kb
Host	smart-be801ad4-b380-4427-a705-0b521be55c86
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070040701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.2070040701
Directory	/workspace/87.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_random.4144762438
Short name	T2456
Test name
Test status
Simulation time	461854472 ps
CPU time	17.66 seconds
Started	Jul 24 07:46:59 PM PDT 24
Finished	Jul 24 07:47:16 PM PDT 24
Peak memory	576240 kb
Host	smart-4e365ccf-8ab1-4364-8c11-1a1397e93f09
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144762438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.4144762438
Directory	/workspace/87.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_random_large_delays.1461409165
Short name	T798
Test name
Test status
Simulation time	26259182665 ps
CPU time	264.07 seconds
Started	Jul 24 07:46:56 PM PDT 24
Finished	Jul 24 07:51:20 PM PDT 24
Peak memory	577144 kb
Host	smart-44646836-8aef-42e5-b191-b1505d617ff7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461409165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.1461409165
Directory	/workspace/87.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.3226681263
Short name	T630
Test name
Test status
Simulation time	44915239909 ps
CPU time	829.22 seconds
Started	Jul 24 07:47:00 PM PDT 24
Finished	Jul 24 08:00:49 PM PDT 24
Peak memory	576300 kb
Host	smart-9578910e-6533-4cbd-9427-96ce240c1ba4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226681263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.3226681263
Directory	/workspace/87.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.4220731074
Short name	T1534
Test name
Test status
Simulation time	32481555 ps
CPU time	5.87 seconds
Started	Jul 24 07:46:55 PM PDT 24
Finished	Jul 24 07:47:02 PM PDT 24
Peak memory	575012 kb
Host	smart-e1dac63f-bc5e-4612-891f-ecab0c3640dd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220731074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.4220731074
Directory	/workspace/87.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_same_source.2067338342
Short name	T2160
Test name
Test status
Simulation time	1880917936 ps
CPU time	53.51 seconds
Started	Jul 24 07:47:17 PM PDT 24
Finished	Jul 24 07:48:11 PM PDT 24
Peak memory	576896 kb
Host	smart-fe66673d-2607-41a5-af95-4a7cb85f2b06
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067338342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.2067338342
Directory	/workspace/87.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke.3000475980
Short name	T1498
Test name
Test status
Simulation time	221476884 ps
CPU time	9.39 seconds
Started	Jul 24 07:46:55 PM PDT 24
Finished	Jul 24 07:47:04 PM PDT 24
Peak memory	576180 kb
Host	smart-a191e29f-812b-4733-8f6e-4a700854d81a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000475980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.3000475980
Directory	/workspace/87.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.3871756325
Short name	T2470
Test name
Test status
Simulation time	5996303393 ps
CPU time	63.93 seconds
Started	Jul 24 07:46:58 PM PDT 24
Finished	Jul 24 07:48:02 PM PDT 24
Peak memory	575064 kb
Host	smart-89f7fcaf-53d5-46b2-95d9-1b91aa4a6778
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871756325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.3871756325
Directory	/workspace/87.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.443093171
Short name	T2497
Test name
Test status
Simulation time	5585259620 ps
CPU time	91.56 seconds
Started	Jul 24 07:46:56 PM PDT 24
Finished	Jul 24 07:48:27 PM PDT 24
Peak memory	575068 kb
Host	smart-ca0b481d-a56b-48e0-a580-50ec77e40525
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443093171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.443093171
Directory	/workspace/87.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.4275190236
Short name	T1609
Test name
Test status
Simulation time	45698534 ps
CPU time	6.43 seconds
Started	Jul 24 07:46:59 PM PDT 24
Finished	Jul 24 07:47:05 PM PDT 24
Peak memory	576136 kb
Host	smart-b56fb436-79e5-4637-89be-8994653fd5f1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275190236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.4275190236
Directory	/workspace/87.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all.3244995793
Short name	T2639
Test name
Test status
Simulation time	1795991930 ps
CPU time	148.45 seconds
Started	Jul 24 07:47:07 PM PDT 24
Finished	Jul 24 07:49:36 PM PDT 24
Peak memory	577168 kb
Host	smart-82512363-de56-498c-bf7f-cddb6f7697e0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244995793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.3244995793
Directory	/workspace/87.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.4119090317
Short name	T1689
Test name
Test status
Simulation time	691534650 ps
CPU time	58.18 seconds
Started	Jul 24 07:47:17 PM PDT 24
Finished	Jul 24 07:48:15 PM PDT 24
Peak memory	576960 kb
Host	smart-d620520d-640a-4b23-b7b9-48fd31d6eb7a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119090317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.4119090317
Directory	/workspace/87.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3812101592
Short name	T2925
Test name
Test status
Simulation time	2332231227 ps
CPU time	324.81 seconds
Started	Jul 24 07:47:05 PM PDT 24
Finished	Jul 24 07:52:30 PM PDT 24
Peak memory	576460 kb
Host	smart-0a3e0c15-c0bd-497d-b7ac-734bdb257f72
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812101592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.3812101592
Directory	/workspace/87.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.512043616
Short name	T2616
Test name
Test status
Simulation time	150681081 ps
CPU time	60.13 seconds
Started	Jul 24 07:47:06 PM PDT 24
Finished	Jul 24 07:48:07 PM PDT 24
Peak memory	576000 kb
Host	smart-66b9c658-e0c6-4016-9aa0-f329ab9688de
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512043616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_reset_error.512043616
Directory	/workspace/87.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.3278292301
Short name	T2709
Test name
Test status
Simulation time	65640846 ps
CPU time	11.02 seconds
Started	Jul 24 07:47:05 PM PDT 24
Finished	Jul 24 07:47:16 PM PDT 24
Peak memory	577000 kb
Host	smart-42d7109d-8683-4e8f-8924-06d9f1e637dd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278292301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.3278292301
Directory	/workspace/87.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_access_same_device.192472973
Short name	T1575
Test name
Test status
Simulation time	3415896607 ps
CPU time	125.48 seconds
Started	Jul 24 07:47:13 PM PDT 24
Finished	Jul 24 07:49:18 PM PDT 24
Peak memory	577200 kb
Host	smart-1a3aeb18-8433-4f51-8f31-231cb7a977f3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192472973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device. 192472973
Directory	/workspace/88.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2592149545
Short name	T2094
Test name
Test status
Simulation time	65954642158 ps
CPU time	1108.38 seconds
Started	Jul 24 07:47:20 PM PDT 24
Finished	Jul 24 08:05:49 PM PDT 24
Peak memory	577228 kb
Host	smart-b388a7ed-4a8c-4c8c-b4b0-6e26854aab88
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592149545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.2592149545
Directory	/workspace/88.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1388975399
Short name	T2355
Test name
Test status
Simulation time	121644515 ps
CPU time	8.04 seconds
Started	Jul 24 07:47:22 PM PDT 24
Finished	Jul 24 07:47:30 PM PDT 24
Peak memory	576136 kb
Host	smart-d3dc70ef-e042-469c-ad29-d1087ff6d871
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388975399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.1388975399
Directory	/workspace/88.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_error_random.2922936
Short name	T1671
Test name
Test status
Simulation time	422234805 ps
CPU time	38.19 seconds
Started	Jul 24 07:47:14 PM PDT 24
Finished	Jul 24 07:47:52 PM PDT 24
Peak memory	576992 kb
Host	smart-27702c9c-ae9f-4e60-9767-6fd71bff42ca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.2922936
Directory	/workspace/88.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_random.4095980925
Short name	T1790
Test name
Test status
Simulation time	1729805353 ps
CPU time	64.62 seconds
Started	Jul 24 07:47:04 PM PDT 24
Finished	Jul 24 07:48:09 PM PDT 24
Peak memory	576988 kb
Host	smart-a65d1b3d-87a6-48ea-976e-5c4b5d49c922
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095980925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.4095980925
Directory	/workspace/88.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_random_large_delays.1056843958
Short name	T616
Test name
Test status
Simulation time	61484619791 ps
CPU time	665.89 seconds
Started	Jul 24 07:47:15 PM PDT 24
Finished	Jul 24 07:58:21 PM PDT 24
Peak memory	576196 kb
Host	smart-5e9a6b09-aed4-474d-91da-886161e94077
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056843958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.1056843958
Directory	/workspace/88.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.1277783292
Short name	T463
Test name
Test status
Simulation time	38850705624 ps
CPU time	714.01 seconds
Started	Jul 24 07:47:06 PM PDT 24
Finished	Jul 24 07:59:00 PM PDT 24
Peak memory	577152 kb
Host	smart-87240875-8268-4999-9ed0-bd1feff12a4b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277783292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.1277783292
Directory	/workspace/88.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.4074592228
Short name	T2627
Test name
Test status
Simulation time	111516099 ps
CPU time	12.27 seconds
Started	Jul 24 07:47:07 PM PDT 24
Finished	Jul 24 07:47:19 PM PDT 24
Peak memory	576992 kb
Host	smart-5dc48d1d-f5c5-452f-8f35-8ead3e90952a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074592228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.4074592228
Directory	/workspace/88.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_same_source.1690724527
Short name	T2044
Test name
Test status
Simulation time	1218902712 ps
CPU time	35.76 seconds
Started	Jul 24 07:47:21 PM PDT 24
Finished	Jul 24 07:47:57 PM PDT 24
Peak memory	576960 kb
Host	smart-c806e456-e94a-44f7-9915-25649cf03ef3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690724527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.1690724527
Directory	/workspace/88.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke.4105299857
Short name	T1749
Test name
Test status
Simulation time	253697978 ps
CPU time	10.29 seconds
Started	Jul 24 07:47:03 PM PDT 24
Finished	Jul 24 07:47:14 PM PDT 24
Peak memory	574992 kb
Host	smart-abe83158-4d24-477a-b270-a235e7b6a300
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105299857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.4105299857
Directory	/workspace/88.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1967382417
Short name	T2289
Test name
Test status
Simulation time	11454262552 ps
CPU time	118.82 seconds
Started	Jul 24 07:47:16 PM PDT 24
Finished	Jul 24 07:49:15 PM PDT 24
Peak memory	574960 kb
Host	smart-caf9a5f0-be2d-47bc-8c86-3c98dbdcfe18
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967382417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1967382417
Directory	/workspace/88.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.832017998
Short name	T599
Test name
Test status
Simulation time	5082061021 ps
CPU time	82.87 seconds
Started	Jul 24 07:47:06 PM PDT 24
Finished	Jul 24 07:48:29 PM PDT 24
Peak memory	576292 kb
Host	smart-a49fee60-405e-4e58-8005-c6b7550f3115
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832017998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.832017998
Directory	/workspace/88.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.90939635
Short name	T1461
Test name
Test status
Simulation time	47106830 ps
CPU time	6.54 seconds
Started	Jul 24 07:47:07 PM PDT 24
Finished	Jul 24 07:47:14 PM PDT 24
Peak memory	576056 kb
Host	smart-d3e4733a-87af-47be-92bd-9fd5e90331e5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90939635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays.90939635
Directory	/workspace/88.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all.760617266
Short name	T1827
Test name
Test status
Simulation time	2718283857 ps
CPU time	208.37 seconds
Started	Jul 24 07:47:20 PM PDT 24
Finished	Jul 24 07:50:49 PM PDT 24
Peak memory	576348 kb
Host	smart-e46b7e14-06ce-4871-9f43-1f75502ee91b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760617266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.760617266
Directory	/workspace/88.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.1724008134
Short name	T2524
Test name
Test status
Simulation time	3064644184 ps
CPU time	254.58 seconds
Started	Jul 24 07:47:14 PM PDT 24
Finished	Jul 24 07:51:29 PM PDT 24
Peak memory	576520 kb
Host	smart-0df4a7ca-e63f-40ac-a456-ff622231a3c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724008134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.1724008134
Directory	/workspace/88.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2378890797
Short name	T2928
Test name
Test status
Simulation time	11723873998 ps
CPU time	712.55 seconds
Started	Jul 24 07:47:13 PM PDT 24
Finished	Jul 24 07:59:06 PM PDT 24
Peak memory	576452 kb
Host	smart-8f59f7ab-62c7-4cde-be10-2501d9404875
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378890797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.2378890797
Directory	/workspace/88.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1497551180
Short name	T2315
Test name
Test status
Simulation time	4081090418 ps
CPU time	227.16 seconds
Started	Jul 24 07:47:14 PM PDT 24
Finished	Jul 24 07:51:01 PM PDT 24
Peak memory	577248 kb
Host	smart-399e728a-980d-4c65-b10a-df10a55d32d3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497551180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.1497551180
Directory	/workspace/88.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.1718159576
Short name	T1555
Test name
Test status
Simulation time	129425258 ps
CPU time	8.32 seconds
Started	Jul 24 07:47:14 PM PDT 24
Finished	Jul 24 07:47:22 PM PDT 24
Peak memory	576236 kb
Host	smart-a9d24b39-fbc7-406d-9089-c7693783c29d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718159576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.1718159576
Directory	/workspace/88.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_access_same_device.2466660615
Short name	T1751
Test name
Test status
Simulation time	887097146 ps
CPU time	36.84 seconds
Started	Jul 24 07:47:20 PM PDT 24
Finished	Jul 24 07:47:57 PM PDT 24
Peak memory	576164 kb
Host	smart-1c6889cf-5121-4259-b456-c05b2a2efbfc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466660615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .2466660615
Directory	/workspace/89.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.31344979
Short name	T2430
Test name
Test status
Simulation time	154570605833 ps
CPU time	2687.2 seconds
Started	Jul 24 07:47:22 PM PDT 24
Finished	Jul 24 08:32:10 PM PDT 24
Peak memory	577276 kb
Host	smart-fa45c6ac-87ca-474d-82f2-fb1a38b95eae
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31344979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_de vice_slow_rsp.31344979
Directory	/workspace/89.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2911823058
Short name	T457
Test name
Test status
Simulation time	665454878 ps
CPU time	25.03 seconds
Started	Jul 24 07:47:21 PM PDT 24
Finished	Jul 24 07:47:46 PM PDT 24
Peak memory	576944 kb
Host	smart-39c2a4ba-d2b4-48aa-822f-5aca137146ca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911823058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.2911823058
Directory	/workspace/89.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_error_random.1705985924
Short name	T1485
Test name
Test status
Simulation time	487008321 ps
CPU time	41.74 seconds
Started	Jul 24 07:47:24 PM PDT 24
Finished	Jul 24 07:48:06 PM PDT 24
Peak memory	576896 kb
Host	smart-fd56cc4e-c26c-494d-bf4f-feaa3da15b89
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705985924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1705985924
Directory	/workspace/89.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_random.2536863993
Short name	T1995
Test name
Test status
Simulation time	68170176 ps
CPU time	6.24 seconds
Started	Jul 24 07:47:12 PM PDT 24
Finished	Jul 24 07:47:18 PM PDT 24
Peak memory	574912 kb
Host	smart-9356e8bf-89eb-4089-b209-a6c3737f4600
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536863993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.2536863993
Directory	/workspace/89.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_random_large_delays.774870753
Short name	T1744
Test name
Test status
Simulation time	77348567272 ps
CPU time	790.31 seconds
Started	Jul 24 07:47:13 PM PDT 24
Finished	Jul 24 08:00:24 PM PDT 24
Peak memory	576292 kb
Host	smart-56e9de6b-ce4f-4357-bea3-cfcd2342bca3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774870753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.774870753
Directory	/workspace/89.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.270454720
Short name	T2288
Test name
Test status
Simulation time	28800907526 ps
CPU time	488.78 seconds
Started	Jul 24 07:47:14 PM PDT 24
Finished	Jul 24 07:55:23 PM PDT 24
Peak memory	577196 kb
Host	smart-ec57756d-089e-4e23-8b62-6a596488e4af
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270454720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.270454720
Directory	/workspace/89.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.3355036879
Short name	T2098
Test name
Test status
Simulation time	371164736 ps
CPU time	34.86 seconds
Started	Jul 24 07:47:12 PM PDT 24
Finished	Jul 24 07:47:47 PM PDT 24
Peak memory	576156 kb
Host	smart-1de8dc27-22bb-4148-a7e6-9e6607d9bfef
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355036879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.3355036879
Directory	/workspace/89.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_same_source.514591422
Short name	T2658
Test name
Test status
Simulation time	508246026 ps
CPU time	35.55 seconds
Started	Jul 24 07:47:24 PM PDT 24
Finished	Jul 24 07:48:00 PM PDT 24
Peak memory	576060 kb
Host	smart-59f58dc4-cdb8-4e13-9fab-7957143d0045
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514591422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.514591422
Directory	/workspace/89.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke.1966162896
Short name	T1682
Test name
Test status
Simulation time	197343863 ps
CPU time	9.29 seconds
Started	Jul 24 07:47:12 PM PDT 24
Finished	Jul 24 07:47:21 PM PDT 24
Peak memory	574844 kb
Host	smart-bc9da07d-4886-43a8-8459-9b146f795760
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966162896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.1966162896
Directory	/workspace/89.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.3261814151
Short name	T2031
Test name
Test status
Simulation time	7513125600 ps
CPU time	72.63 seconds
Started	Jul 24 07:47:13 PM PDT 24
Finished	Jul 24 07:48:26 PM PDT 24
Peak memory	576264 kb
Host	smart-8e9994e7-a99c-4898-9ad9-22d26527b6ef
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261814151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3261814151
Directory	/workspace/89.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3179426021
Short name	T1502
Test name
Test status
Simulation time	4563598207 ps
CPU time	74.8 seconds
Started	Jul 24 07:47:15 PM PDT 24
Finished	Jul 24 07:48:30 PM PDT 24
Peak memory	574988 kb
Host	smart-c384cd62-b239-4648-975c-d65816633cb9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179426021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3179426021
Directory	/workspace/89.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1201303497
Short name	T2283
Test name
Test status
Simulation time	51444775 ps
CPU time	6 seconds
Started	Jul 24 07:47:21 PM PDT 24
Finished	Jul 24 07:47:27 PM PDT 24
Peak memory	574936 kb
Host	smart-5ba6a8b1-da3b-4a99-9387-69c8da3c095b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201303497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.1201303497
Directory	/workspace/89.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all.846867729
Short name	T2798
Test name
Test status
Simulation time	11159880185 ps
CPU time	442.22 seconds
Started	Jul 24 07:47:20 PM PDT 24
Finished	Jul 24 07:54:42 PM PDT 24
Peak memory	577304 kb
Host	smart-357718a2-7077-4b21-8c83-1c9cb908bab9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846867729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.846867729
Directory	/workspace/89.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2599820192
Short name	T2285
Test name
Test status
Simulation time	10643562476 ps
CPU time	400.21 seconds
Started	Jul 24 07:47:29 PM PDT 24
Finished	Jul 24 07:54:10 PM PDT 24
Peak memory	577368 kb
Host	smart-697a0afc-99c0-4e3e-b72e-beb0c7b2333c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599820192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2599820192
Directory	/workspace/89.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.4032109056
Short name	T733
Test name
Test status
Simulation time	2912068294 ps
CPU time	226.11 seconds
Started	Jul 24 07:47:21 PM PDT 24
Finished	Jul 24 07:51:07 PM PDT 24
Peak memory	577272 kb
Host	smart-1f20b689-159c-4d74-9534-9200d299532a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032109056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.4032109056
Directory	/workspace/89.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.684082152
Short name	T2603
Test name
Test status
Simulation time	3422232387 ps
CPU time	469.26 seconds
Started	Jul 24 07:47:19 PM PDT 24
Finished	Jul 24 07:55:09 PM PDT 24
Peak memory	577368 kb
Host	smart-8afa5cd5-5a90-43f0-9714-d1293993d7c8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684082152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_reset_error.684082152
Directory	/workspace/89.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.560633656
Short name	T2151
Test name
Test status
Simulation time	1257036735 ps
CPU time	52.53 seconds
Started	Jul 24 07:47:20 PM PDT 24
Finished	Jul 24 07:48:12 PM PDT 24
Peak memory	576172 kb
Host	smart-622c34db-12fb-49e3-b812-d34c9279c536
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560633656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.560633656
Directory	/workspace/89.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.3123639906
Short name	T1854
Test name
Test status
Simulation time	10901858515 ps
CPU time	855.34 seconds
Started	Jul 24 07:34:30 PM PDT 24
Finished	Jul 24 07:48:46 PM PDT 24
Peak memory	646996 kb
Host	smart-180f609d-78fd-49f6-832d-e648f929046d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123639906 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.3123639906
Directory	/workspace/9.chip_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.475125310
Short name	T392
Test name
Test status
Simulation time	16421347352 ps
CPU time	2117.52 seconds
Started	Jul 24 07:34:11 PM PDT 24
Finished	Jul 24 08:09:29 PM PDT 24
Peak memory	593936 kb
Host	smart-b030b423-9fed-4235-8e59-478d2dc2be9a
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475125310 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.chip_same_csr_outstanding.475125310
Directory	/workspace/9.chip_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/9.chip_tl_errors.3446653754
Short name	T708
Test name
Test status
Simulation time	3369657840 ps
CPU time	141.19 seconds
Started	Jul 24 07:34:11 PM PDT 24
Finished	Jul 24 07:36:32 PM PDT 24
Peak memory	600488 kb
Host	smart-47b1467a-3982-4218-9948-c996c87c4e5a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446653754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3446653754
Directory	/workspace/9.chip_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_access_same_device.3045971933
Short name	T2683
Test name
Test status
Simulation time	524026186 ps
CPU time	48.21 seconds
Started	Jul 24 07:33:58 PM PDT 24
Finished	Jul 24 07:34:46 PM PDT 24
Peak memory	576360 kb
Host	smart-45912b55-dc3d-49d9-9232-c3c49a532e15
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045971933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 3045971933
Directory	/workspace/9.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.1422803814
Short name	T2711
Test name
Test status
Simulation time	63927267465 ps
CPU time	1057.98 seconds
Started	Jul 24 07:33:58 PM PDT 24
Finished	Jul 24 07:51:36 PM PDT 24
Peak memory	577300 kb
Host	smart-8985adc3-414d-4941-822b-2cc451fc7ba5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422803814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.1422803814
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3320636898
Short name	T2367
Test name
Test status
Simulation time	288179875 ps
CPU time	13.78 seconds
Started	Jul 24 07:34:18 PM PDT 24
Finished	Jul 24 07:34:32 PM PDT 24
Peak memory	576968 kb
Host	smart-501e283a-3a4d-4f20-8bdf-94ec64049d5e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320636898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .3320636898
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_error_random.3323226472
Short name	T2390
Test name
Test status
Simulation time	174617100 ps
CPU time	13.79 seconds
Started	Jul 24 07:34:23 PM PDT 24
Finished	Jul 24 07:34:37 PM PDT 24
Peak memory	576124 kb
Host	smart-3c1a5acf-b3df-4709-921a-f1a34942206e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323226472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3323226472
Directory	/workspace/9.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_random.1879077202
Short name	T2357
Test name
Test status
Simulation time	665366786 ps
CPU time	24.87 seconds
Started	Jul 24 07:34:00 PM PDT 24
Finished	Jul 24 07:34:25 PM PDT 24
Peak memory	576192 kb
Host	smart-19907f35-3ef4-4bf4-b9c5-26ce5fc57806
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879077202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.1879077202
Directory	/workspace/9.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_random_large_delays.3058089509
Short name	T538
Test name
Test status
Simulation time	66130051475 ps
CPU time	632.89 seconds
Started	Jul 24 07:34:22 PM PDT 24
Finished	Jul 24 07:44:55 PM PDT 24
Peak memory	576312 kb
Host	smart-8daa413f-a480-4e9b-9b26-c94eb9a08a31
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058089509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3058089509
Directory	/workspace/9.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.3828767090
Short name	T500
Test name
Test status
Simulation time	60946785420 ps
CPU time	950.57 seconds
Started	Jul 24 07:34:11 PM PDT 24
Finished	Jul 24 07:50:02 PM PDT 24
Peak memory	576316 kb
Host	smart-3b970d50-d627-4808-9eb3-0d87b14618de
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828767090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3828767090
Directory	/workspace/9.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2705281293
Short name	T2594
Test name
Test status
Simulation time	292732336 ps
CPU time	23.02 seconds
Started	Jul 24 07:34:11 PM PDT 24
Finished	Jul 24 07:34:34 PM PDT 24
Peak memory	577008 kb
Host	smart-3844f6bc-faac-4215-b6c2-169f0a367d81
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705281293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.2705281293
Directory	/workspace/9.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_same_source.3412937281
Short name	T1955
Test name
Test status
Simulation time	2083468896 ps
CPU time	60.69 seconds
Started	Jul 24 07:34:22 PM PDT 24
Finished	Jul 24 07:35:23 PM PDT 24
Peak memory	577008 kb
Host	smart-95c946ab-35f0-4bcd-8126-64374b7f94c5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412937281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3412937281
Directory	/workspace/9.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke.3396470720
Short name	T1845
Test name
Test status
Simulation time	213244635 ps
CPU time	9.78 seconds
Started	Jul 24 07:33:58 PM PDT 24
Finished	Jul 24 07:34:08 PM PDT 24
Peak memory	574952 kb
Host	smart-747d9a3b-1914-4cd5-ac5c-7a50f401c1f3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396470720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3396470720
Directory	/workspace/9.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.2574910715
Short name	T2442
Test name
Test status
Simulation time	7438473383 ps
CPU time	81.38 seconds
Started	Jul 24 07:34:07 PM PDT 24
Finished	Jul 24 07:35:28 PM PDT 24
Peak memory	576332 kb
Host	smart-ec1661cc-3aa8-4675-b35a-073554bf3144
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574910715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2574910715
Directory	/workspace/9.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.166649191
Short name	T2513
Test name
Test status
Simulation time	5083849208 ps
CPU time	80.79 seconds
Started	Jul 24 07:34:07 PM PDT 24
Finished	Jul 24 07:35:28 PM PDT 24
Peak memory	575004 kb
Host	smart-839d5459-dd90-405d-811e-d24d4d553008
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166649191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.166649191
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1831918579
Short name	T2108
Test name
Test status
Simulation time	49373062 ps
CPU time	6.35 seconds
Started	Jul 24 07:34:01 PM PDT 24
Finished	Jul 24 07:34:08 PM PDT 24
Peak memory	574936 kb
Host	smart-0c45bb5a-9c8c-46ed-ba0d-61038ed05c86
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831918579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .1831918579
Directory	/workspace/9.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all.2481094057
Short name	T2869
Test name
Test status
Simulation time	881511984 ps
CPU time	34.8 seconds
Started	Jul 24 07:34:09 PM PDT 24
Finished	Jul 24 07:34:43 PM PDT 24
Peak memory	577064 kb
Host	smart-e486ff0b-4f22-435d-b1cb-77202a7d7704
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481094057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2481094057
Directory	/workspace/9.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.2395584942
Short name	T1569
Test name
Test status
Simulation time	1283372177 ps
CPU time	93.46 seconds
Started	Jul 24 07:34:28 PM PDT 24
Finished	Jul 24 07:36:02 PM PDT 24
Peak memory	577176 kb
Host	smart-15818067-5e10-4dea-8367-e36344dedb6f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395584942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2395584942
Directory	/workspace/9.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.337289865
Short name	T520
Test name
Test status
Simulation time	20668312274 ps
CPU time	857.52 seconds
Started	Jul 24 07:34:11 PM PDT 24
Finished	Jul 24 07:48:29 PM PDT 24
Peak memory	576384 kb
Host	smart-878c5ec0-e049-4ccc-beb0-349fb62b138d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337289865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_w ith_rand_reset.337289865
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.4106584929
Short name	T1820
Test name
Test status
Simulation time	15535440814 ps
CPU time	680.04 seconds
Started	Jul 24 07:34:07 PM PDT 24
Finished	Jul 24 07:45:27 PM PDT 24
Peak memory	583280 kb
Host	smart-bd1e1aee-620b-422d-ba51-b89b47726dd2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106584929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.4106584929
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3657056873
Short name	T1626
Test name
Test status
Simulation time	23966592 ps
CPU time	5.5 seconds
Started	Jul 24 07:34:30 PM PDT 24
Finished	Jul 24 07:34:36 PM PDT 24
Peak memory	575004 kb
Host	smart-c3c6cbc6-a26e-4756-8dbf-c18bae98e013
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657056873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3657056873
Directory	/workspace/9.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_access_same_device.70092394
Short name	T940
Test name
Test status
Simulation time	360840806 ps
CPU time	16.19 seconds
Started	Jul 24 07:47:31 PM PDT 24
Finished	Jul 24 07:47:47 PM PDT 24
Peak memory	576204 kb
Host	smart-dab7683d-a64e-421b-b371-f640b43db0a9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70092394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device.70092394
Directory	/workspace/90.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1068850625
Short name	T1568
Test name
Test status
Simulation time	754217395 ps
CPU time	28.47 seconds
Started	Jul 24 07:47:30 PM PDT 24
Finished	Jul 24 07:47:59 PM PDT 24
Peak memory	576992 kb
Host	smart-157f6bdf-5ece-46a9-89ef-cbad22094fff
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068850625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.1068850625
Directory	/workspace/90.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_error_random.1078259945
Short name	T1503
Test name
Test status
Simulation time	147563267 ps
CPU time	14.09 seconds
Started	Jul 24 07:47:29 PM PDT 24
Finished	Jul 24 07:47:43 PM PDT 24
Peak memory	576052 kb
Host	smart-a5f34d47-ca95-468c-9359-a0f8ed543f38
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078259945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.1078259945
Directory	/workspace/90.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_random.2625273574
Short name	T2871
Test name
Test status
Simulation time	211846211 ps
CPU time	9.99 seconds
Started	Jul 24 07:47:31 PM PDT 24
Finished	Jul 24 07:47:42 PM PDT 24
Peak memory	574960 kb
Host	smart-2f0218c3-56f6-4410-ab44-1d79ecb9738e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625273574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.2625273574
Directory	/workspace/90.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2798034660
Short name	T1836
Test name
Test status
Simulation time	59355517816 ps
CPU time	641.09 seconds
Started	Jul 24 07:47:31 PM PDT 24
Finished	Jul 24 07:58:13 PM PDT 24
Peak memory	577136 kb
Host	smart-0b0fffa2-71a1-4a1c-a106-2b8d8dd51657
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798034660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.2798034660
Directory	/workspace/90.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.3829092392
Short name	T2482
Test name
Test status
Simulation time	19036009531 ps
CPU time	311.57 seconds
Started	Jul 24 07:47:28 PM PDT 24
Finished	Jul 24 07:52:40 PM PDT 24
Peak memory	576296 kb
Host	smart-7bb5c2b3-0546-41b6-bcc3-e269f9cf4631
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829092392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.3829092392
Directory	/workspace/90.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.3417227815
Short name	T677
Test name
Test status
Simulation time	100190444 ps
CPU time	11.37 seconds
Started	Jul 24 07:47:29 PM PDT 24
Finished	Jul 24 07:47:40 PM PDT 24
Peak memory	576176 kb
Host	smart-9dfcc2eb-6485-4e15-83bf-9a67ed9762b6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417227815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.3417227815
Directory	/workspace/90.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_same_source.114636199
Short name	T2707
Test name
Test status
Simulation time	416356364 ps
CPU time	14.37 seconds
Started	Jul 24 07:47:30 PM PDT 24
Finished	Jul 24 07:47:44 PM PDT 24
Peak memory	576160 kb
Host	smart-9c31e67b-49a9-456a-ae4c-23270fa67021
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114636199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.114636199
Directory	/workspace/90.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke.2272279236
Short name	T2046
Test name
Test status
Simulation time	137704164 ps
CPU time	7.08 seconds
Started	Jul 24 07:47:23 PM PDT 24
Finished	Jul 24 07:47:30 PM PDT 24
Peak memory	574776 kb
Host	smart-89d66338-238e-4569-8f09-be37e7a074af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272279236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.2272279236
Directory	/workspace/90.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.1491626363
Short name	T2081
Test name
Test status
Simulation time	7999792910 ps
CPU time	82.75 seconds
Started	Jul 24 07:47:28 PM PDT 24
Finished	Jul 24 07:48:51 PM PDT 24
Peak memory	574980 kb
Host	smart-6e8cb104-80ea-4e0e-ba33-2dc611a8e0be
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491626363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.1491626363
Directory	/workspace/90.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1087778826
Short name	T702
Test name
Test status
Simulation time	6375941915 ps
CPU time	110.18 seconds
Started	Jul 24 07:47:29 PM PDT 24
Finished	Jul 24 07:49:20 PM PDT 24
Peak memory	574996 kb
Host	smart-59f2a7c5-9ded-41db-b252-31c65a229d27
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087778826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.1087778826
Directory	/workspace/90.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3579162594
Short name	T1716
Test name
Test status
Simulation time	36330647 ps
CPU time	5.92 seconds
Started	Jul 24 07:47:31 PM PDT 24
Finished	Jul 24 07:47:37 PM PDT 24
Peak memory	576212 kb
Host	smart-264535a5-21d8-4059-ab2c-a96e1357678f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579162594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.3579162594
Directory	/workspace/90.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all.174431250
Short name	T2776
Test name
Test status
Simulation time	1660735939 ps
CPU time	156.12 seconds
Started	Jul 24 07:47:30 PM PDT 24
Finished	Jul 24 07:50:06 PM PDT 24
Peak memory	576424 kb
Host	smart-b2deb69e-705e-4b99-be75-16c1d42eb0ee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174431250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.174431250
Directory	/workspace/90.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.2456958048
Short name	T2561
Test name
Test status
Simulation time	448872930 ps
CPU time	29.84 seconds
Started	Jul 24 07:47:29 PM PDT 24
Finished	Jul 24 07:47:59 PM PDT 24
Peak memory	576964 kb
Host	smart-5a9d5a2f-afca-4534-b0e2-6077199ae608
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456958048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.2456958048
Directory	/workspace/90.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.2966820363
Short name	T673
Test name
Test status
Simulation time	9251713112 ps
CPU time	466.29 seconds
Started	Jul 24 07:47:29 PM PDT 24
Finished	Jul 24 07:55:15 PM PDT 24
Peak memory	576404 kb
Host	smart-fff3676a-a559-421d-9484-14ee12d6750d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966820363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.2966820363
Directory	/workspace/90.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.756758891
Short name	T2723
Test name
Test status
Simulation time	8340201577 ps
CPU time	323.89 seconds
Started	Jul 24 07:47:30 PM PDT 24
Finished	Jul 24 07:52:54 PM PDT 24
Peak memory	577252 kb
Host	smart-bb52ff54-b150-47aa-adc9-21007b36d037
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756758891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_reset_error.756758891
Directory	/workspace/90.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3392052399
Short name	T575
Test name
Test status
Simulation time	1001352230 ps
CPU time	45.38 seconds
Started	Jul 24 07:47:27 PM PDT 24
Finished	Jul 24 07:48:13 PM PDT 24
Peak memory	576176 kb
Host	smart-5b828a8d-ac5f-4ada-a9dc-cadacfb57f92
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392052399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3392052399
Directory	/workspace/90.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_access_same_device.3804039766
Short name	T2101
Test name
Test status
Simulation time	361583589 ps
CPU time	15.63 seconds
Started	Jul 24 07:47:37 PM PDT 24
Finished	Jul 24 07:47:53 PM PDT 24
Peak memory	576804 kb
Host	smart-2ccb1781-bf52-4b92-ba1b-400fa5e2318a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804039766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .3804039766
Directory	/workspace/91.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.2230214085
Short name	T2146
Test name
Test status
Simulation time	98209192988 ps
CPU time	2023.76 seconds
Started	Jul 24 07:47:39 PM PDT 24
Finished	Jul 24 08:21:23 PM PDT 24
Peak memory	576360 kb
Host	smart-ee72543d-ada8-4558-999c-9a08b7df7566
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230214085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.2230214085
Directory	/workspace/91.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3209834301
Short name	T1455
Test name
Test status
Simulation time	805830068 ps
CPU time	34.31 seconds
Started	Jul 24 07:47:38 PM PDT 24
Finished	Jul 24 07:48:12 PM PDT 24
Peak memory	576956 kb
Host	smart-e750f413-1c2a-4d6e-b541-0c3c9ab84cfc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209834301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.3209834301
Directory	/workspace/91.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_error_random.2295721946
Short name	T2227
Test name
Test status
Simulation time	601279651 ps
CPU time	22.73 seconds
Started	Jul 24 07:47:38 PM PDT 24
Finished	Jul 24 07:48:01 PM PDT 24
Peak memory	576912 kb
Host	smart-ef0de167-0b62-459b-ae3c-e758dabfe145
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295721946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.2295721946
Directory	/workspace/91.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_random.423021145
Short name	T2136
Test name
Test status
Simulation time	996975631 ps
CPU time	31.86 seconds
Started	Jul 24 07:47:36 PM PDT 24
Finished	Jul 24 07:48:08 PM PDT 24
Peak memory	576960 kb
Host	smart-cf399369-7b71-4d42-bc84-9d5e09e792d1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423021145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.423021145
Directory	/workspace/91.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_random_large_delays.1062280834
Short name	T738
Test name
Test status
Simulation time	43417524834 ps
CPU time	436.36 seconds
Started	Jul 24 07:47:37 PM PDT 24
Finished	Jul 24 07:54:54 PM PDT 24
Peak memory	576272 kb
Host	smart-57c22d75-a908-479c-8e62-1aeb6a444f23
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062280834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.1062280834
Directory	/workspace/91.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.2143503321
Short name	T1470
Test name
Test status
Simulation time	14771085232 ps
CPU time	247.87 seconds
Started	Jul 24 07:47:38 PM PDT 24
Finished	Jul 24 07:51:46 PM PDT 24
Peak memory	577108 kb
Host	smart-0b1539ad-8ee4-4fad-b5fd-246409c7b08f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143503321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.2143503321
Directory	/workspace/91.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.326926054
Short name	T2817
Test name
Test status
Simulation time	307594169 ps
CPU time	25.2 seconds
Started	Jul 24 07:47:37 PM PDT 24
Finished	Jul 24 07:48:03 PM PDT 24
Peak memory	576084 kb
Host	smart-b8f8ed54-70c7-4d9c-992d-4c18992694c5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326926054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_dela ys.326926054
Directory	/workspace/91.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_same_source.3946319051
Short name	T2770
Test name
Test status
Simulation time	2483625890 ps
CPU time	76.47 seconds
Started	Jul 24 07:47:37 PM PDT 24
Finished	Jul 24 07:48:53 PM PDT 24
Peak memory	577028 kb
Host	smart-c5fc7acb-dace-4a38-9c51-feb293141710
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946319051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3946319051
Directory	/workspace/91.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke.2292791280
Short name	T1821
Test name
Test status
Simulation time	45249540 ps
CPU time	5.9 seconds
Started	Jul 24 07:47:28 PM PDT 24
Finished	Jul 24 07:47:34 PM PDT 24
Peak memory	574832 kb
Host	smart-d4356ccf-2c87-4c7a-9fce-540bc9dddec3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292791280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.2292791280
Directory	/workspace/91.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.1496251951
Short name	T2251
Test name
Test status
Simulation time	6985621413 ps
CPU time	70.5 seconds
Started	Jul 24 07:47:27 PM PDT 24
Finished	Jul 24 07:48:38 PM PDT 24
Peak memory	575084 kb
Host	smart-12e5a2a5-6022-4f6e-ad0a-861ed202d900
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496251951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.1496251951
Directory	/workspace/91.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.4243544619
Short name	T1970
Test name
Test status
Simulation time	6347304400 ps
CPU time	104.59 seconds
Started	Jul 24 07:47:39 PM PDT 24
Finished	Jul 24 07:49:24 PM PDT 24
Peak memory	575000 kb
Host	smart-e4d5c2bb-ab77-41a7-aaea-d0fa32b44113
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243544619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.4243544619
Directory	/workspace/91.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1044238287
Short name	T1631
Test name
Test status
Simulation time	51328620 ps
CPU time	6.52 seconds
Started	Jul 24 07:47:29 PM PDT 24
Finished	Jul 24 07:47:36 PM PDT 24
Peak memory	574852 kb
Host	smart-6b749102-f41b-4d60-bda4-3b895791433b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044238287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.1044238287
Directory	/workspace/91.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all.2488777478
Short name	T2789
Test name
Test status
Simulation time	3008992930 ps
CPU time	113.34 seconds
Started	Jul 24 07:50:01 PM PDT 24
Finished	Jul 24 07:51:55 PM PDT 24
Peak memory	577256 kb
Host	smart-6ef7c4ec-fe2f-4a2a-af14-c74022946fc0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488777478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.2488777478
Directory	/workspace/91.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.3697736292
Short name	T1767
Test name
Test status
Simulation time	125563596 ps
CPU time	13.9 seconds
Started	Jul 24 07:47:37 PM PDT 24
Finished	Jul 24 07:47:51 PM PDT 24
Peak memory	576224 kb
Host	smart-2fff6635-3da5-4658-bbed-9b428b62e36d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697736292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.3697736292
Directory	/workspace/91.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.4111929300
Short name	T1677
Test name
Test status
Simulation time	200098769 ps
CPU time	59.18 seconds
Started	Jul 24 07:47:36 PM PDT 24
Finished	Jul 24 07:48:35 PM PDT 24
Peak memory	576316 kb
Host	smart-a5b17e29-fb86-4096-838a-cf683cdc26bd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111929300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.4111929300
Directory	/workspace/91.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2441517846
Short name	T1791
Test name
Test status
Simulation time	4036887709 ps
CPU time	409.89 seconds
Started	Jul 24 07:47:36 PM PDT 24
Finished	Jul 24 07:54:26 PM PDT 24
Peak memory	577292 kb
Host	smart-871133a9-78b0-4b96-8817-2177dde30b2c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441517846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.2441517846
Directory	/workspace/91.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.1262388810
Short name	T1954
Test name
Test status
Simulation time	980827612 ps
CPU time	43.6 seconds
Started	Jul 24 07:47:38 PM PDT 24
Finished	Jul 24 07:48:22 PM PDT 24
Peak memory	576948 kb
Host	smart-7cf36b62-c39a-4ab9-a587-2191313aa0f9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262388810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.1262388810
Directory	/workspace/91.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_access_same_device.1598299722
Short name	T2376
Test name
Test status
Simulation time	263237812 ps
CPU time	17.24 seconds
Started	Jul 24 07:47:39 PM PDT 24
Finished	Jul 24 07:47:56 PM PDT 24
Peak memory	577072 kb
Host	smart-af6ad039-d0cd-4da8-bce6-64ca3a8ff17e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598299722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .1598299722
Directory	/workspace/92.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2373815305
Short name	T2310
Test name
Test status
Simulation time	37629160548 ps
CPU time	709.68 seconds
Started	Jul 24 07:47:35 PM PDT 24
Finished	Jul 24 07:59:25 PM PDT 24
Peak memory	576320 kb
Host	smart-b9954bf7-e2d7-4c3d-8bde-57378bf7c4f1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373815305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.2373815305
Directory	/workspace/92.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.796310984
Short name	T1781
Test name
Test status
Simulation time	49941880 ps
CPU time	8.37 seconds
Started	Jul 24 07:47:44 PM PDT 24
Finished	Jul 24 07:47:53 PM PDT 24
Peak memory	576152 kb
Host	smart-a792210e-3ecb-4cd1-9d41-9d15b80d71d4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796310984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr .796310984
Directory	/workspace/92.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_error_random.57980938
Short name	T1596
Test name
Test status
Simulation time	1980665597 ps
CPU time	66.57 seconds
Started	Jul 24 07:47:45 PM PDT 24
Finished	Jul 24 07:48:52 PM PDT 24
Peak memory	577008 kb
Host	smart-cadab446-54e3-4e5e-869c-7f369e8ef2b8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57980938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.57980938
Directory	/workspace/92.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_random.3396562401
Short name	T2800
Test name
Test status
Simulation time	664728908 ps
CPU time	27.34 seconds
Started	Jul 24 07:47:39 PM PDT 24
Finished	Jul 24 07:48:07 PM PDT 24
Peak memory	576172 kb
Host	smart-80513c39-2dc0-406a-9387-7a46bbdf22dd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396562401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.3396562401
Directory	/workspace/92.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_random_large_delays.524268534
Short name	T2831
Test name
Test status
Simulation time	94775440601 ps
CPU time	1162.79 seconds
Started	Jul 24 07:47:39 PM PDT 24
Finished	Jul 24 08:07:02 PM PDT 24
Peak memory	577160 kb
Host	smart-8088164b-a04c-4faa-a7af-e0fc4b32470c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524268534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.524268534
Directory	/workspace/92.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.739994692
Short name	T2867
Test name
Test status
Simulation time	6625369348 ps
CPU time	112.75 seconds
Started	Jul 24 07:47:38 PM PDT 24
Finished	Jul 24 07:49:31 PM PDT 24
Peak memory	574996 kb
Host	smart-16e53126-90f7-44f5-8f7e-da187d6a124e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739994692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.739994692
Directory	/workspace/92.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.2672002359
Short name	T667
Test name
Test status
Simulation time	476690273 ps
CPU time	42.85 seconds
Started	Jul 24 07:47:36 PM PDT 24
Finished	Jul 24 07:48:19 PM PDT 24
Peak memory	577132 kb
Host	smart-cf511ff1-1171-4c79-93a6-9f459e6ab555
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672002359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.2672002359
Directory	/workspace/92.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_same_source.913966606
Short name	T1963
Test name
Test status
Simulation time	1218283224 ps
CPU time	39.33 seconds
Started	Jul 24 07:47:46 PM PDT 24
Finished	Jul 24 07:48:26 PM PDT 24
Peak memory	576148 kb
Host	smart-1d80f264-ea9d-4f7b-bf56-bc288477560b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913966606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.913966606
Directory	/workspace/92.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke.832241422
Short name	T2706
Test name
Test status
Simulation time	196140579 ps
CPU time	8.69 seconds
Started	Jul 24 07:47:37 PM PDT 24
Finished	Jul 24 07:47:46 PM PDT 24
Peak memory	574908 kb
Host	smart-bb63f61d-1437-4ac7-bbe5-c75925bd0c3e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832241422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.832241422
Directory	/workspace/92.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.2911782635
Short name	T1643
Test name
Test status
Simulation time	7988900989 ps
CPU time	87.22 seconds
Started	Jul 24 07:47:39 PM PDT 24
Finished	Jul 24 07:49:06 PM PDT 24
Peak memory	575000 kb
Host	smart-3cc38bf6-380e-4724-b1c4-3bfb17a318f5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911782635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.2911782635
Directory	/workspace/92.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1502169702
Short name	T1516
Test name
Test status
Simulation time	4986851387 ps
CPU time	83 seconds
Started	Jul 24 07:47:37 PM PDT 24
Finished	Jul 24 07:49:00 PM PDT 24
Peak memory	576328 kb
Host	smart-f118f8b9-0702-49d8-a75f-78e2472fa29e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502169702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.1502169702
Directory	/workspace/92.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1147476052
Short name	T2700
Test name
Test status
Simulation time	44972710 ps
CPU time	6 seconds
Started	Jul 24 07:47:35 PM PDT 24
Finished	Jul 24 07:47:41 PM PDT 24
Peak memory	574892 kb
Host	smart-233e4527-7dc7-44d2-a136-f3bd3aea4fb6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147476052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.1147476052
Directory	/workspace/92.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all.1362720175
Short name	T633
Test name
Test status
Simulation time	3002724468 ps
CPU time	312.56 seconds
Started	Jul 24 07:47:44 PM PDT 24
Finished	Jul 24 07:52:56 PM PDT 24
Peak memory	577292 kb
Host	smart-d82520f2-f112-4e88-b2c0-14b2728e62c8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362720175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.1362720175
Directory	/workspace/92.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.399156819
Short name	T1563
Test name
Test status
Simulation time	4662380494 ps
CPU time	138.82 seconds
Started	Jul 24 07:47:44 PM PDT 24
Finished	Jul 24 07:50:03 PM PDT 24
Peak memory	577132 kb
Host	smart-5d94d02a-8766-4a44-81d5-528aa3ee4bde
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399156819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.399156819
Directory	/workspace/92.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1599832575
Short name	T2000
Test name
Test status
Simulation time	349948542 ps
CPU time	110.25 seconds
Started	Jul 24 07:47:46 PM PDT 24
Finished	Jul 24 07:49:36 PM PDT 24
Peak memory	577152 kb
Host	smart-cb49b279-d3cd-4621-85be-dd3ba45aeacc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599832575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.1599832575
Directory	/workspace/92.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.3424670360
Short name	T1893
Test name
Test status
Simulation time	10460988169 ps
CPU time	505.64 seconds
Started	Jul 24 07:47:46 PM PDT 24
Finished	Jul 24 07:56:12 PM PDT 24
Peak memory	576408 kb
Host	smart-ad66ddfc-d410-470c-b838-c384d5d9af88
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424670360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.3424670360
Directory	/workspace/92.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.26827355
Short name	T2074
Test name
Test status
Simulation time	188991758 ps
CPU time	20.91 seconds
Started	Jul 24 07:47:44 PM PDT 24
Finished	Jul 24 07:48:05 PM PDT 24
Peak memory	576992 kb
Host	smart-f32a9823-4a7f-4363-87e1-d6e11753bc71
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26827355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.26827355
Directory	/workspace/92.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_access_same_device.3005402456
Short name	T2320
Test name
Test status
Simulation time	3115724298 ps
CPU time	139.04 seconds
Started	Jul 24 07:47:55 PM PDT 24
Finished	Jul 24 07:50:14 PM PDT 24
Peak memory	577232 kb
Host	smart-825adde0-f572-4117-bd9c-bbed44c098e2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005402456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .3005402456
Directory	/workspace/93.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.1119719491
Short name	T939
Test name
Test status
Simulation time	5232513724 ps
CPU time	92.41 seconds
Started	Jul 24 07:47:59 PM PDT 24
Finished	Jul 24 07:49:31 PM PDT 24
Peak memory	576264 kb
Host	smart-df511632-1120-419d-b37f-f6ba1644ba9e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119719491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.1119719491
Directory	/workspace/93.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2547814180
Short name	T1981
Test name
Test status
Simulation time	1071514160 ps
CPU time	41.88 seconds
Started	Jul 24 07:47:52 PM PDT 24
Finished	Jul 24 07:48:34 PM PDT 24
Peak memory	576160 kb
Host	smart-2d7f4dcf-24f6-4f84-ae46-f8c2f6272db3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547814180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.2547814180
Directory	/workspace/93.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_error_random.2946886808
Short name	T2290
Test name
Test status
Simulation time	1648447436 ps
CPU time	45.84 seconds
Started	Jul 24 07:47:52 PM PDT 24
Finished	Jul 24 07:48:38 PM PDT 24
Peak memory	577016 kb
Host	smart-608f451d-8b9b-46b7-a2c0-c543b15b8446
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946886808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.2946886808
Directory	/workspace/93.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_random.113201629
Short name	T651
Test name
Test status
Simulation time	711471206 ps
CPU time	28.51 seconds
Started	Jul 24 07:47:49 PM PDT 24
Finished	Jul 24 07:48:18 PM PDT 24
Peak memory	576160 kb
Host	smart-1029ce0b-36d5-43cf-8515-b2a18ed637f9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113201629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.113201629
Directory	/workspace/93.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_random_large_delays.3779383613
Short name	T1656
Test name
Test status
Simulation time	52336273424 ps
CPU time	546.95 seconds
Started	Jul 24 07:47:53 PM PDT 24
Finished	Jul 24 07:57:00 PM PDT 24
Peak memory	577116 kb
Host	smart-a9295608-aaea-4884-875f-d637203ce1c9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779383613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.3779383613
Directory	/workspace/93.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.471102383
Short name	T2591
Test name
Test status
Simulation time	37748371982 ps
CPU time	721.16 seconds
Started	Jul 24 07:47:53 PM PDT 24
Finished	Jul 24 07:59:54 PM PDT 24
Peak memory	576288 kb
Host	smart-6ed74aa3-641c-4627-93cc-da653391fb71
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471102383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.471102383
Directory	/workspace/93.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.3126749748
Short name	T2895
Test name
Test status
Simulation time	184904771 ps
CPU time	20.39 seconds
Started	Jul 24 07:47:44 PM PDT 24
Finished	Jul 24 07:48:05 PM PDT 24
Peak memory	576224 kb
Host	smart-80d83f19-fafc-4e4b-94b8-1165b6f568f2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126749748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.3126749748
Directory	/workspace/93.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_same_source.3722502679
Short name	T2399
Test name
Test status
Simulation time	593503884 ps
CPU time	35.84 seconds
Started	Jul 24 07:47:52 PM PDT 24
Finished	Jul 24 07:48:28 PM PDT 24
Peak memory	576168 kb
Host	smart-865532bc-82e6-45c3-99d7-affaf5e03474
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722502679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.3722502679
Directory	/workspace/93.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke.670683726
Short name	T2633
Test name
Test status
Simulation time	227672198 ps
CPU time	10.2 seconds
Started	Jul 24 07:47:44 PM PDT 24
Finished	Jul 24 07:47:54 PM PDT 24
Peak memory	574904 kb
Host	smart-e5b92b6c-7373-4888-bb6f-ac77c517844f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670683726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.670683726
Directory	/workspace/93.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.577583529
Short name	T2814
Test name
Test status
Simulation time	7986344630 ps
CPU time	81.84 seconds
Started	Jul 24 07:47:44 PM PDT 24
Finished	Jul 24 07:49:06 PM PDT 24
Peak memory	575016 kb
Host	smart-159bd976-d98d-425e-ad5c-a95056c6e2fa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577583529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.577583529
Directory	/workspace/93.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3184512621
Short name	T2619
Test name
Test status
Simulation time	4700256138 ps
CPU time	81.23 seconds
Started	Jul 24 07:47:46 PM PDT 24
Finished	Jul 24 07:49:07 PM PDT 24
Peak memory	575036 kb
Host	smart-284b6153-93f5-49d7-9829-d7550660423f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184512621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.3184512621
Directory	/workspace/93.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.985558165
Short name	T2607
Test name
Test status
Simulation time	38583190 ps
CPU time	5.92 seconds
Started	Jul 24 07:47:44 PM PDT 24
Finished	Jul 24 07:47:50 PM PDT 24
Peak memory	576192 kb
Host	smart-9dc70f6c-dcc1-45aa-80fa-d5b96fc69ab2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985558165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays .985558165
Directory	/workspace/93.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all.1629928239
Short name	T503
Test name
Test status
Simulation time	3546033048 ps
CPU time	112.78 seconds
Started	Jul 24 07:47:51 PM PDT 24
Finished	Jul 24 07:49:44 PM PDT 24
Peak memory	577364 kb
Host	smart-a3f96e37-153c-4685-9b24-54e107e67ab9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629928239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.1629928239
Directory	/workspace/93.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.1539730628
Short name	T1984
Test name
Test status
Simulation time	9506412400 ps
CPU time	319.13 seconds
Started	Jul 24 07:47:53 PM PDT 24
Finished	Jul 24 07:53:12 PM PDT 24
Peak memory	577312 kb
Host	smart-66dbfd91-b4dc-4844-a438-c6c8cbff4bdd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539730628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.1539730628
Directory	/workspace/93.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1594524452
Short name	T1998
Test name
Test status
Simulation time	9877966397 ps
CPU time	585.09 seconds
Started	Jul 24 07:47:52 PM PDT 24
Finished	Jul 24 07:57:37 PM PDT 24
Peak memory	577280 kb
Host	smart-b6ea69eb-aec8-433a-91df-3467638ead84
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594524452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.1594524452
Directory	/workspace/93.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.1944830199
Short name	T716
Test name
Test status
Simulation time	6147862487 ps
CPU time	617.09 seconds
Started	Jul 24 07:47:55 PM PDT 24
Finished	Jul 24 07:58:12 PM PDT 24
Peak memory	577344 kb
Host	smart-618871b8-b871-49da-92ac-51ddb97c8a3a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944830199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.1944830199
Directory	/workspace/93.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.3328768200
Short name	T679
Test name
Test status
Simulation time	1086445458 ps
CPU time	42.98 seconds
Started	Jul 24 07:47:54 PM PDT 24
Finished	Jul 24 07:48:37 PM PDT 24
Peak memory	576996 kb
Host	smart-94ddf7e6-30eb-4e20-a018-7ddc60c2eb18
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328768200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.3328768200
Directory	/workspace/93.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_access_same_device.3409334065
Short name	T1721
Test name
Test status
Simulation time	382553766 ps
CPU time	28.32 seconds
Started	Jul 24 07:48:07 PM PDT 24
Finished	Jul 24 07:48:36 PM PDT 24
Peak memory	577000 kb
Host	smart-431b5ede-4d28-4667-92b9-9ed12f180c26
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409334065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .3409334065
Directory	/workspace/94.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1443189477
Short name	T2423
Test name
Test status
Simulation time	15393435239 ps
CPU time	256.64 seconds
Started	Jul 24 07:48:00 PM PDT 24
Finished	Jul 24 07:52:17 PM PDT 24
Peak memory	577200 kb
Host	smart-2ebb42a1-164a-4e36-9cec-25266051ef6f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443189477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.1443189477
Directory	/workspace/94.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.2684634847
Short name	T2378
Test name
Test status
Simulation time	317786493 ps
CPU time	34.63 seconds
Started	Jul 24 07:48:04 PM PDT 24
Finished	Jul 24 07:48:39 PM PDT 24
Peak memory	575932 kb
Host	smart-b63a8305-5be0-4e0d-a585-afbb0aaca229
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684634847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.2684634847
Directory	/workspace/94.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_error_random.2095576583
Short name	T1547
Test name
Test status
Simulation time	455253641 ps
CPU time	40.6 seconds
Started	Jul 24 07:48:02 PM PDT 24
Finished	Jul 24 07:48:43 PM PDT 24
Peak memory	576964 kb
Host	smart-d8a86053-1e23-4ac6-957f-d2a4167237e8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095576583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.2095576583
Directory	/workspace/94.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_random.272507884
Short name	T2305
Test name
Test status
Simulation time	1597838770 ps
CPU time	51.39 seconds
Started	Jul 24 07:48:02 PM PDT 24
Finished	Jul 24 07:48:54 PM PDT 24
Peak memory	576212 kb
Host	smart-85bea1d4-6af2-460d-a650-0c3a82524f06
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272507884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.272507884
Directory	/workspace/94.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_random_large_delays.490657100
Short name	T2604
Test name
Test status
Simulation time	104052424762 ps
CPU time	1183.63 seconds
Started	Jul 24 07:48:02 PM PDT 24
Finished	Jul 24 08:07:46 PM PDT 24
Peak memory	576324 kb
Host	smart-0f62fb10-a09d-44c2-8be0-1ded0244a7cb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490657100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.490657100
Directory	/workspace/94.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3186842032
Short name	T2055
Test name
Test status
Simulation time	56867829189 ps
CPU time	1150.31 seconds
Started	Jul 24 07:48:01 PM PDT 24
Finished	Jul 24 08:07:11 PM PDT 24
Peak memory	576312 kb
Host	smart-4a8b68bd-1029-4841-847e-c593d1a0fcec
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186842032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3186842032
Directory	/workspace/94.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.4202540902
Short name	T1515
Test name
Test status
Simulation time	316071211 ps
CPU time	28.13 seconds
Started	Jul 24 07:48:06 PM PDT 24
Finished	Jul 24 07:48:34 PM PDT 24
Peak memory	576128 kb
Host	smart-b7325373-4c4a-4133-8e8f-0e10e2a53145
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202540902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.4202540902
Directory	/workspace/94.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_same_source.3223871712
Short name	T2394
Test name
Test status
Simulation time	130441596 ps
CPU time	6.91 seconds
Started	Jul 24 07:48:00 PM PDT 24
Finished	Jul 24 07:48:07 PM PDT 24
Peak memory	574860 kb
Host	smart-7f861fe9-0429-4911-a879-1a7b405efb0a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223871712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3223871712
Directory	/workspace/94.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke.4096070055
Short name	T1663
Test name
Test status
Simulation time	217128401 ps
CPU time	9.44 seconds
Started	Jul 24 07:47:54 PM PDT 24
Finished	Jul 24 07:48:04 PM PDT 24
Peak memory	576120 kb
Host	smart-d056bd48-19da-41b8-a67e-2d9ee81e1cc2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096070055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.4096070055
Directory	/workspace/94.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.2461939815
Short name	T2416
Test name
Test status
Simulation time	8321375263 ps
CPU time	88.71 seconds
Started	Jul 24 07:47:52 PM PDT 24
Finished	Jul 24 07:49:21 PM PDT 24
Peak memory	576296 kb
Host	smart-9547b20f-7693-44e3-a53a-b345fafdbcdc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461939815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.2461939815
Directory	/workspace/94.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.1312507607
Short name	T1661
Test name
Test status
Simulation time	5039088626 ps
CPU time	89.23 seconds
Started	Jul 24 07:48:01 PM PDT 24
Finished	Jul 24 07:49:31 PM PDT 24
Peak memory	575032 kb
Host	smart-990a45d6-2a50-4c91-b57c-d1aff8c5b33b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312507607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.1312507607
Directory	/workspace/94.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.1249952862
Short name	T1549
Test name
Test status
Simulation time	43638818 ps
CPU time	6.43 seconds
Started	Jul 24 07:47:53 PM PDT 24
Finished	Jul 24 07:47:59 PM PDT 24
Peak memory	574860 kb
Host	smart-41604792-fabb-44c8-849b-832f6a53eb32
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249952862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.1249952862
Directory	/workspace/94.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all.362927659
Short name	T482
Test name
Test status
Simulation time	2161445175 ps
CPU time	184.13 seconds
Started	Jul 24 07:48:01 PM PDT 24
Finished	Jul 24 07:51:05 PM PDT 24
Peak memory	576384 kb
Host	smart-56147d40-89c1-4422-bb70-ba1c0c9d7ef1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362927659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.362927659
Directory	/workspace/94.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.3251012072
Short name	T1674
Test name
Test status
Simulation time	8557958657 ps
CPU time	321.83 seconds
Started	Jul 24 07:48:00 PM PDT 24
Finished	Jul 24 07:53:22 PM PDT 24
Peak memory	576180 kb
Host	smart-eed63be5-9982-41c0-90a0-5e66e80f0f16
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251012072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.3251012072
Directory	/workspace/94.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.1312026725
Short name	T2609
Test name
Test status
Simulation time	19222146170 ps
CPU time	992.69 seconds
Started	Jul 24 07:48:09 PM PDT 24
Finished	Jul 24 08:04:42 PM PDT 24
Peak memory	577292 kb
Host	smart-4363e289-d19b-4102-8e2e-cf584ae5a982
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312026725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.1312026725
Directory	/workspace/94.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.711124357
Short name	T1684
Test name
Test status
Simulation time	118747862 ps
CPU time	15.17 seconds
Started	Jul 24 07:48:07 PM PDT 24
Finished	Jul 24 07:48:23 PM PDT 24
Peak memory	576136 kb
Host	smart-bd57d602-5793-4e18-a4b6-c39dbd2f7a76
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711124357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.711124357
Directory	/workspace/94.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1851753601
Short name	T2444
Test name
Test status
Simulation time	65147287104 ps
CPU time	1216.42 seconds
Started	Jul 24 07:48:14 PM PDT 24
Finished	Jul 24 08:08:31 PM PDT 24
Peak memory	577196 kb
Host	smart-deef2803-49f3-4ad7-a3b7-9a2c2b7090a1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851753601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.1851753601
Directory	/workspace/95.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2602411479
Short name	T1477
Test name
Test status
Simulation time	1245268311 ps
CPU time	42.54 seconds
Started	Jul 24 07:48:12 PM PDT 24
Finished	Jul 24 07:48:55 PM PDT 24
Peak memory	577008 kb
Host	smart-d9747013-1706-41c1-b01f-d318937568ec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602411479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.2602411479
Directory	/workspace/95.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_error_random.142961417
Short name	T2197
Test name
Test status
Simulation time	433927875 ps
CPU time	34 seconds
Started	Jul 24 07:48:14 PM PDT 24
Finished	Jul 24 07:48:48 PM PDT 24
Peak memory	576940 kb
Host	smart-b68e4f43-5b40-4fb8-941c-c94cb7884792
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142961417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.142961417
Directory	/workspace/95.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_random.1030879655
Short name	T2744
Test name
Test status
Simulation time	1651549858 ps
CPU time	57.89 seconds
Started	Jul 24 07:48:15 PM PDT 24
Finished	Jul 24 07:49:13 PM PDT 24
Peak memory	576120 kb
Host	smart-f2278ff0-9df6-420f-ab61-b3a14b276287
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030879655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.1030879655
Directory	/workspace/95.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_random_large_delays.1608562024
Short name	T2172
Test name
Test status
Simulation time	80649376763 ps
CPU time	874.2 seconds
Started	Jul 24 07:48:12 PM PDT 24
Finished	Jul 24 08:02:46 PM PDT 24
Peak memory	576244 kb
Host	smart-4c793803-eb28-4b34-9ca8-09d4d648b75c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608562024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.1608562024
Directory	/workspace/95.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.2796253454
Short name	T639
Test name
Test status
Simulation time	32815562739 ps
CPU time	609.43 seconds
Started	Jul 24 07:48:12 PM PDT 24
Finished	Jul 24 07:58:22 PM PDT 24
Peak memory	577080 kb
Host	smart-6d518e9e-c97a-4e4d-ab09-0bf571d0d98d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796253454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.2796253454
Directory	/workspace/95.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.4058106789
Short name	T2030
Test name
Test status
Simulation time	284171317 ps
CPU time	26.81 seconds
Started	Jul 24 07:48:12 PM PDT 24
Finished	Jul 24 07:48:39 PM PDT 24
Peak memory	576220 kb
Host	smart-4f5c75f0-3a91-4ff6-9557-a0d9d2b2a09f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058106789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.4058106789
Directory	/workspace/95.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_same_source.4213926640
Short name	T608
Test name
Test status
Simulation time	534026953 ps
CPU time	38.8 seconds
Started	Jul 24 07:48:13 PM PDT 24
Finished	Jul 24 07:48:52 PM PDT 24
Peak memory	576124 kb
Host	smart-406c051c-6a0d-4af4-9cca-0170f11a568a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213926640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.4213926640
Directory	/workspace/95.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke.1249099614
Short name	T2757
Test name
Test status
Simulation time	198889158 ps
CPU time	8.36 seconds
Started	Jul 24 07:48:01 PM PDT 24
Finished	Jul 24 07:48:10 PM PDT 24
Peak memory	574924 kb
Host	smart-73e4f89b-3335-4673-9bca-876b39287b69
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249099614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1249099614
Directory	/workspace/95.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.4124347795
Short name	T2078
Test name
Test status
Simulation time	8917832869 ps
CPU time	91.77 seconds
Started	Jul 24 07:48:02 PM PDT 24
Finished	Jul 24 07:49:33 PM PDT 24
Peak memory	575016 kb
Host	smart-7e454a09-5c8e-4ef2-9bf3-27116c1db732
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124347795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.4124347795
Directory	/workspace/95.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.4023216996
Short name	T2009
Test name
Test status
Simulation time	5705665596 ps
CPU time	100.4 seconds
Started	Jul 24 07:48:01 PM PDT 24
Finished	Jul 24 07:49:41 PM PDT 24
Peak memory	576268 kb
Host	smart-203098ae-28a6-4fdb-9630-caea6c5b770a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023216996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.4023216996
Directory	/workspace/95.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3280718454
Short name	T2363
Test name
Test status
Simulation time	48670540 ps
CPU time	6.57 seconds
Started	Jul 24 07:48:05 PM PDT 24
Finished	Jul 24 07:48:11 PM PDT 24
Peak memory	574860 kb
Host	smart-2eb15ade-d5bd-459d-8cd7-f20390f8394a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280718454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.3280718454
Directory	/workspace/95.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all.3678912462
Short name	T1891
Test name
Test status
Simulation time	932299894 ps
CPU time	75.35 seconds
Started	Jul 24 07:48:14 PM PDT 24
Finished	Jul 24 07:49:29 PM PDT 24
Peak memory	577104 kb
Host	smart-88cb5df2-6536-43a7-b407-1cd667f23aa9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678912462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.3678912462
Directory	/workspace/95.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.2100888204
Short name	T1754
Test name
Test status
Simulation time	6464034353 ps
CPU time	246.39 seconds
Started	Jul 24 07:48:13 PM PDT 24
Finished	Jul 24 07:52:20 PM PDT 24
Peak memory	576456 kb
Host	smart-5fa135e1-677e-4ef2-beb2-676e5442174f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100888204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.2100888204
Directory	/workspace/95.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.1953169115
Short name	T2494
Test name
Test status
Simulation time	110973182 ps
CPU time	29.22 seconds
Started	Jul 24 07:48:16 PM PDT 24
Finished	Jul 24 07:48:46 PM PDT 24
Peak memory	576376 kb
Host	smart-64e9b0c6-aafe-4e81-82dc-ff6e40fe4149
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953169115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.1953169115
Directory	/workspace/95.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3503067563
Short name	T2492
Test name
Test status
Simulation time	453304126 ps
CPU time	109.56 seconds
Started	Jul 24 07:48:12 PM PDT 24
Finished	Jul 24 07:50:01 PM PDT 24
Peak memory	577104 kb
Host	smart-791bb228-c810-47f4-8bfb-288ea45ecc18
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503067563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.3503067563
Directory	/workspace/95.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.2488132895
Short name	T2542
Test name
Test status
Simulation time	706269301 ps
CPU time	32.88 seconds
Started	Jul 24 07:48:11 PM PDT 24
Finished	Jul 24 07:48:44 PM PDT 24
Peak memory	576192 kb
Host	smart-532224ac-11f9-4d7b-980d-28f2b1371a69
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488132895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.2488132895
Directory	/workspace/95.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_access_same_device.652474810
Short name	T896
Test name
Test status
Simulation time	2490993783 ps
CPU time	100.66 seconds
Started	Jul 24 07:48:21 PM PDT 24
Finished	Jul 24 07:50:02 PM PDT 24
Peak memory	577080 kb
Host	smart-641b0c05-5332-4f50-98a6-aac019027887
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652474810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device. 652474810
Directory	/workspace/96.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.798860950
Short name	T2459
Test name
Test status
Simulation time	16315369009 ps
CPU time	272.88 seconds
Started	Jul 24 07:48:22 PM PDT 24
Finished	Jul 24 07:52:56 PM PDT 24
Peak memory	576176 kb
Host	smart-f0115660-142e-4904-b401-4ab3c9fad129
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798860950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_d evice_slow_rsp.798860950
Directory	/workspace/96.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3765974755
Short name	T2451
Test name
Test status
Simulation time	226822638 ps
CPU time	29.67 seconds
Started	Jul 24 07:48:21 PM PDT 24
Finished	Jul 24 07:48:51 PM PDT 24
Peak memory	576908 kb
Host	smart-ff2ae959-6cf7-4828-8f19-cc3bf52759dc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765974755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.3765974755
Directory	/workspace/96.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_error_random.183210287
Short name	T2710
Test name
Test status
Simulation time	653573145 ps
CPU time	20.41 seconds
Started	Jul 24 07:48:20 PM PDT 24
Finished	Jul 24 07:48:41 PM PDT 24
Peak memory	575864 kb
Host	smart-673871ed-26ad-4d37-89ce-d6d2232271af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183210287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.183210287
Directory	/workspace/96.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_random.816052828
Short name	T1582
Test name
Test status
Simulation time	857533864 ps
CPU time	33.14 seconds
Started	Jul 24 07:48:20 PM PDT 24
Finished	Jul 24 07:48:53 PM PDT 24
Peak memory	576264 kb
Host	smart-52ae01f2-e0ff-4328-8d0d-0b9a5058efb3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816052828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.816052828
Directory	/workspace/96.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_random_large_delays.991470977
Short name	T2892
Test name
Test status
Simulation time	24430524477 ps
CPU time	260.14 seconds
Started	Jul 24 07:48:23 PM PDT 24
Finished	Jul 24 07:52:43 PM PDT 24
Peak memory	576220 kb
Host	smart-d8650fbc-1318-4f1c-a652-e73a1d036ace
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991470977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.991470977
Directory	/workspace/96.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.3535729003
Short name	T2018
Test name
Test status
Simulation time	15102746328 ps
CPU time	267.75 seconds
Started	Jul 24 07:48:20 PM PDT 24
Finished	Jul 24 07:52:48 PM PDT 24
Peak memory	576360 kb
Host	smart-476a9f8f-a2f6-4f6d-9b89-e7d82bc74bae
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535729003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.3535729003
Directory	/workspace/96.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.3808050353
Short name	T467
Test name
Test status
Simulation time	276095011 ps
CPU time	23.12 seconds
Started	Jul 24 07:48:22 PM PDT 24
Finished	Jul 24 07:48:46 PM PDT 24
Peak memory	576216 kb
Host	smart-306133ac-39a5-4930-bae7-79c43502f254
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808050353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.3808050353
Directory	/workspace/96.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_same_source.1863800682
Short name	T521
Test name
Test status
Simulation time	428784212 ps
CPU time	31.59 seconds
Started	Jul 24 07:48:25 PM PDT 24
Finished	Jul 24 07:48:57 PM PDT 24
Peak memory	576180 kb
Host	smart-65798f4d-ff91-49b7-8c06-09bb48ec3616
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863800682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.1863800682
Directory	/workspace/96.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke.2210500857
Short name	T1513
Test name
Test status
Simulation time	34664599 ps
CPU time	5.94 seconds
Started	Jul 24 07:48:11 PM PDT 24
Finished	Jul 24 07:48:17 PM PDT 24
Peak memory	574892 kb
Host	smart-9dc37630-b2c2-4ceb-b3c1-020b1cb2dbf1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210500857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.2210500857
Directory	/workspace/96.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2232099
Short name	T2749
Test name
Test status
Simulation time	8937245542 ps
CPU time	91.06 seconds
Started	Jul 24 07:48:12 PM PDT 24
Finished	Jul 24 07:49:43 PM PDT 24
Peak memory	575036 kb
Host	smart-380b166d-7684-4865-b5ca-9a6f2feb544a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2232099
Directory	/workspace/96.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.3091012736
Short name	T2153
Test name
Test status
Simulation time	4364776818 ps
CPU time	71.76 seconds
Started	Jul 24 07:48:15 PM PDT 24
Finished	Jul 24 07:49:27 PM PDT 24
Peak memory	575048 kb
Host	smart-87a3cc85-95e4-4ffe-bceb-a5250bcb4016
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091012736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.3091012736
Directory	/workspace/96.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.1034495522
Short name	T2645
Test name
Test status
Simulation time	51772346 ps
CPU time	6.32 seconds
Started	Jul 24 07:48:13 PM PDT 24
Finished	Jul 24 07:48:19 PM PDT 24
Peak memory	574912 kb
Host	smart-4642edd7-b76f-4486-bda2-721f91bde995
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034495522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.1034495522
Directory	/workspace/96.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all.2722925242
Short name	T1906
Test name
Test status
Simulation time	3115534875 ps
CPU time	226.45 seconds
Started	Jul 24 07:48:20 PM PDT 24
Finished	Jul 24 07:52:07 PM PDT 24
Peak memory	576464 kb
Host	smart-f88365b5-e8da-4552-9f57-ea6521fc030f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722925242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.2722925242
Directory	/workspace/96.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.1207067696
Short name	T1957
Test name
Test status
Simulation time	9853409203 ps
CPU time	391.74 seconds
Started	Jul 24 07:48:24 PM PDT 24
Finished	Jul 24 07:54:56 PM PDT 24
Peak memory	576204 kb
Host	smart-134e2615-e83d-4c30-9376-ceec21c73bd2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207067696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.1207067696
Directory	/workspace/96.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.56284825
Short name	T1521
Test name
Test status
Simulation time	48832941 ps
CPU time	62.32 seconds
Started	Jul 24 07:48:19 PM PDT 24
Finished	Jul 24 07:49:22 PM PDT 24
Peak memory	576376 kb
Host	smart-32acfcb8-5111-4e83-8779-f927c26ce28a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56284825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_w ith_rand_reset.56284825
Directory	/workspace/96.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.1881959973
Short name	T2849
Test name
Test status
Simulation time	8882050 ps
CPU time	15.01 seconds
Started	Jul 24 07:48:23 PM PDT 24
Finished	Jul 24 07:48:38 PM PDT 24
Peak memory	574980 kb
Host	smart-c3e25a1c-f165-4943-8fc5-8b2c2208abd6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881959973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.1881959973
Directory	/workspace/96.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.1111575539
Short name	T1625
Test name
Test status
Simulation time	101425477 ps
CPU time	15 seconds
Started	Jul 24 07:48:25 PM PDT 24
Finished	Jul 24 07:48:40 PM PDT 24
Peak memory	576224 kb
Host	smart-a5a0aee5-4eb8-4d7f-9402-7ffec0c906e4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111575539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.1111575539
Directory	/workspace/96.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_access_same_device.3203004714
Short name	T1578
Test name
Test status
Simulation time	599003467 ps
CPU time	29.93 seconds
Started	Jul 24 07:48:22 PM PDT 24
Finished	Jul 24 07:48:53 PM PDT 24
Peak memory	576896 kb
Host	smart-02b93f98-226f-4902-9af1-9f58031ae660
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203004714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .3203004714
Directory	/workspace/97.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.4159162176
Short name	T2384
Test name
Test status
Simulation time	98112561267 ps
CPU time	1892 seconds
Started	Jul 24 07:48:34 PM PDT 24
Finished	Jul 24 08:20:07 PM PDT 24
Peak memory	577244 kb
Host	smart-b8d10dda-f25d-405c-b4bc-c19f97bf1db0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159162176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.4159162176
Directory	/workspace/97.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1635300338
Short name	T2203
Test name
Test status
Simulation time	920355896 ps
CPU time	32.13 seconds
Started	Jul 24 07:48:30 PM PDT 24
Finished	Jul 24 07:49:03 PM PDT 24
Peak memory	576192 kb
Host	smart-d82ccd66-ee0c-469e-830a-75a7da135b28
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635300338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.1635300338
Directory	/workspace/97.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_error_random.2173260251
Short name	T1646
Test name
Test status
Simulation time	2192890972 ps
CPU time	74.08 seconds
Started	Jul 24 07:48:34 PM PDT 24
Finished	Jul 24 07:49:48 PM PDT 24
Peak memory	577212 kb
Host	smart-bb1881d6-67a9-4725-b3db-1a795383a3cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173260251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.2173260251
Directory	/workspace/97.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_random.1106500744
Short name	T2202
Test name
Test status
Simulation time	1526005879 ps
CPU time	52.52 seconds
Started	Jul 24 07:48:20 PM PDT 24
Finished	Jul 24 07:49:13 PM PDT 24
Peak memory	576240 kb
Host	smart-25625584-3f6a-42c8-8d4d-0bbecad4bb0e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106500744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.1106500744
Directory	/workspace/97.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_random_large_delays.60646067
Short name	T1979
Test name
Test status
Simulation time	80766901391 ps
CPU time	905.74 seconds
Started	Jul 24 07:48:21 PM PDT 24
Finished	Jul 24 08:03:27 PM PDT 24
Peak memory	576300 kb
Host	smart-074032e4-4f6f-49fd-b37c-aae6d204fd8a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60646067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.60646067
Directory	/workspace/97.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.277300660
Short name	T731
Test name
Test status
Simulation time	9201523585 ps
CPU time	145.45 seconds
Started	Jul 24 07:48:24 PM PDT 24
Finished	Jul 24 07:50:49 PM PDT 24
Peak memory	576324 kb
Host	smart-f87c09b1-d284-49e3-bbf8-68f82f52f96b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277300660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.277300660
Directory	/workspace/97.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.398063828
Short name	T2668
Test name
Test status
Simulation time	171230895 ps
CPU time	16.71 seconds
Started	Jul 24 07:48:21 PM PDT 24
Finished	Jul 24 07:48:37 PM PDT 24
Peak memory	576964 kb
Host	smart-f5a060c2-b98e-4c0c-833d-89583abaa400
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398063828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_dela ys.398063828
Directory	/workspace/97.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_same_source.700657640
Short name	T2236
Test name
Test status
Simulation time	1617502948 ps
CPU time	44.33 seconds
Started	Jul 24 07:48:27 PM PDT 24
Finished	Jul 24 07:49:12 PM PDT 24
Peak memory	576980 kb
Host	smart-ad55d656-62e4-4968-933e-656bd8fe4e9d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700657640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.700657640
Directory	/workspace/97.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke.998568868
Short name	T1801
Test name
Test status
Simulation time	52881867 ps
CPU time	6.32 seconds
Started	Jul 24 07:48:23 PM PDT 24
Finished	Jul 24 07:48:29 PM PDT 24
Peak memory	574884 kb
Host	smart-2575797e-f937-447e-b6e1-b995470a9378
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998568868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.998568868
Directory	/workspace/97.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.318097119
Short name	T2704
Test name
Test status
Simulation time	8700813944 ps
CPU time	91.34 seconds
Started	Jul 24 07:48:22 PM PDT 24
Finished	Jul 24 07:49:53 PM PDT 24
Peak memory	575060 kb
Host	smart-64defd06-b5cb-4e9f-a1dd-7adf300cdfac
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318097119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.318097119
Directory	/workspace/97.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.2765401115
Short name	T2426
Test name
Test status
Simulation time	5596102119 ps
CPU time	91.83 seconds
Started	Jul 24 07:48:20 PM PDT 24
Finished	Jul 24 07:49:52 PM PDT 24
Peak memory	575056 kb
Host	smart-23cd2534-9001-48de-8142-0fd6092795b8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765401115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.2765401115
Directory	/workspace/97.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1264983027
Short name	T730
Test name
Test status
Simulation time	52883687 ps
CPU time	6.71 seconds
Started	Jul 24 07:48:21 PM PDT 24
Finished	Jul 24 07:48:28 PM PDT 24
Peak memory	574852 kb
Host	smart-cfe7f24e-bdb8-4468-aad1-bc8730fb1cec
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264983027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.1264983027
Directory	/workspace/97.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all.4003797763
Short name	T2256
Test name
Test status
Simulation time	16365042233 ps
CPU time	692.57 seconds
Started	Jul 24 07:48:34 PM PDT 24
Finished	Jul 24 08:00:07 PM PDT 24
Peak memory	577248 kb
Host	smart-7272a2f6-c441-4190-9169-8115b92f720c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003797763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.4003797763
Directory	/workspace/97.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.431236574
Short name	T1945
Test name
Test status
Simulation time	3511443130 ps
CPU time	263.02 seconds
Started	Jul 24 07:48:29 PM PDT 24
Finished	Jul 24 07:52:52 PM PDT 24
Peak memory	577100 kb
Host	smart-2b9597a8-269c-4615-9c6a-43e6c6c57eb5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431236574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.431236574
Directory	/workspace/97.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.4185483600
Short name	T2335
Test name
Test status
Simulation time	45304510 ps
CPU time	19.53 seconds
Started	Jul 24 07:48:29 PM PDT 24
Finished	Jul 24 07:48:49 PM PDT 24
Peak memory	575052 kb
Host	smart-7472d187-9a54-45fe-9b86-a4d90753cc73
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185483600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.4185483600
Directory	/workspace/97.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3602365659
Short name	T2743
Test name
Test status
Simulation time	3059407086 ps
CPU time	370.61 seconds
Started	Jul 24 07:48:31 PM PDT 24
Finished	Jul 24 07:54:41 PM PDT 24
Peak memory	576440 kb
Host	smart-efbbc7c8-0c65-454c-9524-4cea7be257c2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602365659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.3602365659
Directory	/workspace/97.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.3121666963
Short name	T1629
Test name
Test status
Simulation time	85041776 ps
CPU time	6.76 seconds
Started	Jul 24 07:48:28 PM PDT 24
Finished	Jul 24 07:48:35 PM PDT 24
Peak memory	574916 kb
Host	smart-3d5109f8-0320-487c-b608-911157dd0004
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121666963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.3121666963
Directory	/workspace/97.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_access_same_device.2331751352
Short name	T2299
Test name
Test status
Simulation time	923350786 ps
CPU time	75.06 seconds
Started	Jul 24 07:48:28 PM PDT 24
Finished	Jul 24 07:49:44 PM PDT 24
Peak memory	577084 kb
Host	smart-44846b8c-dcda-4cb9-a9c6-5e16c95eb26c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331751352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .2331751352
Directory	/workspace/98.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2660286977
Short name	T2063
Test name
Test status
Simulation time	31277180778 ps
CPU time	500.13 seconds
Started	Jul 24 07:48:30 PM PDT 24
Finished	Jul 24 07:56:50 PM PDT 24
Peak memory	577136 kb
Host	smart-3e4099c3-a7b3-4617-acaf-07a718d5f931
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660286977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.2660286977
Directory	/workspace/98.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.1227430989
Short name	T1520
Test name
Test status
Simulation time	122338513 ps
CPU time	14.6 seconds
Started	Jul 24 07:48:28 PM PDT 24
Finished	Jul 24 07:48:43 PM PDT 24
Peak memory	577012 kb
Host	smart-fd7cc409-da52-46d6-bfe2-8a119ae1d080
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227430989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.1227430989
Directory	/workspace/98.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_error_random.3431185365
Short name	T1463
Test name
Test status
Simulation time	77325060 ps
CPU time	8.71 seconds
Started	Jul 24 07:48:28 PM PDT 24
Finished	Jul 24 07:48:37 PM PDT 24
Peak memory	576184 kb
Host	smart-75b6193f-5265-4bfa-925d-c6e4fa213981
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431185365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.3431185365
Directory	/workspace/98.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_random.649636695
Short name	T2173
Test name
Test status
Simulation time	1150639115 ps
CPU time	39.52 seconds
Started	Jul 24 07:48:30 PM PDT 24
Finished	Jul 24 07:49:10 PM PDT 24
Peak memory	576976 kb
Host	smart-5362a91a-83cb-4752-bcd4-6e7c80622aac
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649636695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.649636695
Directory	/workspace/98.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3522728122
Short name	T469
Test name
Test status
Simulation time	44916431583 ps
CPU time	471.43 seconds
Started	Jul 24 07:48:28 PM PDT 24
Finished	Jul 24 07:56:20 PM PDT 24
Peak memory	577060 kb
Host	smart-e7358e66-cde8-4fa3-89b1-08dee3d63169
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522728122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.3522728122
Directory	/workspace/98.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.774721494
Short name	T2232
Test name
Test status
Simulation time	34863798104 ps
CPU time	631.68 seconds
Started	Jul 24 07:48:27 PM PDT 24
Finished	Jul 24 07:59:00 PM PDT 24
Peak memory	577184 kb
Host	smart-426c3ba7-d87e-4696-9ac8-d5b340b6ba15
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774721494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.774721494
Directory	/workspace/98.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1285180931
Short name	T2035
Test name
Test status
Simulation time	552200281 ps
CPU time	45.8 seconds
Started	Jul 24 07:48:29 PM PDT 24
Finished	Jul 24 07:49:15 PM PDT 24
Peak memory	577020 kb
Host	smart-4cb2a353-167f-4d06-8fc9-f62725259367
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285180931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.1285180931
Directory	/workspace/98.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_same_source.43413196
Short name	T1694
Test name
Test status
Simulation time	541576623 ps
CPU time	37.97 seconds
Started	Jul 24 07:48:33 PM PDT 24
Finished	Jul 24 07:49:12 PM PDT 24
Peak memory	576204 kb
Host	smart-c414ab2c-ff63-4eb6-95e2-12c6186e31fe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43413196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.43413196
Directory	/workspace/98.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke.1753527257
Short name	T1667
Test name
Test status
Simulation time	36980720 ps
CPU time	6.16 seconds
Started	Jul 24 07:48:34 PM PDT 24
Finished	Jul 24 07:48:40 PM PDT 24
Peak memory	576132 kb
Host	smart-1044e25e-4da5-4bca-8e14-2c9536cbed2e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753527257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.1753527257
Directory	/workspace/98.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.2866265836
Short name	T2774
Test name
Test status
Simulation time	8431315925 ps
CPU time	88.98 seconds
Started	Jul 24 07:48:30 PM PDT 24
Finished	Jul 24 07:49:59 PM PDT 24
Peak memory	574996 kb
Host	smart-98ff7de9-d12c-4b40-a357-9e53b564e4d4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866265836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.2866265836
Directory	/workspace/98.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1284308005
Short name	T2361
Test name
Test status
Simulation time	4155236890 ps
CPU time	68.14 seconds
Started	Jul 24 07:48:27 PM PDT 24
Finished	Jul 24 07:49:36 PM PDT 24
Peak memory	575136 kb
Host	smart-378372b9-7e42-4625-8ce7-2843459767b2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284308005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.1284308005
Directory	/workspace/98.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.81645072
Short name	T1580
Test name
Test status
Simulation time	47500314 ps
CPU time	6.23 seconds
Started	Jul 24 07:48:28 PM PDT 24
Finished	Jul 24 07:48:34 PM PDT 24
Peak memory	574912 kb
Host	smart-2bd469ea-f2ea-475a-b277-1316ce7e2f2a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81645072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays.81645072
Directory	/workspace/98.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all.584790774
Short name	T2598
Test name
Test status
Simulation time	3069239921 ps
CPU time	98.99 seconds
Started	Jul 24 07:48:30 PM PDT 24
Finished	Jul 24 07:50:09 PM PDT 24
Peak memory	577136 kb
Host	smart-a0b21433-6d92-42e7-b3f0-25f7f772f5c5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584790774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.584790774
Directory	/workspace/98.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.214135365
Short name	T753
Test name
Test status
Simulation time	1695371480 ps
CPU time	122.19 seconds
Started	Jul 24 07:48:28 PM PDT 24
Finished	Jul 24 07:50:30 PM PDT 24
Peak memory	577124 kb
Host	smart-a7e6c2dd-29f2-47e0-9f76-6cb0d9903bae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214135365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.214135365
Directory	/workspace/98.xbar_stress_all_with_error/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3590682704
Short name	T2488
Test name
Test status
Simulation time	1724368773 ps
CPU time	166.37 seconds
Started	Jul 24 07:48:35 PM PDT 24
Finished	Jul 24 07:51:22 PM PDT 24
Peak memory	576424 kb
Host	smart-0050c9a1-0c8e-4fde-b890-7f1053cc3ecc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590682704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.3590682704
Directory	/workspace/98.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.2001658548
Short name	T969
Test name
Test status
Simulation time	5471262647 ps
CPU time	560.74 seconds
Started	Jul 24 07:48:31 PM PDT 24
Finished	Jul 24 07:57:52 PM PDT 24
Peak memory	577268 kb
Host	smart-e73eb934-2d3b-42c9-b3b7-6f6ea6f105ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001658548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.2001658548
Directory	/workspace/98.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1226007289
Short name	T1734
Test name
Test status
Simulation time	300160004 ps
CPU time	32.75 seconds
Started	Jul 24 07:48:35 PM PDT 24
Finished	Jul 24 07:49:08 PM PDT 24
Peak memory	576360 kb
Host	smart-cd8d8a06-029c-4d96-9444-317f724beeb7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226007289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1226007289
Directory	/workspace/98.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_access_same_device.3729334438
Short name	T1786
Test name
Test status
Simulation time	2062393359 ps
CPU time	93.23 seconds
Started	Jul 24 07:48:48 PM PDT 24
Finished	Jul 24 07:50:21 PM PDT 24
Peak memory	576184 kb
Host	smart-57339cb0-757b-480d-b474-cff73b0eed04
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729334438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .3729334438
Directory	/workspace/99.xbar_access_same_device/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2150758570
Short name	T2266
Test name
Test status
Simulation time	85900478622 ps
CPU time	1453.57 seconds
Started	Jul 24 07:48:50 PM PDT 24
Finished	Jul 24 08:13:04 PM PDT 24
Peak memory	576196 kb
Host	smart-fa786704-53e2-4db2-9fb3-a2ff41a7520d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150758570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.2150758570
Directory	/workspace/99.xbar_access_same_device_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2195962510
Short name	T2490
Test name
Test status
Simulation time	174802619 ps
CPU time	18.74 seconds
Started	Jul 24 07:48:59 PM PDT 24
Finished	Jul 24 07:49:18 PM PDT 24
Peak memory	576908 kb
Host	smart-878efe00-5fd3-4d54-805d-da39e04efb94
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195962510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.2195962510
Directory	/workspace/99.xbar_error_and_unmapped_addr/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_error_random.4056254358
Short name	T2910
Test name
Test status
Simulation time	281851049 ps
CPU time	12.93 seconds
Started	Jul 24 07:48:50 PM PDT 24
Finished	Jul 24 07:49:03 PM PDT 24
Peak memory	576092 kb
Host	smart-515d8346-aec9-4d67-9bbd-45522bc90044
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056254358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.4056254358
Directory	/workspace/99.xbar_error_random/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_random.3805038089
Short name	T1636
Test name
Test status
Simulation time	2031788188 ps
CPU time	67.32 seconds
Started	Jul 24 07:48:48 PM PDT 24
Finished	Jul 24 07:49:55 PM PDT 24
Peak memory	576168 kb
Host	smart-b2c50982-bebe-4444-b84b-c4283decb6c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805038089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.3805038089
Directory	/workspace/99.xbar_random/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_random_large_delays.1510641742
Short name	T598
Test name
Test status
Simulation time	57112828119 ps
CPU time	620.41 seconds
Started	Jul 24 07:48:48 PM PDT 24
Finished	Jul 24 07:59:09 PM PDT 24
Peak memory	577100 kb
Host	smart-489185d8-14cf-4fa8-87f4-8c69d0d043ec
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510641742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.1510641742
Directory	/workspace/99.xbar_random_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.1872762978
Short name	T488
Test name
Test status
Simulation time	45009324541 ps
CPU time	869.77 seconds
Started	Jul 24 07:48:50 PM PDT 24
Finished	Jul 24 08:03:20 PM PDT 24
Peak memory	577116 kb
Host	smart-c0656d95-c671-42ec-8ff8-42a7e598fb5d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872762978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.1872762978
Directory	/workspace/99.xbar_random_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.299232160
Short name	T2887
Test name
Test status
Simulation time	415889672 ps
CPU time	38.28 seconds
Started	Jul 24 07:48:53 PM PDT 24
Finished	Jul 24 07:49:31 PM PDT 24
Peak memory	576188 kb
Host	smart-a7cf1450-4f74-4dac-8585-2f190d1cceff
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299232160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_dela ys.299232160
Directory	/workspace/99.xbar_random_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_same_source.598079417
Short name	T2311
Test name
Test status
Simulation time	1025965370 ps
CPU time	30.74 seconds
Started	Jul 24 07:48:50 PM PDT 24
Finished	Jul 24 07:49:21 PM PDT 24
Peak memory	576940 kb
Host	smart-31ee7559-a1a8-499a-83e1-57a3fa0a9aed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598079417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.598079417
Directory	/workspace/99.xbar_same_source/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke.3573462375
Short name	T2758
Test name
Test status
Simulation time	190928018 ps
CPU time	8.59 seconds
Started	Jul 24 07:48:34 PM PDT 24
Finished	Jul 24 07:48:42 PM PDT 24
Peak memory	576172 kb
Host	smart-5ddfca70-6c78-46cc-a4b5-b16c3d04954e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573462375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3573462375
Directory	/workspace/99.xbar_smoke/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.399877762
Short name	T2872
Test name
Test status
Simulation time	7134041251 ps
CPU time	75.12 seconds
Started	Jul 24 07:48:30 PM PDT 24
Finished	Jul 24 07:49:45 PM PDT 24
Peak memory	576300 kb
Host	smart-01ec2356-51ea-4624-a65c-b6a0efe0cc50
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399877762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.399877762
Directory	/workspace/99.xbar_smoke_large_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3280678750
Short name	T1678
Test name
Test status
Simulation time	5250074534 ps
CPU time	89.5 seconds
Started	Jul 24 07:48:49 PM PDT 24
Finished	Jul 24 07:50:18 PM PDT 24
Peak memory	575044 kb
Host	smart-97b0fd74-3b9a-4585-9c1b-ac27c51bd257
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280678750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.3280678750
Directory	/workspace/99.xbar_smoke_slow_rsp/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.726786365
Short name	T2518
Test name
Test status
Simulation time	53407774 ps
CPU time	6.42 seconds
Started	Jul 24 07:48:27 PM PDT 24
Finished	Jul 24 07:48:34 PM PDT 24
Peak memory	574864 kb
Host	smart-dd98bf61-055c-4a53-89a8-c0b83a18713a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726786365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays .726786365
Directory	/workspace/99.xbar_smoke_zero_delays/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all.838234747
Short name	T2890
Test name
Test status
Simulation time	1853402495 ps
CPU time	61.37 seconds
Started	Jul 24 07:48:56 PM PDT 24
Finished	Jul 24 07:49:57 PM PDT 24
Peak memory	576252 kb
Host	smart-66831802-c5e4-4463-9346-d6b3f24311a9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838234747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.838234747
Directory	/workspace/99.xbar_stress_all/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.769615634
Short name	T2013
Test name
Test status
Simulation time	3798194893 ps
CPU time	314.36 seconds
Started	Jul 24 07:49:01 PM PDT 24
Finished	Jul 24 07:54:15 PM PDT 24
Peak memory	577284 kb
Host	smart-690e8312-edc9-4905-bfcb-c6c3054fa88f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769615634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_ with_rand_reset.769615634
Directory	/workspace/99.xbar_stress_all_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3688577852
Short name	T2102
Test name
Test status
Simulation time	6563143316 ps
CPU time	678.78 seconds
Started	Jul 24 07:48:56 PM PDT 24
Finished	Jul 24 08:00:15 PM PDT 24
Peak memory	577276 kb
Host	smart-ed61fe4e-88e7-44db-b6b4-cfb86c12b6bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688577852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.3688577852
Directory	/workspace/99.xbar_stress_all_with_reset_error/latest

---

Test location	/workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.3891872415
Short name	T1958
Test name
Test status
Simulation time	1121674562 ps
CPU time	43.42 seconds
Started	Jul 24 07:49:02 PM PDT 24
Finished	Jul 24 07:49:45 PM PDT 24
Peak memory	577036 kb
Host	smart-9092769c-a3ae-4385-8157-5a802c323f67
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891872415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.3891872415
Directory	/workspace/99.xbar_unmapped_addr/latest

---

Test location	/workspace/coverage/default/0.chip_jtag_csr_rw.3289409415
Short name	T198
Test name
Test status
Simulation time	18953799638 ps
CPU time	2388.61 seconds
Started	Jul 24 07:50:09 PM PDT 24
Finished	Jul 24 08:29:58 PM PDT 24
Peak memory	608356 kb
Host	smart-380c9ba6-b1bb-4ee3-9740-10c698fe4bbb
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289409415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.3289409415
Directory	/workspace/0.chip_jtag_csr_rw/latest

---

Test location	/workspace/coverage/default/0.chip_jtag_mem_access.598279964
Short name	T78
Test name
Test status
Simulation time	13438193864 ps
CPU time	1429.11 seconds
Started	Jul 24 07:50:15 PM PDT 24
Finished	Jul 24 08:14:04 PM PDT 24
Peak memory	608336 kb
Host	smart-f2f31775-6dc7-4625-a36b-076be6278791
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598279964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.598279964
Directory	/workspace/0.chip_jtag_mem_access/latest

---

Test location	/workspace/coverage/default/0.chip_sival_flash_info_access.3132542770
Short name	T1257
Test name
Test status
Simulation time	3049577232 ps
CPU time	297.93 seconds
Started	Jul 24 07:59:00 PM PDT 24
Finished	Jul 24 08:03:59 PM PDT 24
Peak memory	610104 kb
Host	smart-cf72db4f-6f60-40a8-895f-1ac840e045aa
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3132542770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3132542770
Directory	/workspace/0.chip_sival_flash_info_access/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aes_enc.348365780
Short name	T387
Test name
Test status
Simulation time	2894039400 ps
CPU time	278.01 seconds
Started	Jul 24 07:57:24 PM PDT 24
Finished	Jul 24 08:02:02 PM PDT 24
Peak memory	610216 kb
Host	smart-92720b7a-f296-453d-bd05-0e62a0444faf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348365780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.348365780
Directory	/workspace/0.chip_sw_aes_enc/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2913720329
Short name	T1041
Test name
Test status
Simulation time	3104697513 ps
CPU time	269.41 seconds
Started	Jul 24 07:56:31 PM PDT 24
Finished	Jul 24 08:01:01 PM PDT 24
Peak memory	610244 kb
Host	smart-1f1d130c-e59b-436f-9c76-0d43e77553bf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913 720329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2913720329
Directory	/workspace/0.chip_sw_aes_enc_jitter_en/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1748222740
Short name	T1110
Test name
Test status
Simulation time	3270875409 ps
CPU time	280.52 seconds
Started	Jul 24 07:59:43 PM PDT 24
Finished	Jul 24 08:04:24 PM PDT 24
Peak memory	610224 kb
Host	smart-92fd4249-57ca-442b-981b-9e3afa5d02a2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748222740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.1748222740
Directory	/workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aes_entropy.1942622574
Short name	T1292
Test name
Test status
Simulation time	3286487682 ps
CPU time	275.3 seconds
Started	Jul 24 07:58:19 PM PDT 24
Finished	Jul 24 08:02:55 PM PDT 24
Peak memory	610216 kb
Host	smart-e347d42f-a6f8-422e-bd61-2e137537a4d6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942622574 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.1942622574
Directory	/workspace/0.chip_sw_aes_entropy/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aes_idle.2971432425
Short name	T1330
Test name
Test status
Simulation time	3322505154 ps
CPU time	207.86 seconds
Started	Jul 24 07:57:34 PM PDT 24
Finished	Jul 24 08:01:02 PM PDT 24
Peak memory	609816 kb
Host	smart-d48f3ef8-d245-4bd4-af8a-b915fdf21c9b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971432425 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.2971432425
Directory	/workspace/0.chip_sw_aes_idle/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aes_masking_off.982345784
Short name	T1373
Test name
Test status
Simulation time	3104648710 ps
CPU time	305.12 seconds
Started	Jul 24 07:56:36 PM PDT 24
Finished	Jul 24 08:01:42 PM PDT 24
Peak memory	609904 kb
Host	smart-aa55abad-85df-47ed-89b5-de4d64d8472e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982345784 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.982345784
Directory	/workspace/0.chip_sw_aes_masking_off/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aes_smoketest.2980685380
Short name	T1386
Test name
Test status
Simulation time	2567866576 ps
CPU time	338.57 seconds
Started	Jul 24 08:01:50 PM PDT 24
Finished	Jul 24 08:07:30 PM PDT 24
Peak memory	609804 kb
Host	smart-91f88b4a-2117-40c8-a977-786a0494be0c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980685380 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.2980685380
Directory	/workspace/0.chip_sw_aes_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1815305453
Short name	T85
Test name
Test status
Simulation time	3739689848 ps
CPU time	330.39 seconds
Started	Jul 24 08:01:24 PM PDT 24
Finished	Jul 24 08:06:56 PM PDT 24
Peak memory	610020 kb
Host	smart-b0cbb8e6-72a3-4989-8fb0-6556adc3ee18
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1815305453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1815305453
Directory	/workspace/0.chip_sw_alert_handler_entropy/latest

---

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1937718752
Short name	T248
Test name
Test status
Simulation time	5685975036 ps
CPU time	614.13 seconds
Started	Jul 24 07:58:08 PM PDT 24
Finished	Jul 24 08:08:22 PM PDT 24
Peak memory	620012 kb
Host	smart-caeffa6e-22c8-47f7-ac0a-377afa845c23
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1937718752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.1937718752
Directory	/workspace/0.chip_sw_alert_handler_escalation/latest

---

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2705700923
Short name	T1153
Test name
Test status
Simulation time	9466378488 ps
CPU time	2345.72 seconds
Started	Jul 24 08:08:37 PM PDT 24
Finished	Jul 24 08:47:43 PM PDT 24
Peak memory	610432 kb
Host	smart-b3352792-1606-4f54-95e2-773dc300ee0c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2705700923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.2705700923
Directory	/workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

---

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2809060775
Short name	T209
Test name
Test status
Simulation time	8769003780 ps
CPU time	1900.18 seconds
Started	Jul 24 07:57:22 PM PDT 24
Finished	Jul 24 08:29:03 PM PDT 24
Peak memory	610532 kb
Host	smart-7496b34a-febd-4767-b641-23c5a43c9d2b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809060775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.2809060775
Directory	/workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

---

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.639295800
Short name	T319
Test name
Test status
Simulation time	3383940256 ps
CPU time	287.93 seconds
Started	Jul 24 07:56:34 PM PDT 24
Finished	Jul 24 08:01:22 PM PDT 24
Peak memory	649104 kb
Host	smart-d8fca6f9-5ddb-489d-8628-00eb0674cd65
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639295800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _alert_handler_lpg_sleep_mode_alerts.639295800
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2626763063
Short name	T1430
Test name
Test status
Simulation time	8547052280 ps
CPU time	1576.41 seconds
Started	Jul 24 07:58:54 PM PDT 24
Finished	Jul 24 08:25:11 PM PDT 24
Peak memory	610608 kb
Host	smart-d5f751bd-bea0-454a-91ae-3b87df64b29b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2626763063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.2626763063
Directory	/workspace/0.chip_sw_alert_handler_ping_ok/latest

---

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2055339238
Short name	T1346
Test name
Test status
Simulation time	4481496300 ps
CPU time	393.67 seconds
Started	Jul 24 07:59:12 PM PDT 24
Finished	Jul 24 08:05:47 PM PDT 24
Peak memory	610540 kb
Host	smart-e67517c9-87cc-4c4e-b30f-702dcf28cdba
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2055339238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.2055339238
Directory	/workspace/0.chip_sw_alert_handler_ping_timeout/latest

---

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1323971929
Short name	T1301
Test name
Test status
Simulation time	254972031914 ps
CPU time	11714.6 seconds
Started	Jul 24 07:58:06 PM PDT 24
Finished	Jul 24 11:13:22 PM PDT 24
Peak memory	611092 kb
Host	smart-d224052d-cf66-4430-be83-58b3948c2faa
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323971929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1323971929
Directory	/workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

---

Test location	/workspace/coverage/default/0.chip_sw_alert_test.3567186704
Short name	T51
Test name
Test status
Simulation time	3141139568 ps
CPU time	348.15 seconds
Started	Jul 24 07:59:14 PM PDT 24
Finished	Jul 24 08:05:03 PM PDT 24
Peak memory	610204 kb
Host	smart-03504f8d-b431-471e-b705-1f4fb421c43a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567186704 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.3567186704
Directory	/workspace/0.chip_sw_alert_test/latest

---

Test location	/workspace/coverage/default/0.chip_sw_all_escalation_resets.1775024606
Short name	T805
Test name
Test status
Simulation time	5889927110 ps
CPU time	773.88 seconds
Started	Jul 24 08:00:33 PM PDT 24
Finished	Jul 24 08:13:28 PM PDT 24
Peak memory	650200 kb
Host	smart-9b9bce31-5d9b-49d3-b8b7-d5c77e3f7d7c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1775024606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.1775024606
Directory	/workspace/0.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_irq.3097811911
Short name	T1239
Test name
Test status
Simulation time	4087909868 ps
CPU time	525.84 seconds
Started	Jul 24 08:00:52 PM PDT 24
Finished	Jul 24 08:09:39 PM PDT 24
Peak memory	610044 kb
Host	smart-bd013eea-51dc-4291-a4d6-0ae3e15c913d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097811911 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3097811911
Directory	/workspace/0.chip_sw_aon_timer_irq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4228121356
Short name	T999
Test name
Test status
Simulation time	8302700118 ps
CPU time	541.99 seconds
Started	Jul 24 07:57:44 PM PDT 24
Finished	Jul 24 08:06:46 PM PDT 24
Peak memory	609928 kb
Host	smart-f94ad18d-1f10-40d1-9af6-a0b76aa2760d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4228121356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4228121356
Directory	/workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1948418734
Short name	T109
Test name
Test status
Simulation time	2512773944 ps
CPU time	242.51 seconds
Started	Jul 24 07:58:36 PM PDT 24
Finished	Jul 24 08:02:38 PM PDT 24
Peak memory	609856 kb
Host	smart-b65ac167-8407-4b09-b03c-15b79cb55309
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948418734 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.1948418734
Directory	/workspace/0.chip_sw_aon_timer_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.90734902
Short name	T1250
Test name
Test status
Simulation time	8396074720 ps
CPU time	689.56 seconds
Started	Jul 24 08:01:16 PM PDT 24
Finished	Jul 24 08:12:46 PM PDT 24
Peak memory	610660 kb
Host	smart-ee7be12f-9180-4e0d-a8fc-2b76153bd83f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 90734902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.90734902
Directory	/workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1030961683
Short name	T1370
Test name
Test status
Simulation time	6289154900 ps
CPU time	832.31 seconds
Started	Jul 24 07:58:21 PM PDT 24
Finished	Jul 24 08:12:13 PM PDT 24
Peak memory	611032 kb
Host	smart-26150df8-9722-4080-91c6-849424f13dca
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1030961683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.1030961683
Directory	/workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

---

Test location	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3228191033
Short name	T1000
Test name
Test status
Simulation time	7778284740 ps
CPU time	1120.01 seconds
Started	Jul 24 07:59:26 PM PDT 24
Finished	Jul 24 08:18:06 PM PDT 24
Peak memory	617516 kb
Host	smart-97299d06-89fa-405e-8c77-3c1be9b24b0b
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228191033 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.3228191033
Directory	/workspace/0.chip_sw_ast_clk_outputs/latest

---

Test location	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.781610935
Short name	T139
Test name
Test status
Simulation time	22836292447 ps
CPU time	3830.6 seconds
Started	Jul 24 08:00:17 PM PDT 24
Finished	Jul 24 09:04:10 PM PDT 24
Peak memory	611192 kb
Host	smart-edb5010a-6a5e-40ba-81a4-7c374570e7dc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781610935 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.781610935
Directory	/workspace/0.chip_sw_ast_clk_rst_inputs/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3236896877
Short name	T173
Test name
Test status
Simulation time	12785428765 ps
CPU time	1101.31 seconds
Started	Jul 24 07:58:39 PM PDT 24
Finished	Jul 24 08:17:01 PM PDT 24
Peak memory	622964 kb
Host	smart-e7b15a71-e1b7-416c-acbc-693d66f6c7a4
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3236896877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.3236896877
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1416297322
Short name	T1294
Test name
Test status
Simulation time	4243883988 ps
CPU time	695.04 seconds
Started	Jul 24 08:07:56 PM PDT 24
Finished	Jul 24 08:19:32 PM PDT 24
Peak memory	613348 kb
Host	smart-8a89417d-4909-4fea-a2c3-fc7c58e35cbd
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416297322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1416297322
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.526667729
Short name	T121
Test name
Test status
Simulation time	4563510488 ps
CPU time	635.16 seconds
Started	Jul 24 08:00:16 PM PDT 24
Finished	Jul 24 08:10:52 PM PDT 24
Peak memory	613416 kb
Host	smart-7e57a686-d65c-446f-92d8-f307b66062c5
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526667729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.526667729
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.138888737
Short name	T1109
Test name
Test status
Simulation time	4699590680 ps
CPU time	728.47 seconds
Started	Jul 24 07:59:30 PM PDT 24
Finished	Jul 24 08:11:39 PM PDT 24
Peak memory	613484 kb
Host	smart-272b5851-12ed-4075-b4a2-84ef56005174
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138888737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.138888737
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2427740982
Short name	T1433
Test name
Test status
Simulation time	4482703960 ps
CPU time	621.88 seconds
Started	Jul 24 08:01:34 PM PDT 24
Finished	Jul 24 08:11:57 PM PDT 24
Peak memory	613172 kb
Host	smart-365cb1fa-9b5d-410b-87cf-8b54d5afc494
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427740982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2427740982
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2014533715
Short name	T1050
Test name
Test status
Simulation time	5050106538 ps
CPU time	734.18 seconds
Started	Jul 24 08:08:11 PM PDT 24
Finished	Jul 24 08:20:26 PM PDT 24
Peak memory	613116 kb
Host	smart-1659ee0a-1595-4383-a788-5d6449a03e1d
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014533715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2014533715
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1715521362
Short name	T991
Test name
Test status
Simulation time	3426973210 ps
CPU time	256.66 seconds
Started	Jul 24 07:58:53 PM PDT 24
Finished	Jul 24 08:03:10 PM PDT 24
Peak memory	610036 kb
Host	smart-ec81bf7b-9a1a-480b-be1a-947b8ee3e419
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715521362 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.1715521362
Directory	/workspace/0.chip_sw_clkmgr_jitter/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.203711977
Short name	T1048
Test name
Test status
Simulation time	4255928800 ps
CPU time	398.02 seconds
Started	Jul 24 07:58:44 PM PDT 24
Finished	Jul 24 08:05:22 PM PDT 24
Peak memory	609936 kb
Host	smart-0019f02f-5092-4fc6-8d90-3acc7d26775d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203711977 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.203711977
Directory	/workspace/0.chip_sw_clkmgr_jitter_frequency/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1237306858
Short name	T1348
Test name
Test status
Simulation time	2879990348 ps
CPU time	214.95 seconds
Started	Jul 24 07:57:06 PM PDT 24
Finished	Jul 24 08:00:41 PM PDT 24
Peak memory	609908 kb
Host	smart-b6fbd85b-1bd1-4e3b-9b62-c1874ebe9bcd
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237306858 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1237306858
Directory	/workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1715434869
Short name	T1012
Test name
Test status
Simulation time	4745941950 ps
CPU time	509.7 seconds
Started	Jul 24 08:00:55 PM PDT 24
Finished	Jul 24 08:09:25 PM PDT 24
Peak memory	609920 kb
Host	smart-47cd4dd9-3a18-4d35-9956-dbc333ca4b6d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715434869 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.1715434869
Directory	/workspace/0.chip_sw_clkmgr_off_aes_trans/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3910168899
Short name	T1424
Test name
Test status
Simulation time	4884316470 ps
CPU time	506.06 seconds
Started	Jul 24 08:00:13 PM PDT 24
Finished	Jul 24 08:08:39 PM PDT 24
Peak memory	609980 kb
Host	smart-014810b7-8217-4dca-94e7-339c08f3b664
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910168899 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.3910168899
Directory	/workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2312803682
Short name	T1353
Test name
Test status
Simulation time	5215662960 ps
CPU time	422.23 seconds
Started	Jul 24 07:59:51 PM PDT 24
Finished	Jul 24 08:06:54 PM PDT 24
Peak memory	609980 kb
Host	smart-a0ef5852-22c2-4285-830f-c4f9f807ce07
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312803682 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.2312803682
Directory	/workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.4068793791
Short name	T1044
Test name
Test status
Simulation time	4914241996 ps
CPU time	605.55 seconds
Started	Jul 24 08:00:03 PM PDT 24
Finished	Jul 24 08:10:12 PM PDT 24
Peak memory	610904 kb
Host	smart-37778762-4e64-41b7-af6f-77674c5f9abc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068793791 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.4068793791
Directory	/workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1666726953
Short name	T1439
Test name
Test status
Simulation time	12820546928 ps
CPU time	1566.36 seconds
Started	Jul 24 07:59:48 PM PDT 24
Finished	Jul 24 08:25:55 PM PDT 24
Peak memory	610664 kb
Host	smart-abcc10c1-6209-46d1-8acb-5ee707414df3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666726953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.1666726953
Directory	/workspace/0.chip_sw_clkmgr_off_peri/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.643675587
Short name	T777
Test name
Test status
Simulation time	3350615324 ps
CPU time	484.95 seconds
Started	Jul 24 07:57:43 PM PDT 24
Finished	Jul 24 08:05:49 PM PDT 24
Peak memory	610080 kb
Host	smart-82a1fac0-a385-4eb9-b94d-b0a10fa0e889
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643675587 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.643675587
Directory	/workspace/0.chip_sw_clkmgr_reset_frequency/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3013956315
Short name	T1155
Test name
Test status
Simulation time	4406744100 ps
CPU time	509.54 seconds
Started	Jul 24 08:01:23 PM PDT 24
Finished	Jul 24 08:09:53 PM PDT 24
Peak memory	610732 kb
Host	smart-9fb36102-3829-4e64-bead-2a45c6ab0ed4
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013956315 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.3013956315
Directory	/workspace/0.chip_sw_clkmgr_sleep_frequency/latest

---

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2387018495
Short name	T982
Test name
Test status
Simulation time	2642457130 ps
CPU time	182.37 seconds
Started	Jul 24 08:02:28 PM PDT 24
Finished	Jul 24 08:05:31 PM PDT 24
Peak memory	609808 kb
Host	smart-10bd2826-4e0b-4146-8557-dc3ce7487962
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387018495 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.2387018495
Directory	/workspace/0.chip_sw_clkmgr_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_coremark.2859660873
Short name	T1354
Test name
Test status
Simulation time	71681793300 ps
CPU time	13504.3 seconds
Started	Jul 24 07:58:51 PM PDT 24
Finished	Jul 24 11:43:58 PM PDT 24
Peak memory	610712 kb
Host	smart-e585c9c5-524c-4835-b50c-d0ecda8d419c
User	root
Command	/workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2859660873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.2859660873
Directory	/workspace/0.chip_sw_coremark/latest

---

Test location	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1550087254
Short name	T1078
Test name
Test status
Simulation time	16075187668 ps
CPU time	4207.39 seconds
Started	Jul 24 07:58:55 PM PDT 24
Finished	Jul 24 09:09:03 PM PDT 24
Peak memory	610800 kb
Host	smart-804997a0-249f-4735-91ca-c58c8459deaa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550087254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.1550087254
Directory	/workspace/0.chip_sw_csrng_edn_concurrency/latest

---

Test location	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2398394920
Short name	T116
Test name
Test status
Simulation time	41297016328 ps
CPU time	7558.85 seconds
Started	Jul 24 07:59:35 PM PDT 24
Finished	Jul 24 10:05:35 PM PDT 24
Peak memory	610796 kb
Host	smart-5bcb2bb8-3435-4c1a-a567-8ec21e6942c6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2398394920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.2398394920
Directory	/workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3949311725
Short name	T1258
Test name
Test status
Simulation time	4856016000 ps
CPU time	464.05 seconds
Started	Jul 24 08:01:19 PM PDT 24
Finished	Jul 24 08:09:04 PM PDT 24
Peak memory	610068 kb
Host	smart-13fa11de-2d67-4367-bb6d-3e05edf6fed7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39493 11725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.3949311725
Directory	/workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

---

Test location	/workspace/coverage/default/0.chip_sw_csrng_kat_test.3806964113
Short name	T1156
Test name
Test status
Simulation time	2560179584 ps
CPU time	231.15 seconds
Started	Jul 24 08:01:38 PM PDT 24
Finished	Jul 24 08:05:30 PM PDT 24
Peak memory	609896 kb
Host	smart-2feee8be-5d5c-401d-86a7-ba64c1807465
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806964113 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.3806964113
Directory	/workspace/0.chip_sw_csrng_kat_test/latest

---

Test location	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1797819776
Short name	T186
Test name
Test status
Simulation time	6223581596 ps
CPU time	627.19 seconds
Started	Jul 24 07:58:13 PM PDT 24
Finished	Jul 24 08:08:40 PM PDT 24
Peak memory	611232 kb
Host	smart-082b48b2-b310-4c8f-a19f-cc3a1eb8efd8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797819776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.1797819776
Directory	/workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

---

Test location	/workspace/coverage/default/0.chip_sw_csrng_smoketest.899922005
Short name	T1097
Test name
Test status
Simulation time	2521546250 ps
CPU time	173.06 seconds
Started	Jul 24 07:58:42 PM PDT 24
Finished	Jul 24 08:01:35 PM PDT 24
Peak memory	610172 kb
Host	smart-18b6b84b-f448-4c91-8da6-e0819ab634bb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899922005 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_csrng_smoketest.899922005
Directory	/workspace/0.chip_sw_csrng_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.84317090
Short name	T242
Test name
Test status
Simulation time	5567388904 ps
CPU time	639.43 seconds
Started	Jul 24 07:55:46 PM PDT 24
Finished	Jul 24 08:06:26 PM PDT 24
Peak memory	611396 kb
Host	smart-71cb6cdc-48f7-4f38-b58e-5fd34dc3173e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=84317090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.84317090
Directory	/workspace/0.chip_sw_data_integrity_escalation/latest

---

Test location	/workspace/coverage/default/0.chip_sw_edn_auto_mode.1060688007
Short name	T1119
Test name
Test status
Simulation time	4675968686 ps
CPU time	978.31 seconds
Started	Jul 24 07:57:34 PM PDT 24
Finished	Jul 24 08:13:53 PM PDT 24
Peak memory	609300 kb
Host	smart-14a4cd82-2198-4266-8e4f-42500a6c0c84
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060688007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.1060688007
Directory	/workspace/0.chip_sw_edn_auto_mode/latest

---

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.384059740
Short name	T1404
Test name
Test status
Simulation time	5957927698 ps
CPU time	1208.3 seconds
Started	Jul 24 08:06:55 PM PDT 24
Finished	Jul 24 08:27:04 PM PDT 24
Peak memory	611212 kb
Host	smart-b5ab747c-8852-4451-b1a0-ca92914c685d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=384059740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.384059740
Directory	/workspace/0.chip_sw_edn_entropy_reqs/latest

---

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2964346068
Short name	T1138
Test name
Test status
Simulation time	7023897496 ps
CPU time	909.5 seconds
Started	Jul 24 08:02:05 PM PDT 24
Finished	Jul 24 08:17:14 PM PDT 24
Peak memory	611244 kb
Host	smart-5383355e-7491-4d5a-837b-606a0f3ea00f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964346068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2964346068
Directory	/workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

---

Test location	/workspace/coverage/default/0.chip_sw_edn_kat.3342894084
Short name	T1427
Test name
Test status
Simulation time	3418142820 ps
CPU time	622.52 seconds
Started	Jul 24 07:59:35 PM PDT 24
Finished	Jul 24 08:09:58 PM PDT 24
Peak memory	615824 kb
Host	smart-ea3783bf-6aee-48b8-90f1-ff51b58e7d47
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342894084 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.3342894084
Directory	/workspace/0.chip_sw_edn_kat/latest

---

Test location	/workspace/coverage/default/0.chip_sw_edn_sw_mode.2239701304
Short name	T1179
Test name
Test status
Simulation time	9488666472 ps
CPU time	2417.37 seconds
Started	Jul 24 07:57:21 PM PDT 24
Finished	Jul 24 08:37:39 PM PDT 24
Peak memory	610436 kb
Host	smart-4e741532-7fb5-4c66-9cd8-1b3ff9c0db23
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239701304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.2239701304
Directory	/workspace/0.chip_sw_edn_sw_mode/latest

---

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.4090775276
Short name	T1272
Test name
Test status
Simulation time	2308978378 ps
CPU time	224.58 seconds
Started	Jul 24 08:05:58 PM PDT 24
Finished	Jul 24 08:09:43 PM PDT 24
Peak memory	609832 kb
Host	smart-69e9046c-0c67-40a8-81d2-2d4cd7cc562e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40 90775276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.4090775276
Directory	/workspace/0.chip_sw_entropy_src_ast_rng_req/latest

---

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2390479070
Short name	T95
Test name
Test status
Simulation time	7660252750 ps
CPU time	1977.73 seconds
Started	Jul 24 07:56:39 PM PDT 24
Finished	Jul 24 08:29:37 PM PDT 24
Peak memory	609960 kb
Host	smart-748ed888-286e-4b97-97dc-85711367006d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2390479070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2390479070
Directory	/workspace/0.chip_sw_entropy_src_csrng/latest

---

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.671099028
Short name	T1150
Test name
Test status
Simulation time	2988881106 ps
CPU time	266.4 seconds
Started	Jul 24 08:02:10 PM PDT 24
Finished	Jul 24 08:06:37 PM PDT 24
Peak memory	609876 kb
Host	smart-81f3a9c4-84c9-4343-8ccf-7b784638787c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671099028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.671099028
Directory	/workspace/0.chip_sw_entropy_src_kat_test/latest

---

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3737325577
Short name	T1395
Test name
Test status
Simulation time	3439543020 ps
CPU time	446.54 seconds
Started	Jul 24 08:02:15 PM PDT 24
Finished	Jul 24 08:09:42 PM PDT 24
Peak memory	609988 kb
Host	smart-c52833ad-c1a0-4bd8-b7ca-38672fe7e083
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3737325577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3737325577
Directory	/workspace/0.chip_sw_entropy_src_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_example_concurrency.1722050373
Short name	T1140
Test name
Test status
Simulation time	2934974792 ps
CPU time	225.13 seconds
Started	Jul 24 07:57:19 PM PDT 24
Finished	Jul 24 08:01:04 PM PDT 24
Peak memory	609904 kb
Host	smart-6d70f99a-a1c7-4699-adfd-d8fd8f004333
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722050373 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.1722050373
Directory	/workspace/0.chip_sw_example_concurrency/latest

---

Test location	/workspace/coverage/default/0.chip_sw_example_flash.254765162
Short name	T1037
Test name
Test status
Simulation time	2968614604 ps
CPU time	187.2 seconds
Started	Jul 24 07:55:00 PM PDT 24
Finished	Jul 24 07:58:08 PM PDT 24
Peak memory	609800 kb
Host	smart-a2679b83-0211-4da1-9758-ae24bc7c3f92
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254765162 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.254765162
Directory	/workspace/0.chip_sw_example_flash/latest

---

Test location	/workspace/coverage/default/0.chip_sw_example_manufacturer.1204155146
Short name	T268
Test name
Test status
Simulation time	2734961656 ps
CPU time	203.05 seconds
Started	Jul 24 07:56:34 PM PDT 24
Finished	Jul 24 07:59:58 PM PDT 24
Peak memory	610080 kb
Host	smart-29994b1f-9707-49ab-af6c-3f5ea8e85edd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204155146 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.1204155146
Directory	/workspace/0.chip_sw_example_manufacturer/latest

---

Test location	/workspace/coverage/default/0.chip_sw_example_rom.2238073260
Short name	T282
Test name
Test status
Simulation time	3101914472 ps
CPU time	134.77 seconds
Started	Jul 24 07:55:26 PM PDT 24
Finished	Jul 24 07:57:42 PM PDT 24
Peak memory	609792 kb
Host	smart-5c9ba984-df30-4fb0-b183-8b30be503ab1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238073260 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.2238073260
Directory	/workspace/0.chip_sw_example_rom/latest

---

Test location	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1143284401
Short name	T69
Test name
Test status
Simulation time	58427588958 ps
CPU time	10308.5 seconds
Started	Jul 24 07:57:00 PM PDT 24
Finished	Jul 24 10:48:50 PM PDT 24
Peak memory	625328 kb
Host	smart-dde58ccc-0e95-4bff-b2aa-2bb7322a0413
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1143284401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.1143284401
Directory	/workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_crash_alert.1008699341
Short name	T219
Test name
Test status
Simulation time	4508380100 ps
CPU time	781.26 seconds
Started	Jul 24 07:59:17 PM PDT 24
Finished	Jul 24 08:12:19 PM PDT 24
Peak memory	611388 kb
Host	smart-471c0002-d879-4ea6-8c08-98ecb2b9a3e1
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1008699341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.1008699341
Directory	/workspace/0.chip_sw_flash_crash_alert/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2662559788
Short name	T976
Test name
Test status
Simulation time	5696974674 ps
CPU time	990.4 seconds
Started	Jul 24 07:58:27 PM PDT 24
Finished	Jul 24 08:14:59 PM PDT 24
Peak memory	609952 kb
Host	smart-a1c577ef-77c8-4cb9-a374-dd49aa509fa5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662559788 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.2662559788
Directory	/workspace/0.chip_sw_flash_ctrl_access/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.259562447
Short name	T1414
Test name
Test status
Simulation time	6344940153 ps
CPU time	1315.14 seconds
Started	Jul 24 07:57:56 PM PDT 24
Finished	Jul 24 08:19:52 PM PDT 24
Peak memory	610476 kb
Host	smart-7f96ae29-f01c-45c1-bbf6-2d2210ca730d
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259562447 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.259562447
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1323599884
Short name	T1280
Test name
Test status
Simulation time	7177164887 ps
CPU time	1200.85 seconds
Started	Jul 24 08:00:38 PM PDT 24
Finished	Jul 24 08:20:39 PM PDT 24
Peak memory	609836 kb
Host	smart-06afdffa-05a0-4cef-8ab3-0e0ad754cc7d
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323599884 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1323599884
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2824457529
Short name	T1087
Test name
Test status
Simulation time	6303613980 ps
CPU time	1007.06 seconds
Started	Jul 24 07:59:02 PM PDT 24
Finished	Jul 24 08:15:49 PM PDT 24
Peak memory	609856 kb
Host	smart-38dcdfe6-19cd-4c04-9aa0-15490fc5131a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824457529 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.2824457529
Directory	/workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.110035780
Short name	T1336
Test name
Test status
Simulation time	3498038570 ps
CPU time	443.07 seconds
Started	Jul 24 07:57:09 PM PDT 24
Finished	Jul 24 08:04:33 PM PDT 24
Peak memory	610420 kb
Host	smart-892e857b-1a86-4864-90b2-2163ee74843a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110035780 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.110035780
Directory	/workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3349632179
Short name	T230
Test name
Test status
Simulation time	5093477815 ps
CPU time	456.01 seconds
Started	Jul 24 08:01:11 PM PDT 24
Finished	Jul 24 08:08:48 PM PDT 24
Peak memory	611040 kb
Host	smart-260e83e3-4dde-4877-a30f-f5f5e635a60e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33 49632179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.3349632179
Directory	/workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3546437534
Short name	T1331
Test name
Test status
Simulation time	4880843064 ps
CPU time	1144.69 seconds
Started	Jul 24 07:59:22 PM PDT 24
Finished	Jul 24 08:18:28 PM PDT 24
Peak memory	610504 kb
Host	smart-5f4cd9da-5ec7-42f7-8877-be67384f83d5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546437534 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.3546437534
Directory	/workspace/0.chip_sw_flash_ctrl_mem_protection/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1575531468
Short name	T353
Test name
Test status
Simulation time	4903143000 ps
CPU time	656.56 seconds
Started	Jul 24 07:57:07 PM PDT 24
Finished	Jul 24 08:08:04 PM PDT 24
Peak memory	610476 kb
Host	smart-27900b6e-0403-4c25-b855-e4e595d495fd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1575531468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.1575531468
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1218002959
Short name	T1022
Test name
Test status
Simulation time	2861041528 ps
CPU time	345.01 seconds
Started	Jul 24 08:08:33 PM PDT 24
Finished	Jul 24 08:14:19 PM PDT 24
Peak memory	609856 kb
Host	smart-fe506067-5b9a-4704-b276-21a227458517
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218002 959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.1218002959
Directory	/workspace/0.chip_sw_flash_ctrl_write_clear/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_init.3863957158
Short name	T234
Test name
Test status
Simulation time	17062283000 ps
CPU time	2464.66 seconds
Started	Jul 24 07:58:29 PM PDT 24
Finished	Jul 24 08:39:34 PM PDT 24
Peak memory	612840 kb
Host	smart-d4ba9a45-56d7-4c2b-a6de-6371706a76ba
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863957158 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.3863957158
Directory	/workspace/0.chip_sw_flash_init/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3718012515
Short name	T233
Test name
Test status
Simulation time	19565275331 ps
CPU time	2080.26 seconds
Started	Jul 24 07:58:55 PM PDT 24
Finished	Jul 24 08:33:36 PM PDT 24
Peak memory	613864 kb
Host	smart-5a7bdc64-6ca5-4662-8f7a-44fc03158c04
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3718012515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.3718012515
Directory	/workspace/0.chip_sw_flash_init_reduced_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1751964125
Short name	T1422
Test name
Test status
Simulation time	3093069824 ps
CPU time	181.17 seconds
Started	Jul 24 08:04:39 PM PDT 24
Finished	Jul 24 08:07:41 PM PDT 24
Peak memory	610408 kb
Host	smart-fa2c406d-e238-473a-b7bd-dd65384a918a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1751964125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.1751964125
Directory	/workspace/0.chip_sw_flash_scrambling_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2006038134
Short name	T16
Test name
Test status
Simulation time	3161748952 ps
CPU time	248.16 seconds
Started	Jul 24 08:00:27 PM PDT 24
Finished	Jul 24 08:04:36 PM PDT 24
Peak memory	610648 kb
Host	smart-6224d1ab-c08a-486b-bbef-f0e55ca3744b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006038134 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2006038134
Directory	/workspace/0.chip_sw_gpio_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc.149802469
Short name	T1357
Test name
Test status
Simulation time	2715352400 ps
CPU time	248.13 seconds
Started	Jul 24 08:02:08 PM PDT 24
Finished	Jul 24 08:06:17 PM PDT 24
Peak memory	609800 kb
Host	smart-5635cd9e-0b0d-4d6b-93ff-73ad1aa84f9d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149802469 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.149802469
Directory	/workspace/0.chip_sw_hmac_enc/latest

---

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.761704829
Short name	T3
Test name
Test status
Simulation time	3642071540 ps
CPU time	297.69 seconds
Started	Jul 24 07:56:33 PM PDT 24
Finished	Jul 24 08:01:31 PM PDT 24
Peak memory	609832 kb
Host	smart-80a82b02-020d-4fb1-847a-ea24c68c8249
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761704829 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_hmac_enc_idle.761704829
Directory	/workspace/0.chip_sw_hmac_enc_idle/latest

---

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.125253357
Short name	T1026
Test name
Test status
Simulation time	2341557973 ps
CPU time	271.24 seconds
Started	Jul 24 08:07:32 PM PDT 24
Finished	Jul 24 08:12:05 PM PDT 24
Peak memory	609776 kb
Host	smart-98b14625-3e4a-4ec5-8232-904324a2c66e
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125253357 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.125253357
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en/latest

---

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.491922372
Short name	T423
Test name
Test status
Simulation time	2960959483 ps
CPU time	295.18 seconds
Started	Jul 24 08:00:56 PM PDT 24
Finished	Jul 24 08:05:51 PM PDT 24
Peak memory	610352 kb
Host	smart-38d29778-79b1-474f-973c-dee736e76156
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491922372 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.491922372
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_hmac_multistream.3448411337
Short name	T1045
Test name
Test status
Simulation time	8022496810 ps
CPU time	1941.43 seconds
Started	Jul 24 07:59:14 PM PDT 24
Finished	Jul 24 08:31:36 PM PDT 24
Peak memory	610364 kb
Host	smart-33c764df-f6cd-4be5-953a-afba2ea4a2ef
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448411337 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.3448411337
Directory	/workspace/0.chip_sw_hmac_multistream/latest

---

Test location	/workspace/coverage/default/0.chip_sw_hmac_oneshot.3157005700
Short name	T1089
Test name
Test status
Simulation time	3087971860 ps
CPU time	334.63 seconds
Started	Jul 24 07:59:11 PM PDT 24
Finished	Jul 24 08:04:46 PM PDT 24
Peak memory	609900 kb
Host	smart-5099019e-c1d1-410b-86c2-186a88ccbd7d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157005700 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.3157005700
Directory	/workspace/0.chip_sw_hmac_oneshot/latest

---

Test location	/workspace/coverage/default/0.chip_sw_hmac_smoketest.2227143959
Short name	T1237
Test name
Test status
Simulation time	3692030000 ps
CPU time	307.05 seconds
Started	Jul 24 08:02:28 PM PDT 24
Finished	Jul 24 08:07:35 PM PDT 24
Peak memory	609812 kb
Host	smart-bb5fc143-1dd4-4c31-8b34-95e653d01e6d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227143959 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.2227143959
Directory	/workspace/0.chip_sw_hmac_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1975178721
Short name	T345
Test name
Test status
Simulation time	3611490996 ps
CPU time	563.46 seconds
Started	Jul 24 07:57:13 PM PDT 24
Finished	Jul 24 08:06:37 PM PDT 24
Peak memory	610324 kb
Host	smart-341534d0-1298-49ce-bd41-719693c7a271
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975178721 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1975178721
Directory	/workspace/0.chip_sw_i2c_device_tx_rx/latest

---

Test location	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3515596910
Short name	T1441
Test name
Test status
Simulation time	65961251010 ps
CPU time	12309 seconds
Started	Jul 24 07:57:42 PM PDT 24
Finished	Jul 24 11:22:54 PM PDT 24
Peak memory	625292 kb
Host	smart-8fde6506-319c-489e-956b-d6d2b8480d20
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3515596910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3515596910
Directory	/workspace/0.chip_sw_inject_scramble_seed/latest

---

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.152097851
Short name	T1282
Test name
Test status
Simulation time	8243993548 ps
CPU time	1668.62 seconds
Started	Jul 24 07:58:15 PM PDT 24
Finished	Jul 24 08:26:04 PM PDT 24
Peak memory	618220 kb
Host	smart-776afb80-7231-41d5-aaf7-7cd3cfe86c79
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520 97851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.152097851
Directory	/workspace/0.chip_sw_keymgr_key_derivation/latest

---

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3458160367
Short name	T1315
Test name
Test status
Simulation time	7605642212 ps
CPU time	1780.69 seconds
Started	Jul 24 07:58:06 PM PDT 24
Finished	Jul 24 08:27:47 PM PDT 24
Peak memory	618004 kb
Host	smart-f38048ab-5bc4-406d-b261-924b46f93ae7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3458160367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.3458160367
Directory	/workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

---

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1852595521
Short name	T1112
Test name
Test status
Simulation time	10844650033 ps
CPU time	2063.05 seconds
Started	Jul 24 07:58:11 PM PDT 24
Finished	Jul 24 08:32:35 PM PDT 24
Peak memory	616900 kb
Host	smart-87f03207-61af-4d2f-ba90-51bdd70e16e2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1852595521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1852595521
Directory	/workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.339733298
Short name	T222
Test name
Test status
Simulation time	7897267850 ps
CPU time	1475.43 seconds
Started	Jul 24 07:59:08 PM PDT 24
Finished	Jul 24 08:23:44 PM PDT 24
Peak memory	618312 kb
Host	smart-9130d2c4-3f0c-46d2-a0ba-0800591d02fe
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=339733298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.339733298
Directory	/workspace/0.chip_sw_keymgr_key_derivation_prod/latest

---

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2906691820
Short name	T1437
Test name
Test status
Simulation time	6249162554 ps
CPU time	1536.8 seconds
Started	Jul 24 07:59:39 PM PDT 24
Finished	Jul 24 08:25:16 PM PDT 24
Peak memory	611380 kb
Host	smart-88707541-7a71-4982-a515-a72daa1dbf7f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29066 91820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.2906691820
Directory	/workspace/0.chip_sw_keymgr_sideload_kmac/latest

---

Test location	/workspace/coverage/default/0.chip_sw_kmac_app_rom.4292146426
Short name	T1337
Test name
Test status
Simulation time	3052975420 ps
CPU time	275.99 seconds
Started	Jul 24 07:56:12 PM PDT 24
Finished	Jul 24 08:00:48 PM PDT 24
Peak memory	609780 kb
Host	smart-302c5b55-5d2a-4c58-9d45-6c306b872fec
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292146426 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.4292146426
Directory	/workspace/0.chip_sw_kmac_app_rom/latest

---

Test location	/workspace/coverage/default/0.chip_sw_kmac_entropy.2034698917
Short name	T1204
Test name
Test status
Simulation time	2905658528 ps
CPU time	222.17 seconds
Started	Jul 24 07:57:42 PM PDT 24
Finished	Jul 24 08:01:25 PM PDT 24
Peak memory	609716 kb
Host	smart-afa3124c-452c-4d9f-9969-e04d28894f36
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034698917 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.2034698917
Directory	/workspace/0.chip_sw_kmac_entropy/latest

---

Test location	/workspace/coverage/default/0.chip_sw_kmac_idle.1687078444
Short name	T1064
Test name
Test status
Simulation time	2484990076 ps
CPU time	251.02 seconds
Started	Jul 24 07:59:00 PM PDT 24
Finished	Jul 24 08:03:12 PM PDT 24
Peak memory	609860 kb
Host	smart-1e07a1c8-9121-444e-b944-508e6c86332d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687078444 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.1687078444
Directory	/workspace/0.chip_sw_kmac_idle/latest

---

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2861792655
Short name	T1243
Test name
Test status
Simulation time	2501372472 ps
CPU time	294.52 seconds
Started	Jul 24 07:58:31 PM PDT 24
Finished	Jul 24 08:03:26 PM PDT 24
Peak memory	609796 kb
Host	smart-4c719bc5-a329-4c34-ae41-9baa89ebb2c6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861792655 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.2861792655
Directory	/workspace/0.chip_sw_kmac_mode_cshake/latest

---

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1346629511
Short name	T1157
Test name
Test status
Simulation time	3262794696 ps
CPU time	332.9 seconds
Started	Jul 24 07:59:24 PM PDT 24
Finished	Jul 24 08:04:58 PM PDT 24
Peak memory	609904 kb
Host	smart-dbbdcd77-8d97-4ac4-ba5b-cd07289e071e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346629511 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.1346629511
Directory	/workspace/0.chip_sw_kmac_mode_kmac/latest

---

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.845900041
Short name	T1168
Test name
Test status
Simulation time	3922104990 ps
CPU time	337.35 seconds
Started	Jul 24 07:59:52 PM PDT 24
Finished	Jul 24 08:05:29 PM PDT 24
Peak memory	609864 kb
Host	smart-e04fc44d-1db1-4276-a781-675fe9addc62
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845900041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.845900041
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

---

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3364483346
Short name	T1205
Test name
Test status
Simulation time	3607523113 ps
CPU time	280.75 seconds
Started	Jul 24 08:01:13 PM PDT 24
Finished	Jul 24 08:05:54 PM PDT 24
Peak memory	610240 kb
Host	smart-9a13b2f1-3966-453a-9c66-768fc6a17249
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33644833 46 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3364483346
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_kmac_smoketest.1695765023
Short name	T1255
Test name
Test status
Simulation time	3275047412 ps
CPU time	372.34 seconds
Started	Jul 24 08:00:57 PM PDT 24
Finished	Jul 24 08:07:09 PM PDT 24
Peak memory	610136 kb
Host	smart-eb5781a4-14b9-4970-9d48-43f0ac1cda7f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695765023 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.1695765023
Directory	/workspace/0.chip_sw_kmac_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1283026899
Short name	T439
Test name
Test status
Simulation time	3556638620 ps
CPU time	274.58 seconds
Started	Jul 24 07:56:20 PM PDT 24
Finished	Jul 24 08:00:55 PM PDT 24
Peak memory	609968 kb
Host	smart-5d62684d-bbb9-408f-a39d-fde2e88b18cf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283026899 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.1283026899
Directory	/workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2313103636
Short name	T176
Test name
Test status
Simulation time	3195066704 ps
CPU time	153.85 seconds
Started	Jul 24 07:57:02 PM PDT 24
Finished	Jul 24 07:59:36 PM PDT 24
Peak memory	620456 kb
Host	smart-7db3ef1f-a75a-4333-8d90-ba72861996c3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313103636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.2313103636
Directory	/workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3353750568
Short name	T175
Test name
Test status
Simulation time	3297838866 ps
CPU time	279.68 seconds
Started	Jul 24 07:57:48 PM PDT 24
Finished	Jul 24 08:02:29 PM PDT 24
Peak memory	622116 kb
Host	smart-15c0ae8f-c19b-4930-824e-5fc5319b7afe
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353750568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3353750568
Directory	/workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.448846244
Short name	T433
Test name
Test status
Simulation time	3752588186 ps
CPU time	129.26 seconds
Started	Jul 24 07:59:17 PM PDT 24
Finished	Jul 24 08:01:27 PM PDT 24
Peak memory	619960 kb
Host	smart-c9c99b0a-b356-41bb-9f82-a5cd24bb87e1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=448846244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.448846244
Directory	/workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3493430324
Short name	T1003
Test name
Test status
Simulation time	12312396541 ps
CPU time	1201.79 seconds
Started	Jul 24 08:01:06 PM PDT 24
Finished	Jul 24 08:21:09 PM PDT 24
Peak memory	620992 kb
Host	smart-82d527ae-fbda-4660-a589-c0d8dc729a53
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493430324 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.3493430324
Directory	/workspace/0.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.763451732
Short name	T1211
Test name
Test status
Simulation time	2292269931 ps
CPU time	113.74 seconds
Started	Jul 24 07:57:31 PM PDT 24
Finished	Jul 24 07:59:25 PM PDT 24
Peak memory	616980 kb
Host	smart-5a21b198-5da8-4678-b2d8-7afbd1777572
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=763451732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.763451732
Directory	/workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2432810493
Short name	T120
Test name
Test status
Simulation time	1999906836 ps
CPU time	103.4 seconds
Started	Jul 24 07:57:56 PM PDT 24
Finished	Jul 24 07:59:40 PM PDT 24
Peak memory	617752 kb
Host	smart-3efc98c0-f328-4839-823f-885f2e2a79fd
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432810493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2432810493
Directory	/workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2396501686
Short name	T988
Test name
Test status
Simulation time	10366814804 ps
CPU time	1009.33 seconds
Started	Jul 24 08:01:08 PM PDT 24
Finished	Jul 24 08:18:00 PM PDT 24
Peak memory	619616 kb
Host	smart-9de47a81-1136-45ac-a38c-eaa8c7588a07
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396501686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.2396501686
Directory	/workspace/0.chip_sw_lc_walkthrough_prodend/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3530244683
Short name	T1242
Test name
Test status
Simulation time	48998024850 ps
CPU time	5791.76 seconds
Started	Jul 24 07:57:04 PM PDT 24
Finished	Jul 24 09:33:38 PM PDT 24
Peak memory	620924 kb
Host	smart-dd0fba7b-7995-4075-8fae-7a8de2af388b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530244683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.3530244683
Directory	/workspace/0.chip_sw_lc_walkthrough_rma/latest

---

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2104719342
Short name	T1411
Test name
Test status
Simulation time	24681330296 ps
CPU time	2353.49 seconds
Started	Jul 24 07:57:41 PM PDT 24
Finished	Jul 24 08:36:55 PM PDT 24
Peak memory	620456 kb
Host	smart-e2995ade-d8d8-4143-b767-8bc976ba05c1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2104719342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.2104719342
Directory	/workspace/0.chip_sw_lc_walkthrough_testunlocks/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3786444429
Short name	T1135
Test name
Test status
Simulation time	17132791968 ps
CPU time	3630.51 seconds
Started	Jul 24 07:57:44 PM PDT 24
Finished	Jul 24 08:58:15 PM PDT 24
Peak memory	610728 kb
Host	smart-e4411542-d739-453c-93f1-484c57c1cfdf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3786444429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.3786444429
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1699352437
Short name	T455
Test name
Test status
Simulation time	19207866128 ps
CPU time	3841.37 seconds
Started	Jul 24 07:57:59 PM PDT 24
Finished	Jul 24 09:02:02 PM PDT 24
Peak memory	610732 kb
Host	smart-ea3688ad-4f52-47b7-a5d3-3000d585b6e0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1699352437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1699352437
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2247359412
Short name	T291
Test name
Test status
Simulation time	3350093300 ps
CPU time	519.39 seconds
Started	Jul 24 07:56:43 PM PDT 24
Finished	Jul 24 08:05:23 PM PDT 24
Peak memory	609784 kb
Host	smart-f8af73b7-94c3-46db-8ab2-742f10a82e9f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247359412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2247359412
Directory	/workspace/0.chip_sw_otbn_mem_scramble/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otbn_randomness.190350049
Short name	T329
Test name
Test status
Simulation time	6040443760 ps
CPU time	942.11 seconds
Started	Jul 24 07:59:36 PM PDT 24
Finished	Jul 24 08:15:18 PM PDT 24
Peak memory	609948 kb
Host	smart-541f1e1e-5a94-4997-8312-2a2e8033995c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=190350049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.190350049
Directory	/workspace/0.chip_sw_otbn_randomness/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otbn_smoketest.3873111609
Short name	T1405
Test name
Test status
Simulation time	6795680350 ps
CPU time	1444.73 seconds
Started	Jul 24 08:00:41 PM PDT 24
Finished	Jul 24 08:24:46 PM PDT 24
Peak memory	609916 kb
Host	smart-8f1f72b1-47c6-4f24-94d0-d024f3d84596
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873111609 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.3873111609
Directory	/workspace/0.chip_sw_otbn_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1930276882
Short name	T1299
Test name
Test status
Simulation time	27857714960 ps
CPU time	5324.33 seconds
Started	Jul 24 07:59:47 PM PDT 24
Finished	Jul 24 09:28:33 PM PDT 24
Peak memory	611012 kb
Host	smart-948aafdd-a06d-43fe-91f9-e3455d101b6b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193027 6882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.1930276882
Directory	/workspace/0.chip_sw_otp_ctrl_dai_lock/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1270289965
Short name	T1333
Test name
Test status
Simulation time	2952305809 ps
CPU time	257.44 seconds
Started	Jul 24 07:59:32 PM PDT 24
Finished	Jul 24 08:03:51 PM PDT 24
Peak memory	609944 kb
Host	smart-581f5b3d-65c7-437e-a508-6c4f157a9447
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270289965 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.1270289965
Directory	/workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4068714553
Short name	T437
Test name
Test status
Simulation time	7716326624 ps
CPU time	1354.31 seconds
Started	Jul 24 07:59:23 PM PDT 24
Finished	Jul 24 08:21:58 PM PDT 24
Peak memory	611028 kb
Host	smart-d7e1c67b-c915-4207-8265-9f6fb91a3e98
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4068714553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.4068714553
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.903515993
Short name	T1092
Test name
Test status
Simulation time	7712567070 ps
CPU time	1431.64 seconds
Started	Jul 24 07:58:45 PM PDT 24
Finished	Jul 24 08:22:37 PM PDT 24
Peak memory	611212 kb
Host	smart-dc7d1886-8542-4ab3-abb3-7dfe9fe2b623
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=903515993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.903515993
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1054531356
Short name	T1066
Test name
Test status
Simulation time	9260020904 ps
CPU time	1340.07 seconds
Started	Jul 24 07:58:28 PM PDT 24
Finished	Jul 24 08:20:49 PM PDT 24
Peak memory	610840 kb
Host	smart-fc623d2f-0e6b-4825-a76e-b49559c977fd
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1054531356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.1054531356
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3602026522
Short name	T1225
Test name
Test status
Simulation time	4618264996 ps
CPU time	767.92 seconds
Started	Jul 24 07:58:24 PM PDT 24
Finished	Jul 24 08:11:13 PM PDT 24
Peak memory	609836 kb
Host	smart-5f55ed33-1a94-426b-95b8-913c3ee55518
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3602026522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3602026522
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.513603478
Short name	T1435
Test name
Test status
Simulation time	2925162120 ps
CPU time	282.13 seconds
Started	Jul 24 08:02:33 PM PDT 24
Finished	Jul 24 08:07:15 PM PDT 24
Peak memory	609808 kb
Host	smart-ab33e340-b70a-480a-be1f-4f6573015f31
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513603478 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_otp_ctrl_smoketest.513603478
Directory	/workspace/0.chip_sw_otp_ctrl_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pattgen_ios.3730389195
Short name	T800
Test name
Test status
Simulation time	2702991908 ps
CPU time	266.33 seconds
Started	Jul 24 07:56:58 PM PDT 24
Finished	Jul 24 08:01:25 PM PDT 24
Peak memory	613508 kb
Host	smart-ca3d598f-c58b-48d6-924f-a3d21763fdcc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730389195 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3730389195
Directory	/workspace/0.chip_sw_pattgen_ios/latest

---

Test location	/workspace/coverage/default/0.chip_sw_power_idle_load.3609652066
Short name	T1162
Test name
Test status
Simulation time	4782792908 ps
CPU time	637.6 seconds
Started	Jul 24 07:57:51 PM PDT 24
Finished	Jul 24 08:08:28 PM PDT 24
Peak memory	609824 kb
Host	smart-9f23a3df-2a21-4b85-8a2c-760071f503a7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609652066 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.3609652066
Directory	/workspace/0.chip_sw_power_idle_load/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3670314825
Short name	T1383
Test name
Test status
Simulation time	12554840130 ps
CPU time	1989.37 seconds
Started	Jul 24 08:00:43 PM PDT 24
Finished	Jul 24 08:33:53 PM PDT 24
Peak memory	611812 kb
Host	smart-4e2304d2-c439-41d4-ac34-69b87420fd33
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670 314825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.3670314825
Directory	/workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2905156230
Short name	T427
Test name
Test status
Simulation time	31022335250 ps
CPU time	3038.29 seconds
Started	Jul 24 07:59:19 PM PDT 24
Finished	Jul 24 08:49:59 PM PDT 24
Peak memory	611264 kb
Host	smart-99e217eb-85e1-4301-8fb5-21ce9ef92eec
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290 5156230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.2905156230
Directory	/workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2410543425
Short name	T1342
Test name
Test status
Simulation time	12980759008 ps
CPU time	1376.72 seconds
Started	Jul 24 07:56:51 PM PDT 24
Finished	Jul 24 08:19:49 PM PDT 24
Peak memory	611908 kb
Host	smart-76494f8c-3e08-44bf-b40c-d13251c08809
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2410543425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2410543425
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.623604792
Short name	T431
Test name
Test status
Simulation time	26824214354 ps
CPU time	1992.36 seconds
Started	Jul 24 08:01:22 PM PDT 24
Finished	Jul 24 08:34:35 PM PDT 24
Peak memory	611420 kb
Host	smart-11b961ca-e069-47d5-8540-1d39fe88df3d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 623604792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.623604792
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1105649910
Short name	T1197
Test name
Test status
Simulation time	5167312900 ps
CPU time	416.5 seconds
Started	Jul 24 07:56:49 PM PDT 24
Finished	Jul 24 08:03:46 PM PDT 24
Peak memory	618016 kb
Host	smart-9370c1c1-3b3d-45d0-923e-2e144cfe527a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1105649910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.1105649910
Directory	/workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3364288581
Short name	T324
Test name
Test status
Simulation time	11371615043 ps
CPU time	1504.93 seconds
Started	Jul 24 07:56:13 PM PDT 24
Finished	Jul 24 08:21:19 PM PDT 24
Peak memory	611828 kb
Host	smart-d894dc61-84aa-408b-b2b8-a99dc10974a4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364288581 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3364288581
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.513314224
Short name	T104
Test name
Test status
Simulation time	7735789658 ps
CPU time	470.12 seconds
Started	Jul 24 07:59:46 PM PDT 24
Finished	Jul 24 08:07:36 PM PDT 24
Peak memory	611048 kb
Host	smart-a6d14cf5-f704-4a5c-9234-2e5380683b21
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513314224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.513314224
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1916997919
Short name	T1049
Test name
Test status
Simulation time	7440465328 ps
CPU time	864.9 seconds
Started	Jul 24 07:58:54 PM PDT 24
Finished	Jul 24 08:13:20 PM PDT 24
Peak memory	610964 kb
Host	smart-19ee7c0d-ba1a-45f6-8f38-743e2ecddebf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916997919 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.1916997919
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3695062838
Short name	T1316
Test name
Test status
Simulation time	21400833419 ps
CPU time	1753.26 seconds
Started	Jul 24 07:57:17 PM PDT 24
Finished	Jul 24 08:26:31 PM PDT 24
Peak memory	611896 kb
Host	smart-5b2f086a-110d-4eb6-ac50-4594b8f5ce50
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3695062838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3695062838
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4201900803
Short name	T302
Test name
Test status
Simulation time	39933922052 ps
CPU time	3203.76 seconds
Started	Jul 24 07:57:20 PM PDT 24
Finished	Jul 24 08:50:45 PM PDT 24
Peak memory	612112 kb
Host	smart-a2cd806d-0869-453a-99b0-53491e1d5ea5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201900803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.4201900803
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2917358040
Short name	T280
Test name
Test status
Simulation time	2814158752 ps
CPU time	337.66 seconds
Started	Jul 24 08:02:06 PM PDT 24
Finished	Jul 24 08:07:44 PM PDT 24
Peak memory	609912 kb
Host	smart-42b070ee-2d39-464b-8770-a6fcbb8c08ac
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917358040 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.2917358040
Directory	/workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2626980988
Short name	T60
Test name
Test status
Simulation time	6262440174 ps
CPU time	581.64 seconds
Started	Jul 24 07:57:43 PM PDT 24
Finished	Jul 24 08:07:25 PM PDT 24
Peak memory	618152 kb
Host	smart-038bf286-e777-46c5-9adb-b1fab6bc514b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2626980988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.2626980988
Directory	/workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4281006769
Short name	T1115
Test name
Test status
Simulation time	5557193584 ps
CPU time	681.28 seconds
Started	Jul 24 08:02:26 PM PDT 24
Finished	Jul 24 08:13:48 PM PDT 24
Peak memory	611240 kb
Host	smart-2483e93c-524f-424f-82d0-f0c73f520e68
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4281006769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.4281006769
Directory	/workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.4107196301
Short name	T1284
Test name
Test status
Simulation time	5792495000 ps
CPU time	448.65 seconds
Started	Jul 24 08:01:25 PM PDT 24
Finished	Jul 24 08:08:55 PM PDT 24
Peak memory	610644 kb
Host	smart-a0527c07-0aca-4250-9bb5-7d61339022fb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107196301 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.4107196301
Directory	/workspace/0.chip_sw_pwrmgr_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1041379761
Short name	T1082
Test name
Test status
Simulation time	8273295980 ps
CPU time	1237.61 seconds
Started	Jul 24 07:57:48 PM PDT 24
Finished	Jul 24 08:18:26 PM PDT 24
Peak memory	610096 kb
Host	smart-73fca8a5-1705-4e99-9c6a-9c42a63317cf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041379761 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.1041379761
Directory	/workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1962800299
Short name	T1376
Test name
Test status
Simulation time	5313469884 ps
CPU time	397.53 seconds
Started	Jul 24 08:01:56 PM PDT 24
Finished	Jul 24 08:08:34 PM PDT 24
Peak memory	610880 kb
Host	smart-ecb9e4b3-80de-47d3-b07d-5a0946c223ed
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962800299 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1962800299
Directory	/workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3280327025
Short name	T19
Test name
Test status
Simulation time	6273575940 ps
CPU time	475.26 seconds
Started	Jul 24 08:01:30 PM PDT 24
Finished	Jul 24 08:09:26 PM PDT 24
Peak memory	610116 kb
Host	smart-120830b5-f0b0-465d-9822-f90a3ce30768
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280327025 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.3280327025
Directory	/workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.870295749
Short name	T1289
Test name
Test status
Simulation time	5949376004 ps
CPU time	615.77 seconds
Started	Jul 24 08:02:10 PM PDT 24
Finished	Jul 24 08:12:27 PM PDT 24
Peak memory	610880 kb
Host	smart-cd1c6dea-7439-45a8-a6aa-8c98fad73132
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870 295749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.870295749
Directory	/workspace/0.chip_sw_pwrmgr_wdog_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1003169956
Short name	T278
Test name
Test status
Simulation time	8442643830 ps
CPU time	673.71 seconds
Started	Jul 24 07:59:59 PM PDT 24
Finished	Jul 24 08:11:13 PM PDT 24
Peak memory	624320 kb
Host	smart-f357d2ed-c317-4fec-9e0a-6fad3c3d35d1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003169956 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.1003169956
Directory	/workspace/0.chip_sw_rom_ctrl_integrity_check/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.333081540
Short name	T267
Test name
Test status
Simulation time	6535751776 ps
CPU time	671.5 seconds
Started	Jul 24 07:59:54 PM PDT 24
Finished	Jul 24 08:11:06 PM PDT 24
Peak memory	610592 kb
Host	smart-763a55cf-42c0-46f2-a40b-24a95f5205dc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333081540 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_rstmgr_cpu_info.333081540
Directory	/workspace/0.chip_sw_rstmgr_cpu_info/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2687498640
Short name	T1276
Test name
Test status
Simulation time	5338607928 ps
CPU time	693.32 seconds
Started	Jul 24 07:58:11 PM PDT 24
Finished	Jul 24 08:09:46 PM PDT 24
Peak memory	642008 kb
Host	smart-26eac2ad-c4f7-4f21-b0eb-0a0189cd4f3e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2687498640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.2687498640
Directory	/workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.124561256
Short name	T1060
Test name
Test status
Simulation time	2727319238 ps
CPU time	291.98 seconds
Started	Jul 24 08:01:42 PM PDT 24
Finished	Jul 24 08:06:34 PM PDT 24
Peak memory	609832 kb
Host	smart-01a691e0-a763-4759-a97d-55331944d664
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124561256 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_rstmgr_smoketest.124561256
Directory	/workspace/0.chip_sw_rstmgr_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2141017852
Short name	T1307
Test name
Test status
Simulation time	4463257208 ps
CPU time	531.31 seconds
Started	Jul 24 07:58:23 PM PDT 24
Finished	Jul 24 08:07:15 PM PDT 24
Peak memory	610796 kb
Host	smart-cb70dcd2-23b5-42d3-bc4f-45151f3035a6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141017852 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.2141017852
Directory	/workspace/0.chip_sw_rstmgr_sw_req/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.457401035
Short name	T1230
Test name
Test status
Simulation time	2804592154 ps
CPU time	252.48 seconds
Started	Jul 24 07:58:37 PM PDT 24
Finished	Jul 24 08:02:51 PM PDT 24
Peak memory	610112 kb
Host	smart-1e584eb4-2df2-4957-8f74-3a631da2248e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457401035 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.457401035
Directory	/workspace/0.chip_sw_rstmgr_sw_rst/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.599485804
Short name	T180
Test name
Test status
Simulation time	3803228160 ps
CPU time	313.06 seconds
Started	Jul 24 08:00:54 PM PDT 24
Finished	Jul 24 08:06:07 PM PDT 24
Peak memory	609852 kb
Host	smart-7d9b6c53-c254-4544-b024-de955a63fd84
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=599485804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.599485804
Directory	/workspace/0.chip_sw_rv_core_ibex_address_translation/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1108325000
Short name	T182
Test name
Test status
Simulation time	2112131465 ps
CPU time	252.84 seconds
Started	Jul 24 07:57:51 PM PDT 24
Finished	Jul 24 08:02:05 PM PDT 24
Peak memory	609776 kb
Host	smart-2b2e5c55-a8df-40fc-9c6d-a484c2636653
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108325000 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.1108325000
Directory	/workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3938880784
Short name	T1025
Test name
Test status
Simulation time	6136540844 ps
CPU time	1024.81 seconds
Started	Jul 24 07:58:57 PM PDT 24
Finished	Jul 24 08:16:02 PM PDT 24
Peak memory	610652 kb
Host	smart-5162b107-926e-4a86-8ab6-bbfd0b161fbb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3938880784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.3938880784
Directory	/workspace/0.chip_sw_rv_core_ibex_rnd/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3036133266
Short name	T762
Test name
Test status
Simulation time	5068418030 ps
CPU time	605.01 seconds
Started	Jul 24 08:01:55 PM PDT 24
Finished	Jul 24 08:12:01 PM PDT 24
Peak memory	624664 kb
Host	smart-2025c569-ea6a-46f6-b371-935d87cce426
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036133266 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.3036133266
Directory	/workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2093980391
Short name	T1101
Test name
Test status
Simulation time	5841098168 ps
CPU time	359.98 seconds
Started	Jul 24 07:58:20 PM PDT 24
Finished	Jul 24 08:04:20 PM PDT 24
Peak memory	624628 kb
Host	smart-948627b7-1c14-4b49-b38f-22e6c7afbfb5
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093980391 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.2093980391
Directory	/workspace/0.chip_sw_rv_dm_access_after_wakeup/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.705715914
Short name	T313
Test name
Test status
Simulation time	5679850216 ps
CPU time	675.42 seconds
Started	Jul 24 07:59:06 PM PDT 24
Finished	Jul 24 08:10:22 PM PDT 24
Peak memory	619880 kb
Host	smart-23d5029a-6b53-4c84-897a-92eb9a6dcfc0
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705715 914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.705715914
Directory	/workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1913087017
Short name	T294
Test name
Test status
Simulation time	3214957460 ps
CPU time	302.17 seconds
Started	Jul 24 08:05:07 PM PDT 24
Finished	Jul 24 08:10:10 PM PDT 24
Peak memory	609820 kb
Host	smart-c0d08d16-5fce-4c6a-927a-06f1c50738b0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913087017 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.1913087017
Directory	/workspace/0.chip_sw_rv_plic_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_irq.985286250
Short name	T1278
Test name
Test status
Simulation time	2707400076 ps
CPU time	317.17 seconds
Started	Jul 24 07:57:31 PM PDT 24
Finished	Jul 24 08:02:48 PM PDT 24
Peak memory	609848 kb
Host	smart-d51e229a-8006-40b0-acdf-68499f934d30
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985286250 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_irq.985286250
Directory	/workspace/0.chip_sw_rv_timer_irq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3624673507
Short name	T257
Test name
Test status
Simulation time	3347669880 ps
CPU time	257.2 seconds
Started	Jul 24 08:02:19 PM PDT 24
Finished	Jul 24 08:06:36 PM PDT 24
Peak memory	609892 kb
Host	smart-fb4ce710-3b73-4e52-9c63-09b6f65e35ac
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624673507 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.3624673507
Directory	/workspace/0.chip_sw_rv_timer_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.591652709
Short name	T1236
Test name
Test status
Simulation time	2886037292 ps
CPU time	324.65 seconds
Started	Jul 24 08:01:32 PM PDT 24
Finished	Jul 24 08:06:57 PM PDT 24
Peak memory	610192 kb
Host	smart-be50cb72-c4c2-4bd0-8c3b-09dc62294ae8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5916527 09 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.591652709
Directory	/workspace/0.chip_sw_sensor_ctrl_status/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3171057683
Short name	T55
Test name
Test status
Simulation time	3049938804 ps
CPU time	312.18 seconds
Started	Jul 24 07:56:28 PM PDT 24
Finished	Jul 24 08:01:40 PM PDT 24
Peak memory	609820 kb
Host	smart-94a77693-0519-459c-8a28-f060fce96aa4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171057683 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.3171057683
Directory	/workspace/0.chip_sw_sleep_pin_retention/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1108415473
Short name	T216
Test name
Test status
Simulation time	8249131664 ps
CPU time	1210.96 seconds
Started	Jul 24 07:57:07 PM PDT 24
Finished	Jul 24 08:17:19 PM PDT 24
Peak memory	610392 kb
Host	smart-e671c552-d288-4a29-9608-22d78a1aef51
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108415473 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.1108415473
Directory	/workspace/0.chip_sw_sleep_pwm_pulses/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.781851572
Short name	T124
Test name
Test status
Simulation time	8076412800 ps
CPU time	857.56 seconds
Started	Jul 24 08:01:00 PM PDT 24
Finished	Jul 24 08:15:18 PM PDT 24
Peak memory	610736 kb
Host	smart-55359981-457a-4aeb-84f5-7a91b309e1c6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781851572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sle ep_sram_ret_contents_no_scramble.781851572
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.893849143
Short name	T1008
Test name
Test status
Simulation time	9173111140 ps
CPU time	727.14 seconds
Started	Jul 24 08:01:15 PM PDT 24
Finished	Jul 24 08:13:22 PM PDT 24
Peak memory	610756 kb
Host	smart-9c19015d-8bbe-4086-b079-04500dab483a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893849143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_ sram_ret_contents_scramble.893849143
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

---

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2355008148
Short name	T196
Test name
Test status
Simulation time	6894711793 ps
CPU time	820.46 seconds
Started	Jul 24 07:57:33 PM PDT 24
Finished	Jul 24 08:11:14 PM PDT 24
Peak memory	625440 kb
Host	smart-01e9d24e-f09e-4fae-b31b-af89dc6caffe
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355008148 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.2355008148
Directory	/workspace/0.chip_sw_spi_device_pass_through/latest

---

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1392611691
Short name	T13
Test name
Test status
Simulation time	4384579326 ps
CPU time	537.51 seconds
Started	Jul 24 07:56:53 PM PDT 24
Finished	Jul 24 08:05:51 PM PDT 24
Peak memory	625500 kb
Host	smart-49b92f16-e2e0-4c9e-8a2e-b43dfbaa2c7e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392611691 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.1392611691
Directory	/workspace/0.chip_sw_spi_device_pass_through_collision/latest

---

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2596972733
Short name	T56
Test name
Test status
Simulation time	3690480969 ps
CPU time	403.53 seconds
Started	Jul 24 07:58:00 PM PDT 24
Finished	Jul 24 08:04:43 PM PDT 24
Peak memory	618496 kb
Host	smart-0fd0f9c2-21fe-45fd-bef8-35a057d144bf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596972733 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.2596972733
Directory	/workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest

---

Test location	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2084622503
Short name	T43
Test name
Test status
Simulation time	3571177570 ps
CPU time	372.39 seconds
Started	Jul 24 07:57:29 PM PDT 24
Finished	Jul 24 08:03:42 PM PDT 24
Peak memory	618888 kb
Host	smart-774cf4fb-4b38-4a4a-9d05-adabb6322b1c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084622503 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2084622503
Directory	/workspace/0.chip_sw_spi_device_tpm/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.286418925
Short name	T1249
Test name
Test status
Simulation time	5819279616 ps
CPU time	671.11 seconds
Started	Jul 24 07:59:12 PM PDT 24
Finished	Jul 24 08:10:24 PM PDT 24
Peak memory	611444 kb
Host	smart-1dbd2d7a-e0ca-4215-9879-1c68e9390a37
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286418925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ sram_ctrl_scrambled_access.286418925
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2653407100
Short name	T293
Test name
Test status
Simulation time	4877131848 ps
CPU time	627.63 seconds
Started	Jul 24 07:57:58 PM PDT 24
Finished	Jul 24 08:08:27 PM PDT 24
Peak memory	611532 kb
Host	smart-42e021fe-3e30-4897-af89-1a2f178ec56c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653407100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2653407100
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.546261317
Short name	T1432
Test name
Test status
Simulation time	5586108169 ps
CPU time	511.95 seconds
Started	Jul 24 07:59:22 PM PDT 24
Finished	Jul 24 08:07:55 PM PDT 24
Peak memory	611240 kb
Host	smart-cb124b77-1131-429f-9d39-be4c5cac2be2
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546261317 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.546261317
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.4213964143
Short name	T111
Test name
Test status
Simulation time	2941469744 ps
CPU time	258.1 seconds
Started	Jul 24 08:03:58 PM PDT 24
Finished	Jul 24 08:08:16 PM PDT 24
Peak memory	609996 kb
Host	smart-6b39d357-b4f6-4716-b2b0-04ac95185bf0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213964143 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.4213964143
Directory	/workspace/0.chip_sw_sram_ctrl_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1084167250
Short name	T1309
Test name
Test status
Simulation time	4371783642 ps
CPU time	525.47 seconds
Started	Jul 24 07:56:27 PM PDT 24
Finished	Jul 24 08:05:14 PM PDT 24
Peak memory	614108 kb
Host	smart-6bdd16f9-0f09-4c80-964d-1978de55381b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084167250 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1084167250
Directory	/workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4207311337
Short name	T202
Test name
Test status
Simulation time	2963613883 ps
CPU time	258.04 seconds
Started	Jul 24 08:00:51 PM PDT 24
Finished	Jul 24 08:05:10 PM PDT 24
Peak memory	613792 kb
Host	smart-4e79f59b-e8b5-4810-9ef4-13212dc90615
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207311337 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.4207311337
Directory	/workspace/0.chip_sw_sysrst_ctrl_inputs/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.318227302
Short name	T1379
Test name
Test status
Simulation time	3699741480 ps
CPU time	361.05 seconds
Started	Jul 24 08:01:13 PM PDT 24
Finished	Jul 24 08:07:15 PM PDT 24
Peak memory	609768 kb
Host	smart-788b7a7c-caa5-4ff3-a15e-948e70c02c33
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318227302 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.318227302
Directory	/workspace/0.chip_sw_sysrst_ctrl_outputs/latest

---

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3960051340
Short name	T40
Test name
Test status
Simulation time	6555174740 ps
CPU time	602.71 seconds
Started	Jul 24 07:56:43 PM PDT 24
Finished	Jul 24 08:06:46 PM PDT 24
Peak memory	610140 kb
Host	smart-ad5b79ec-1b89-4ece-9148-252d3ee741ad
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960051340 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3960051340
Directory	/workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

---

Test location	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1785333676
Short name	T339
Test name
Test status
Simulation time	4252207056 ps
CPU time	535.15 seconds
Started	Jul 24 07:56:03 PM PDT 24
Finished	Jul 24 08:04:58 PM PDT 24
Peak memory	619588 kb
Host	smart-d50412b5-6779-4150-a72f-e47775ad8a33
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1785333676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1785333676
Directory	/workspace/0.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/0.chip_sw_uart_smoketest.4149727613
Short name	T1334
Test name
Test status
Simulation time	2403018172 ps
CPU time	208.21 seconds
Started	Jul 24 08:00:40 PM PDT 24
Finished	Jul 24 08:04:09 PM PDT 24
Peak memory	616328 kb
Host	smart-df18e423-ff07-480a-82bc-89a285dde222
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149727613 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.4149727613
Directory	/workspace/0.chip_sw_uart_smoketest/latest

---

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx.4088954524
Short name	T1124
Test name
Test status
Simulation time	4402703988 ps
CPU time	774.94 seconds
Started	Jul 24 07:56:12 PM PDT 24
Finished	Jul 24 08:09:08 PM PDT 24
Peak memory	623016 kb
Host	smart-d6fb3e16-3772-49d2-81d0-7e98eb0dee47
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088954524 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.4088954524
Directory	/workspace/0.chip_sw_uart_tx_rx/latest

---

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.81196388
Short name	T1164
Test name
Test status
Simulation time	8822314297 ps
CPU time	1787.12 seconds
Started	Jul 24 07:56:44 PM PDT 24
Finished	Jul 24 08:26:32 PM PDT 24
Peak memory	625164 kb
Host	smart-42ef2172-f3df-4f49-8172-35eeba84933b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81196388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_bau drate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_a lt_clk_freq.81196388
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest

---

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.494077035
Short name	T343
Test name
Test status
Simulation time	13852585130 ps
CPU time	2291.3 seconds
Started	Jul 24 07:56:39 PM PDT 24
Finished	Jul 24 08:34:52 PM PDT 24
Peak memory	619152 kb
Host	smart-e5425e4c-2b96-41e4-904e-743279919839
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494077035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.494077035
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

---

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2087253525
Short name	T1011
Test name
Test status
Simulation time	4497466914 ps
CPU time	661.35 seconds
Started	Jul 24 07:56:46 PM PDT 24
Finished	Jul 24 08:07:48 PM PDT 24
Peak memory	625236 kb
Host	smart-a88aa542-4f2b-4baf-a436-3789031676db
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087253525 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.2087253525
Directory	/workspace/0.chip_sw_uart_tx_rx_idx1/latest

---

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1608827838
Short name	T1304
Test name
Test status
Simulation time	4843699440 ps
CPU time	795.22 seconds
Started	Jul 24 07:56:51 PM PDT 24
Finished	Jul 24 08:10:06 PM PDT 24
Peak memory	623316 kb
Host	smart-2e9d63f6-5f2d-49f6-869a-d2a6447d7d87
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608827838 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.1608827838
Directory	/workspace/0.chip_sw_uart_tx_rx_idx2/latest

---

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1036522158
Short name	T1415
Test name
Test status
Simulation time	4469635864 ps
CPU time	611.25 seconds
Started	Jul 24 07:57:44 PM PDT 24
Finished	Jul 24 08:07:56 PM PDT 24
Peak memory	625232 kb
Host	smart-4e60be77-a7a0-4bb1-b107-edd9760c2511
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036522158 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.1036522158
Directory	/workspace/0.chip_sw_uart_tx_rx_idx3/latest

---

Test location	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.4060343232
Short name	T1420
Test name
Test status
Simulation time	3321972784 ps
CPU time	255.1 seconds
Started	Jul 24 08:00:07 PM PDT 24
Finished	Jul 24 08:04:22 PM PDT 24
Peak memory	609508 kb
Host	smart-321075f6-7dc0-4925-a48f-9ad6c500596c
User	root
Command	/workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060343232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.4060343232
Directory	/workspace/0.chip_sw_usb_ast_clk_calib/latest

---

Test location	/workspace/coverage/default/0.chip_sw_usbdev_config_host.644481609
Short name	T25
Test name
Test status
Simulation time	7963478830 ps
CPU time	1994.21 seconds
Started	Jul 24 07:55:41 PM PDT 24
Finished	Jul 24 08:28:56 PM PDT 24
Peak memory	609852 kb
Host	smart-1e7c58be-2fd6-4cfc-90cd-b09c2fe1d59d
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64448 1609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.644481609
Directory	/workspace/0.chip_sw_usbdev_config_host/latest

---

Test location	/workspace/coverage/default/0.chip_sw_usbdev_dpi.4203512144
Short name	T146
Test name
Test status
Simulation time	12231327526 ps
CPU time	3165.9 seconds
Started	Jul 24 07:58:03 PM PDT 24
Finished	Jul 24 08:50:49 PM PDT 24
Peak memory	609868 kb
Host	smart-fadec828-dd0c-4c39-a33c-59d96e1137e2
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4203512144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.4203512144
Directory	/workspace/0.chip_sw_usbdev_dpi/latest

---

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pullup.3656320864
Short name	T72
Test name
Test status
Simulation time	3132298620 ps
CPU time	378.47 seconds
Started	Jul 24 07:57:12 PM PDT 24
Finished	Jul 24 08:03:31 PM PDT 24
Peak memory	610268 kb
Host	smart-2aeadfda-9164-4057-b416-9a4e03fb9f9a
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656320864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.3656320864
Directory	/workspace/0.chip_sw_usbdev_pullup/latest

---

Test location	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1301462289
Short name	T1160
Test name
Test status
Simulation time	3460529346 ps
CPU time	506.73 seconds
Started	Jul 24 07:57:40 PM PDT 24
Finished	Jul 24 08:06:08 PM PDT 24
Peak memory	609860 kb
Host	smart-7dbf5f80-2d46-428c-9341-155e384a6eb2
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130146228 9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.1301462289
Directory	/workspace/0.chip_sw_usbdev_setuprx/latest

---

Test location	/workspace/coverage/default/0.chip_sw_usbdev_stream.3762760422
Short name	T26
Test name
Test status
Simulation time	18121029568 ps
CPU time	4382.99 seconds
Started	Jul 24 07:57:01 PM PDT 24
Finished	Jul 24 09:10:05 PM PDT 24
Peak memory	609868 kb
Host	smart-34187a6e-2a62-43bc-b775-f6da20f3a553
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3762760422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3762760422
Directory	/workspace/0.chip_sw_usbdev_stream/latest

---

Test location	/workspace/coverage/default/0.chip_sw_usbdev_vbus.480243499
Short name	T1132
Test name
Test status
Simulation time	3463833328 ps
CPU time	268.57 seconds
Started	Jul 24 07:56:59 PM PDT 24
Finished	Jul 24 08:01:28 PM PDT 24
Peak memory	610108 kb
Host	smart-96b00ffd-f7df-4e63-a8c4-97b538f58143
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480243499 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.480243499
Directory	/workspace/0.chip_sw_usbdev_vbus/latest

---

Test location	/workspace/coverage/default/0.chip_tap_straps_dev.985180783
Short name	T995
Test name
Test status
Simulation time	2586420278 ps
CPU time	184.66 seconds
Started	Jul 24 08:02:08 PM PDT 24
Finished	Jul 24 08:05:13 PM PDT 24
Peak memory	622020 kb
Host	smart-ee27e0a4-c519-4af4-9cf2-575674472a21
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=985180783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.985180783
Directory	/workspace/0.chip_tap_straps_dev/latest

---

Test location	/workspace/coverage/default/0.chip_tap_straps_prod.2807893527
Short name	T1058
Test name
Test status
Simulation time	2923534668 ps
CPU time	141.66 seconds
Started	Jul 24 08:07:50 PM PDT 24
Finished	Jul 24 08:10:13 PM PDT 24
Peak memory	620564 kb
Host	smart-7af11f33-7ae9-4c52-b709-cf015050c236
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807893527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2807893527
Directory	/workspace/0.chip_tap_straps_prod/latest

---

Test location	/workspace/coverage/default/0.chip_tap_straps_rma.1866034838
Short name	T64
Test name
Test status
Simulation time	4572087262 ps
CPU time	387.63 seconds
Started	Jul 24 07:58:42 PM PDT 24
Finished	Jul 24 08:05:11 PM PDT 24
Peak memory	621540 kb
Host	smart-6f703aec-4431-49df-8e74-18a443aee19f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866034838 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.1866034838
Directory	/workspace/0.chip_tap_straps_rma/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_dev.683463261
Short name	T1127
Test name
Test status
Simulation time	15746366405 ps
CPU time	3403.34 seconds
Started	Jul 24 08:07:52 PM PDT 24
Finished	Jul 24 09:04:36 PM PDT 24
Peak memory	610828 kb
Host	smart-127e4f6e-6996-4da7-a98e-92b57669cdfb
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683463261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rom_e2e_asm_init_dev.683463261
Directory	/workspace/0.rom_e2e_asm_init_dev/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_prod.96552432
Short name	T1372
Test name
Test status
Simulation time	15271222445 ps
CPU time	3863.44 seconds
Started	Jul 24 08:06:04 PM PDT 24
Finished	Jul 24 09:10:28 PM PDT 24
Peak memory	610824 kb
Host	smart-25d81a38-779f-4c74-aafa-e2f6b6b1a0e0
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96552432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rom_e2e_asm_init_prod.96552432
Directory	/workspace/0.rom_e2e_asm_init_prod/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2865586286
Short name	T1108
Test name
Test status
Simulation time	15831013317 ps
CPU time	4219.52 seconds
Started	Jul 24 08:05:48 PM PDT 24
Finished	Jul 24 09:16:09 PM PDT 24
Peak memory	610884 kb
Host	smart-17ae4d38-dfa1-4b60-a99a-4cd7a253fe25
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865586286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.2865586286
Directory	/workspace/0.rom_e2e_asm_init_prod_end/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_rma.2548018824
Short name	T1063
Test name
Test status
Simulation time	14622583877 ps
CPU time	3702.65 seconds
Started	Jul 24 08:05:52 PM PDT 24
Finished	Jul 24 09:07:35 PM PDT 24
Peak memory	610636 kb
Host	smart-301d986d-7e29-4b0a-9341-fcee58fa265c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548018824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.2548018824
Directory	/workspace/0.rom_e2e_asm_init_rma/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3446588763
Short name	T1085
Test name
Test status
Simulation time	11960299828 ps
CPU time	3413.03 seconds
Started	Jul 24 08:05:13 PM PDT 24
Finished	Jul 24 09:02:06 PM PDT 24
Peak memory	610076 kb
Host	smart-f38a5e2f-73df-4c99-a38c-a81169259778
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446588763 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.3446588763
Directory	/workspace/0.rom_e2e_asm_init_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2592193447
Short name	T401
Test name
Test status
Simulation time	24328333900 ps
CPU time	5490.67 seconds
Started	Jul 24 08:04:28 PM PDT 24
Finished	Jul 24 09:35:59 PM PDT 24
Peak memory	610416 kb
Host	smart-86a4d059-73c2-4398-8973-7a8861e08ee0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2592193447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2592193447
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.804557305
Short name	T402
Test name
Test status
Simulation time	23718261400 ps
CPU time	5976.99 seconds
Started	Jul 24 08:06:14 PM PDT 24
Finished	Jul 24 09:45:52 PM PDT 24
Peak memory	610628 kb
Host	smart-4c31b0fe-bc77-4fad-bfe6-98e8230bc2e7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=804557305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.804557305
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2909859205
Short name	T1248
Test name
Test status
Simulation time	22825026140 ps
CPU time	5757.77 seconds
Started	Jul 24 08:05:46 PM PDT 24
Finished	Jul 24 09:41:45 PM PDT 24
Peak memory	609992 kb
Host	smart-a49b25df-a3fa-41fb-a4a8-c8f498232786
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2909859205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2909859205
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2173252416
Short name	T1195
Test name
Test status
Simulation time	18324614558 ps
CPU time	5542.51 seconds
Started	Jul 24 08:06:17 PM PDT 24
Finished	Jul 24 09:38:40 PM PDT 24
Peak memory	609956 kb
Host	smart-f55712de-114e-4614-9abe-1f6036a4c91b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173252416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2173252416
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1359161820
Short name	T1401
Test name
Test status
Simulation time	15362831712 ps
CPU time	3959.46 seconds
Started	Jul 24 08:06:19 PM PDT 24
Finished	Jul 24 09:12:19 PM PDT 24
Peak memory	609944 kb
Host	smart-a0c63c40-0f42-4ee7-a98a-b5af8fa63d89
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1359161820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1359161820
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1292699941
Short name	T1036
Test name
Test status
Simulation time	15941879048 ps
CPU time	3880.54 seconds
Started	Jul 24 08:04:17 PM PDT 24
Finished	Jul 24 09:08:58 PM PDT 24
Peak memory	609928 kb
Host	smart-00f519da-9215-49df-badd-7ae89574c78c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1292699941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1292699941
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.860749599
Short name	T1029
Test name
Test status
Simulation time	15105247320 ps
CPU time	3916.09 seconds
Started	Jul 24 08:05:27 PM PDT 24
Finished	Jul 24 09:10:44 PM PDT 24
Peak memory	609972 kb
Host	smart-a5e85593-1aea-43ec-8410-854b4c9f1c64
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=860749599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.860749599
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3605707618
Short name	T411
Test name
Test status
Simulation time	15582426880 ps
CPU time	4006.66 seconds
Started	Jul 24 08:08:00 PM PDT 24
Finished	Jul 24 09:14:48 PM PDT 24
Peak memory	609912 kb
Host	smart-31ea8c37-3083-495e-8c2e-82d9757bc507
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3605707618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3605707618
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1523937231
Short name	T1407
Test name
Test status
Simulation time	11047407496 ps
CPU time	2354.81 seconds
Started	Jul 24 08:05:39 PM PDT 24
Finished	Jul 24 08:44:54 PM PDT 24
Peak memory	609972 kb
Host	smart-839cabd3-9db4-414f-82c1-e24119caa219
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523937231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1523937231
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.4150412330
Short name	T1114
Test name
Test status
Simulation time	14960235744 ps
CPU time	3747.31 seconds
Started	Jul 24 08:05:30 PM PDT 24
Finished	Jul 24 09:07:58 PM PDT 24
Peak memory	609904 kb
Host	smart-b0e3026a-9293-4252-a7e4-9ffe2852a6c3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150412330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.4150412330
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1689911173
Short name	T1226
Test name
Test status
Simulation time	15461486284 ps
CPU time	4580.44 seconds
Started	Jul 24 08:06:17 PM PDT 24
Finished	Jul 24 09:22:38 PM PDT 24
Peak memory	609956 kb
Host	smart-2d18d044-32fc-417d-9a1a-e6ae51867194
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689911173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1689911173
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1060434514
Short name	T1145
Test name
Test status
Simulation time	15760413940 ps
CPU time	4151.84 seconds
Started	Jul 24 08:03:44 PM PDT 24
Finished	Jul 24 09:12:56 PM PDT 24
Peak memory	609852 kb
Host	smart-6625d10c-d293-49a2-afa6-21994ea44646
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106043 4514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1060434514
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.54306416
Short name	T1126
Test name
Test status
Simulation time	14820459984 ps
CPU time	3541.49 seconds
Started	Jul 24 08:05:39 PM PDT 24
Finished	Jul 24 09:04:41 PM PDT 24
Peak memory	609816 kb
Host	smart-b17c0812-5b5d-4172-8f69-aa45e2f67801
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54306416 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.54306416
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3549616103
Short name	T1340
Test name
Test status
Simulation time	11315723348 ps
CPU time	2916.98 seconds
Started	Jul 24 08:04:02 PM PDT 24
Finished	Jul 24 08:52:39 PM PDT 24
Peak memory	609904 kb
Host	smart-4231cf64-c26b-43fe-9a67-d984c0b3d644
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3549616103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3549616103
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.715646093
Short name	T261
Test name
Test status
Simulation time	10817389982 ps
CPU time	2178.5 seconds
Started	Jul 24 08:02:12 PM PDT 24
Finished	Jul 24 08:38:32 PM PDT 24
Peak memory	624316 kb
Host	smart-62194ee9-411d-47fa-8121-f989124fd125
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71564 6093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.715646093
Directory	/workspace/0.rom_e2e_jtag_debug_rma/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2555739939
Short name	T262
Test name
Test status
Simulation time	10950425907 ps
CPU time	1843.38 seconds
Started	Jul 24 08:02:40 PM PDT 24
Finished	Jul 24 08:33:24 PM PDT 24
Peak memory	624660 kb
Host	smart-94aede60-d209-4834-b44d-f706a1f300c9
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2555739939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.2555739939
Directory	/workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1458680197
Short name	T67
Test name
Test status
Simulation time	24299170186 ps
CPU time	2837.49 seconds
Started	Jul 24 08:02:44 PM PDT 24
Finished	Jul 24 08:50:02 PM PDT 24
Peak memory	620696 kb
Host	smart-44d02c64-cb38-40b5-a96e-368e30bd0e3f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1458680197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.1458680197
Directory	/workspace/0.rom_e2e_jtag_inject_dev/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.354133881
Short name	T990
Test name
Test status
Simulation time	24313258783 ps
CPU time	2085.98 seconds
Started	Jul 24 08:02:10 PM PDT 24
Finished	Jul 24 08:36:57 PM PDT 24
Peak memory	621648 kb
Host	smart-528e51bf-72c3-471d-b8e2-67bdd2e4695d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=354133881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.354133881
Directory	/workspace/0.rom_e2e_jtag_inject_rma/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1151884217
Short name	T442
Test name
Test status
Simulation time	27785536199 ps
CPU time	2152.3 seconds
Started	Jul 24 08:02:47 PM PDT 24
Finished	Jul 24 08:38:40 PM PDT 24
Peak memory	622004 kb
Host	smart-9fc6bb45-1bfc-443a-b89e-49170ebaa90a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151884217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.1151884217
Directory	/workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2955066166
Short name	T1421
Test name
Test status
Simulation time	14640492844 ps
CPU time	3961.94 seconds
Started	Jul 24 08:08:21 PM PDT 24
Finished	Jul 24 09:14:24 PM PDT 24
Peak memory	610624 kb
Host	smart-c90af940-cb1c-4aea-9531-d3f92bcdb6c9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955066166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2955066166
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2027276337
Short name	T1182
Test name
Test status
Simulation time	15067710710 ps
CPU time	3518.57 seconds
Started	Jul 24 08:06:28 PM PDT 24
Finished	Jul 24 09:05:08 PM PDT 24
Peak memory	610856 kb
Host	smart-e8826fed-43a3-43ec-b7aa-1dcace700ca0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027276337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2027276337
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1723886980
Short name	T1320
Test name
Test status
Simulation time	15027257224 ps
CPU time	3823.51 seconds
Started	Jul 24 08:06:09 PM PDT 24
Finished	Jul 24 09:09:53 PM PDT 24
Peak memory	610632 kb
Host	smart-a8a32a0b-3e2a-4089-8f6d-f212399de874
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723886980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.1723886980
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_self_hash.2877703156
Short name	T1438
Test name
Test status
Simulation time	26361659288 ps
CPU time	5885.35 seconds
Started	Jul 24 08:05:47 PM PDT 24
Finished	Jul 24 09:43:53 PM PDT 24
Peak memory	610848 kb
Host	smart-3ffad33c-331e-4782-a27e-669dd7c16618
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877703156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.2877703156
Directory	/workspace/0.rom_e2e_self_hash/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3861883986
Short name	T1091
Test name
Test status
Simulation time	14090445058 ps
CPU time	3521.88 seconds
Started	Jul 24 08:03:58 PM PDT 24
Finished	Jul 24 09:02:41 PM PDT 24
Peak memory	611652 kb
Host	smart-17c8e9ba-d378-4ad1-9e0a-5ce64ce8c56c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861883986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.3861883986
Directory	/workspace/0.rom_e2e_shutdown_exception_c/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_shutdown_output.2457315503
Short name	T274
Test name
Test status
Simulation time	26541111800 ps
CPU time	3696.33 seconds
Started	Jul 24 08:03:32 PM PDT 24
Finished	Jul 24 09:05:10 PM PDT 24
Peak memory	611788 kb
Host	smart-9f289fe3-a47c-4bd5-9169-cdbd81ecec85
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457315503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.2457315503
Directory	/workspace/0.rom_e2e_shutdown_output/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2403346645
Short name	T1413
Test name
Test status
Simulation time	24015612836 ps
CPU time	4665.05 seconds
Started	Jul 24 08:02:33 PM PDT 24
Finished	Jul 24 09:20:18 PM PDT 24
Peak memory	611464 kb
Host	smart-59a1d94b-c30d-4870-bd51-c1f21ea0d826
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2403346645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.2403346645
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.799542469
Short name	T273
Test name
Test status
Simulation time	23542255295 ps
CPU time	6092.01 seconds
Started	Jul 24 08:04:37 PM PDT 24
Finished	Jul 24 09:46:10 PM PDT 24
Peak memory	609764 kb
Host	smart-6107d542-e30a-4492-9a37-b3148653b8d6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=799542469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_prod.799542469
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1334111084
Short name	T1081
Test name
Test status
Simulation time	22655332047 ps
CPU time	6362.6 seconds
Started	Jul 24 08:07:01 PM PDT 24
Finished	Jul 24 09:53:04 PM PDT 24
Peak memory	609760 kb
Host	smart-5e24bc52-082d-4b2f-b4d5-99b275f52de0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1334111084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.1334111084
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4210303398
Short name	T1440
Test name
Test status
Simulation time	22356663480 ps
CPU time	5493.34 seconds
Started	Jul 24 08:05:39 PM PDT 24
Finished	Jul 24 09:37:13 PM PDT 24
Peak memory	611708 kb
Host	smart-72d1c2db-c334-4f66-ad44-044ad15a8995
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=4210303398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.4210303398
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3982599873
Short name	T47
Test name
Test status
Simulation time	17206957705 ps
CPU time	4280.93 seconds
Started	Jul 24 08:08:15 PM PDT 24
Finished	Jul 24 09:19:36 PM PDT 24
Peak memory	610016 kb
Host	smart-e84d1fe1-d46a-4a1d-a69e-b5a93a88b67d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3982599873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.3982599873
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2646591100
Short name	T1219
Test name
Test status
Simulation time	14711256612 ps
CPU time	4506.54 seconds
Started	Jul 24 08:06:32 PM PDT 24
Finished	Jul 24 09:21:39 PM PDT 24
Peak memory	609952 kb
Host	smart-9fab4a85-8ce0-4047-afcd-2bab521cd622
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646591100 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2646591100
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2945607237
Short name	T1290
Test name
Test status
Simulation time	15096560659 ps
CPU time	3881.16 seconds
Started	Jul 24 08:04:04 PM PDT 24
Finished	Jul 24 09:08:46 PM PDT 24
Peak memory	609888 kb
Host	smart-78ff1621-b52e-4d34-8604-f513a0d2869f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945607237 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2945607237
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2423694639
Short name	T45
Test name
Test status
Simulation time	14113225401 ps
CPU time	4144.56 seconds
Started	Jul 24 08:04:08 PM PDT 24
Finished	Jul 24 09:13:13 PM PDT 24
Peak memory	611768 kb
Host	smart-4424ca3c-7fe5-4fba-9bcb-2d14c3e55650
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423694639 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2423694639
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.4025140563
Short name	T275
Test name
Test status
Simulation time	13958112210 ps
CPU time	3896.94 seconds
Started	Jul 24 08:04:45 PM PDT 24
Finished	Jul 24 09:09:43 PM PDT 24
Peak memory	609836 kb
Host	smart-086e367e-7d2d-473c-9ef9-a3c3b2bb7ba2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025140563 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.4025140563
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.370467343
Short name	T1262
Test name
Test status
Simulation time	11571196100 ps
CPU time	2895.08 seconds
Started	Jul 24 08:04:34 PM PDT 24
Finished	Jul 24 08:52:50 PM PDT 24
Peak memory	611128 kb
Host	smart-058767e7-48fa-478a-8130-824790607f0e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370467343 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.370467343
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1541205650
Short name	T1187
Test name
Test status
Simulation time	15136983984 ps
CPU time	3274.27 seconds
Started	Jul 24 08:05:43 PM PDT 24
Finished	Jul 24 09:00:18 PM PDT 24
Peak memory	609896 kb
Host	smart-54f6d2c3-6e3b-4123-affa-e0eb65ce3faf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541205650 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1541205650
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2717191861
Short name	T1206
Test name
Test status
Simulation time	14612016305 ps
CPU time	4362.94 seconds
Started	Jul 24 08:04:06 PM PDT 24
Finished	Jul 24 09:16:50 PM PDT 24
Peak memory	609872 kb
Host	smart-112f45af-3124-4090-b50c-1aa9cb59f6ea
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717191861 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2717191861
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1385459076
Short name	T1074
Test name
Test status
Simulation time	14628702454 ps
CPU time	3551.4 seconds
Started	Jul 24 08:05:17 PM PDT 24
Finished	Jul 24 09:04:29 PM PDT 24
Peak memory	611852 kb
Host	smart-9949f2db-75ab-42ff-ad6b-d5f44286f9de
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385459076 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1385459076
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3737485695
Short name	T277
Test name
Test status
Simulation time	13844465100 ps
CPU time	3753.22 seconds
Started	Jul 24 08:08:37 PM PDT 24
Finished	Jul 24 09:11:11 PM PDT 24
Peak memory	609876 kb
Host	smart-eb92e1b4-9a29-44ab-a2bd-8d2aaeae5fde
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737485695 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3737485695
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1837728287
Short name	T1308
Test name
Test status
Simulation time	10415828658 ps
CPU time	3024.25 seconds
Started	Jul 24 08:08:04 PM PDT 24
Finished	Jul 24 08:58:29 PM PDT 24
Peak memory	610996 kb
Host	smart-e9748568-7dd0-4dfe-85c0-8504b333f15e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837728287 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1837728287
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_smoke.2483005315
Short name	T1103
Test name
Test status
Simulation time	14530647160 ps
CPU time	3876.93 seconds
Started	Jul 24 08:05:26 PM PDT 24
Finished	Jul 24 09:10:04 PM PDT 24
Peak memory	611520 kb
Host	smart-21515fb4-4a27-413e-a958-c14f8f5190aa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2483005315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.2483005315
Directory	/workspace/0.rom_e2e_smoke/latest

---

Test location	/workspace/coverage/default/0.rom_e2e_static_critical.1370807452
Short name	T997
Test name
Test status
Simulation time	17291904440 ps
CPU time	3994.39 seconds
Started	Jul 24 08:02:36 PM PDT 24
Finished	Jul 24 09:09:11 PM PDT 24
Peak memory	610600 kb
Host	smart-ad9a6005-ea89-48b0-bb9b-75905e08a308
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370807452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.1370807452
Directory	/workspace/0.rom_e2e_static_critical/latest

---

Test location	/workspace/coverage/default/0.rom_keymgr_functest.4216589585
Short name	T271
Test name
Test status
Simulation time	4155635798 ps
CPU time	493.92 seconds
Started	Jul 24 08:05:35 PM PDT 24
Finished	Jul 24 08:13:49 PM PDT 24
Peak memory	609852 kb
Host	smart-73dd9627-c52c-4d1d-8313-1f45a84e1e51
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216589585 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.4216589585
Directory	/workspace/0.rom_keymgr_functest/latest

---

Test location	/workspace/coverage/default/0.rom_raw_unlock.978430445
Short name	T151
Test name
Test status
Simulation time	4963500837 ps
CPU time	258.9 seconds
Started	Jul 24 08:01:49 PM PDT 24
Finished	Jul 24 08:06:08 PM PDT 24
Peak memory	620868 kb
Host	smart-611e5dc9-7709-40b8-a38e-4cc196642093
User	root
Command	/workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=978430445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.978430445
Directory	/workspace/0.rom_raw_unlock/latest

---

Test location	/workspace/coverage/default/0.rom_volatile_raw_unlock.669254629
Short name	T1364
Test name
Test status
Simulation time	2053765478 ps
CPU time	118.76 seconds
Started	Jul 24 08:01:45 PM PDT 24
Finished	Jul 24 08:03:44 PM PDT 24
Peak memory	623428 kb
Host	smart-54299e76-56aa-43c1-b7df-fdd225df7830
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669254629 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.669254629
Directory	/workspace/0.rom_volatile_raw_unlock/latest

---

Test location	/workspace/coverage/default/1.chip_jtag_mem_access.536298783
Short name	T197
Test name
Test status
Simulation time	13861224729 ps
CPU time	1590.83 seconds
Started	Jul 24 07:59:39 PM PDT 24
Finished	Jul 24 08:26:10 PM PDT 24
Peak memory	608252 kb
Host	smart-8d70c0b2-2aa6-4f92-b34f-ee75494e767a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536298783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.536298783
Directory	/workspace/1.chip_jtag_mem_access/latest

---

Test location	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3280893556
Short name	T416
Test name
Test status
Simulation time	3291917330 ps
CPU time	337.71 seconds
Started	Jul 24 08:06:33 PM PDT 24
Finished	Jul 24 08:12:11 PM PDT 24
Peak memory	624128 kb
Host	smart-12ee512a-f5ee-4824-95e5-ea5d9ba846aa
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 280893556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.3280893556
Directory	/workspace/1.chip_rv_dm_ndm_reset_req/latest

---

Test location	/workspace/coverage/default/1.chip_sival_flash_info_access.3465296363
Short name	T330
Test name
Test status
Simulation time	2524488620 ps
CPU time	312.8 seconds
Started	Jul 24 07:59:49 PM PDT 24
Finished	Jul 24 08:05:02 PM PDT 24
Peak memory	609996 kb
Host	smart-abdaa2fb-c461-4b2c-9276-de9940522c27
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3465296363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3465296363
Directory	/workspace/1.chip_sival_flash_info_access/latest

---

Test location	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1518260833
Short name	T361
Test name
Test status
Simulation time	18647622928 ps
CPU time	616.25 seconds
Started	Jul 24 08:05:00 PM PDT 24
Finished	Jul 24 08:15:17 PM PDT 24
Peak memory	619880 kb
Host	smart-e35da11a-a2fa-407c-9d94-1ddc2218e24d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1518260833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1518260833
Directory	/workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aes_enc.2253994614
Short name	T797
Test name
Test status
Simulation time	2843048976 ps
CPU time	263.24 seconds
Started	Jul 24 08:05:37 PM PDT 24
Finished	Jul 24 08:10:00 PM PDT 24
Peak memory	610192 kb
Host	smart-0b99ae5e-a29a-4caf-a34c-292f1c7ee866
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253994614 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.2253994614
Directory	/workspace/1.chip_sw_aes_enc/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1573103652
Short name	T1291
Test name
Test status
Simulation time	3071166196 ps
CPU time	321.85 seconds
Started	Jul 24 08:07:48 PM PDT 24
Finished	Jul 24 08:13:10 PM PDT 24
Peak memory	609952 kb
Host	smart-4bac3483-7631-4f20-a89b-a8fc401b93ee
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573 103652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1573103652
Directory	/workspace/1.chip_sw_aes_enc_jitter_en/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3652605272
Short name	T1256
Test name
Test status
Simulation time	3220805955 ps
CPU time	241.65 seconds
Started	Jul 24 08:07:38 PM PDT 24
Finished	Jul 24 08:11:40 PM PDT 24
Peak memory	609840 kb
Host	smart-79c5df5c-b3f8-4d73-88df-fb009ae4969b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652605272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.3652605272
Directory	/workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aes_entropy.125232351
Short name	T1229
Test name
Test status
Simulation time	3182416384 ps
CPU time	262.62 seconds
Started	Jul 24 08:05:39 PM PDT 24
Finished	Jul 24 08:10:02 PM PDT 24
Peak memory	610164 kb
Host	smart-4a0381d0-3410-4d67-b4ba-841f381d89f6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125232351 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.125232351
Directory	/workspace/1.chip_sw_aes_entropy/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aes_idle.1287567811
Short name	T270
Test name
Test status
Simulation time	3104932000 ps
CPU time	292.57 seconds
Started	Jul 24 08:05:27 PM PDT 24
Finished	Jul 24 08:10:20 PM PDT 24
Peak memory	610292 kb
Host	smart-ba4431ac-1300-422f-a75b-bc30ecfda883
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287567811 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.1287567811
Directory	/workspace/1.chip_sw_aes_idle/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aes_masking_off.1314277732
Short name	T1265
Test name
Test status
Simulation time	3384775522 ps
CPU time	376.21 seconds
Started	Jul 24 08:03:24 PM PDT 24
Finished	Jul 24 08:09:41 PM PDT 24
Peak memory	609884 kb
Host	smart-690f4426-af9a-40ee-8b19-f7f448c60a97
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314277732 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.1314277732
Directory	/workspace/1.chip_sw_aes_masking_off/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aes_smoketest.2525669382
Short name	T1019
Test name
Test status
Simulation time	2800802166 ps
CPU time	336.97 seconds
Started	Jul 24 08:09:25 PM PDT 24
Finished	Jul 24 08:15:02 PM PDT 24
Peak memory	609840 kb
Host	smart-09f53c11-2e42-4b4a-b154-d4e4bc16c10a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525669382 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.2525669382
Directory	/workspace/1.chip_sw_aes_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1692758362
Short name	T160
Test name
Test status
Simulation time	3709922451 ps
CPU time	379.18 seconds
Started	Jul 24 08:06:06 PM PDT 24
Finished	Jul 24 08:12:26 PM PDT 24
Peak memory	610076 kb
Host	smart-6864b37a-9557-41af-8477-09be203a9c21
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1692758362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.1692758362
Directory	/workspace/1.chip_sw_alert_handler_entropy/latest

---

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1157434555
Short name	T226
Test name
Test status
Simulation time	6008217576 ps
CPU time	574.46 seconds
Started	Jul 24 08:05:57 PM PDT 24
Finished	Jul 24 08:15:33 PM PDT 24
Peak memory	620004 kb
Host	smart-198d9b06-4841-49da-91da-dd10f2b34acb
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1157434555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1157434555
Directory	/workspace/1.chip_sw_alert_handler_escalation/latest

---

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.4116092871
Short name	T451
Test name
Test status
Simulation time	7134401430 ps
CPU time	1689.22 seconds
Started	Jul 24 08:06:53 PM PDT 24
Finished	Jul 24 08:35:03 PM PDT 24
Peak memory	610552 kb
Host	smart-b72c591d-32f4-4fbb-af15-211b224dcd9e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4116092871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.4116092871
Directory	/workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

---

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.543557713
Short name	T1054
Test name
Test status
Simulation time	7780916094 ps
CPU time	1701.1 seconds
Started	Jul 24 08:06:04 PM PDT 24
Finished	Jul 24 08:34:26 PM PDT 24
Peak memory	610596 kb
Host	smart-9c7bf09c-f9a3-4e7a-8739-87f07da857f5
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543557713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.543557713
Directory	/workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

---

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.746869739
Short name	T84
Test name
Test status
Simulation time	11290032828 ps
CPU time	1403.29 seconds
Started	Jul 24 08:05:57 PM PDT 24
Finished	Jul 24 08:29:21 PM PDT 24
Peak memory	611216 kb
Host	smart-a6a9da26-0cdd-42a7-afa8-17d974615a7e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746869739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.746869739
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

---

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2899527011
Short name	T804
Test name
Test status
Simulation time	8071764340 ps
CPU time	1441.21 seconds
Started	Jul 24 08:05:42 PM PDT 24
Finished	Jul 24 08:29:44 PM PDT 24
Peak memory	610408 kb
Host	smart-284a088c-7877-4d15-8b75-64d085fb2325
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2899527011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.2899527011
Directory	/workspace/1.chip_sw_alert_handler_ping_ok/latest

---

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.633185210
Short name	T1148
Test name
Test status
Simulation time	4228959040 ps
CPU time	498.66 seconds
Started	Jul 24 08:06:30 PM PDT 24
Finished	Jul 24 08:14:49 PM PDT 24
Peak memory	610308 kb
Host	smart-1cebe4b3-d6d7-4cba-b7f9-a2d827392a9c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=633185210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.633185210
Directory	/workspace/1.chip_sw_alert_handler_ping_timeout/latest

---

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.896312430
Short name	T1238
Test name
Test status
Simulation time	254366646780 ps
CPU time	11748.7 seconds
Started	Jul 24 08:06:21 PM PDT 24
Finished	Jul 24 11:22:11 PM PDT 24
Peak memory	611040 kb
Host	smart-bd7e8c10-75e7-44bb-8f65-eb414858b71b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=896312430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.896312430
Directory	/workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

---

Test location	/workspace/coverage/default/1.chip_sw_alert_test.1215996078
Short name	T249
Test name
Test status
Simulation time	3212493736 ps
CPU time	382.69 seconds
Started	Jul 24 08:04:46 PM PDT 24
Finished	Jul 24 08:11:09 PM PDT 24
Peak memory	610216 kb
Host	smart-f9c4a70c-2f1a-4a03-a0d9-f7b1c17fae55
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215996078 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.1215996078
Directory	/workspace/1.chip_sw_alert_test/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_irq.1998676454
Short name	T374
Test name
Test status
Simulation time	4426965200 ps
CPU time	474.71 seconds
Started	Jul 24 08:01:26 PM PDT 24
Finished	Jul 24 08:09:20 PM PDT 24
Peak memory	609432 kb
Host	smart-5c36500c-8cfb-4a88-ae75-79e319093d25
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998676454 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.1998676454
Directory	/workspace/1.chip_sw_aon_timer_irq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1893635
Short name	T429
Test name
Test status
Simulation time	7079495684 ps
CPU time	512.37 seconds
Started	Jul 24 08:03:41 PM PDT 24
Finished	Jul 24 08:12:14 PM PDT 24
Peak memory	610596 kb
Host	smart-e7ae1a3c-b84d-4caf-8aff-298ef12e82e0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1893635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1893635
Directory	/workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2487969556
Short name	T1169
Test name
Test status
Simulation time	3109038200 ps
CPU time	267.26 seconds
Started	Jul 24 08:08:22 PM PDT 24
Finished	Jul 24 08:12:49 PM PDT 24
Peak memory	609920 kb
Host	smart-e2c5be0f-5508-409a-9d51-e62b88dfd2d7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487969556 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.2487969556
Directory	/workspace/1.chip_sw_aon_timer_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3122226683
Short name	T996
Test name
Test status
Simulation time	7272949160 ps
CPU time	757.86 seconds
Started	Jul 24 08:05:11 PM PDT 24
Finished	Jul 24 08:17:49 PM PDT 24
Peak memory	611016 kb
Host	smart-7dfc5a97-942c-4876-8865-0947e75865f3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3122226683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.3122226683
Directory	/workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1645527284
Short name	T1253
Test name
Test status
Simulation time	4433581946 ps
CPU time	555.16 seconds
Started	Jul 24 08:03:56 PM PDT 24
Finished	Jul 24 08:13:11 PM PDT 24
Peak memory	610724 kb
Host	smart-3ead21d1-d8f7-40cb-a523-4463992d62d7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1645527284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.1645527284
Directory	/workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

---

Test location	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3415111547
Short name	T97
Test name
Test status
Simulation time	7701655842 ps
CPU time	934.25 seconds
Started	Jul 24 08:08:34 PM PDT 24
Finished	Jul 24 08:24:08 PM PDT 24
Peak memory	617736 kb
Host	smart-57c61d9e-329a-4720-b99e-598b724c734d
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415111547 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3415111547
Directory	/workspace/1.chip_sw_ast_clk_outputs/latest

---

Test location	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.440643197
Short name	T117
Test name
Test status
Simulation time	19847128233 ps
CPU time	2750.54 seconds
Started	Jul 24 08:08:20 PM PDT 24
Finished	Jul 24 08:54:11 PM PDT 24
Peak memory	611476 kb
Host	smart-337d8546-506c-4e3a-8249-dbf73df300a0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440643197 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.440643197
Directory	/workspace/1.chip_sw_ast_clk_rst_inputs/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1282658249
Short name	T171
Test name
Test status
Simulation time	10231755416 ps
CPU time	1048.27 seconds
Started	Jul 24 08:07:26 PM PDT 24
Finished	Jul 24 08:24:55 PM PDT 24
Peak memory	625380 kb
Host	smart-e8b9b0d7-7d3c-4e13-9ae1-3785d6449de3
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1282658249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1282658249
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1270632300
Short name	T1190
Test name
Test status
Simulation time	4198214168 ps
CPU time	633.56 seconds
Started	Jul 24 08:08:04 PM PDT 24
Finished	Jul 24 08:18:38 PM PDT 24
Peak memory	613404 kb
Host	smart-b9d14169-347f-4dd1-acfe-e0c664e83908
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270632300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1270632300
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2127589170
Short name	T1102
Test name
Test status
Simulation time	3956666232 ps
CPU time	673.92 seconds
Started	Jul 24 08:09:35 PM PDT 24
Finished	Jul 24 08:20:49 PM PDT 24
Peak memory	613164 kb
Host	smart-3c6af733-40b0-4529-8e4f-d628bc07c20e
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127589170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2127589170
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1160696224
Short name	T436
Test name
Test status
Simulation time	4293088940 ps
CPU time	761.68 seconds
Started	Jul 24 08:06:49 PM PDT 24
Finished	Jul 24 08:19:31 PM PDT 24
Peak memory	613404 kb
Host	smart-48a7205d-cb47-4d63-87a5-0d9cc9767199
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160696224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1160696224
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2347123376
Short name	T122
Test name
Test status
Simulation time	4908428120 ps
CPU time	697.3 seconds
Started	Jul 24 08:06:45 PM PDT 24
Finished	Jul 24 08:18:23 PM PDT 24
Peak memory	613392 kb
Host	smart-45ce07ce-113e-4442-b8bf-77bcbb4233a2
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347123376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2347123376
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3048790159
Short name	T1043
Test name
Test status
Simulation time	4874271810 ps
CPU time	744.88 seconds
Started	Jul 24 08:06:04 PM PDT 24
Finished	Jul 24 08:18:29 PM PDT 24
Peak memory	613192 kb
Host	smart-98fda491-2f96-4afa-ae43-49b993aa0657
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048790159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3048790159
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2764875613
Short name	T1001
Test name
Test status
Simulation time	4700329824 ps
CPU time	706.6 seconds
Started	Jul 24 08:09:46 PM PDT 24
Finished	Jul 24 08:21:33 PM PDT 24
Peak memory	613240 kb
Host	smart-b1a4ac4e-8969-42d1-b1fa-9897bd50ea74
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764875613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2764875613
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1925296442
Short name	T420
Test name
Test status
Simulation time	2916728839 ps
CPU time	297.3 seconds
Started	Jul 24 08:08:05 PM PDT 24
Finished	Jul 24 08:13:02 PM PDT 24
Peak memory	610076 kb
Host	smart-71235ff8-51d7-4cd8-87fe-79474797cb88
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925296442 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.1925296442
Directory	/workspace/1.chip_sw_clkmgr_jitter/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.486369875
Short name	T1015
Test name
Test status
Simulation time	4285521034 ps
CPU time	579.43 seconds
Started	Jul 24 08:06:13 PM PDT 24
Finished	Jul 24 08:15:53 PM PDT 24
Peak memory	610268 kb
Host	smart-91c7819c-80e6-4757-a8da-06880e33e5c5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486369875 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.486369875
Directory	/workspace/1.chip_sw_clkmgr_jitter_frequency/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1865763901
Short name	T980
Test name
Test status
Simulation time	2790171218 ps
CPU time	175.1 seconds
Started	Jul 24 08:07:31 PM PDT 24
Finished	Jul 24 08:10:26 PM PDT 24
Peak memory	610004 kb
Host	smart-c46fa7f4-e6ec-41cd-81d0-86ae0b8a679b
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865763901 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1865763901
Directory	/workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.666323160
Short name	T269
Test name
Test status
Simulation time	4729443202 ps
CPU time	581.75 seconds
Started	Jul 24 08:08:36 PM PDT 24
Finished	Jul 24 08:18:18 PM PDT 24
Peak memory	610956 kb
Host	smart-dc8dafd0-b04e-4cd1-a6e8-b2e9e6a77cab
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666323160 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.666323160
Directory	/workspace/1.chip_sw_clkmgr_off_aes_trans/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2417781350
Short name	T1305
Test name
Test status
Simulation time	3906447180 ps
CPU time	459.88 seconds
Started	Jul 24 08:07:40 PM PDT 24
Finished	Jul 24 08:15:20 PM PDT 24
Peak memory	610652 kb
Host	smart-d12a8922-a5de-4dfb-824f-7f16c8c389ea
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417781350 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.2417781350
Directory	/workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2715118792
Short name	T986
Test name
Test status
Simulation time	4589405718 ps
CPU time	364.63 seconds
Started	Jul 24 08:06:54 PM PDT 24
Finished	Jul 24 08:12:59 PM PDT 24
Peak memory	609876 kb
Host	smart-18cab5f2-b644-4a98-b4bb-844488d4c166
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715118792 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.2715118792
Directory	/workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3568582127
Short name	T1224
Test name
Test status
Simulation time	5254821608 ps
CPU time	524.15 seconds
Started	Jul 24 08:10:33 PM PDT 24
Finished	Jul 24 08:19:17 PM PDT 24
Peak memory	610732 kb
Host	smart-98beaef6-5466-45e4-8c46-b971dfee65c1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568582127 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.3568582127
Directory	/workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.4234368512
Short name	T316
Test name
Test status
Simulation time	12628192616 ps
CPU time	1599.15 seconds
Started	Jul 24 08:10:13 PM PDT 24
Finished	Jul 24 08:36:53 PM PDT 24
Peak memory	610992 kb
Host	smart-f0ce14f9-4594-434e-ab12-08a6604f6bba
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234368512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.4234368512
Directory	/workspace/1.chip_sw_clkmgr_off_peri/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.306509445
Short name	T1028
Test name
Test status
Simulation time	3110999200 ps
CPU time	452.82 seconds
Started	Jul 24 08:12:57 PM PDT 24
Finished	Jul 24 08:20:30 PM PDT 24
Peak memory	610064 kb
Host	smart-e28d02cb-b2be-4c20-aa3d-93efc5adca3c
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306509445 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.306509445
Directory	/workspace/1.chip_sw_clkmgr_reset_frequency/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.488095758
Short name	T1002
Test name
Test status
Simulation time	4089862486 ps
CPU time	583.72 seconds
Started	Jul 24 08:07:04 PM PDT 24
Finished	Jul 24 08:16:48 PM PDT 24
Peak memory	610432 kb
Host	smart-e455ae20-0bb1-49aa-942f-699c9ca05b40
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488095758 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.488095758
Directory	/workspace/1.chip_sw_clkmgr_sleep_frequency/latest

---

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1921706404
Short name	T1356
Test name
Test status
Simulation time	2480140832 ps
CPU time	237.46 seconds
Started	Jul 24 08:08:54 PM PDT 24
Finished	Jul 24 08:12:52 PM PDT 24
Peak memory	609924 kb
Host	smart-7407e07a-246e-466b-a2b0-dc31d51d74ef
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921706404 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1921706404
Directory	/workspace/1.chip_sw_clkmgr_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2564141314
Short name	T1191
Test name
Test status
Simulation time	17415672952 ps
CPU time	3762.5 seconds
Started	Jul 24 08:05:06 PM PDT 24
Finished	Jul 24 09:07:49 PM PDT 24
Peak memory	610820 kb
Host	smart-06688242-1273-4274-94be-7bf00d355ffd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564141314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.2564141314
Directory	/workspace/1.chip_sw_csrng_edn_concurrency/latest

---

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1592566241
Short name	T1363
Test name
Test status
Simulation time	31750441759 ps
CPU time	5049.39 seconds
Started	Jul 24 08:11:05 PM PDT 24
Finished	Jul 24 09:35:15 PM PDT 24
Peak memory	610800 kb
Host	smart-d1b5908f-479a-4a02-bbf7-e50f2b2902b4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1592566241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.1592566241
Directory	/workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1726704992
Short name	T1398
Test name
Test status
Simulation time	5251172386 ps
CPU time	580.69 seconds
Started	Jul 24 08:05:20 PM PDT 24
Finished	Jul 24 08:15:01 PM PDT 24
Peak memory	610312 kb
Host	smart-a27b5a91-c1df-4c9a-b962-fa55447674e9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17267 04992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1726704992
Directory	/workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

---

Test location	/workspace/coverage/default/1.chip_sw_csrng_kat_test.908267689
Short name	T390
Test name
Test status
Simulation time	3345439900 ps
CPU time	247.97 seconds
Started	Jul 24 08:08:42 PM PDT 24
Finished	Jul 24 08:12:51 PM PDT 24
Peak memory	610260 kb
Host	smart-5d832ceb-e2a7-4111-861b-e9be463a5077
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908267689 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.908267689
Directory	/workspace/1.chip_sw_csrng_kat_test/latest

---

Test location	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3150025763
Short name	T1380
Test name
Test status
Simulation time	6637877795 ps
CPU time	858.2 seconds
Started	Jul 24 08:06:11 PM PDT 24
Finished	Jul 24 08:20:30 PM PDT 24
Peak memory	610964 kb
Host	smart-fc584e21-b0f2-43f5-b60d-d43b0d1dcc87
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150025763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.3150025763
Directory	/workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

---

Test location	/workspace/coverage/default/1.chip_sw_csrng_smoketest.2967493139
Short name	T1104
Test name
Test status
Simulation time	3226733976 ps
CPU time	242.17 seconds
Started	Jul 24 08:08:46 PM PDT 24
Finished	Jul 24 08:12:48 PM PDT 24
Peak memory	609896 kb
Host	smart-c293ebf1-0771-40e6-a657-aac1f384b04d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967493139 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.2967493139
Directory	/workspace/1.chip_sw_csrng_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.755310410
Short name	T243
Test name
Test status
Simulation time	5117861290 ps
CPU time	710.21 seconds
Started	Jul 24 08:05:42 PM PDT 24
Finished	Jul 24 08:17:33 PM PDT 24
Peak memory	611276 kb
Host	smart-f32681bf-6c5a-4420-8eca-22d7e05abcee
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=755310410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.755310410
Directory	/workspace/1.chip_sw_data_integrity_escalation/latest

---

Test location	/workspace/coverage/default/1.chip_sw_edn_auto_mode.3497031405
Short name	T1375
Test name
Test status
Simulation time	4677590520 ps
CPU time	1159.09 seconds
Started	Jul 24 08:08:44 PM PDT 24
Finished	Jul 24 08:28:04 PM PDT 24
Peak memory	609320 kb
Host	smart-d81de4ba-c7d8-4e16-9016-08173332f1af
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497031405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.3497031405
Directory	/workspace/1.chip_sw_edn_auto_mode/latest

---

Test location	/workspace/coverage/default/1.chip_sw_edn_boot_mode.851481034
Short name	T126
Test name
Test status
Simulation time	3474128118 ps
CPU time	476.53 seconds
Started	Jul 24 08:05:00 PM PDT 24
Finished	Jul 24 08:12:57 PM PDT 24
Peak memory	609256 kb
Host	smart-9b17e404-ebab-4988-ad1f-885065b6ac10
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851481034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b oot_mode.851481034
Directory	/workspace/1.chip_sw_edn_boot_mode/latest

---

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.855266906
Short name	T1362
Test name
Test status
Simulation time	7373949680 ps
CPU time	1510.81 seconds
Started	Jul 24 08:05:18 PM PDT 24
Finished	Jul 24 08:30:30 PM PDT 24
Peak memory	611068 kb
Host	smart-18acd7a6-7a0c-41d9-afa6-6b8e0e111d57
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=855266906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.855266906
Directory	/workspace/1.chip_sw_edn_entropy_reqs/latest

---

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1052969425
Short name	T453
Test name
Test status
Simulation time	6471897444 ps
CPU time	1236.17 seconds
Started	Jul 24 08:03:51 PM PDT 24
Finished	Jul 24 08:24:28 PM PDT 24
Peak memory	611256 kb
Host	smart-eb3f1905-8494-4fb3-b6fa-200989c7600e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052969425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.1052969425
Directory	/workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

---

Test location	/workspace/coverage/default/1.chip_sw_edn_kat.1595795451
Short name	T1228
Test name
Test status
Simulation time	3125145690 ps
CPU time	646.04 seconds
Started	Jul 24 08:07:07 PM PDT 24
Finished	Jul 24 08:17:54 PM PDT 24
Peak memory	615860 kb
Host	smart-d15b5b43-7da4-49b8-8af2-3bc47f256b60
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595795451 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.1595795451
Directory	/workspace/1.chip_sw_edn_kat/latest

---

Test location	/workspace/coverage/default/1.chip_sw_edn_sw_mode.3586398719
Short name	T1077
Test name
Test status
Simulation time	9801370790 ps
CPU time	2480.35 seconds
Started	Jul 24 08:06:44 PM PDT 24
Finished	Jul 24 08:48:04 PM PDT 24
Peak memory	609828 kb
Host	smart-9b3bc659-409e-41f1-a456-cb46a60a8cdb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586398719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.3586398719
Directory	/workspace/1.chip_sw_edn_sw_mode/latest

---

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2513962839
Short name	T1275
Test name
Test status
Simulation time	3229451392 ps
CPU time	285.2 seconds
Started	Jul 24 08:06:12 PM PDT 24
Finished	Jul 24 08:10:57 PM PDT 24
Peak memory	610300 kb
Host	smart-8bcbcb97-07dd-4e39-b020-1e7d11de2051
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25 13962839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2513962839
Directory	/workspace/1.chip_sw_entropy_src_ast_rng_req/latest

---

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3294142063
Short name	T367
Test name
Test status
Simulation time	5380709248 ps
CPU time	1177.96 seconds
Started	Jul 24 08:06:45 PM PDT 24
Finished	Jul 24 08:26:24 PM PDT 24
Peak memory	609964 kb
Host	smart-d139dc31-4d66-463c-b2ec-504fae251896
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3294142063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3294142063
Directory	/workspace/1.chip_sw_entropy_src_csrng/latest

---

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1776116334
Short name	T981
Test name
Test status
Simulation time	2426070700 ps
CPU time	222.39 seconds
Started	Jul 24 08:05:29 PM PDT 24
Finished	Jul 24 08:09:12 PM PDT 24
Peak memory	609956 kb
Host	smart-0c279a32-f2c9-4c85-8498-d8dd7d382ba8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776116334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1776116334
Directory	/workspace/1.chip_sw_entropy_src_kat_test/latest

---

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3343727596
Short name	T1298
Test name
Test status
Simulation time	3310054116 ps
CPU time	435.26 seconds
Started	Jul 24 08:10:11 PM PDT 24
Finished	Jul 24 08:17:27 PM PDT 24
Peak memory	610000 kb
Host	smart-4c8dd3c6-5ca1-49ad-bce8-26d6343e3ad4
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3343727596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.3343727596
Directory	/workspace/1.chip_sw_entropy_src_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_example_concurrency.295262342
Short name	T1288
Test name
Test status
Simulation time	2954320062 ps
CPU time	264.35 seconds
Started	Jul 24 08:04:07 PM PDT 24
Finished	Jul 24 08:08:32 PM PDT 24
Peak memory	610072 kb
Host	smart-4929fe76-286e-4cf6-9794-791c5d7ff526
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295262342 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.295262342
Directory	/workspace/1.chip_sw_example_concurrency/latest

---

Test location	/workspace/coverage/default/1.chip_sw_example_flash.2072730500
Short name	T110
Test name
Test status
Simulation time	2489779900 ps
CPU time	246.37 seconds
Started	Jul 24 08:01:46 PM PDT 24
Finished	Jul 24 08:05:52 PM PDT 24
Peak memory	609832 kb
Host	smart-53e57054-5453-44ac-9bd2-ffe4493bea2b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072730500 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.2072730500
Directory	/workspace/1.chip_sw_example_flash/latest

---

Test location	/workspace/coverage/default/1.chip_sw_example_manufacturer.3783468093
Short name	T388
Test name
Test status
Simulation time	2396641884 ps
CPU time	253.99 seconds
Started	Jul 24 08:06:02 PM PDT 24
Finished	Jul 24 08:10:16 PM PDT 24
Peak memory	609992 kb
Host	smart-97f71b1d-5891-4d7a-902e-d54aa5566142
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783468093 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.3783468093
Directory	/workspace/1.chip_sw_example_manufacturer/latest

---

Test location	/workspace/coverage/default/1.chip_sw_example_rom.2006340642
Short name	T1100
Test name
Test status
Simulation time	2975436344 ps
CPU time	143.63 seconds
Started	Jul 24 08:00:32 PM PDT 24
Finished	Jul 24 08:02:57 PM PDT 24
Peak memory	610672 kb
Host	smart-7acee9fe-9fc8-48bb-93ec-59bfe9dd0594
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006340642 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.2006340642
Directory	/workspace/1.chip_sw_example_rom/latest

---

Test location	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.15968193
Short name	T1303
Test name
Test status
Simulation time	58272490295 ps
CPU time	10453.8 seconds
Started	Jul 24 08:04:21 PM PDT 24
Finished	Jul 24 10:58:37 PM PDT 24
Peak memory	625320 kb
Host	smart-5d87dcad-cec1-488b-a53d-8d71ec543a81
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=15968193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.15968193
Directory	/workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_crash_alert.2408376646
Short name	T1360
Test name
Test status
Simulation time	6737681850 ps
CPU time	829.48 seconds
Started	Jul 24 08:14:28 PM PDT 24
Finished	Jul 24 08:28:18 PM PDT 24
Peak memory	611524 kb
Host	smart-994e0436-0052-4249-8af8-30687febf7c8
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2408376646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.2408376646
Directory	/workspace/1.chip_sw_flash_crash_alert/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1395376578
Short name	T1137
Test name
Test status
Simulation time	5798357458 ps
CPU time	1017.37 seconds
Started	Jul 24 08:00:52 PM PDT 24
Finished	Jul 24 08:17:50 PM PDT 24
Peak memory	610356 kb
Host	smart-b293eb6d-84fc-4790-9e73-3cc454a7db05
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395376578 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.1395376578
Directory	/workspace/1.chip_sw_flash_ctrl_access/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.332112616
Short name	T1173
Test name
Test status
Simulation time	6584163827 ps
CPU time	1082.79 seconds
Started	Jul 24 08:03:27 PM PDT 24
Finished	Jul 24 08:21:31 PM PDT 24
Peak memory	609968 kb
Host	smart-ee233f9f-8f18-40af-bd15-0d08d5e02a2c
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332112616 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.332112616
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1730897506
Short name	T1338
Test name
Test status
Simulation time	7525981262 ps
CPU time	1206.75 seconds
Started	Jul 24 08:07:30 PM PDT 24
Finished	Jul 24 08:27:37 PM PDT 24
Peak memory	609828 kb
Host	smart-d40ef939-a5f1-48b1-b624-665a53ef9360
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730897506 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1730897506
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3775141645
Short name	T993
Test name
Test status
Simulation time	5445283198 ps
CPU time	1103.27 seconds
Started	Jul 24 08:02:27 PM PDT 24
Finished	Jul 24 08:20:50 PM PDT 24
Peak memory	609908 kb
Host	smart-3b354045-4961-4716-9b79-9bbf81a30d70
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775141645 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3775141645
Directory	/workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1186388266
Short name	T1283
Test name
Test status
Simulation time	3157345640 ps
CPU time	332.75 seconds
Started	Jul 24 08:03:53 PM PDT 24
Finished	Jul 24 08:09:26 PM PDT 24
Peak memory	610516 kb
Host	smart-d96acadf-278b-425b-9063-3764c0484761
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186388266 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1186388266
Directory	/workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3787363233
Short name	T1194
Test name
Test status
Simulation time	5627808522 ps
CPU time	567.12 seconds
Started	Jul 24 08:02:06 PM PDT 24
Finished	Jul 24 08:11:34 PM PDT 24
Peak memory	611152 kb
Host	smart-ed484b60-8601-48ed-b77c-8abcd4b12a6c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37 87363233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.3787363233
Directory	/workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2598588780
Short name	T1080
Test name
Test status
Simulation time	5482912764 ps
CPU time	1308.86 seconds
Started	Jul 24 08:09:19 PM PDT 24
Finished	Jul 24 08:31:09 PM PDT 24
Peak memory	610484 kb
Host	smart-27bd6e42-e091-44a0-9258-309e8ebbd293
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598588780 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.2598588780
Directory	/workspace/1.chip_sw_flash_ctrl_mem_protection/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.83347043
Short name	T354
Test name
Test status
Simulation time	4547217208 ps
CPU time	726.47 seconds
Started	Jul 24 08:02:26 PM PDT 24
Finished	Jul 24 08:14:33 PM PDT 24
Peak memory	609848 kb
Host	smart-3f32e916-0d3d-4c2a-99fc-e8e0199fc282
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83347043 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.83347043
Directory	/workspace/1.chip_sw_flash_ctrl_ops/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.887332129
Short name	T352
Test name
Test status
Simulation time	4267070220 ps
CPU time	710.38 seconds
Started	Jul 24 08:03:29 PM PDT 24
Finished	Jul 24 08:15:20 PM PDT 24
Peak memory	610328 kb
Host	smart-1b9151d7-6b8e-4137-9cce-9877399149e5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=887332129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.887332129
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1492377923
Short name	T364
Test name
Test status
Simulation time	4617382904 ps
CPU time	735.39 seconds
Started	Jul 24 08:10:07 PM PDT 24
Finished	Jul 24 08:22:22 PM PDT 24
Peak memory	610512 kb
Host	smart-95bfb907-2ee0-4687-bea4-ca3cf124caa6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1492377923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1492377923
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2308565596
Short name	T1247
Test name
Test status
Simulation time	3202983872 ps
CPU time	504.45 seconds
Started	Jul 24 08:06:44 PM PDT 24
Finished	Jul 24 08:15:08 PM PDT 24
Peak memory	609828 kb
Host	smart-c01882fb-cec7-445a-8dcb-db99caa9c90a
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308565 596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.2308565596
Directory	/workspace/1.chip_sw_flash_ctrl_write_clear/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3879728469
Short name	T238
Test name
Test status
Simulation time	17536232937 ps
CPU time	2018.41 seconds
Started	Jul 24 08:07:27 PM PDT 24
Finished	Jul 24 08:41:06 PM PDT 24
Peak memory	614120 kb
Host	smart-72392451-f4e4-4b69-a1e1-99b7a7d6d0e7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3879728469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.3879728469
Directory	/workspace/1.chip_sw_flash_init_reduced_freq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2850915051
Short name	T1323
Test name
Test status
Simulation time	2947803992 ps
CPU time	196.46 seconds
Started	Jul 24 08:12:23 PM PDT 24
Finished	Jul 24 08:15:40 PM PDT 24
Peak memory	609792 kb
Host	smart-d10af620-9624-4bc4-86b6-e6c9f9197fea
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2850915051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.2850915051
Directory	/workspace/1.chip_sw_flash_scrambling_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_gpio.342357448
Short name	T29
Test name
Test status
Simulation time	4036755348 ps
CPU time	491.55 seconds
Started	Jul 24 08:01:51 PM PDT 24
Finished	Jul 24 08:10:03 PM PDT 24
Peak memory	610888 kb
Host	smart-f1719572-2bf1-45ed-a04a-5607c30893e8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342357448 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_gpio.342357448
Directory	/workspace/1.chip_sw_gpio/latest

---

Test location	/workspace/coverage/default/1.chip_sw_gpio_smoketest.4194686647
Short name	T1259
Test name
Test status
Simulation time	2809998369 ps
CPU time	281.77 seconds
Started	Jul 24 08:09:38 PM PDT 24
Finished	Jul 24 08:14:21 PM PDT 24
Peak memory	609796 kb
Host	smart-c301f7a3-3241-47dc-9741-667e42692d6f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194686647 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.4194686647
Directory	/workspace/1.chip_sw_gpio_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc.3369909097
Short name	T376
Test name
Test status
Simulation time	3385732636 ps
CPU time	265.86 seconds
Started	Jul 24 08:06:39 PM PDT 24
Finished	Jul 24 08:11:06 PM PDT 24
Peak memory	610304 kb
Host	smart-d2447a6d-dbcd-4ad7-8388-d67a0a78a5c2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369909097 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.3369909097
Directory	/workspace/1.chip_sw_hmac_enc/latest

---

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.337269378
Short name	T1084
Test name
Test status
Simulation time	2412295304 ps
CPU time	279.83 seconds
Started	Jul 24 08:06:13 PM PDT 24
Finished	Jul 24 08:10:54 PM PDT 24
Peak memory	610000 kb
Host	smart-6a2059c3-651f-463f-9f5d-cff8116fd9a7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337269378 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_hmac_enc_idle.337269378
Directory	/workspace/1.chip_sw_hmac_enc_idle/latest

---

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.621088456
Short name	T101
Test name
Test status
Simulation time	3130231636 ps
CPU time	239.99 seconds
Started	Jul 24 08:08:58 PM PDT 24
Finished	Jul 24 08:12:59 PM PDT 24
Peak memory	610112 kb
Host	smart-f0a7130a-6132-4a71-b99e-246aa87d9c2a
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621088456 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.621088456
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_hmac_multistream.856671698
Short name	T86
Test name
Test status
Simulation time	7608461708 ps
CPU time	1945.31 seconds
Started	Jul 24 08:08:40 PM PDT 24
Finished	Jul 24 08:41:06 PM PDT 24
Peak memory	609844 kb
Host	smart-484e82a9-6e34-4e3f-9286-03ae9e2be275
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856671698 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_hmac_multistream.856671698
Directory	/workspace/1.chip_sw_hmac_multistream/latest

---

Test location	/workspace/coverage/default/1.chip_sw_hmac_oneshot.1951601340
Short name	T1163
Test name
Test status
Simulation time	2356836500 ps
CPU time	296.81 seconds
Started	Jul 24 08:08:21 PM PDT 24
Finished	Jul 24 08:13:18 PM PDT 24
Peak memory	610116 kb
Host	smart-13173f49-92c2-4ab6-977c-80d07f6a4321
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951601340 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.1951601340
Directory	/workspace/1.chip_sw_hmac_oneshot/latest

---

Test location	/workspace/coverage/default/1.chip_sw_hmac_smoketest.2849232370
Short name	T1094
Test name
Test status
Simulation time	3624048736 ps
CPU time	518.04 seconds
Started	Jul 24 08:09:19 PM PDT 24
Finished	Jul 24 08:17:57 PM PDT 24
Peak memory	610136 kb
Host	smart-c4d63445-74dd-4483-ba69-14ad76f5f5e0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849232370 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.2849232370
Directory	/workspace/1.chip_sw_hmac_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1581009737
Short name	T347
Test name
Test status
Simulation time	3888827376 ps
CPU time	459.92 seconds
Started	Jul 24 08:00:59 PM PDT 24
Finished	Jul 24 08:08:40 PM PDT 24
Peak memory	610340 kb
Host	smart-a8dc5e6f-97ae-474c-bb24-c91b539e840f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581009737 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.1581009737
Directory	/workspace/1.chip_sw_i2c_device_tx_rx/latest

---

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2634723451
Short name	T370
Test name
Test status
Simulation time	4723048796 ps
CPU time	930.35 seconds
Started	Jul 24 08:03:44 PM PDT 24
Finished	Jul 24 08:19:16 PM PDT 24
Peak memory	609876 kb
Host	smart-13e4755c-e345-4aa0-88f1-0973c6184dcf
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634723451 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.2634723451
Directory	/workspace/1.chip_sw_i2c_host_tx_rx/latest

---

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1854388179
Short name	T399
Test name
Test status
Simulation time	5045942824 ps
CPU time	1063.02 seconds
Started	Jul 24 08:03:59 PM PDT 24
Finished	Jul 24 08:21:43 PM PDT 24
Peak memory	609888 kb
Host	smart-a88032e8-ac02-40e6-bd45-ee3a8d339082
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854388179 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.1854388179
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

---

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3218158742
Short name	T341
Test name
Test status
Simulation time	5210154720 ps
CPU time	825.89 seconds
Started	Jul 24 08:02:24 PM PDT 24
Finished	Jul 24 08:16:10 PM PDT 24
Peak memory	610968 kb
Host	smart-1f5a47e6-372f-4c5d-8196-903cb1e3e1c3
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218158742 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.3218158742
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

---

Test location	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.2301582373
Short name	T1302
Test name
Test status
Simulation time	65207384056 ps
CPU time	12439.6 seconds
Started	Jul 24 08:00:47 PM PDT 24
Finished	Jul 24 11:28:09 PM PDT 24
Peak memory	625256 kb
Host	smart-fbb85ed6-2ef6-4d9a-9d2e-99929a43a316
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2301582373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.2301582373
Directory	/workspace/1.chip_sw_inject_scramble_seed/latest

---

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2925009618
Short name	T1167
Test name
Test status
Simulation time	9605499284 ps
CPU time	1708.51 seconds
Started	Jul 24 08:08:07 PM PDT 24
Finished	Jul 24 08:36:36 PM PDT 24
Peak memory	617956 kb
Host	smart-fbe13e7c-8716-41a5-9c1d-cd5a9396dd68
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925 009618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.2925009618
Directory	/workspace/1.chip_sw_keymgr_key_derivation/latest

---

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.4287934645
Short name	T35
Test name
Test status
Simulation time	9203898004 ps
CPU time	2013.19 seconds
Started	Jul 24 08:07:46 PM PDT 24
Finished	Jul 24 08:41:20 PM PDT 24
Peak memory	617248 kb
Host	smart-d47cf744-5fdc-427e-bbfe-5d9926dd0285
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4287934645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.4287934645
Directory	/workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest

---

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1201436459
Short name	T1021
Test name
Test status
Simulation time	13772357623 ps
CPU time	2009.9 seconds
Started	Jul 24 08:08:19 PM PDT 24
Finished	Jul 24 08:41:49 PM PDT 24
Peak memory	617268 kb
Host	smart-a2d1aa38-e744-4086-9a04-75928e4b7c17
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1201436459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1201436459
Directory	/workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2117970331
Short name	T1032
Test name
Test status
Simulation time	9766979796 ps
CPU time	2050.19 seconds
Started	Jul 24 08:06:06 PM PDT 24
Finished	Jul 24 08:40:17 PM PDT 24
Peak memory	618268 kb
Host	smart-28bb593d-9edc-4f32-b141-bb12f0b1f806
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2117970331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.2117970331
Directory	/workspace/1.chip_sw_keymgr_key_derivation_prod/latest

---

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.67069663
Short name	T228
Test name
Test status
Simulation time	9900760520 ps
CPU time	1857.44 seconds
Started	Jul 24 08:03:38 PM PDT 24
Finished	Jul 24 08:34:35 PM PDT 24
Peak memory	611312 kb
Host	smart-d8eb0f96-5015-48aa-bbbb-6b5d788420f0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670696 63 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.67069663
Directory	/workspace/1.chip_sw_keymgr_sideload_aes/latest

---

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1595822212
Short name	T223
Test name
Test status
Simulation time	6256595952 ps
CPU time	1042.73 seconds
Started	Jul 24 08:06:20 PM PDT 24
Finished	Jul 24 08:23:44 PM PDT 24
Peak memory	611700 kb
Host	smart-0b0b10d1-75f1-46ea-8f23-0b0638103c18
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15958 22212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1595822212
Directory	/workspace/1.chip_sw_keymgr_sideload_kmac/latest

---

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2786759775
Short name	T231
Test name
Test status
Simulation time	15674118686 ps
CPU time	4810.24 seconds
Started	Jul 24 08:05:58 PM PDT 24
Finished	Jul 24 09:26:09 PM PDT 24
Peak memory	611236 kb
Host	smart-352ecb3b-0004-4b0b-b314-46b91e6b6176
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867 59775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2786759775
Directory	/workspace/1.chip_sw_keymgr_sideload_otbn/latest

---

Test location	/workspace/coverage/default/1.chip_sw_kmac_app_rom.3182226004
Short name	T415
Test name
Test status
Simulation time	2751971720 ps
CPU time	263.84 seconds
Started	Jul 24 08:05:02 PM PDT 24
Finished	Jul 24 08:09:26 PM PDT 24
Peak memory	609816 kb
Host	smart-7f1b2eeb-424e-489e-9cff-2213b056e0d9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182226004 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.3182226004
Directory	/workspace/1.chip_sw_kmac_app_rom/latest

---

Test location	/workspace/coverage/default/1.chip_sw_kmac_idle.1084694688
Short name	T1047
Test name
Test status
Simulation time	2682909320 ps
CPU time	282.24 seconds
Started	Jul 24 08:06:37 PM PDT 24
Finished	Jul 24 08:11:20 PM PDT 24
Peak memory	609836 kb
Host	smart-e565f151-f1c5-472a-bccb-bdd6bfebf79c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084694688 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1084694688
Directory	/workspace/1.chip_sw_kmac_idle/latest

---

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3939310841
Short name	T108
Test name
Test status
Simulation time	2473642988 ps
CPU time	270.86 seconds
Started	Jul 24 08:08:29 PM PDT 24
Finished	Jul 24 08:13:00 PM PDT 24
Peak memory	609844 kb
Host	smart-74b0466b-42cf-418b-b2bd-2b5532a04f7e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939310841 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3939310841
Directory	/workspace/1.chip_sw_kmac_mode_cshake/latest

---

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1105056077
Short name	T1312
Test name
Test status
Simulation time	2415226140 ps
CPU time	322.03 seconds
Started	Jul 24 08:05:36 PM PDT 24
Finished	Jul 24 08:10:58 PM PDT 24
Peak memory	609864 kb
Host	smart-9b45bd2d-f0da-49b2-b33d-6ec11c613749
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105056077 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.1105056077
Directory	/workspace/1.chip_sw_kmac_mode_kmac/latest

---

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.93726115
Short name	T1144
Test name
Test status
Simulation time	2541466571 ps
CPU time	370.23 seconds
Started	Jul 24 08:05:34 PM PDT 24
Finished	Jul 24 08:11:45 PM PDT 24
Peak memory	610152 kb
Host	smart-b17d3525-940f-400d-8caf-642543268c43
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93726115 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.93726115
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

---

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1058080967
Short name	T1083
Test name
Test status
Simulation time	4210119749 ps
CPU time	377.73 seconds
Started	Jul 24 08:14:04 PM PDT 24
Finished	Jul 24 08:20:23 PM PDT 24
Peak memory	610180 kb
Host	smart-51a3b70e-779d-4a06-b256-a42ed9c92efb
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10580809 67 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1058080967
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_kmac_smoketest.2694699756
Short name	T1268
Test name
Test status
Simulation time	2789350620 ps
CPU time	409.06 seconds
Started	Jul 24 08:09:30 PM PDT 24
Finished	Jul 24 08:16:19 PM PDT 24
Peak memory	609948 kb
Host	smart-ca379bb0-0883-448e-adad-759d4a1ef6d3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694699756 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.2694699756
Directory	/workspace/1.chip_sw_kmac_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3908930083
Short name	T1390
Test name
Test status
Simulation time	3440652204 ps
CPU time	370.07 seconds
Started	Jul 24 08:02:19 PM PDT 24
Finished	Jul 24 08:08:30 PM PDT 24
Peak memory	609924 kb
Host	smart-af4c7db5-5592-4a3c-ba85-b8b565cfbc66
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908930083 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.3908930083
Directory	/workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

---

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3182578734
Short name	T167
Test name
Test status
Simulation time	5465007440 ps
CPU time	648.78 seconds
Started	Jul 24 08:08:27 PM PDT 24
Finished	Jul 24 08:19:16 PM PDT 24
Peak memory	611372 kb
Host	smart-f1eb6593-a3f6-45eb-b3ff-a07887c56a5d
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3182578734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.3182578734
Directory	/workspace/1.chip_sw_lc_ctrl_program_error/latest

---

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.897693624
Short name	T1261
Test name
Test status
Simulation time	3369094839 ps
CPU time	296.05 seconds
Started	Jul 24 08:02:40 PM PDT 24
Finished	Jul 24 08:07:38 PM PDT 24
Peak memory	622176 kb
Host	smart-5c6c291a-8867-41d5-9039-1088fc3f8ba8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89769362 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.897693624
Directory	/workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest

---

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3181771615
Short name	T1269
Test name
Test status
Simulation time	12305386534 ps
CPU time	1354.12 seconds
Started	Jul 24 08:01:32 PM PDT 24
Finished	Jul 24 08:24:06 PM PDT 24
Peak memory	621676 kb
Host	smart-46a1e54f-d2b3-434d-8bc7-73ef95acdded
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181771615 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.3181771615
Directory	/workspace/1.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1878774325
Short name	T1212
Test name
Test status
Simulation time	2804831363 ps
CPU time	98.52 seconds
Started	Jul 24 08:01:06 PM PDT 24
Finished	Jul 24 08:02:45 PM PDT 24
Peak memory	617032 kb
Host	smart-7613ef8c-c5fd-42ed-bcec-6c8bbf5b3abe
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1878774325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.1878774325
Directory	/workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest

---

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3119740784
Short name	T769
Test name
Test status
Simulation time	2702895911 ps
CPU time	107.54 seconds
Started	Jul 24 08:01:44 PM PDT 24
Finished	Jul 24 08:03:31 PM PDT 24
Peak memory	623536 kb
Host	smart-33f0e085-bca8-4f67-a104-11ea98f6cc67
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119740784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3119740784
Directory	/workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

---

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1194269199
Short name	T1183
Test name
Test status
Simulation time	47329749418 ps
CPU time	5861.08 seconds
Started	Jul 24 08:02:10 PM PDT 24
Finished	Jul 24 09:39:52 PM PDT 24
Peak memory	619768 kb
Host	smart-361eba3c-5a0d-4b03-8cf6-ec7733764a10
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194269199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.1194269199
Directory	/workspace/1.chip_sw_lc_walkthrough_prod/latest

---

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1565679428
Short name	T287
Test name
Test status
Simulation time	9179704576 ps
CPU time	632.94 seconds
Started	Jul 24 08:04:08 PM PDT 24
Finished	Jul 24 08:14:41 PM PDT 24
Peak memory	620508 kb
Host	smart-bb07d470-5262-4d22-8818-876f3a10bee8
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565679428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1565679428
Directory	/workspace/1.chip_sw_lc_walkthrough_prodend/latest

---

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1661167315
Short name	T240
Test name
Test status
Simulation time	46476811260 ps
CPU time	4896.51 seconds
Started	Jul 24 08:04:09 PM PDT 24
Finished	Jul 24 09:25:46 PM PDT 24
Peak memory	620764 kb
Host	smart-1c448386-675e-4ccd-8e5d-65b3b2e7824d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661167315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1661167315
Directory	/workspace/1.chip_sw_lc_walkthrough_rma/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.560573346
Short name	T148
Test name
Test status
Simulation time	17641910450 ps
CPU time	3664.32 seconds
Started	Jul 24 08:04:30 PM PDT 24
Finished	Jul 24 09:05:36 PM PDT 24
Peak memory	610692 kb
Host	smart-a0c9f7d2-d62a-4604-9334-eb9f82ca2376
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=560573346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.560573346
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2781168984
Short name	T1057
Test name
Test status
Simulation time	18639719533 ps
CPU time	3344.27 seconds
Started	Jul 24 08:04:46 PM PDT 24
Finished	Jul 24 09:00:31 PM PDT 24
Peak memory	610512 kb
Host	smart-4514e3ad-9265-4e90-9232-bd0f6ee2ac3d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2781168984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2781168984
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3760759714
Short name	T740
Test name
Test status
Simulation time	24535627604 ps
CPU time	3516.33 seconds
Started	Jul 24 08:08:50 PM PDT 24
Finished	Jul 24 09:07:27 PM PDT 24
Peak memory	610768 kb
Host	smart-18d29c2a-e03d-433e-88f6-eaa58fd91e6c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760759714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3760759714
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1932438097
Short name	T425
Test name
Test status
Simulation time	4205709296 ps
CPU time	493.16 seconds
Started	Jul 24 08:06:28 PM PDT 24
Finished	Jul 24 08:14:41 PM PDT 24
Peak memory	610088 kb
Host	smart-fef66a65-505f-4414-a183-1f20d928c026
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932438097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.1932438097
Directory	/workspace/1.chip_sw_otbn_mem_scramble/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otbn_randomness.4091602452
Short name	T1123
Test name
Test status
Simulation time	5890041728 ps
CPU time	979.35 seconds
Started	Jul 24 08:06:46 PM PDT 24
Finished	Jul 24 08:23:06 PM PDT 24
Peak memory	610756 kb
Host	smart-f2a46448-1855-4cd1-a0a1-c0ed9ba8b120
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4091602452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.4091602452
Directory	/workspace/1.chip_sw_otbn_randomness/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otbn_smoketest.980854392
Short name	T149
Test name
Test status
Simulation time	7142626930 ps
CPU time	1565.86 seconds
Started	Jul 24 08:09:44 PM PDT 24
Finished	Jul 24 08:35:50 PM PDT 24
Peak memory	609980 kb
Host	smart-f9f3d84d-44e5-4fad-bb2a-8188b4251c10
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980854392 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_smoketest.980854392
Directory	/workspace/1.chip_sw_otbn_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.4159878811
Short name	T1061
Test name
Test status
Simulation time	3091538850 ps
CPU time	308.02 seconds
Started	Jul 24 08:02:38 PM PDT 24
Finished	Jul 24 08:07:47 PM PDT 24
Peak memory	609836 kb
Host	smart-3fa05ed7-a88b-4c2d-8d24-ea08a20bd281
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159878811 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.4159878811
Directory	/workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.506942504
Short name	T1295
Test name
Test status
Simulation time	8676446920 ps
CPU time	1402.36 seconds
Started	Jul 24 08:03:22 PM PDT 24
Finished	Jul 24 08:26:46 PM PDT 24
Peak memory	611200 kb
Host	smart-5d97e5a5-bb39-410d-8fd9-cde7fae29bf0
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=506942504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.506942504
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3948342413
Short name	T1170
Test name
Test status
Simulation time	7740662416 ps
CPU time	1102.5 seconds
Started	Jul 24 07:59:46 PM PDT 24
Finished	Jul 24 08:18:09 PM PDT 24
Peak memory	610840 kb
Host	smart-25102c0b-52e7-44fc-adff-c3ad720f46a8
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3948342413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.3948342413
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3058861689
Short name	T1322
Test name
Test status
Simulation time	6787812360 ps
CPU time	1255.25 seconds
Started	Jul 24 08:06:40 PM PDT 24
Finished	Jul 24 08:27:36 PM PDT 24
Peak memory	611176 kb
Host	smart-fb44fdd3-a653-4871-99c9-61d229ae95c3
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3058861689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3058861689
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2782189420
Short name	T2
Test name
Test status
Simulation time	4631199568 ps
CPU time	877.93 seconds
Started	Jul 24 08:03:09 PM PDT 24
Finished	Jul 24 08:17:47 PM PDT 24
Peak memory	609776 kb
Host	smart-63cf6d93-f14a-4e96-b798-c883ff3b20c2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2782189420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2782189420
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

---

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2286185766
Short name	T1313
Test name
Test status
Simulation time	3441932070 ps
CPU time	388.31 seconds
Started	Jul 24 08:08:52 PM PDT 24
Finished	Jul 24 08:15:20 PM PDT 24
Peak memory	609824 kb
Host	smart-3545e195-4c1f-4a09-87f5-f4320acd701c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286185766 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.2286185766
Directory	/workspace/1.chip_sw_otp_ctrl_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_plic_sw_irq.591468168
Short name	T256
Test name
Test status
Simulation time	3566053784 ps
CPU time	330.07 seconds
Started	Jul 24 08:09:18 PM PDT 24
Finished	Jul 24 08:14:48 PM PDT 24
Peak memory	609812 kb
Host	smart-15743bc8-e3ab-42e7-9dc2-c06641b79add
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591468168 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_plic_sw_irq.591468168
Directory	/workspace/1.chip_sw_plic_sw_irq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_power_idle_load.2174968698
Short name	T759
Test name
Test status
Simulation time	3942368514 ps
CPU time	606.51 seconds
Started	Jul 24 08:08:45 PM PDT 24
Finished	Jul 24 08:18:51 PM PDT 24
Peak memory	609904 kb
Host	smart-14532941-d3f2-48e9-b495-f7a64238694b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174968698 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.2174968698
Directory	/workspace/1.chip_sw_power_idle_load/latest

---

Test location	/workspace/coverage/default/1.chip_sw_power_sleep_load.611172686
Short name	T106
Test name
Test status
Simulation time	4335523560 ps
CPU time	402.6 seconds
Started	Jul 24 08:09:12 PM PDT 24
Finished	Jul 24 08:15:55 PM PDT 24
Peak memory	609936 kb
Host	smart-11436806-ec26-4e54-bd04-a3535f5e4a1c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611172686 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.611172686
Directory	/workspace/1.chip_sw_power_sleep_load/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2978598920
Short name	T1111
Test name
Test status
Simulation time	11522807841 ps
CPU time	1539.84 seconds
Started	Jul 24 08:04:01 PM PDT 24
Finished	Jul 24 08:29:41 PM PDT 24
Peak memory	611804 kb
Host	smart-201dafd4-93f4-4d96-a852-3d48539dc141
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978 598920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2978598920
Directory	/workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.771344683
Short name	T1034
Test name
Test status
Simulation time	27151214720 ps
CPU time	2589.54 seconds
Started	Jul 24 08:06:56 PM PDT 24
Finished	Jul 24 08:50:06 PM PDT 24
Peak memory	611284 kb
Host	smart-6717a48b-fdc2-4087-8aa4-972e908a61c9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771 344683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.771344683
Directory	/workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3835587317
Short name	T1347
Test name
Test status
Simulation time	15795284432 ps
CPU time	1973.56 seconds
Started	Jul 24 08:03:52 PM PDT 24
Finished	Jul 24 08:36:46 PM PDT 24
Peak memory	611808 kb
Host	smart-2f63ac41-f4f6-47d9-9100-7e1ac56c59b6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3835587317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3835587317
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2786644205
Short name	T432
Test name
Test status
Simulation time	22698123808 ps
CPU time	1919.67 seconds
Started	Jul 24 08:07:27 PM PDT 24
Finished	Jul 24 08:39:27 PM PDT 24
Peak memory	611100 kb
Host	smart-f4e0c070-bab6-46bc-951e-cac17c7b2344
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2786644205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2786644205
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.4213434430
Short name	T1387
Test name
Test status
Simulation time	7587782934 ps
CPU time	660.25 seconds
Started	Jul 24 08:03:15 PM PDT 24
Finished	Jul 24 08:14:16 PM PDT 24
Peak memory	611316 kb
Host	smart-10a454fb-49d7-425b-9502-9517485fa639
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213434430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.4213434430
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2949136426
Short name	T1350
Test name
Test status
Simulation time	7197992696 ps
CPU time	595.23 seconds
Started	Jul 24 08:06:23 PM PDT 24
Finished	Jul 24 08:16:19 PM PDT 24
Peak memory	617820 kb
Host	smart-2553b6e3-4bee-407b-9875-4aa98e75c87c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2949136426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2949136426
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.562496233
Short name	T286
Test name
Test status
Simulation time	7616690106 ps
CPU time	519.47 seconds
Started	Jul 24 08:03:29 PM PDT 24
Finished	Jul 24 08:12:09 PM PDT 24
Peak memory	611204 kb
Host	smart-1c4655cc-3730-4d8d-aca7-c03fec6abb13
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562496233 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.562496233
Directory	/workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.805222648
Short name	T1129
Test name
Test status
Simulation time	3483002720 ps
CPU time	394.91 seconds
Started	Jul 24 08:02:17 PM PDT 24
Finished	Jul 24 08:08:53 PM PDT 24
Peak memory	616776 kb
Host	smart-b98d2eee-f6a4-41d2-85a0-b544e803b6f0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=805222648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.805222648
Directory	/workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2117478079
Short name	T1223
Test name
Test status
Simulation time	10752978241 ps
CPU time	1167.32 seconds
Started	Jul 24 08:04:00 PM PDT 24
Finished	Jul 24 08:23:27 PM PDT 24
Peak memory	611740 kb
Host	smart-c7040602-1afc-4b7d-97a7-a5eebad3e17d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117478079 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2117478079
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3365878452
Short name	T73
Test name
Test status
Simulation time	7945920784 ps
CPU time	520.72 seconds
Started	Jul 24 08:07:34 PM PDT 24
Finished	Jul 24 08:16:15 PM PDT 24
Peak memory	610956 kb
Host	smart-ae46fd2a-a4f9-4951-96b2-ceb4bc5bdf00
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365878452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3365878452
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3628163264
Short name	T424
Test name
Test status
Simulation time	4565949350 ps
CPU time	457.2 seconds
Started	Jul 24 08:03:45 PM PDT 24
Finished	Jul 24 08:11:23 PM PDT 24
Peak memory	610992 kb
Host	smart-51f33fe1-0a29-4eda-bf34-b469f530e9ae
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628163264 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.3628163264
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2549766755
Short name	T1263
Test name
Test status
Simulation time	26305132239 ps
CPU time	1884.56 seconds
Started	Jul 24 08:04:03 PM PDT 24
Finished	Jul 24 08:35:27 PM PDT 24
Peak memory	611524 kb
Host	smart-1604ad14-9cc9-4b06-a19c-29bfec86d17e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2549766755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2549766755
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.102696909
Short name	T103
Test name
Test status
Simulation time	19358161896 ps
CPU time	1250.52 seconds
Started	Jul 24 08:08:22 PM PDT 24
Finished	Jul 24 08:29:13 PM PDT 24
Peak memory	611228 kb
Host	smart-936a74af-f4cc-409f-9e9e-18751709ba92
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=102696909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.102696909
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1513586837
Short name	T1431
Test name
Test status
Simulation time	32648066231 ps
CPU time	3763.94 seconds
Started	Jul 24 08:04:41 PM PDT 24
Finished	Jul 24 09:07:25 PM PDT 24
Peak memory	612716 kb
Host	smart-b7345348-7010-4d34-9af5-4f510f161b08
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513586837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1513586837
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2875975985
Short name	T378
Test name
Test status
Simulation time	6170556884 ps
CPU time	434.91 seconds
Started	Jul 24 08:08:36 PM PDT 24
Finished	Jul 24 08:15:51 PM PDT 24
Peak memory	611212 kb
Host	smart-7fde5be1-57ec-4a87-9c7b-812a44f554df
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2875975985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2875975985
Directory	/workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2178348686
Short name	T785
Test name
Test status
Simulation time	2464878856 ps
CPU time	229.61 seconds
Started	Jul 24 08:03:57 PM PDT 24
Finished	Jul 24 08:07:47 PM PDT 24
Peak memory	610172 kb
Host	smart-25d22ad7-d5e0-4b02-90b0-d691971ad883
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178348686 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.2178348686
Directory	/workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2452127733
Short name	T430
Test name
Test status
Simulation time	6433183536 ps
CPU time	585.89 seconds
Started	Jul 24 08:02:54 PM PDT 24
Finished	Jul 24 08:12:40 PM PDT 24
Peak memory	618176 kb
Host	smart-ef7e7769-6acd-4de8-ab0e-327909d84d0d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2452127733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.2452127733
Directory	/workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3140610111
Short name	T131
Test name
Test status
Simulation time	5338770224 ps
CPU time	479.75 seconds
Started	Jul 24 08:07:37 PM PDT 24
Finished	Jul 24 08:15:37 PM PDT 24
Peak memory	609856 kb
Host	smart-0b70953c-d23c-4c60-95e7-d1bfbf90c4fa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31406101 11 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3140610111
Directory	/workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2955772301
Short name	T998
Test name
Test status
Simulation time	4988754076 ps
CPU time	455.45 seconds
Started	Jul 24 08:08:11 PM PDT 24
Finished	Jul 24 08:15:46 PM PDT 24
Peak memory	610876 kb
Host	smart-d4addceb-58ea-45b8-83f2-7595a5573829
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2955772301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2955772301
Directory	/workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2137238122
Short name	T1245
Test name
Test status
Simulation time	5819159960 ps
CPU time	427.86 seconds
Started	Jul 24 08:12:23 PM PDT 24
Finished	Jul 24 08:19:31 PM PDT 24
Peak memory	610916 kb
Host	smart-61fb7fcc-b8ce-47ef-a6ac-907837896a00
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137238122 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.2137238122
Directory	/workspace/1.chip_sw_pwrmgr_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.459735170
Short name	T1392
Test name
Test status
Simulation time	7759907518 ps
CPU time	1429.33 seconds
Started	Jul 24 08:03:08 PM PDT 24
Finished	Jul 24 08:26:58 PM PDT 24
Peak memory	611128 kb
Host	smart-5fbd6c4d-b0d3-4f52-bc3a-57970dbb513f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459735170 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.459735170
Directory	/workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2036475057
Short name	T1093
Test name
Test status
Simulation time	5494970664 ps
CPU time	569.38 seconds
Started	Jul 24 08:03:50 PM PDT 24
Finished	Jul 24 08:13:20 PM PDT 24
Peak memory	609996 kb
Host	smart-011c008a-cd28-406f-b643-adbcf5efc2f3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036475057 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2036475057
Directory	/workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1820419357
Short name	T1359
Test name
Test status
Simulation time	5739121604 ps
CPU time	389.29 seconds
Started	Jul 24 08:09:32 PM PDT 24
Finished	Jul 24 08:16:01 PM PDT 24
Peak memory	609936 kb
Host	smart-b25bddba-8582-4d68-b855-739a22a1e5ba
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820419357 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.1820419357
Directory	/workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.4012051208
Short name	T1147
Test name
Test status
Simulation time	5048805056 ps
CPU time	677.72 seconds
Started	Jul 24 08:04:51 PM PDT 24
Finished	Jul 24 08:16:09 PM PDT 24
Peak memory	610852 kb
Host	smart-f33752ed-e3ff-482b-a4a3-447c35f0efc0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401 2051208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.4012051208
Directory	/workspace/1.chip_sw_pwrmgr_wdog_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3542059706
Short name	T414
Test name
Test status
Simulation time	9646765727 ps
CPU time	439.7 seconds
Started	Jul 24 08:05:19 PM PDT 24
Finished	Jul 24 08:12:39 PM PDT 24
Peak memory	625288 kb
Host	smart-83a48a41-f735-4125-af6e-c99294ac8d30
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542059706 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.3542059706
Directory	/workspace/1.chip_sw_rom_ctrl_integrity_check/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3227031107
Short name	T334
Test name
Test status
Simulation time	10622450848 ps
CPU time	1782.54 seconds
Started	Jul 24 08:02:18 PM PDT 24
Finished	Jul 24 08:32:01 PM PDT 24
Peak memory	611344 kb
Host	smart-89fc4f89-89cc-41f8-a2d6-2b671ba56e0b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3227031107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3227031107
Directory	/workspace/1.chip_sw_rstmgr_alert_info/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3100898574
Short name	T244
Test name
Test status
Simulation time	6534525076 ps
CPU time	654.81 seconds
Started	Jul 24 08:02:16 PM PDT 24
Finished	Jul 24 08:13:11 PM PDT 24
Peak memory	610004 kb
Host	smart-65323389-3cd8-465b-bccf-07704a64d971
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100898574 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.3100898574
Directory	/workspace/1.chip_sw_rstmgr_cpu_info/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1036228355
Short name	T834
Test name
Test status
Simulation time	5651021744 ps
CPU time	691.28 seconds
Started	Jul 24 08:05:30 PM PDT 24
Finished	Jul 24 08:17:02 PM PDT 24
Peak memory	641984 kb
Host	smart-8af5b179-c270-4b14-81e4-5adddc2917e5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1036228355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1036228355
Directory	/workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1442864261
Short name	T283
Test name
Test status
Simulation time	2586094856 ps
CPU time	205.14 seconds
Started	Jul 24 08:09:24 PM PDT 24
Finished	Jul 24 08:12:49 PM PDT 24
Peak memory	609796 kb
Host	smart-9cf7f361-21d5-4b81-891f-a593bf0110a2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442864261 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.1442864261
Directory	/workspace/1.chip_sw_rstmgr_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3239676277
Short name	T300
Test name
Test status
Simulation time	4999314432 ps
CPU time	570.4 seconds
Started	Jul 24 08:04:24 PM PDT 24
Finished	Jul 24 08:13:54 PM PDT 24
Peak memory	610568 kb
Host	smart-4ed24544-9af1-4f70-9b1f-eaaade43491f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239676277 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.3239676277
Directory	/workspace/1.chip_sw_rstmgr_sw_req/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2588516552
Short name	T408
Test name
Test status
Simulation time	2966519264 ps
CPU time	251.28 seconds
Started	Jul 24 08:03:43 PM PDT 24
Finished	Jul 24 08:07:55 PM PDT 24
Peak memory	609920 kb
Host	smart-53700263-f69d-498d-8f4f-2e4ae7bc9a19
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588516552 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.2588516552
Directory	/workspace/1.chip_sw_rstmgr_sw_rst/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1564463346
Short name	T304
Test name
Test status
Simulation time	3605242150 ps
CPU time	352.43 seconds
Started	Jul 24 08:13:25 PM PDT 24
Finished	Jul 24 08:19:19 PM PDT 24
Peak memory	609828 kb
Host	smart-ccb68e3e-d48c-4471-9a74-12fc3c18b44d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1564463346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1564463346
Directory	/workspace/1.chip_sw_rv_core_ibex_address_translation/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.890208779
Short name	T303
Test name
Test status
Simulation time	2384666644 ps
CPU time	188.57 seconds
Started	Jul 24 08:07:12 PM PDT 24
Finished	Jul 24 08:10:21 PM PDT 24
Peak memory	609844 kb
Host	smart-bd5d7315-8524-4e6d-acb8-3cb648259140
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890208779 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.890208779
Directory	/workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1383482812
Short name	T541
Test name
Test status
Simulation time	4642872690 ps
CPU time	870.16 seconds
Started	Jul 24 08:06:42 PM PDT 24
Finished	Jul 24 08:21:13 PM PDT 24
Peak memory	609956 kb
Host	smart-f7dca944-f160-4538-964f-2cf9de365310
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13834 82812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1383482812
Directory	/workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.998505603
Short name	T1071
Test name
Test status
Simulation time	5600333308 ps
CPU time	1092.78 seconds
Started	Jul 24 08:04:16 PM PDT 24
Finished	Jul 24 08:22:30 PM PDT 24
Peak memory	610432 kb
Host	smart-9942daf3-17c4-406c-8253-ce2dd001049a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=998505603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.998505603
Directory	/workspace/1.chip_sw_rv_core_ibex_rnd/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.327606566
Short name	T1030
Test name
Test status
Simulation time	6325629932 ps
CPU time	466.85 seconds
Started	Jul 24 08:07:15 PM PDT 24
Finished	Jul 24 08:15:02 PM PDT 24
Peak memory	624260 kb
Host	smart-213b5255-e14d-4800-b4e0-74d11dad13ed
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327606566 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.327606566
Directory	/workspace/1.chip_sw_rv_dm_access_after_wakeup/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.956956873
Short name	T311
Test name
Test status
Simulation time	4802707400 ps
CPU time	485.49 seconds
Started	Jul 24 08:07:56 PM PDT 24
Finished	Jul 24 08:16:01 PM PDT 24
Peak memory	619768 kb
Host	smart-217b5307-3ba5-44fe-988c-61b65eb57bee
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956956 873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.956956873
Directory	/workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.137222715
Short name	T1088
Test name
Test status
Simulation time	3304828998 ps
CPU time	231.22 seconds
Started	Jul 24 08:09:17 PM PDT 24
Finished	Jul 24 08:13:08 PM PDT 24
Peak memory	609836 kb
Host	smart-e1cafc94-ec35-4452-8e2b-c0e22ea22c73
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137222715 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rv_plic_smoketest.137222715
Directory	/workspace/1.chip_sw_rv_plic_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_irq.9229719
Short name	T258
Test name
Test status
Simulation time	2753993320 ps
CPU time	301.97 seconds
Started	Jul 24 08:01:14 PM PDT 24
Finished	Jul 24 08:06:16 PM PDT 24
Peak memory	609772 kb
Host	smart-bb2c377d-5159-4876-b8ba-d13230432297
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9229719 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_rv_timer_irq.9229719
Directory	/workspace/1.chip_sw_rv_timer_irq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2269886677
Short name	T1408
Test name
Test status
Simulation time	3798771960 ps
CPU time	327.67 seconds
Started	Jul 24 08:10:58 PM PDT 24
Finished	Jul 24 08:16:26 PM PDT 24
Peak memory	609840 kb
Host	smart-bb79de4d-2760-4e47-8c9f-1de1d7b276af
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269886677 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2269886677
Directory	/workspace/1.chip_sw_rv_timer_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.94761004
Short name	T140
Test name
Test status
Simulation time	3125317567 ps
CPU time	286.06 seconds
Started	Jul 24 08:05:18 PM PDT 24
Finished	Jul 24 08:10:04 PM PDT 24
Peak memory	610136 kb
Host	smart-b1eae12e-7a42-4d93-97b9-a1a7c26dafaf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9476100 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.94761004
Directory	/workspace/1.chip_sw_sensor_ctrl_status/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.791288748
Short name	T54
Test name
Test status
Simulation time	3796653658 ps
CPU time	214.62 seconds
Started	Jul 24 08:03:05 PM PDT 24
Finished	Jul 24 08:06:40 PM PDT 24
Peak memory	609804 kb
Host	smart-9b9811be-dd07-449e-9207-e9bdc8589ae0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791288748 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.791288748
Directory	/workspace/1.chip_sw_sleep_pin_retention/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3839878399
Short name	T102
Test name
Test status
Simulation time	3103083656 ps
CPU time	242.84 seconds
Started	Jul 24 08:06:19 PM PDT 24
Finished	Jul 24 08:10:22 PM PDT 24
Peak memory	609924 kb
Host	smart-b465dc61-c629-4fac-bec7-136d48d2ec6e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839878399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.3839878399
Directory	/workspace/1.chip_sw_sleep_pin_wake/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1276755930
Short name	T1020
Test name
Test status
Simulation time	8050744990 ps
CPU time	1145.71 seconds
Started	Jul 24 07:59:25 PM PDT 24
Finished	Jul 24 08:18:31 PM PDT 24
Peak memory	611224 kb
Host	smart-a8ba8ecd-718a-4c1e-8535-484805374593
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276755930 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1276755930
Directory	/workspace/1.chip_sw_sleep_pwm_pulses/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4247782156
Short name	T1059
Test name
Test status
Simulation time	8049456438 ps
CPU time	844.95 seconds
Started	Jul 24 08:07:16 PM PDT 24
Finished	Jul 24 08:21:21 PM PDT 24
Peak memory	610924 kb
Host	smart-59201525-6018-4897-91c9-287fbf62050a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247782156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.4247782156
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1902554448
Short name	T1203
Test name
Test status
Simulation time	7766973868 ps
CPU time	942.28 seconds
Started	Jul 24 08:06:37 PM PDT 24
Finished	Jul 24 08:22:20 PM PDT 24
Peak memory	611040 kb
Host	smart-eab7fdd4-5426-402b-a0c1-9168b962e1ed
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902554448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1902554448
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

---

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3112744999
Short name	T195
Test name
Test status
Simulation time	7232157379 ps
CPU time	850.71 seconds
Started	Jul 24 08:01:15 PM PDT 24
Finished	Jul 24 08:15:27 PM PDT 24
Peak memory	625532 kb
Host	smart-2bb39e57-a187-4427-9956-cb5020b2ece7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112744999 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3112744999
Directory	/workspace/1.chip_sw_spi_device_pass_through/latest

---

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.748320548
Short name	T194
Test name
Test status
Simulation time	4637941700 ps
CPU time	560.03 seconds
Started	Jul 24 08:05:18 PM PDT 24
Finished	Jul 24 08:14:38 PM PDT 24
Peak memory	625436 kb
Host	smart-a54113a9-093e-4d25-8d3c-089e03ff3538
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748320548 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.748320548
Directory	/workspace/1.chip_sw_spi_device_pass_through_collision/latest

---

Test location	/workspace/coverage/default/1.chip_sw_spi_device_tpm.3625130703
Short name	T42
Test name
Test status
Simulation time	3366585058 ps
CPU time	436.9 seconds
Started	Jul 24 08:03:33 PM PDT 24
Finished	Jul 24 08:10:50 PM PDT 24
Peak memory	619900 kb
Host	smart-e143f756-bdec-4c91-bf4f-a2269750a68e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625130703 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.3625130703
Directory	/workspace/1.chip_sw_spi_device_tpm/latest

---

Test location	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1978815016
Short name	T36
Test name
Test status
Simulation time	3227940472 ps
CPU time	330.63 seconds
Started	Jul 24 08:02:19 PM PDT 24
Finished	Jul 24 08:07:51 PM PDT 24
Peak memory	610688 kb
Host	smart-e2f744cc-bbd4-4a1a-b640-ddb83b94ec54
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978815016 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.1978815016
Directory	/workspace/1.chip_sw_spi_host_tx_rx/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3199154217
Short name	T309
Test name
Test status
Simulation time	9202594082 ps
CPU time	995.78 seconds
Started	Jul 24 08:04:46 PM PDT 24
Finished	Jul 24 08:21:22 PM PDT 24
Peak memory	610904 kb
Host	smart-93f9a03f-0a86-47a8-bfa3-20b0b3a7cae7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199154217 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3199154217
Directory	/workspace/1.chip_sw_sram_ctrl_execution_main/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1517352386
Short name	T178
Test name
Test status
Simulation time	5297709560 ps
CPU time	620.71 seconds
Started	Jul 24 08:04:51 PM PDT 24
Finished	Jul 24 08:15:12 PM PDT 24
Peak memory	611272 kb
Host	smart-4cbcd8d9-a51e-46fa-9189-06f629c76fa5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517352386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.1517352386
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1093762669
Short name	T290
Test name
Test status
Simulation time	5022389405 ps
CPU time	593.6 seconds
Started	Jul 24 08:05:41 PM PDT 24
Finished	Jul 24 08:15:35 PM PDT 24
Peak memory	611400 kb
Host	smart-2ffdc95d-4894-4878-b5cc-9723b11365fb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093762669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1093762669
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3989435644
Short name	T994
Test name
Test status
Simulation time	2173573480 ps
CPU time	257.95 seconds
Started	Jul 24 08:12:53 PM PDT 24
Finished	Jul 24 08:17:11 PM PDT 24
Peak memory	610272 kb
Host	smart-0aa31981-38e0-4325-bc76-7e3546d67243
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989435644 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.3989435644
Directory	/workspace/1.chip_sw_sram_ctrl_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.948254836
Short name	T217
Test name
Test status
Simulation time	20210695399 ps
CPU time	3744.02 seconds
Started	Jul 24 08:03:04 PM PDT 24
Finished	Jul 24 09:05:30 PM PDT 24
Peak memory	610004 kb
Host	smart-7703fbd6-e5ac-44fb-8b78-55a729f79ef0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948254836 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.948254836
Directory	/workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.734499635
Short name	T205
Test name
Test status
Simulation time	4642342713 ps
CPU time	625.34 seconds
Started	Jul 24 08:03:43 PM PDT 24
Finished	Jul 24 08:14:11 PM PDT 24
Peak memory	614304 kb
Host	smart-0b4e2b25-da53-4ebf-b22d-d04c3435a5b7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734499635 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.734499635
Directory	/workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3164371053
Short name	T204
Test name
Test status
Simulation time	2663816858 ps
CPU time	286.67 seconds
Started	Jul 24 08:06:00 PM PDT 24
Finished	Jul 24 08:10:48 PM PDT 24
Peak memory	613424 kb
Host	smart-4c5c6d3e-9613-46c7-8d09-6964f65ff2fd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164371053 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3164371053
Directory	/workspace/1.chip_sw_sysrst_ctrl_inputs/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.929279908
Short name	T1368
Test name
Test status
Simulation time	3791717199 ps
CPU time	343.19 seconds
Started	Jul 24 08:04:00 PM PDT 24
Finished	Jul 24 08:09:43 PM PDT 24
Peak memory	609804 kb
Host	smart-e11e082c-5a19-499e-9b7c-8813708458bc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929279908 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.929279908
Directory	/workspace/1.chip_sw_sysrst_ctrl_outputs/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4188584692
Short name	T206
Test name
Test status
Simulation time	24660603120 ps
CPU time	2017.64 seconds
Started	Jul 24 08:06:35 PM PDT 24
Finished	Jul 24 08:40:14 PM PDT 24
Peak memory	614584 kb
Host	smart-8fba7b3b-0884-4b62-9554-293fe5156887
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41885846 92 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.4188584692
Directory	/workspace/1.chip_sw_sysrst_ctrl_reset/latest

---

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2268559080
Short name	T39
Test name
Test status
Simulation time	5723091100 ps
CPU time	450.33 seconds
Started	Jul 24 08:02:15 PM PDT 24
Finished	Jul 24 08:09:46 PM PDT 24
Peak memory	611272 kb
Host	smart-9c95ffab-e905-41d1-a251-d51a7dcae3bf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268559080 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2268559080
Directory	/workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

---

Test location	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2253127073
Short name	T1023
Test name
Test status
Simulation time	3079876524 ps
CPU time	503.69 seconds
Started	Jul 24 08:01:57 PM PDT 24
Finished	Jul 24 08:10:21 PM PDT 24
Peak memory	619192 kb
Host	smart-020f3ba7-582b-4b31-9739-e36c5baf50ed
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2253127073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.2253127073
Directory	/workspace/1.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/1.chip_sw_uart_smoketest.213656859
Short name	T1285
Test name
Test status
Simulation time	2604652060 ps
CPU time	233.48 seconds
Started	Jul 24 08:08:57 PM PDT 24
Finished	Jul 24 08:12:51 PM PDT 24
Peak memory	616260 kb
Host	smart-f096c654-7921-410d-8293-bba8b66e1777
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213656859 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.213656859
Directory	/workspace/1.chip_sw_uart_smoketest/latest

---

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx.2548170457
Short name	T356
Test name
Test status
Simulation time	4791529566 ps
CPU time	708.63 seconds
Started	Jul 24 08:05:58 PM PDT 24
Finished	Jul 24 08:17:47 PM PDT 24
Peak memory	625200 kb
Host	smart-b70e7f1f-9e91-4160-9c8c-a054d4fc09a7
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548170457 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.2548170457
Directory	/workspace/1.chip_sw_uart_tx_rx/latest

---

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3630865857
Short name	T1235
Test name
Test status
Simulation time	3850935450 ps
CPU time	597.07 seconds
Started	Jul 24 08:05:25 PM PDT 24
Finished	Jul 24 08:15:23 PM PDT 24
Peak memory	622664 kb
Host	smart-c0c2cee7-7638-4f52-b7f1-216fa3d804f2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630865857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.3630865857
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest

---

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1695114433
Short name	T1214
Test name
Test status
Simulation time	13353511074 ps
CPU time	2128.07 seconds
Started	Jul 24 08:02:06 PM PDT 24
Finished	Jul 24 08:37:35 PM PDT 24
Peak memory	618872 kb
Host	smart-fe49208a-7cda-4eab-9260-0b7d377e037d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695114433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1695114433
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

---

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3771707923
Short name	T199
Test name
Test status
Simulation time	78582998860 ps
CPU time	14001.1 seconds
Started	Jul 24 08:05:32 PM PDT 24
Finished	Jul 24 11:58:55 PM PDT 24
Peak memory	634428 kb
Host	smart-202548ce-60d9-414b-9163-8c003c97d5af
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3771707923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.3771707923
Directory	/workspace/1.chip_sw_uart_tx_rx_bootstrap/latest

---

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.4127005156
Short name	T214
Test name
Test status
Simulation time	4015425080 ps
CPU time	816.11 seconds
Started	Jul 24 08:02:18 PM PDT 24
Finished	Jul 24 08:15:55 PM PDT 24
Peak memory	622972 kb
Host	smart-56450734-355b-4618-94f8-955b1856a67e
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127005156 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.4127005156
Directory	/workspace/1.chip_sw_uart_tx_rx_idx1/latest

---

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1749253729
Short name	T1016
Test name
Test status
Simulation time	4325759672 ps
CPU time	593.54 seconds
Started	Jul 24 08:00:41 PM PDT 24
Finished	Jul 24 08:10:35 PM PDT 24
Peak memory	625184 kb
Host	smart-b07f7fe3-390a-4591-8f6f-40ff95bf686e
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749253729 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1749253729
Directory	/workspace/1.chip_sw_uart_tx_rx_idx2/latest

---

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.402498613
Short name	T1139
Test name
Test status
Simulation time	3939633204 ps
CPU time	575.72 seconds
Started	Jul 24 08:02:33 PM PDT 24
Finished	Jul 24 08:12:10 PM PDT 24
Peak memory	623076 kb
Host	smart-996b68a0-9c52-4240-b85d-6c6dd3b1d1cf
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402498613 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.402498613
Directory	/workspace/1.chip_sw_uart_tx_rx_idx3/latest

---

Test location	/workspace/coverage/default/1.chip_tap_straps_dev.1912668132
Short name	T1189
Test name
Test status
Simulation time	2613248492 ps
CPU time	221.22 seconds
Started	Jul 24 08:07:17 PM PDT 24
Finished	Jul 24 08:10:58 PM PDT 24
Peak memory	622404 kb
Host	smart-41f308d8-2d70-4db5-bf6e-86a996a9493c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1912668132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.1912668132
Directory	/workspace/1.chip_tap_straps_dev/latest

---

Test location	/workspace/coverage/default/1.chip_tap_straps_prod.3788313316
Short name	T1175
Test name
Test status
Simulation time	2906157582 ps
CPU time	159.9 seconds
Started	Jul 24 08:13:02 PM PDT 24
Finished	Jul 24 08:15:43 PM PDT 24
Peak memory	620604 kb
Host	smart-281e9c6e-c937-403e-b89e-491c1bec85bd
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788313316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.3788313316
Directory	/workspace/1.chip_tap_straps_prod/latest

---

Test location	/workspace/coverage/default/1.chip_tap_straps_rma.1915888816
Short name	T70
Test name
Test status
Simulation time	4274887300 ps
CPU time	388.82 seconds
Started	Jul 24 08:11:18 PM PDT 24
Finished	Jul 24 08:17:48 PM PDT 24
Peak memory	621512 kb
Host	smart-80112daa-2664-4fd7-9da6-d0a8e5bde3aa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915888816 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1915888816
Directory	/workspace/1.chip_tap_straps_rma/latest

---

Test location	/workspace/coverage/default/1.chip_tap_straps_testunlock0.3881486190
Short name	T1351
Test name
Test status
Simulation time	5570366442 ps
CPU time	480.93 seconds
Started	Jul 24 08:11:28 PM PDT 24
Finished	Jul 24 08:19:30 PM PDT 24
Peak memory	623932 kb
Host	smart-4cead262-2d07-4b17-8b4c-edf7ae7d8bc1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881486190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.3881486190
Directory	/workspace/1.chip_tap_straps_testunlock0/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_dev.3484793749
Short name	T391
Test name
Test status
Simulation time	15074481339 ps
CPU time	4205.93 seconds
Started	Jul 24 08:13:17 PM PDT 24
Finished	Jul 24 09:23:24 PM PDT 24
Peak memory	610912 kb
Host	smart-84ddafdf-86e2-4a3b-8919-b7fc71a56653
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484793749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.3484793749
Directory	/workspace/1.rom_e2e_asm_init_dev/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_prod.1717250896
Short name	T1172
Test name
Test status
Simulation time	15355995731 ps
CPU time	3463.46 seconds
Started	Jul 24 08:12:59 PM PDT 24
Finished	Jul 24 09:10:43 PM PDT 24
Peak memory	610856 kb
Host	smart-b546facb-ec58-4899-839b-73a8d38ba57e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717250896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.1717250896
Directory	/workspace/1.rom_e2e_asm_init_prod/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3583638397
Short name	T1014
Test name
Test status
Simulation time	15798539883 ps
CPU time	3714.15 seconds
Started	Jul 24 08:13:04 PM PDT 24
Finished	Jul 24 09:14:59 PM PDT 24
Peak memory	610828 kb
Host	smart-9b22e1b6-47d3-4e32-aa4c-496b7c478476
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583638397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.3583638397
Directory	/workspace/1.rom_e2e_asm_init_prod_end/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_rma.458558273
Short name	T1343
Test name
Test status
Simulation time	14496781060 ps
CPU time	3256.89 seconds
Started	Jul 24 08:19:38 PM PDT 24
Finished	Jul 24 09:13:55 PM PDT 24
Peak memory	610864 kb
Host	smart-2f14804f-2b8d-44a1-922c-ae4ce0738b27
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458558273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_rma.458558273
Directory	/workspace/1.rom_e2e_asm_init_rma/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3245018570
Short name	T1273
Test name
Test status
Simulation time	11511441873 ps
CPU time	2828.08 seconds
Started	Jul 24 08:12:11 PM PDT 24
Finished	Jul 24 08:59:20 PM PDT 24
Peak memory	611100 kb
Host	smart-53700e72-19d4-4f12-9dde-43411edf267f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245018570 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.3245018570
Directory	/workspace/1.rom_e2e_asm_init_test_unlocked0/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.4145268469
Short name	T1118
Test name
Test status
Simulation time	15325747226 ps
CPU time	3818.15 seconds
Started	Jul 24 08:12:48 PM PDT 24
Finished	Jul 24 09:16:27 PM PDT 24
Peak memory	610332 kb
Host	smart-13952ce7-c81f-4023-9153-eda2a8c600a4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145268469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.4145268469
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2751860263
Short name	T1428
Test name
Test status
Simulation time	14390899450 ps
CPU time	3346.86 seconds
Started	Jul 24 08:13:59 PM PDT 24
Finished	Jul 24 09:09:46 PM PDT 24
Peak memory	610528 kb
Host	smart-48883f2d-d182-4143-8869-b0a91d4c8e52
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751860263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.2751860263
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.686206169
Short name	T49
Test name
Test status
Simulation time	15191193640 ps
CPU time	3877.98 seconds
Started	Jul 24 08:14:27 PM PDT 24
Finished	Jul 24 09:19:06 PM PDT 24
Peak memory	610024 kb
Host	smart-19d13aae-0331-4296-8c08-87573b270069
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686206169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_ no_meas.686206169
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_self_hash.2772182225
Short name	T1300
Test name
Test status
Simulation time	26213423764 ps
CPU time	5941.6 seconds
Started	Jul 24 08:13:04 PM PDT 24
Finished	Jul 24 09:52:07 PM PDT 24
Peak memory	610800 kb
Host	smart-e9b073fe-c9a3-4464-8144-3bbda8201dc9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772182225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.2772182225
Directory	/workspace/1.rom_e2e_self_hash/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2089564487
Short name	T1418
Test name
Test status
Simulation time	14698898805 ps
CPU time	3306.35 seconds
Started	Jul 24 08:12:57 PM PDT 24
Finished	Jul 24 09:08:04 PM PDT 24
Peak memory	611620 kb
Host	smart-02cdc902-73f6-485e-b68b-03d82a2e4bb2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089564487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.2089564487
Directory	/workspace/1.rom_e2e_shutdown_exception_c/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_smoke.1849451019
Short name	T1374
Test name
Test status
Simulation time	15664041340 ps
CPU time	3174.74 seconds
Started	Jul 24 08:12:21 PM PDT 24
Finished	Jul 24 09:05:16 PM PDT 24
Peak memory	610776 kb
Host	smart-ff5d03f9-1b15-4af0-9ff1-48d2a41f51cf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1849451019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.1849451019
Directory	/workspace/1.rom_e2e_smoke/latest

---

Test location	/workspace/coverage/default/1.rom_e2e_static_critical.3019588383
Short name	T1004
Test name
Test status
Simulation time	16889050768 ps
CPU time	4146.8 seconds
Started	Jul 24 08:13:31 PM PDT 24
Finished	Jul 24 09:22:38 PM PDT 24
Peak memory	610692 kb
Host	smart-90fed2d0-28fb-4d1c-8586-b0449dd3e569
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019588383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3019588383
Directory	/workspace/1.rom_e2e_static_critical/latest

---

Test location	/workspace/coverage/default/1.rom_keymgr_functest.1654762498
Short name	T1365
Test name
Test status
Simulation time	4562548100 ps
CPU time	659.47 seconds
Started	Jul 24 08:08:53 PM PDT 24
Finished	Jul 24 08:19:53 PM PDT 24
Peak memory	610028 kb
Host	smart-c00e657c-0f6f-406f-8f34-813af42fcbb8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654762498 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.1654762498
Directory	/workspace/1.rom_keymgr_functest/latest

---

Test location	/workspace/coverage/default/1.rom_raw_unlock.282955214
Short name	T1310
Test name
Test status
Simulation time	5366527877 ps
CPU time	280.48 seconds
Started	Jul 24 08:10:01 PM PDT 24
Finished	Jul 24 08:14:43 PM PDT 24
Peak memory	620908 kb
Host	smart-686ea75d-228b-452a-ad79-9f557ebb6bff
User	root
Command	/workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=282955214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.282955214
Directory	/workspace/1.rom_raw_unlock/latest

---

Test location	/workspace/coverage/default/1.rom_volatile_raw_unlock.3262096337
Short name	T766
Test name
Test status
Simulation time	2439726864 ps
CPU time	104.45 seconds
Started	Jul 24 08:08:26 PM PDT 24
Finished	Jul 24 08:10:10 PM PDT 24
Peak memory	623452 kb
Host	smart-2f9a828e-5688-45ff-a496-5b312dc3b436
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262096337 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.3262096337
Directory	/workspace/1.rom_volatile_raw_unlock/latest

---

Test location	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.4033086117
Short name	T1116
Test name
Test status
Simulation time	10154005392 ps
CPU time	1047.53 seconds
Started	Jul 24 08:22:15 PM PDT 24
Finished	Jul 24 08:39:43 PM PDT 24
Peak memory	625296 kb
Host	smart-c373051d-76f8-482c-b57e-df07544010fd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033086117 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.4033086117
Directory	/workspace/10.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.4073011994
Short name	T1051
Test name
Test status
Simulation time	4032579702 ps
CPU time	479.03 seconds
Started	Jul 24 08:21:39 PM PDT 24
Finished	Jul 24 08:29:39 PM PDT 24
Peak memory	619272 kb
Host	smart-5de31c50-2c1f-4eb6-8c54-3ec0e517db99
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4073011994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.4073011994
Directory	/workspace/10.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3172158961
Short name	T7
Test name
Test status
Simulation time	6013141951 ps
CPU time	468.43 seconds
Started	Jul 24 08:23:18 PM PDT 24
Finished	Jul 24 08:31:07 PM PDT 24
Peak memory	621672 kb
Host	smart-7d2b0f50-6106-4d9e-b902-e183a5fa7a16
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172158961 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.3172158961
Directory	/workspace/11.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1079944911
Short name	T338
Test name
Test status
Simulation time	3303464716 ps
CPU time	631.43 seconds
Started	Jul 24 08:22:00 PM PDT 24
Finished	Jul 24 08:32:32 PM PDT 24
Peak memory	619308 kb
Host	smart-0daa6bc5-ef9b-438c-a0f7-88ee99f2296b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1079944911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1079944911
Directory	/workspace/11.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3765975460
Short name	T1335
Test name
Test status
Simulation time	13470280539 ps
CPU time	1004.45 seconds
Started	Jul 24 08:22:14 PM PDT 24
Finished	Jul 24 08:38:59 PM PDT 24
Peak memory	625364 kb
Host	smart-7fd7c43b-9b87-4dc1-8771-1bd767f016df
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765975460 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.3765975460
Directory	/workspace/12.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2429265688
Short name	T1409
Test name
Test status
Simulation time	8088703426 ps
CPU time	1416.31 seconds
Started	Jul 24 08:22:47 PM PDT 24
Finished	Jul 24 08:46:24 PM PDT 24
Peak memory	619296 kb
Host	smart-0d1d3537-2365-4855-b4bc-69a6c1f417de
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2429265688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.2429265688
Directory	/workspace/12.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3541910706
Short name	T1274
Test name
Test status
Simulation time	11681787764 ps
CPU time	919.6 seconds
Started	Jul 24 08:23:26 PM PDT 24
Finished	Jul 24 08:38:46 PM PDT 24
Peak memory	625352 kb
Host	smart-072f940a-3389-483e-8777-6dab1abd8c64
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541910706 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.3541910706
Directory	/workspace/13.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3245628521
Short name	T1076
Test name
Test status
Simulation time	4577335976 ps
CPU time	600.65 seconds
Started	Jul 24 08:23:02 PM PDT 24
Finished	Jul 24 08:33:03 PM PDT 24
Peak memory	619556 kb
Host	smart-7339a9cb-4cfb-45eb-bc79-42c640b5fafd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3245628521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.3245628521
Directory	/workspace/13.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1434961136
Short name	T1210
Test name
Test status
Simulation time	6441039513 ps
CPU time	467.88 seconds
Started	Jul 24 08:23:02 PM PDT 24
Finished	Jul 24 08:30:51 PM PDT 24
Peak memory	621620 kb
Host	smart-158c6f6d-7dc5-4da4-a68b-0d6de01ebe58
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434961136 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1434961136
Directory	/workspace/14.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1110138827
Short name	T456
Test name
Test status
Simulation time	3400383834 ps
CPU time	484.72 seconds
Started	Jul 24 08:24:34 PM PDT 24
Finished	Jul 24 08:32:39 PM PDT 24
Peak memory	649164 kb
Host	smart-eddb09da-d572-428f-ad39-ecb924cb87bd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110138827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1110138827
Directory	/workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1344203949
Short name	T1326
Test name
Test status
Simulation time	13019485880 ps
CPU time	2157.84 seconds
Started	Jul 24 08:23:36 PM PDT 24
Finished	Jul 24 08:59:34 PM PDT 24
Peak memory	619388 kb
Host	smart-e4b96aed-a769-4547-9cad-1ffd39cea7fb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1344203949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1344203949
Directory	/workspace/15.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3974904827
Short name	T373
Test name
Test status
Simulation time	4633729288 ps
CPU time	500.61 seconds
Started	Jul 24 08:23:41 PM PDT 24
Finished	Jul 24 08:32:02 PM PDT 24
Peak memory	649848 kb
Host	smart-e2305725-187f-46c5-a4fd-ce586f7364f1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974904827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3974904827
Directory	/workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.39211055
Short name	T1389
Test name
Test status
Simulation time	8117172096 ps
CPU time	1251.11 seconds
Started	Jul 24 08:24:39 PM PDT 24
Finished	Jul 24 08:45:31 PM PDT 24
Peak memory	619332 kb
Host	smart-a5403630-6cff-412e-9e75-2f9c24f4fc4b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=39211055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.39211055
Directory	/workspace/16.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.519309451
Short name	T213
Test name
Test status
Simulation time	12598075800 ps
CPU time	2124.92 seconds
Started	Jul 24 08:24:04 PM PDT 24
Finished	Jul 24 08:59:29 PM PDT 24
Peak memory	618928 kb
Host	smart-0202c22d-93ac-45b0-9e27-446c4b761dc6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=519309451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.519309451
Directory	/workspace/17.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3201299293
Short name	T1279
Test name
Test status
Simulation time	8600545802 ps
CPU time	1611.27 seconds
Started	Jul 24 08:24:46 PM PDT 24
Finished	Jul 24 08:51:37 PM PDT 24
Peak memory	619276 kb
Host	smart-467c9477-a49a-4541-8ead-a30c119d8d71
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3201299293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3201299293
Directory	/workspace/18.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1069028549
Short name	T1260
Test name
Test status
Simulation time	4221713808 ps
CPU time	595.93 seconds
Started	Jul 24 08:23:12 PM PDT 24
Finished	Jul 24 08:33:09 PM PDT 24
Peak memory	619336 kb
Host	smart-d3244e6b-0efc-4d7a-aa07-0f4b7ea8ee6b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1069028549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.1069028549
Directory	/workspace/19.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/2.chip_jtag_mem_access.2506985848
Short name	T77
Test name
Test status
Simulation time	13990831544 ps
CPU time	1418.72 seconds
Started	Jul 24 08:09:16 PM PDT 24
Finished	Jul 24 08:32:55 PM PDT 24
Peak memory	608344 kb
Host	smart-e4c9a11f-63e8-42b1-8c80-b0b7232e5613
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506985848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.2 506985848
Directory	/workspace/2.chip_jtag_mem_access/latest

---

Test location	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3164986818
Short name	T112
Test name
Test status
Simulation time	4421777942 ps
CPU time	473.63 seconds
Started	Jul 24 08:19:13 PM PDT 24
Finished	Jul 24 08:27:06 PM PDT 24
Peak memory	624164 kb
Host	smart-e48e1327-4ce5-4932-9453-9ca7b0424cdb
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 164986818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3164986818
Directory	/workspace/2.chip_rv_dm_ndm_reset_req/latest

---

Test location	/workspace/coverage/default/2.chip_sival_flash_info_access.667829663
Short name	T1125
Test name
Test status
Simulation time	2997482950 ps
CPU time	275.53 seconds
Started	Jul 24 08:11:32 PM PDT 24
Finished	Jul 24 08:16:08 PM PDT 24
Peak memory	610180 kb
Host	smart-066e07ab-e5c5-49d0-8330-96372e88a291
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=667829663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.667829663
Directory	/workspace/2.chip_sival_flash_info_access/latest

---

Test location	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3014302263
Short name	T1128
Test name
Test status
Simulation time	18580659256 ps
CPU time	633.29 seconds
Started	Jul 24 08:15:11 PM PDT 24
Finished	Jul 24 08:25:44 PM PDT 24
Peak memory	619744 kb
Host	smart-62d14229-b8da-47af-8c6b-c331453e2a1a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3014302263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3014302263
Directory	/workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aes_enc.2963954338
Short name	T1192
Test name
Test status
Simulation time	3111871064 ps
CPU time	334.99 seconds
Started	Jul 24 08:18:07 PM PDT 24
Finished	Jul 24 08:23:44 PM PDT 24
Peak memory	609976 kb
Host	smart-779f4d02-0f4f-4fe1-a2bf-159e944cda3a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963954338 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.2963954338
Directory	/workspace/2.chip_sw_aes_enc/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3237521120
Short name	T1117
Test name
Test status
Simulation time	2236104877 ps
CPU time	272.82 seconds
Started	Jul 24 08:14:46 PM PDT 24
Finished	Jul 24 08:19:19 PM PDT 24
Peak memory	609852 kb
Host	smart-80d6e9f7-86d4-4cde-9bf6-74ef4efe2bbf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237 521120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.3237521120
Directory	/workspace/2.chip_sw_aes_enc_jitter_en/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3803086324
Short name	T1233
Test name
Test status
Simulation time	2373526535 ps
CPU time	286.74 seconds
Started	Jul 24 08:17:00 PM PDT 24
Finished	Jul 24 08:21:47 PM PDT 24
Peak memory	609856 kb
Host	smart-620dac58-6e80-426c-a99c-81413e0706f1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803086324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3803086324
Directory	/workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aes_entropy.1186043654
Short name	T1349
Test name
Test status
Simulation time	3296129160 ps
CPU time	295.06 seconds
Started	Jul 24 08:14:39 PM PDT 24
Finished	Jul 24 08:19:34 PM PDT 24
Peak memory	610312 kb
Host	smart-59c3c282-e3db-4211-9460-01d9c3417269
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186043654 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.1186043654
Directory	/workspace/2.chip_sw_aes_entropy/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aes_idle.3356903694
Short name	T985
Test name
Test status
Simulation time	3018318256 ps
CPU time	289.39 seconds
Started	Jul 24 08:14:45 PM PDT 24
Finished	Jul 24 08:19:35 PM PDT 24
Peak memory	610072 kb
Host	smart-718db4ee-f289-47e1-bd2d-e0c4a31c0d26
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356903694 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.3356903694
Directory	/workspace/2.chip_sw_aes_idle/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aes_masking_off.3131464407
Short name	T1367
Test name
Test status
Simulation time	3947680756 ps
CPU time	358.48 seconds
Started	Jul 24 08:14:40 PM PDT 24
Finished	Jul 24 08:20:39 PM PDT 24
Peak memory	609868 kb
Host	smart-3bd44660-927d-4218-9c61-53c49097cd2e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131464407 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.3131464407
Directory	/workspace/2.chip_sw_aes_masking_off/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aes_smoketest.4012996243
Short name	T1218
Test name
Test status
Simulation time	3350458834 ps
CPU time	340.33 seconds
Started	Jul 24 08:18:38 PM PDT 24
Finished	Jul 24 08:24:19 PM PDT 24
Peak memory	609904 kb
Host	smart-5c9fbb96-5882-4b61-ab9e-2186a89dfc0f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012996243 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.4012996243
Directory	/workspace/2.chip_sw_aes_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1120105148
Short name	T1311
Test name
Test status
Simulation time	3651357409 ps
CPU time	319.18 seconds
Started	Jul 24 08:16:02 PM PDT 24
Finished	Jul 24 08:21:23 PM PDT 24
Peak memory	610036 kb
Host	smart-16a2deb3-9a5f-46af-9a38-042853f74b68
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1120105148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1120105148
Directory	/workspace/2.chip_sw_alert_handler_entropy/latest

---

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.278479789
Short name	T1361
Test name
Test status
Simulation time	6029337678 ps
CPU time	771.21 seconds
Started	Jul 24 08:13:54 PM PDT 24
Finished	Jul 24 08:26:46 PM PDT 24
Peak memory	620044 kb
Host	smart-d9c7f57b-48b2-44dc-85cc-88d6c22b9d4b
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=278479789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.278479789
Directory	/workspace/2.chip_sw_alert_handler_escalation/latest

---

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2316936716
Short name	T1406
Test name
Test status
Simulation time	6896218360 ps
CPU time	1786.38 seconds
Started	Jul 24 08:13:48 PM PDT 24
Finished	Jul 24 08:43:35 PM PDT 24
Peak memory	610716 kb
Host	smart-5b59f0c5-f70d-404c-9ccc-dfca3c202c39
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2316936716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.2316936716
Directory	/workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

---

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3983184180
Short name	T210
Test name
Test status
Simulation time	7146810780 ps
CPU time	1782.29 seconds
Started	Jul 24 08:16:21 PM PDT 24
Finished	Jul 24 08:46:03 PM PDT 24
Peak memory	610552 kb
Host	smart-0ab6c9f3-1060-4136-a95e-d439e628029a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983184180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.3983184180
Directory	/workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

---

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2336790302
Short name	T841
Test name
Test status
Simulation time	13104388976 ps
CPU time	1430.91 seconds
Started	Jul 24 08:19:32 PM PDT 24
Finished	Jul 24 08:43:24 PM PDT 24
Peak memory	611116 kb
Host	smart-9e1cbd56-e51b-494d-8114-ff2007edc92c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336790302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.2336790302
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

---

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2650968600
Short name	T306
Test name
Test status
Simulation time	8413485560 ps
CPU time	1371.86 seconds
Started	Jul 24 08:14:36 PM PDT 24
Finished	Jul 24 08:37:28 PM PDT 24
Peak memory	609508 kb
Host	smart-477a660d-9669-4534-a467-8eb1a69e1856
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2650968600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2650968600
Directory	/workspace/2.chip_sw_alert_handler_ping_ok/latest

---

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.677094992
Short name	T295
Test name
Test status
Simulation time	2949571456 ps
CPU time	321.72 seconds
Started	Jul 24 08:14:35 PM PDT 24
Finished	Jul 24 08:19:57 PM PDT 24
Peak memory	610436 kb
Host	smart-9ebcea6a-41aa-4cff-991b-b9be9f619fc6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=677094992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.677094992
Directory	/workspace/2.chip_sw_alert_handler_ping_timeout/latest

---

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1513026659
Short name	T314
Test name
Test status
Simulation time	255620682774 ps
CPU time	12663.1 seconds
Started	Jul 24 08:13:31 PM PDT 24
Finished	Jul 24 11:44:36 PM PDT 24
Peak memory	610964 kb
Host	smart-6d97679c-a971-4904-9102-527453db6c89
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1513026659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1513026659
Directory	/workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

---

Test location	/workspace/coverage/default/2.chip_sw_all_escalation_resets.1224147185
Short name	T1393
Test name
Test status
Simulation time	4810589518 ps
CPU time	721.58 seconds
Started	Jul 24 08:11:40 PM PDT 24
Finished	Jul 24 08:23:42 PM PDT 24
Peak memory	620124 kb
Host	smart-1a8307d7-7be8-43c2-9267-679520f2ab85
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1224147185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1224147185
Directory	/workspace/2.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_irq.371231284
Short name	T1053
Test name
Test status
Simulation time	3862936208 ps
CPU time	365.16 seconds
Started	Jul 24 08:17:01 PM PDT 24
Finished	Jul 24 08:23:07 PM PDT 24
Peak memory	610064 kb
Host	smart-1bb25149-f3cd-42a1-aed7-53401bbbb3cc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371231284 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.371231284
Directory	/workspace/2.chip_sw_aon_timer_irq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2885517790
Short name	T1152
Test name
Test status
Simulation time	7211284280 ps
CPU time	246.99 seconds
Started	Jul 24 08:17:17 PM PDT 24
Finished	Jul 24 08:21:25 PM PDT 24
Peak memory	611028 kb
Host	smart-97ec2020-114e-4ad5-bec6-465c006f634a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2885517790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2885517790
Directory	/workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.49902967
Short name	T1324
Test name
Test status
Simulation time	2946770928 ps
CPU time	360.18 seconds
Started	Jul 24 08:20:19 PM PDT 24
Finished	Jul 24 08:26:19 PM PDT 24
Peak memory	609736 kb
Host	smart-234c209d-eb4c-4cc6-8495-fc172dffad76
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49902967 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_aon_timer_smoketest.49902967
Directory	/workspace/2.chip_sw_aon_timer_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4140970963
Short name	T1142
Test name
Test status
Simulation time	10616184040 ps
CPU time	1064.6 seconds
Started	Jul 24 08:12:43 PM PDT 24
Finished	Jul 24 08:30:28 PM PDT 24
Peak memory	610088 kb
Host	smart-f0198a23-a572-48e7-a6c5-2c76190cb576
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4140970963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.4140970963
Directory	/workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3477218061
Short name	T1099
Test name
Test status
Simulation time	4426969900 ps
CPU time	488.16 seconds
Started	Jul 24 08:17:51 PM PDT 24
Finished	Jul 24 08:25:59 PM PDT 24
Peak memory	611028 kb
Host	smart-cb43b9d0-9047-4871-a12b-4d6e36d0e1ec
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3477218061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.3477218061
Directory	/workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

---

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3321648797
Short name	T1033
Test name
Test status
Simulation time	8300608802 ps
CPU time	1180.75 seconds
Started	Jul 24 08:17:05 PM PDT 24
Finished	Jul 24 08:36:46 PM PDT 24
Peak memory	617752 kb
Host	smart-97f4d896-2598-4f91-bc33-0f26b2b6c1f5
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321648797 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.3321648797
Directory	/workspace/2.chip_sw_ast_clk_outputs/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1125301654
Short name	T1270
Test name
Test status
Simulation time	6102649914 ps
CPU time	485.81 seconds
Started	Jul 24 08:15:18 PM PDT 24
Finished	Jul 24 08:23:24 PM PDT 24
Peak memory	621680 kb
Host	smart-3a63602a-9ed0-4dd9-90bb-ec6672331454
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1125301654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1125301654
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3145238208
Short name	T1328
Test name
Test status
Simulation time	4288249610 ps
CPU time	528.17 seconds
Started	Jul 24 08:19:40 PM PDT 24
Finished	Jul 24 08:28:29 PM PDT 24
Peak memory	613400 kb
Host	smart-fd87e5ff-6470-4f9b-afa3-1933e94f7aba
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145238208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3145238208
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2330640555
Short name	T1200
Test name
Test status
Simulation time	4593656304 ps
CPU time	681.77 seconds
Started	Jul 24 08:17:19 PM PDT 24
Finished	Jul 24 08:28:41 PM PDT 24
Peak memory	613444 kb
Host	smart-b5b5d17b-19a5-4bf0-9f93-32c5672915b8
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330640555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2330640555
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.15543573
Short name	T984
Test name
Test status
Simulation time	3604019008 ps
CPU time	563.9 seconds
Started	Jul 24 08:19:46 PM PDT 24
Finished	Jul 24 08:29:10 PM PDT 24
Peak memory	613116 kb
Host	smart-0a2490c4-a6fe-46d6-910d-9b8e6eff1548
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15543573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.15543573
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3052742844
Short name	T1399
Test name
Test status
Simulation time	4591916308 ps
CPU time	700.62 seconds
Started	Jul 24 08:15:40 PM PDT 24
Finished	Jul 24 08:27:21 PM PDT 24
Peak memory	613420 kb
Host	smart-9150aeb3-2d37-4de1-9b45-db034bccdcdc
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052742844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3052742844
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4019235946
Short name	T1317
Test name
Test status
Simulation time	4940506888 ps
CPU time	709.26 seconds
Started	Jul 24 08:15:55 PM PDT 24
Finished	Jul 24 08:27:44 PM PDT 24
Peak memory	613344 kb
Host	smart-96cc5a56-3263-4547-bd32-ecbbb7b31433
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019235946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.4019235946
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3049823078
Short name	T1403
Test name
Test status
Simulation time	4517188056 ps
CPU time	685.3 seconds
Started	Jul 24 08:16:53 PM PDT 24
Finished	Jul 24 08:28:19 PM PDT 24
Peak memory	613072 kb
Host	smart-ebe24420-b145-41b2-88a9-601f729916b5
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049823078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3049823078
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3920043320
Short name	T1052
Test name
Test status
Simulation time	2779368881 ps
CPU time	242.48 seconds
Started	Jul 24 08:15:52 PM PDT 24
Finished	Jul 24 08:19:54 PM PDT 24
Peak memory	610108 kb
Host	smart-adaffaad-a645-4e13-ac53-218c772f6747
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920043320 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.3920043320
Directory	/workspace/2.chip_sw_clkmgr_jitter/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3929663028
Short name	T88
Test name
Test status
Simulation time	3484533944 ps
CPU time	590.56 seconds
Started	Jul 24 08:17:05 PM PDT 24
Finished	Jul 24 08:26:56 PM PDT 24
Peak memory	610260 kb
Host	smart-2993901c-c136-4b53-aa5e-2428c532b715
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929663028 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.3929663028
Directory	/workspace/2.chip_sw_clkmgr_jitter_frequency/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1552845651
Short name	T1426
Test name
Test status
Simulation time	2747540911 ps
CPU time	249.98 seconds
Started	Jul 24 08:17:44 PM PDT 24
Finished	Jul 24 08:21:54 PM PDT 24
Peak memory	610100 kb
Host	smart-bb8f7afe-cb0d-4a4e-b518-fbaf4ca4ef52
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552845651 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.1552845651
Directory	/workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4249305881
Short name	T1266
Test name
Test status
Simulation time	4875836336 ps
CPU time	565.58 seconds
Started	Jul 24 08:16:20 PM PDT 24
Finished	Jul 24 08:25:45 PM PDT 24
Peak memory	610864 kb
Host	smart-5cb91253-92da-4107-9de7-8e45d71b238e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249305881 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.4249305881
Directory	/workspace/2.chip_sw_clkmgr_off_aes_trans/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2103580848
Short name	T1166
Test name
Test status
Simulation time	5059523088 ps
CPU time	683.17 seconds
Started	Jul 24 08:15:41 PM PDT 24
Finished	Jul 24 08:27:04 PM PDT 24
Peak memory	610648 kb
Host	smart-3d07ab85-95c4-4aaa-87ba-2e2b988e87c4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103580848 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2103580848
Directory	/workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.199828149
Short name	T987
Test name
Test status
Simulation time	5616529790 ps
CPU time	592.57 seconds
Started	Jul 24 08:15:48 PM PDT 24
Finished	Jul 24 08:25:41 PM PDT 24
Peak memory	610860 kb
Host	smart-536b2944-8d7d-499d-91c0-a09db192ae3b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199828149 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.199828149
Directory	/workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3848760405
Short name	T247
Test name
Test status
Simulation time	4403581158 ps
CPU time	347.99 seconds
Started	Jul 24 08:16:35 PM PDT 24
Finished	Jul 24 08:22:23 PM PDT 24
Peak memory	610964 kb
Host	smart-53f475af-c4a0-4202-9700-38834ff80e25
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848760405 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.3848760405
Directory	/workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1871777503
Short name	T407
Test name
Test status
Simulation time	11453457912 ps
CPU time	1025.03 seconds
Started	Jul 24 08:16:19 PM PDT 24
Finished	Jul 24 08:33:25 PM PDT 24
Peak memory	610708 kb
Host	smart-6cd37625-f483-4e8e-bb6f-b0e3d72287eb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871777503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.1871777503
Directory	/workspace/2.chip_sw_clkmgr_off_peri/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3807992351
Short name	T389
Test name
Test status
Simulation time	3486509912 ps
CPU time	499.91 seconds
Started	Jul 24 08:17:00 PM PDT 24
Finished	Jul 24 08:25:20 PM PDT 24
Peak memory	610248 kb
Host	smart-962ebfdd-8cdf-4aa6-bae5-520f5cd82484
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807992351 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3807992351
Directory	/workspace/2.chip_sw_clkmgr_reset_frequency/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1019416726
Short name	T1234
Test name
Test status
Simulation time	4669026936 ps
CPU time	634.13 seconds
Started	Jul 24 08:17:52 PM PDT 24
Finished	Jul 24 08:28:27 PM PDT 24
Peak memory	610736 kb
Host	smart-1d14efa9-4f87-47f7-b56b-9f20702fbcfa
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019416726 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.1019416726
Directory	/workspace/2.chip_sw_clkmgr_sleep_frequency/latest

---

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2186972786
Short name	T1056
Test name
Test status
Simulation time	2741977820 ps
CPU time	245.32 seconds
Started	Jul 24 08:18:03 PM PDT 24
Finished	Jul 24 08:22:09 PM PDT 24
Peak memory	609788 kb
Host	smart-c8d1edd7-fca8-4bd1-b17c-faeabb784983
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186972786 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.2186972786
Directory	/workspace/2.chip_sw_clkmgr_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.61895065
Short name	T1013
Test name
Test status
Simulation time	18043924948 ps
CPU time	4304.81 seconds
Started	Jul 24 08:14:52 PM PDT 24
Finished	Jul 24 09:26:38 PM PDT 24
Peak memory	610492 kb
Host	smart-2b158e17-2578-4c67-80f4-a206bec76fd6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61895065 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.61895065
Directory	/workspace/2.chip_sw_csrng_edn_concurrency/latest

---

Test location	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3161773836
Short name	T1154
Test name
Test status
Simulation time	21304617687 ps
CPU time	3006.72 seconds
Started	Jul 24 08:17:28 PM PDT 24
Finished	Jul 24 09:07:36 PM PDT 24
Peak memory	610052 kb
Host	smart-4c936275-14db-4214-bbfd-1b9bd5c3026f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3161773836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.3161773836
Directory	/workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2488051076
Short name	T185
Test name
Test status
Simulation time	3808505944 ps
CPU time	440.82 seconds
Started	Jul 24 08:14:37 PM PDT 24
Finished	Jul 24 08:21:59 PM PDT 24
Peak memory	610988 kb
Host	smart-af0afa2d-3aee-4be6-893c-d2d227469655
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24880 51076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.2488051076
Directory	/workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

---

Test location	/workspace/coverage/default/2.chip_sw_csrng_kat_test.874372472
Short name	T1332
Test name
Test status
Simulation time	2443324004 ps
CPU time	252.37 seconds
Started	Jul 24 08:15:17 PM PDT 24
Finished	Jul 24 08:19:30 PM PDT 24
Peak memory	610296 kb
Host	smart-864b0a19-367a-455f-947e-3ebc83ba139f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874372472 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.874372472
Directory	/workspace/2.chip_sw_csrng_kat_test/latest

---

Test location	/workspace/coverage/default/2.chip_sw_csrng_smoketest.3572376090
Short name	T1067
Test name
Test status
Simulation time	3269369448 ps
CPU time	218.78 seconds
Started	Jul 24 08:19:26 PM PDT 24
Finished	Jul 24 08:23:05 PM PDT 24
Peak memory	610004 kb
Host	smart-9389e24d-55d5-4b6a-9bf6-e32b8de3ef9e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572376090 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.3572376090
Directory	/workspace/2.chip_sw_csrng_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.741988261
Short name	T1159
Test name
Test status
Simulation time	5369330000 ps
CPU time	622.47 seconds
Started	Jul 24 08:09:32 PM PDT 24
Finished	Jul 24 08:19:55 PM PDT 24
Peak memory	611120 kb
Host	smart-fd2a4983-8451-4716-9654-64b573b28f52
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=741988261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.741988261
Directory	/workspace/2.chip_sw_data_integrity_escalation/latest

---

Test location	/workspace/coverage/default/2.chip_sw_edn_auto_mode.1907965128
Short name	T1251
Test name
Test status
Simulation time	7228966300 ps
CPU time	1661.27 seconds
Started	Jul 24 08:21:15 PM PDT 24
Finished	Jul 24 08:48:56 PM PDT 24
Peak memory	610632 kb
Host	smart-f034baca-d07c-44d6-b0e8-78d2d6800de3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907965128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.1907965128
Directory	/workspace/2.chip_sw_edn_auto_mode/latest

---

Test location	/workspace/coverage/default/2.chip_sw_edn_boot_mode.1177176138
Short name	T745
Test name
Test status
Simulation time	2779502452 ps
CPU time	618.69 seconds
Started	Jul 24 08:20:46 PM PDT 24
Finished	Jul 24 08:31:06 PM PDT 24
Peak memory	609784 kb
Host	smart-5f5745e3-08fe-444d-a1f2-df85b5a7cc39
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177176138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.1177176138
Directory	/workspace/2.chip_sw_edn_boot_mode/latest

---

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3303611703
Short name	T454
Test name
Test status
Simulation time	5382487852 ps
CPU time	913.75 seconds
Started	Jul 24 08:21:18 PM PDT 24
Finished	Jul 24 08:36:32 PM PDT 24
Peak memory	611156 kb
Host	smart-14a2b2ad-8f33-4879-aee1-8cc6193f172a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3303611703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.3303611703
Directory	/workspace/2.chip_sw_edn_entropy_reqs/latest

---

Test location	/workspace/coverage/default/2.chip_sw_edn_kat.350702710
Short name	T744
Test name
Test status
Simulation time	3734118920 ps
CPU time	645.31 seconds
Started	Jul 24 08:19:44 PM PDT 24
Finished	Jul 24 08:30:31 PM PDT 24
Peak memory	615800 kb
Host	smart-4a5408e2-0afd-4be6-86b2-9eec9f71beb0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350702710 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_edn_kat.350702710
Directory	/workspace/2.chip_sw_edn_kat/latest

---

Test location	/workspace/coverage/default/2.chip_sw_edn_sw_mode.849406841
Short name	T1038
Test name
Test status
Simulation time	8340949322 ps
CPU time	1962.21 seconds
Started	Jul 24 08:14:17 PM PDT 24
Finished	Jul 24 08:47:00 PM PDT 24
Peak memory	610468 kb
Host	smart-d9af6a46-4559-4e4d-9d8d-92c933aec722
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849406841 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.849406841
Directory	/workspace/2.chip_sw_edn_sw_mode/latest

---

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.136722229
Short name	T1178
Test name
Test status
Simulation time	2308291184 ps
CPU time	227.62 seconds
Started	Jul 24 08:14:52 PM PDT 24
Finished	Jul 24 08:18:40 PM PDT 24
Peak memory	610224 kb
Host	smart-d52d1bdc-834a-4864-8f78-f8031a7b526d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13 6722229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.136722229
Directory	/workspace/2.chip_sw_entropy_src_ast_rng_req/latest

---

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.61661746
Short name	T989
Test name
Test status
Simulation time	2722177720 ps
CPU time	291.07 seconds
Started	Jul 24 08:15:24 PM PDT 24
Finished	Jul 24 08:20:15 PM PDT 24
Peak memory	610344 kb
Host	smart-1d555b03-5f24-4cc4-89ba-0c70e84a4f31
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61661746 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.61661746
Directory	/workspace/2.chip_sw_entropy_src_kat_test/latest

---

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3806940920
Short name	T1086
Test name
Test status
Simulation time	3279615142 ps
CPU time	524.61 seconds
Started	Jul 24 08:19:56 PM PDT 24
Finished	Jul 24 08:28:41 PM PDT 24
Peak memory	609976 kb
Host	smart-98d3137d-2f7e-4e53-91d3-06cfa650bcf8
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3806940920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.3806940920
Directory	/workspace/2.chip_sw_entropy_src_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_example_concurrency.323521602
Short name	T983
Test name
Test status
Simulation time	2307813224 ps
CPU time	192.85 seconds
Started	Jul 24 08:11:03 PM PDT 24
Finished	Jul 24 08:14:16 PM PDT 24
Peak memory	609848 kb
Host	smart-bc19722f-f2bf-46f8-9425-6d5b5a0e4624
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323521602 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.323521602
Directory	/workspace/2.chip_sw_example_concurrency/latest

---

Test location	/workspace/coverage/default/2.chip_sw_example_flash.3652392010
Short name	T1075
Test name
Test status
Simulation time	2760893336 ps
CPU time	167.17 seconds
Started	Jul 24 08:10:30 PM PDT 24
Finished	Jul 24 08:13:18 PM PDT 24
Peak memory	609772 kb
Host	smart-2da79640-92b7-4abf-8b9c-c234578a61be
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652392010 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.3652392010
Directory	/workspace/2.chip_sw_example_flash/latest

---

Test location	/workspace/coverage/default/2.chip_sw_example_manufacturer.3221793755
Short name	T1366
Test name
Test status
Simulation time	2304411540 ps
CPU time	207.97 seconds
Started	Jul 24 08:11:44 PM PDT 24
Finished	Jul 24 08:15:13 PM PDT 24
Peak memory	609984 kb
Host	smart-5bef27bb-aa4d-46ca-a4a1-c5c952202c9b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221793755 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.3221793755
Directory	/workspace/2.chip_sw_example_manufacturer/latest

---

Test location	/workspace/coverage/default/2.chip_sw_example_rom.3924019203
Short name	T1202
Test name
Test status
Simulation time	2438558222 ps
CPU time	131.48 seconds
Started	Jul 24 08:11:36 PM PDT 24
Finished	Jul 24 08:13:47 PM PDT 24
Peak memory	610804 kb
Host	smart-77c58eb3-dc0b-4e46-814f-362e6840ebcc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924019203 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.3924019203
Directory	/workspace/2.chip_sw_example_rom/latest

---

Test location	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2779478548
Short name	T152
Test name
Test status
Simulation time	57915544082 ps
CPU time	11339.9 seconds
Started	Jul 24 08:10:33 PM PDT 24
Finished	Jul 24 11:19:35 PM PDT 24
Peak memory	625372 kb
Host	smart-3fc678ea-717e-44bf-8915-35883c181df4
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2779478548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.2779478548
Directory	/workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_crash_alert.804117604
Short name	T1402
Test name
Test status
Simulation time	4728266280 ps
CPU time	912.18 seconds
Started	Jul 24 08:19:16 PM PDT 24
Finished	Jul 24 08:34:28 PM PDT 24
Peak memory	611144 kb
Host	smart-d9cd59c0-58f3-4e37-8694-106fc0a07951
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=804117604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.804117604
Directory	/workspace/2.chip_sw_flash_crash_alert/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.1648947638
Short name	T1267
Test name
Test status
Simulation time	5910814406 ps
CPU time	1162.65 seconds
Started	Jul 24 08:15:05 PM PDT 24
Finished	Jul 24 08:34:28 PM PDT 24
Peak memory	609836 kb
Host	smart-2d134a96-5bad-418d-84ab-6a5387b1a073
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648947638 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.1648947638
Directory	/workspace/2.chip_sw_flash_ctrl_access/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3237316585
Short name	T1122
Test name
Test status
Simulation time	6191335027 ps
CPU time	1329.06 seconds
Started	Jul 24 08:15:47 PM PDT 24
Finished	Jul 24 08:37:56 PM PDT 24
Peak memory	610424 kb
Host	smart-186c4bf8-8a9c-4a1b-beaf-e8892c868f25
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237316585 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.3237316585
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.565763560
Short name	T118
Test name
Test status
Simulation time	7385730508 ps
CPU time	1070.96 seconds
Started	Jul 24 08:18:34 PM PDT 24
Finished	Jul 24 08:36:25 PM PDT 24
Peak memory	609916 kb
Host	smart-a8ad7538-9977-41ee-96a7-207674c44952
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565763560 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.565763560
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1595799655
Short name	T1396
Test name
Test status
Simulation time	5325483736 ps
CPU time	1189.81 seconds
Started	Jul 24 08:11:52 PM PDT 24
Finished	Jul 24 08:31:43 PM PDT 24
Peak memory	609968 kb
Host	smart-2322b643-a27f-41a9-88ed-41913c4c7b61
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595799655 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.1595799655
Directory	/workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2979045757
Short name	T1369
Test name
Test status
Simulation time	3407518140 ps
CPU time	348.7 seconds
Started	Jul 24 08:10:38 PM PDT 24
Finished	Jul 24 08:16:27 PM PDT 24
Peak memory	610388 kb
Host	smart-c19b8cd3-35cc-4d38-b909-854ab62c02f0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979045757 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.2979045757
Directory	/workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.4162829858
Short name	T1181
Test name
Test status
Simulation time	5983983616 ps
CPU time	1111.97 seconds
Started	Jul 24 08:25:39 PM PDT 24
Finished	Jul 24 08:44:11 PM PDT 24
Peak memory	609772 kb
Host	smart-027bc112-c811-4977-95cf-017ce912829e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162829858 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.4162829858
Directory	/workspace/2.chip_sw_flash_ctrl_mem_protection/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2618643123
Short name	T362
Test name
Test status
Simulation time	4330086846 ps
CPU time	867.34 seconds
Started	Jul 24 08:12:52 PM PDT 24
Finished	Jul 24 08:27:19 PM PDT 24
Peak memory	610708 kb
Host	smart-c94fb39a-8546-4d7e-8651-d3a9f8e077b9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618643123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.2618643123
Directory	/workspace/2.chip_sw_flash_ctrl_ops/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.922862736
Short name	T363
Test name
Test status
Simulation time	4314308830 ps
CPU time	625.18 seconds
Started	Jul 24 08:15:45 PM PDT 24
Finished	Jul 24 08:26:10 PM PDT 24
Peak memory	610580 kb
Host	smart-46473cc8-945c-4678-b5bd-df4da66bc878
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=922862736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.922862736
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2845703732
Short name	T375
Test name
Test status
Simulation time	5174705189 ps
CPU time	659.16 seconds
Started	Jul 24 08:18:52 PM PDT 24
Finished	Jul 24 08:29:51 PM PDT 24
Peak memory	610548 kb
Host	smart-e7858f1a-90aa-4c34-934e-67af7f063d48
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2845703732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2845703732
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3688000059
Short name	T1039
Test name
Test status
Simulation time	3114293336 ps
CPU time	337.97 seconds
Started	Jul 24 08:16:47 PM PDT 24
Finished	Jul 24 08:22:26 PM PDT 24
Peak memory	610220 kb
Host	smart-aae49051-0835-4d43-81a1-86450d10eb84
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688000 059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.3688000059
Directory	/workspace/2.chip_sw_flash_ctrl_write_clear/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_init.2541937177
Short name	T1246
Test name
Test status
Simulation time	17078568500 ps
CPU time	1933.17 seconds
Started	Jul 24 08:14:23 PM PDT 24
Finished	Jul 24 08:46:37 PM PDT 24
Peak memory	613336 kb
Host	smart-5e8adf60-dd08-4960-8e6c-8652b3c1a2e4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541937177 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.2541937177
Directory	/workspace/2.chip_sw_flash_init/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2713929281
Short name	T1281
Test name
Test status
Simulation time	24380960917 ps
CPU time	1637.85 seconds
Started	Jul 24 08:17:24 PM PDT 24
Finished	Jul 24 08:44:42 PM PDT 24
Peak memory	613420 kb
Host	smart-fad8e600-d1a9-4276-96a7-dc2e6f50fee9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2713929281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.2713929281
Directory	/workspace/2.chip_sw_flash_init_reduced_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.395281252
Short name	T413
Test name
Test status
Simulation time	3254129000 ps
CPU time	252.3 seconds
Started	Jul 24 08:29:15 PM PDT 24
Finished	Jul 24 08:33:28 PM PDT 24
Peak memory	610108 kb
Host	smart-2b52f963-2e29-4bbc-a2db-e1b051c7f7af
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=395281252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.395281252
Directory	/workspace/2.chip_sw_flash_scrambling_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_gpio_smoketest.583913815
Short name	T212
Test name
Test status
Simulation time	3074325893 ps
CPU time	312.47 seconds
Started	Jul 24 08:19:10 PM PDT 24
Finished	Jul 24 08:24:23 PM PDT 24
Peak memory	610692 kb
Host	smart-39b29548-3e42-4c5a-ae43-8e5ad68936f7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583913815 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_gpio_smoketest.583913815
Directory	/workspace/2.chip_sw_gpio_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc.54219615
Short name	T377
Test name
Test status
Simulation time	2816070016 ps
CPU time	367.01 seconds
Started	Jul 24 08:15:44 PM PDT 24
Finished	Jul 24 08:21:52 PM PDT 24
Peak memory	609956 kb
Host	smart-7e04603c-311c-4dde-9163-e94e67493eb6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54219615 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_hmac_enc.54219615
Directory	/workspace/2.chip_sw_hmac_enc/latest

---

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.618726314
Short name	T96
Test name
Test status
Simulation time	2827240100 ps
CPU time	304.51 seconds
Started	Jul 24 08:15:15 PM PDT 24
Finished	Jul 24 08:20:20 PM PDT 24
Peak memory	610056 kb
Host	smart-ce175a74-bffd-4154-9837-5ee463ff0aa0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618726314 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_hmac_enc_idle.618726314
Directory	/workspace/2.chip_sw_hmac_enc_idle/latest

---

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.4191379355
Short name	T366
Test name
Test status
Simulation time	2501710048 ps
CPU time	211.43 seconds
Started	Jul 24 08:14:24 PM PDT 24
Finished	Jul 24 08:17:56 PM PDT 24
Peak memory	610016 kb
Host	smart-a1d1b30c-b3ab-444d-9474-fad76409490a
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191379355 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.4191379355
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en/latest

---

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.474369446
Short name	T1391
Test name
Test status
Simulation time	2637412017 ps
CPU time	285.97 seconds
Started	Jul 24 08:17:37 PM PDT 24
Finished	Jul 24 08:22:24 PM PDT 24
Peak memory	609852 kb
Host	smart-45764b27-a1b4-43b6-a14a-0d226dc53259
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474369446 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.474369446
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_hmac_multistream.2884919319
Short name	T272
Test name
Test status
Simulation time	6980651190 ps
CPU time	1249.63 seconds
Started	Jul 24 08:17:12 PM PDT 24
Finished	Jul 24 08:38:02 PM PDT 24
Peak memory	610344 kb
Host	smart-360fa553-73a6-41c9-820f-bda36cae6aa8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884919319 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.2884919319
Directory	/workspace/2.chip_sw_hmac_multistream/latest

---

Test location	/workspace/coverage/default/2.chip_sw_hmac_oneshot.1849218501
Short name	T1007
Test name
Test status
Simulation time	2804285616 ps
CPU time	261.32 seconds
Started	Jul 24 08:15:09 PM PDT 24
Finished	Jul 24 08:19:31 PM PDT 24
Peak memory	609780 kb
Host	smart-d5f6a2c7-6b77-42a9-bffd-29f8aa42e0c7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849218501 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.1849218501
Directory	/workspace/2.chip_sw_hmac_oneshot/latest

---

Test location	/workspace/coverage/default/2.chip_sw_hmac_smoketest.2730494491
Short name	T1252
Test name
Test status
Simulation time	3170726070 ps
CPU time	300.51 seconds
Started	Jul 24 08:18:30 PM PDT 24
Finished	Jul 24 08:23:31 PM PDT 24
Peak memory	609864 kb
Host	smart-d698a552-f1fc-4bdc-9b82-5a9e51724cc9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730494491 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.2730494491
Directory	/workspace/2.chip_sw_hmac_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2222633689
Short name	T215
Test name
Test status
Simulation time	4239287384 ps
CPU time	590.46 seconds
Started	Jul 24 08:11:39 PM PDT 24
Finished	Jul 24 08:21:30 PM PDT 24
Peak memory	611120 kb
Host	smart-79935f0a-901a-43bb-a936-2a904e78fb28
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222633689 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2222633689
Directory	/workspace/2.chip_sw_i2c_device_tx_rx/latest

---

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.988462401
Short name	T211
Test name
Test status
Simulation time	4952652704 ps
CPU time	783.97 seconds
Started	Jul 24 08:11:28 PM PDT 24
Finished	Jul 24 08:24:34 PM PDT 24
Peak memory	609856 kb
Host	smart-1217e2eb-9313-4a50-b6f7-b4c77e6ff0ce
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988462401 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.988462401
Directory	/workspace/2.chip_sw_i2c_host_tx_rx/latest

---

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.4018301916
Short name	T332
Test name
Test status
Simulation time	5345047752 ps
CPU time	837.81 seconds
Started	Jul 24 08:12:01 PM PDT 24
Finished	Jul 24 08:26:00 PM PDT 24
Peak memory	610936 kb
Host	smart-80854378-a9a7-4e52-bfed-e190f1dfa09f
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018301916 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.4018301916
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

---

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3534648770
Short name	T340
Test name
Test status
Simulation time	4657166890 ps
CPU time	899.78 seconds
Started	Jul 24 08:11:35 PM PDT 24
Finished	Jul 24 08:26:36 PM PDT 24
Peak memory	610016 kb
Host	smart-e5266d2f-4650-4eba-83d3-85a063eb2bf6
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534648770 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3534648770
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

---

Test location	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1280058038
Short name	T201
Test name
Test status
Simulation time	65709922527 ps
CPU time	11790.2 seconds
Started	Jul 24 08:12:55 PM PDT 24
Finished	Jul 24 11:29:27 PM PDT 24
Peak memory	625240 kb
Host	smart-911b3317-a10b-4156-91f4-bcf12c5cbf77
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1280058038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.1280058038
Directory	/workspace/2.chip_sw_inject_scramble_seed/latest

---

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.242958528
Short name	T224
Test name
Test status
Simulation time	9238478680 ps
CPU time	1565.64 seconds
Started	Jul 24 08:17:44 PM PDT 24
Finished	Jul 24 08:43:50 PM PDT 24
Peak memory	617964 kb
Host	smart-2c7a4000-6ad7-4eb2-8dd9-221d232ea81d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429 58528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.242958528
Directory	/workspace/2.chip_sw_keymgr_key_derivation/latest

---

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2740169661
Short name	T225
Test name
Test status
Simulation time	10052042524 ps
CPU time	1495.41 seconds
Started	Jul 24 08:15:16 PM PDT 24
Finished	Jul 24 08:40:12 PM PDT 24
Peak memory	618212 kb
Host	smart-78ea68b5-7075-4ceb-ac81-2d606f9dcbe2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2740169661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.2740169661
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

---

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.103272201
Short name	T221
Test name
Test status
Simulation time	10285795118 ps
CPU time	1771 seconds
Started	Jul 24 08:17:48 PM PDT 24
Finished	Jul 24 08:47:20 PM PDT 24
Peak memory	617208 kb
Host	smart-651ae621-e835-4cdd-a79f-927338a95d47
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=103272201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.103272201
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2831463121
Short name	T166
Test name
Test status
Simulation time	12447254552 ps
CPU time	2070.56 seconds
Started	Jul 24 08:15:42 PM PDT 24
Finished	Jul 24 08:50:13 PM PDT 24
Peak memory	618540 kb
Host	smart-152230d3-f5fd-4be7-a614-8c04c8c47ea5
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2831463121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.2831463121
Directory	/workspace/2.chip_sw_keymgr_key_derivation_prod/latest

---

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1450874047
Short name	T227
Test name
Test status
Simulation time	11763580060 ps
CPU time	2229.54 seconds
Started	Jul 24 08:14:37 PM PDT 24
Finished	Jul 24 08:51:47 PM PDT 24
Peak memory	611640 kb
Host	smart-358a936a-ed6e-4019-bbff-fd7c7feed351
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145087 4047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.1450874047
Directory	/workspace/2.chip_sw_keymgr_sideload_aes/latest

---

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2103270943
Short name	T1055
Test name
Test status
Simulation time	7117797244 ps
CPU time	1436.43 seconds
Started	Jul 24 08:15:33 PM PDT 24
Finished	Jul 24 08:39:30 PM PDT 24
Peak memory	611416 kb
Host	smart-8663b82c-f20b-4b54-8cf9-cac1dc457a21
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21032 70943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.2103270943
Directory	/workspace/2.chip_sw_keymgr_sideload_kmac/latest

---

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1890423074
Short name	T232
Test name
Test status
Simulation time	13181316808 ps
CPU time	3422.08 seconds
Started	Jul 24 08:15:04 PM PDT 24
Finished	Jul 24 09:12:07 PM PDT 24
Peak memory	610232 kb
Host	smart-b965697a-ac9e-4cfe-9049-dd3f50da9189
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18904 23074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.1890423074
Directory	/workspace/2.chip_sw_keymgr_sideload_otbn/latest

---

Test location	/workspace/coverage/default/2.chip_sw_kmac_app_rom.3512425170
Short name	T1314
Test name
Test status
Simulation time	2803876248 ps
CPU time	264.76 seconds
Started	Jul 24 08:16:09 PM PDT 24
Finished	Jul 24 08:20:34 PM PDT 24
Peak memory	609816 kb
Host	smart-6139f381-9507-4b65-a812-f447416561be
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512425170 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.3512425170
Directory	/workspace/2.chip_sw_kmac_app_rom/latest

---

Test location	/workspace/coverage/default/2.chip_sw_kmac_entropy.838757334
Short name	T1220
Test name
Test status
Simulation time	2798374520 ps
CPU time	330.48 seconds
Started	Jul 24 08:14:31 PM PDT 24
Finished	Jul 24 08:20:02 PM PDT 24
Peak memory	609836 kb
Host	smart-b60285c7-5377-4e7e-a71a-bd5880ed2393
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838757334 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_entropy.838757334
Directory	/workspace/2.chip_sw_kmac_entropy/latest

---

Test location	/workspace/coverage/default/2.chip_sw_kmac_idle.3669589648
Short name	T1417
Test name
Test status
Simulation time	3429314720 ps
CPU time	242.15 seconds
Started	Jul 24 08:15:47 PM PDT 24
Finished	Jul 24 08:19:49 PM PDT 24
Peak memory	609788 kb
Host	smart-511c79ec-6a4d-474b-9644-a8d2f634b9dd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669589648 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.3669589648
Directory	/workspace/2.chip_sw_kmac_idle/latest

---

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2643386697
Short name	T1208
Test name
Test status
Simulation time	2547185640 ps
CPU time	275.03 seconds
Started	Jul 24 08:15:11 PM PDT 24
Finished	Jul 24 08:19:47 PM PDT 24
Peak memory	610164 kb
Host	smart-36f8573a-257e-408e-8bb6-0645cced42ae
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643386697 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.2643386697
Directory	/workspace/2.chip_sw_kmac_mode_cshake/latest

---

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3064130405
Short name	T1062
Test name
Test status
Simulation time	2553887148 ps
CPU time	264.02 seconds
Started	Jul 24 08:14:22 PM PDT 24
Finished	Jul 24 08:18:46 PM PDT 24
Peak memory	610052 kb
Host	smart-a4fd6c04-48e8-40db-b80f-86f79b9684ca
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064130405 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.3064130405
Directory	/workspace/2.chip_sw_kmac_mode_kmac/latest

---

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.210341236
Short name	T1186
Test name
Test status
Simulation time	2998564000 ps
CPU time	315.12 seconds
Started	Jul 24 08:15:19 PM PDT 24
Finished	Jul 24 08:20:34 PM PDT 24
Peak memory	610008 kb
Host	smart-9ad41b69-74df-4498-82ed-2b3de7eefeef
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210341236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.210341236
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

---

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.531119228
Short name	T449
Test name
Test status
Simulation time	3825493588 ps
CPU time	319.07 seconds
Started	Jul 24 08:18:58 PM PDT 24
Finished	Jul 24 08:24:18 PM PDT 24
Peak memory	610044 kb
Host	smart-272c765c-dac7-4a17-a8ab-dc551e4b6e04
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53111922 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.531119228
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_kmac_smoketest.1738312468
Short name	T1176
Test name
Test status
Simulation time	2762310952 ps
CPU time	275.53 seconds
Started	Jul 24 08:20:16 PM PDT 24
Finished	Jul 24 08:24:52 PM PDT 24
Peak memory	609832 kb
Host	smart-6050a2fc-c613-4eca-a30c-23f3c009cfc0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738312468 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.1738312468
Directory	/workspace/2.chip_sw_kmac_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3348187434
Short name	T1031
Test name
Test status
Simulation time	2995609376 ps
CPU time	417.74 seconds
Started	Jul 24 08:11:37 PM PDT 24
Finished	Jul 24 08:18:35 PM PDT 24
Peak memory	609924 kb
Host	smart-7b66891f-5022-48e0-a7fe-9fefd0ebaf51
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348187434 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.3348187434
Directory	/workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

---

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1645567317
Short name	T169
Test name
Test status
Simulation time	4645754100 ps
CPU time	495.99 seconds
Started	Jul 24 08:17:06 PM PDT 24
Finished	Jul 24 08:25:22 PM PDT 24
Peak memory	611448 kb
Host	smart-3c5889a6-8686-4bc4-802d-858ab2c4c745
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1645567317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.1645567317
Directory	/workspace/2.chip_sw_lc_ctrl_program_error/latest

---

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.622995137
Short name	T768
Test name
Test status
Simulation time	4145257694 ps
CPU time	207.94 seconds
Started	Jul 24 08:11:37 PM PDT 24
Finished	Jul 24 08:15:05 PM PDT 24
Peak memory	620380 kb
Host	smart-0250d895-0c51-45f1-9273-ed0ec1ce2c11
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62299513 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.622995137
Directory	/workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest

---

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2599771965
Short name	T1339
Test name
Test status
Simulation time	8825410741 ps
CPU time	917.25 seconds
Started	Jul 24 08:12:16 PM PDT 24
Finished	Jul 24 08:27:34 PM PDT 24
Peak memory	620732 kb
Host	smart-f01d5fbd-86e3-4d7c-a770-ea073f865701
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599771965 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.2599771965
Directory	/workspace/2.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.4119840906
Short name	T764
Test name
Test status
Simulation time	2953988933 ps
CPU time	115.89 seconds
Started	Jul 24 08:11:29 PM PDT 24
Finished	Jul 24 08:13:26 PM PDT 24
Peak memory	617432 kb
Host	smart-9e7dcb76-5e8c-456a-8fc3-9b791c7318c2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4119840906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.4119840906
Directory	/workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest

---

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3433979333
Short name	T767
Test name
Test status
Simulation time	2633713776 ps
CPU time	123.23 seconds
Started	Jul 24 08:11:52 PM PDT 24
Finished	Jul 24 08:13:55 PM PDT 24
Peak memory	623524 kb
Host	smart-1ec0c75e-4bd5-49af-8313-0b210b90c8e9
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433979333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3433979333
Directory	/workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

---

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1698428675
Short name	T237
Test name
Test status
Simulation time	50894440326 ps
CPU time	5333.23 seconds
Started	Jul 24 08:11:51 PM PDT 24
Finished	Jul 24 09:40:45 PM PDT 24
Peak memory	621040 kb
Host	smart-b45f6af3-58ca-48ae-8501-978e2f9af41f
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698428675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.1698428675
Directory	/workspace/2.chip_sw_lc_walkthrough_dev/latest

---

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1728411855
Short name	T236
Test name
Test status
Simulation time	47718989100 ps
CPU time	5494.44 seconds
Started	Jul 24 08:12:28 PM PDT 24
Finished	Jul 24 09:44:04 PM PDT 24
Peak memory	624368 kb
Host	smart-0f0eff5d-52f2-4089-8d95-f16cdea7fbb5
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728411855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.1728411855
Directory	/workspace/2.chip_sw_lc_walkthrough_prod/latest

---

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2413509144
Short name	T1073
Test name
Test status
Simulation time	12541628652 ps
CPU time	1212.46 seconds
Started	Jul 24 08:11:59 PM PDT 24
Finished	Jul 24 08:32:12 PM PDT 24
Peak memory	620608 kb
Host	smart-0558500f-c253-4b5d-8027-8d27b0c1af22
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413509144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.2413509144
Directory	/workspace/2.chip_sw_lc_walkthrough_prodend/latest

---

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3463116617
Short name	T235
Test name
Test status
Simulation time	48659168288 ps
CPU time	5232.94 seconds
Started	Jul 24 08:11:37 PM PDT 24
Finished	Jul 24 09:38:51 PM PDT 24
Peak memory	620732 kb
Host	smart-071a1d66-d29d-42e0-9ea7-5f499f476680
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463116617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.3463116617
Directory	/workspace/2.chip_sw_lc_walkthrough_rma/latest

---

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.183513854
Short name	T1130
Test name
Test status
Simulation time	22425964008 ps
CPU time	1723.41 seconds
Started	Jul 24 08:11:19 PM PDT 24
Finished	Jul 24 08:40:03 PM PDT 24
Peak memory	621416 kb
Host	smart-fe3a2f08-bbfd-42bf-8fdf-b496c7ca58b3
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=183513854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunl ocks.183513854
Directory	/workspace/2.chip_sw_lc_walkthrough_testunlocks/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3346866463
Short name	T150
Test name
Test status
Simulation time	17726066180 ps
CPU time	3398.78 seconds
Started	Jul 24 08:13:55 PM PDT 24
Finished	Jul 24 09:10:34 PM PDT 24
Peak memory	610668 kb
Host	smart-2d10def5-ca4d-4330-b46f-9d3778f7e82c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3346866463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.3346866463
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3090207692
Short name	T1005
Test name
Test status
Simulation time	18506701721 ps
CPU time	3329.71 seconds
Started	Jul 24 08:15:28 PM PDT 24
Finished	Jul 24 09:10:59 PM PDT 24
Peak memory	610800 kb
Host	smart-0da9e6a1-4741-45b0-a6e6-97de40d85db1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3090207692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3090207692
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3568734349
Short name	T741
Test name
Test status
Simulation time	24838595441 ps
CPU time	3538.19 seconds
Started	Jul 24 08:17:29 PM PDT 24
Finished	Jul 24 09:16:28 PM PDT 24
Peak memory	610896 kb
Host	smart-eb2eac2f-9043-42a4-9c47-673a54c06f1c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568734349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3568734349
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1223289259
Short name	T1416
Test name
Test status
Simulation time	4166095824 ps
CPU time	546.72 seconds
Started	Jul 24 08:15:39 PM PDT 24
Finished	Jul 24 08:24:46 PM PDT 24
Peak memory	610220 kb
Host	smart-7b2051ee-94f4-4ad9-a544-939d7889cd3e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223289259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1223289259
Directory	/workspace/2.chip_sw_otbn_mem_scramble/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otbn_randomness.791823606
Short name	T1345
Test name
Test status
Simulation time	6242084884 ps
CPU time	1042.66 seconds
Started	Jul 24 08:13:32 PM PDT 24
Finished	Jul 24 08:30:55 PM PDT 24
Peak memory	610664 kb
Host	smart-900c6099-fd00-47dd-91ac-11d05e5e6fa2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=791823606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.791823606
Directory	/workspace/2.chip_sw_otbn_randomness/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otbn_smoketest.1302504128
Short name	T1429
Test name
Test status
Simulation time	11590657312 ps
CPU time	1782.55 seconds
Started	Jul 24 08:19:42 PM PDT 24
Finished	Jul 24 08:49:26 PM PDT 24
Peak memory	609924 kb
Host	smart-59afa4af-c5f7-44a1-8042-8ae9deb3a644
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302504128 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.1302504128
Directory	/workspace/2.chip_sw_otbn_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2741080787
Short name	T1010
Test name
Test status
Simulation time	2870351832 ps
CPU time	337.42 seconds
Started	Jul 24 08:12:21 PM PDT 24
Finished	Jul 24 08:17:59 PM PDT 24
Peak memory	610080 kb
Host	smart-4a69df12-4cbf-4607-b1e6-f9e639125fe5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741080787 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.2741080787
Directory	/workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3256490962
Short name	T1188
Test name
Test status
Simulation time	8374388408 ps
CPU time	1211.27 seconds
Started	Jul 24 08:17:52 PM PDT 24
Finished	Jul 24 08:38:04 PM PDT 24
Peak memory	611068 kb
Host	smart-7af60a6e-e151-4f38-8468-943ffc231946
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3256490962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.3256490962
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1483375082
Short name	T1358
Test name
Test status
Simulation time	7437630398 ps
CPU time	1166.55 seconds
Started	Jul 24 08:11:57 PM PDT 24
Finished	Jul 24 08:31:24 PM PDT 24
Peak memory	610920 kb
Host	smart-ec2d8afa-0b14-4b56-9da2-d19a48cd74b4
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1483375082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1483375082
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4084980966
Short name	T1207
Test name
Test status
Simulation time	9280824760 ps
CPU time	1346.79 seconds
Started	Jul 24 08:11:57 PM PDT 24
Finished	Jul 24 08:34:24 PM PDT 24
Peak memory	610832 kb
Host	smart-f89a5005-f640-45e2-9371-67688601d9d7
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4084980966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.4084980966
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.118722108
Short name	T1318
Test name
Test status
Simulation time	4534173416 ps
CPU time	785.04 seconds
Started	Jul 24 08:12:32 PM PDT 24
Finished	Jul 24 08:25:37 PM PDT 24
Peak memory	610648 kb
Host	smart-405daf8d-33a8-4590-ab5d-f845fedbc46d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=118722108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.118722108
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

---

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.4174034219
Short name	T1096
Test name
Test status
Simulation time	2497093932 ps
CPU time	275.93 seconds
Started	Jul 24 08:18:46 PM PDT 24
Finished	Jul 24 08:23:22 PM PDT 24
Peak memory	609992 kb
Host	smart-5358f816-e164-4ee2-a76c-217c1e65e570
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174034219 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.4174034219
Directory	/workspace/2.chip_sw_otp_ctrl_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pattgen_ios.2621932296
Short name	T358
Test name
Test status
Simulation time	2704939448 ps
CPU time	276.05 seconds
Started	Jul 24 08:12:19 PM PDT 24
Finished	Jul 24 08:16:56 PM PDT 24
Peak memory	611856 kb
Host	smart-da314a06-a68f-43e6-a51a-c877db6d1478
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621932296 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2621932296
Directory	/workspace/2.chip_sw_pattgen_ios/latest

---

Test location	/workspace/coverage/default/2.chip_sw_plic_sw_irq.232840430
Short name	T787
Test name
Test status
Simulation time	3006896694 ps
CPU time	342.75 seconds
Started	Jul 24 08:16:47 PM PDT 24
Finished	Jul 24 08:22:30 PM PDT 24
Peak memory	609840 kb
Host	smart-4310c845-a73b-47c9-88d7-34f59efcd6d8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232840430 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_plic_sw_irq.232840430
Directory	/workspace/2.chip_sw_plic_sw_irq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_power_idle_load.2397408860
Short name	T1434
Test name
Test status
Simulation time	4498333350 ps
CPU time	655.65 seconds
Started	Jul 24 08:18:44 PM PDT 24
Finished	Jul 24 08:29:40 PM PDT 24
Peak memory	609816 kb
Host	smart-119ec92a-2ddb-463f-a873-9ddcf7b6491f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397408860 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.2397408860
Directory	/workspace/2.chip_sw_power_idle_load/latest

---

Test location	/workspace/coverage/default/2.chip_sw_power_sleep_load.1768446595
Short name	T1352
Test name
Test status
Simulation time	10146595836 ps
CPU time	536.82 seconds
Started	Jul 24 08:17:57 PM PDT 24
Finished	Jul 24 08:26:55 PM PDT 24
Peak memory	611420 kb
Host	smart-0973b3ad-8b42-4cda-96f0-c11fd1f4a0f5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768446595 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.1768446595
Directory	/workspace/2.chip_sw_power_sleep_load/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.367750875
Short name	T542
Test name
Test status
Simulation time	10863037869 ps
CPU time	1284.03 seconds
Started	Jul 24 08:12:15 PM PDT 24
Finished	Jul 24 08:33:40 PM PDT 24
Peak memory	611908 kb
Host	smart-92490543-64c4-456a-9524-666d074bbc06
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677 50875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.367750875
Directory	/workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2528660945
Short name	T1213
Test name
Test status
Simulation time	25178182528 ps
CPU time	2196.66 seconds
Started	Jul 24 08:18:33 PM PDT 24
Finished	Jul 24 08:55:11 PM PDT 24
Peak memory	610852 kb
Host	smart-12757777-61c7-48ee-8de0-71bbf9ac9d68
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252 8660945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2528660945
Directory	/workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2696107911
Short name	T1184
Test name
Test status
Simulation time	16120752610 ps
CPU time	1412.46 seconds
Started	Jul 24 08:14:03 PM PDT 24
Finished	Jul 24 08:37:36 PM PDT 24
Peak memory	611656 kb
Host	smart-6ebbf2c5-76a1-43e8-b5be-b9d10214cd3e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2696107911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2696107911
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2443593919
Short name	T105
Test name
Test status
Simulation time	24878720586 ps
CPU time	1485.88 seconds
Started	Jul 24 08:19:29 PM PDT 24
Finished	Jul 24 08:44:15 PM PDT 24
Peak memory	611432 kb
Host	smart-c290901b-7124-45ba-95aa-2722f3525220
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2443593919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2443593919
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.840679432
Short name	T801
Test name
Test status
Simulation time	8857217232 ps
CPU time	747.62 seconds
Started	Jul 24 08:13:58 PM PDT 24
Finished	Jul 24 08:26:26 PM PDT 24
Peak memory	611288 kb
Host	smart-cafe57b8-5c71-411f-9ae3-16c38cdfe0a4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840679432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.840679432
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2730862712
Short name	T125
Test name
Test status
Simulation time	7537167320 ps
CPU time	459.5 seconds
Started	Jul 24 08:14:06 PM PDT 24
Finished	Jul 24 08:21:46 PM PDT 24
Peak memory	618132 kb
Host	smart-8de3bd8f-0077-4840-aea0-bed497675914
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2730862712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2730862712
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2277510305
Short name	T435
Test name
Test status
Simulation time	8412501145 ps
CPU time	569.04 seconds
Started	Jul 24 08:12:31 PM PDT 24
Finished	Jul 24 08:22:01 PM PDT 24
Peak memory	610908 kb
Host	smart-bc273ee7-6997-4491-a330-9fb6fc9cdd31
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277510305 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.2277510305
Directory	/workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.750203685
Short name	T349
Test name
Test status
Simulation time	3418684900 ps
CPU time	446.36 seconds
Started	Jul 24 08:17:12 PM PDT 24
Finished	Jul 24 08:24:39 PM PDT 24
Peak memory	610196 kb
Host	smart-796fc0c5-3727-4245-a4b3-5a5913045894
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750203685 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.750203685
Directory	/workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.715018136
Short name	T1134
Test name
Test status
Simulation time	4135233252 ps
CPU time	465.97 seconds
Started	Jul 24 08:12:58 PM PDT 24
Finished	Jul 24 08:20:44 PM PDT 24
Peak memory	617368 kb
Host	smart-51c06890-4093-49b9-813f-4634722699d8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=715018136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.715018136
Directory	/workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2381393568
Short name	T1107
Test name
Test status
Simulation time	13193809735 ps
CPU time	1648.12 seconds
Started	Jul 24 08:12:06 PM PDT 24
Finished	Jul 24 08:39:34 PM PDT 24
Peak memory	611824 kb
Host	smart-11e422e3-7725-4de3-a793-90d6b52862cd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381393568 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2381393568
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2930642538
Short name	T417
Test name
Test status
Simulation time	7680376142 ps
CPU time	550.73 seconds
Started	Jul 24 08:17:10 PM PDT 24
Finished	Jul 24 08:26:21 PM PDT 24
Peak memory	610956 kb
Host	smart-396180e0-f22f-472f-a858-0d12b458b7b8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930642538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2930642538
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3270074485
Short name	T422
Test name
Test status
Simulation time	6103918611 ps
CPU time	620.43 seconds
Started	Jul 24 08:15:06 PM PDT 24
Finished	Jul 24 08:25:27 PM PDT 24
Peak memory	610932 kb
Host	smart-c8d4dfe3-23cf-4769-8a74-58ee7b0fb05f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270074485 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3270074485
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2316869727
Short name	T98
Test name
Test status
Simulation time	21568306362 ps
CPU time	2464.23 seconds
Started	Jul 24 08:13:02 PM PDT 24
Finished	Jul 24 08:54:06 PM PDT 24
Peak memory	611668 kb
Host	smart-e106a6bc-e3da-4d0b-b1b2-be149f4f793f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2316869727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2316869727
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3952278655
Short name	T20
Test name
Test status
Simulation time	20084365068 ps
CPU time	1362.83 seconds
Started	Jul 24 08:16:28 PM PDT 24
Finished	Jul 24 08:39:12 PM PDT 24
Peak memory	611172 kb
Host	smart-b3ea87ca-8ec5-4ed3-8b69-c2ac6e7935e8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3952278655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3952278655
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.77369142
Short name	T1024
Test name
Test status
Simulation time	39095227725 ps
CPU time	2864.9 seconds
Started	Jul 24 08:13:54 PM PDT 24
Finished	Jul 24 09:01:40 PM PDT 24
Peak memory	612376 kb
Host	smart-211a6a02-b619-490e-8655-e47be38767da
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77369142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitch _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sle ep_power_glitch_reset.77369142
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2522573741
Short name	T380
Test name
Test status
Simulation time	5495891030 ps
CPU time	457.33 seconds
Started	Jul 24 08:17:17 PM PDT 24
Finished	Jul 24 08:24:54 PM PDT 24
Peak memory	611648 kb
Host	smart-cf98d089-1a62-4ae5-9c2f-fe7359d0c1ad
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2522573741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2522573741
Directory	/workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.671271937
Short name	T786
Test name
Test status
Simulation time	2851711376 ps
CPU time	381.98 seconds
Started	Jul 24 08:13:32 PM PDT 24
Finished	Jul 24 08:19:54 PM PDT 24
Peak memory	610312 kb
Host	smart-0e4f874c-1ed5-4e63-9720-cd7eb5f549d3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671271937 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.671271937
Directory	/workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3771324506
Short name	T1177
Test name
Test status
Simulation time	4682133910 ps
CPU time	427.86 seconds
Started	Jul 24 08:12:11 PM PDT 24
Finished	Jul 24 08:19:19 PM PDT 24
Peak memory	617596 kb
Host	smart-9c5a8a0b-840f-4206-97dc-3d9f8fdebc0d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3771324506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.3771324506
Directory	/workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.548154033
Short name	T130
Test name
Test status
Simulation time	5351540400 ps
CPU time	469.57 seconds
Started	Jul 24 08:15:43 PM PDT 24
Finished	Jul 24 08:23:33 PM PDT 24
Peak memory	610348 kb
Host	smart-7de959c7-95b6-47c2-9b1a-023454ae49fc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54815403 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.548154033
Directory	/workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4270781197
Short name	T1042
Test name
Test status
Simulation time	6482132278 ps
CPU time	636.51 seconds
Started	Jul 24 08:17:42 PM PDT 24
Finished	Jul 24 08:28:19 PM PDT 24
Peak memory	610880 kb
Host	smart-b357bc5f-d58b-44ed-9de8-f821d80b6034
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4270781197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.4270781197
Directory	/workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1586909440
Short name	T1185
Test name
Test status
Simulation time	5179039248 ps
CPU time	439.6 seconds
Started	Jul 24 08:20:30 PM PDT 24
Finished	Jul 24 08:27:50 PM PDT 24
Peak memory	611012 kb
Host	smart-5889e663-31cf-4afe-8d68-5bcb6c7dd8a4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586909440 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1586909440
Directory	/workspace/2.chip_sw_pwrmgr_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3955900726
Short name	T1090
Test name
Test status
Simulation time	6968570273 ps
CPU time	989.19 seconds
Started	Jul 24 08:13:13 PM PDT 24
Finished	Jul 24 08:29:43 PM PDT 24
Peak memory	611064 kb
Host	smart-0648d411-d860-428d-8907-77dbdb0236f7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955900726 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.3955900726
Directory	/workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2391853870
Short name	T1306
Test name
Test status
Simulation time	4494542544 ps
CPU time	513.01 seconds
Started	Jul 24 08:13:18 PM PDT 24
Finished	Jul 24 08:21:51 PM PDT 24
Peak memory	610976 kb
Host	smart-e852b990-84bf-4e05-9a55-5e0c19c8143b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391853870 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2391853870
Directory	/workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1778356494
Short name	T1146
Test name
Test status
Simulation time	5908177720 ps
CPU time	532.02 seconds
Started	Jul 24 08:18:55 PM PDT 24
Finished	Jul 24 08:27:47 PM PDT 24
Peak memory	610604 kb
Host	smart-32e7ee60-1cb0-4e76-9693-68a88cd3a1cd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778356494 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1778356494
Directory	/workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.452890069
Short name	T977
Test name
Test status
Simulation time	4388759038 ps
CPU time	394.62 seconds
Started	Jul 24 08:18:04 PM PDT 24
Finished	Jul 24 08:24:39 PM PDT 24
Peak memory	610792 kb
Host	smart-c23394e4-4d92-4165-b8db-082d15f17efd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452 890069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.452890069
Directory	/workspace/2.chip_sw_pwrmgr_wdog_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.719412550
Short name	T1384
Test name
Test status
Simulation time	8869784412 ps
CPU time	605.57 seconds
Started	Jul 24 08:16:04 PM PDT 24
Finished	Jul 24 08:26:10 PM PDT 24
Peak memory	625344 kb
Host	smart-f43b1c14-dc0f-43ba-b6fe-65cd2da63dfb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719412550 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.719412550
Directory	/workspace/2.chip_sw_rom_ctrl_integrity_check/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1916004209
Short name	T245
Test name
Test status
Simulation time	5664149604 ps
CPU time	578.41 seconds
Started	Jul 24 08:13:18 PM PDT 24
Finished	Jul 24 08:22:57 PM PDT 24
Peak memory	610916 kb
Host	smart-eb43eb28-c1c7-4649-9e0a-f51b3b041c59
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916004209 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1916004209
Directory	/workspace/2.chip_sw_rstmgr_cpu_info/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1250675501
Short name	T835
Test name
Test status
Simulation time	5099042720 ps
CPU time	646.11 seconds
Started	Jul 24 08:10:39 PM PDT 24
Finished	Jul 24 08:21:26 PM PDT 24
Peak memory	641880 kb
Host	smart-a59f4b9a-50ba-42b8-bb35-5639fdcb9ce4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1250675501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.1250675501
Directory	/workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1891863215
Short name	T1425
Test name
Test status
Simulation time	3328788922 ps
CPU time	255.3 seconds
Started	Jul 24 08:19:06 PM PDT 24
Finished	Jul 24 08:23:22 PM PDT 24
Peak memory	610208 kb
Host	smart-fd243f9b-75a0-49fb-aef8-28a5da8d46db
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891863215 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.1891863215
Directory	/workspace/2.chip_sw_rstmgr_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3727734993
Short name	T978
Test name
Test status
Simulation time	5030383892 ps
CPU time	494.22 seconds
Started	Jul 24 08:12:00 PM PDT 24
Finished	Jul 24 08:20:14 PM PDT 24
Peak memory	610532 kb
Host	smart-9b491355-0e1f-4106-948c-55a10d338385
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727734993 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.3727734993
Directory	/workspace/2.chip_sw_rstmgr_sw_req/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3663176028
Short name	T397
Test name
Test status
Simulation time	2916097952 ps
CPU time	292.19 seconds
Started	Jul 24 08:11:36 PM PDT 24
Finished	Jul 24 08:16:29 PM PDT 24
Peak memory	609836 kb
Host	smart-459dc02a-6186-4e2f-8f49-b6e3ab20a7d5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663176028 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3663176028
Directory	/workspace/2.chip_sw_rstmgr_sw_rst/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1023445299
Short name	T305
Test name
Test status
Simulation time	2368931955 ps
CPU time	219.99 seconds
Started	Jul 24 08:18:09 PM PDT 24
Finished	Jul 24 08:21:50 PM PDT 24
Peak memory	609804 kb
Host	smart-a2f4e9bb-9046-4cce-ab6a-faf702a9a8fb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023445299 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.1023445299
Directory	/workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.961232936
Short name	T426
Test name
Test status
Simulation time	4995676828 ps
CPU time	1030.11 seconds
Started	Jul 24 08:14:29 PM PDT 24
Finished	Jul 24 08:31:39 PM PDT 24
Peak memory	609908 kb
Host	smart-85501559-9ad1-45f3-b159-de189a1abb17
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96123 2936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.961232936
Directory	/workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2830544606
Short name	T1009
Test name
Test status
Simulation time	6051956746 ps
CPU time	1112.96 seconds
Started	Jul 24 08:13:53 PM PDT 24
Finished	Jul 24 08:32:26 PM PDT 24
Peak memory	609856 kb
Host	smart-5f9d13f3-6ae6-4283-b5f7-b6ca6d55da01
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2830544606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.2830544606
Directory	/workspace/2.chip_sw_rv_core_ibex_rnd/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1476705929
Short name	T761
Test name
Test status
Simulation time	6529003275 ps
CPU time	889.84 seconds
Started	Jul 24 08:20:31 PM PDT 24
Finished	Jul 24 08:35:21 PM PDT 24
Peak memory	624672 kb
Host	smart-d3fb1fde-e994-4327-8758-3fd8913da186
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476705929 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.1476705929
Directory	/workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3386324816
Short name	T1120
Test name
Test status
Simulation time	6381447480 ps
CPU time	592.18 seconds
Started	Jul 24 08:17:36 PM PDT 24
Finished	Jul 24 08:27:29 PM PDT 24
Peak memory	624248 kb
Host	smart-daf63db8-dc19-4001-b265-74978eb12579
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386324816 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.3386324816
Directory	/workspace/2.chip_sw_rv_dm_access_after_wakeup/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.378993695
Short name	T312
Test name
Test status
Simulation time	4874522660 ps
CPU time	573.83 seconds
Started	Jul 24 08:16:50 PM PDT 24
Finished	Jul 24 08:26:24 PM PDT 24
Peak memory	619736 kb
Host	smart-c9ce4ef2-2060-4350-bd5c-9299b0b92dae
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378993 695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.378993695
Directory	/workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3127512286
Short name	T342
Test name
Test status
Simulation time	3036004504 ps
CPU time	228.92 seconds
Started	Jul 24 08:19:30 PM PDT 24
Finished	Jul 24 08:23:20 PM PDT 24
Peak memory	609848 kb
Host	smart-d630114d-29c9-4009-aa45-3d34bfe17ff6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127512286 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.3127512286
Directory	/workspace/2.chip_sw_rv_plic_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_irq.3355971181
Short name	T1296
Test name
Test status
Simulation time	3178233688 ps
CPU time	188.25 seconds
Started	Jul 24 08:15:05 PM PDT 24
Finished	Jul 24 08:18:14 PM PDT 24
Peak memory	609984 kb
Host	smart-ec90f2b3-6303-43d4-bbff-0c31c28dfd9a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355971181 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.3355971181
Directory	/workspace/2.chip_sw_rv_timer_irq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1436446507
Short name	T1385
Test name
Test status
Simulation time	3044616190 ps
CPU time	313.35 seconds
Started	Jul 24 08:20:13 PM PDT 24
Finished	Jul 24 08:25:26 PM PDT 24
Peak memory	610088 kb
Host	smart-0fb71b3e-5fc3-469a-954b-0d62937f55ef
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436446507 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.1436446507
Directory	/workspace/2.chip_sw_rv_timer_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.4233461645
Short name	T138
Test name
Test status
Simulation time	5951858370 ps
CPU time	639.67 seconds
Started	Jul 24 08:17:00 PM PDT 24
Finished	Jul 24 08:27:40 PM PDT 24
Peak memory	610680 kb
Host	smart-074b2b32-21cc-4900-85a8-33fafec3c6f0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42334616 45 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.4233461645
Directory	/workspace/2.chip_sw_sensor_ctrl_alert/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3895835147
Short name	T142
Test name
Test status
Simulation time	3193922531 ps
CPU time	357.98 seconds
Started	Jul 24 08:15:30 PM PDT 24
Finished	Jul 24 08:21:29 PM PDT 24
Peak memory	611148 kb
Host	smart-d865246d-333d-4a9c-88ed-78e0651251dd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895835 147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3895835147
Directory	/workspace/2.chip_sw_sensor_ctrl_status/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1163138496
Short name	T1121
Test name
Test status
Simulation time	8841219050 ps
CPU time	1582.98 seconds
Started	Jul 24 08:10:27 PM PDT 24
Finished	Jul 24 08:36:51 PM PDT 24
Peak memory	610360 kb
Host	smart-857122fc-cd14-45b9-8d4f-25a8aded6ef4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163138496 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.1163138496
Directory	/workspace/2.chip_sw_sleep_pwm_pulses/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3649385481
Short name	T979
Test name
Test status
Simulation time	6358720760 ps
CPU time	573.05 seconds
Started	Jul 24 08:24:02 PM PDT 24
Finished	Jul 24 08:33:36 PM PDT 24
Peak memory	610884 kb
Host	smart-a12561f8-30ce-4185-85ad-37af39154e78
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649385481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.3649385481
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1446551221
Short name	T1018
Test name
Test status
Simulation time	7903750920 ps
CPU time	728.85 seconds
Started	Jul 24 08:15:35 PM PDT 24
Finished	Jul 24 08:27:44 PM PDT 24
Peak memory	611036 kb
Host	smart-0636d083-ce86-43b6-a44e-4e21867c612d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446551221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.1446551221
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

---

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3559868279
Short name	T14
Test name
Test status
Simulation time	4940067682 ps
CPU time	705.01 seconds
Started	Jul 24 08:11:16 PM PDT 24
Finished	Jul 24 08:23:01 PM PDT 24
Peak memory	625560 kb
Host	smart-7abbc0e5-7ed4-4a0d-9a98-f4a121f215b2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559868279 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3559868279
Directory	/workspace/2.chip_sw_spi_device_pass_through/latest

---

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1451657518
Short name	T53
Test name
Test status
Simulation time	3293323769 ps
CPU time	364.44 seconds
Started	Jul 24 08:11:37 PM PDT 24
Finished	Jul 24 08:17:42 PM PDT 24
Peak memory	618228 kb
Host	smart-ff8437f4-b500-401f-b50b-833af8651624
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451657518 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.1451657518
Directory	/workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest

---

Test location	/workspace/coverage/default/2.chip_sw_spi_device_tpm.2712732823
Short name	T44
Test name
Test status
Simulation time	3665418002 ps
CPU time	356.71 seconds
Started	Jul 24 08:11:37 PM PDT 24
Finished	Jul 24 08:17:34 PM PDT 24
Peak memory	619812 kb
Host	smart-3ace7ddd-e928-4186-9528-de3bd54ac9da
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712732823 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.2712732823
Directory	/workspace/2.chip_sw_spi_device_tpm/latest

---

Test location	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3725968210
Short name	T37
Test name
Test status
Simulation time	2365904076 ps
CPU time	249.31 seconds
Started	Jul 24 08:10:53 PM PDT 24
Finished	Jul 24 08:15:02 PM PDT 24
Peak memory	610708 kb
Host	smart-b685ae3e-9d43-4810-aa99-843e413d6532
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725968210 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3725968210
Directory	/workspace/2.chip_sw_spi_host_tx_rx/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1641380807
Short name	T310
Test name
Test status
Simulation time	8895939527 ps
CPU time	1182.41 seconds
Started	Jul 24 08:16:03 PM PDT 24
Finished	Jul 24 08:35:45 PM PDT 24
Peak memory	611096 kb
Host	smart-634891be-f2ea-49fe-a5cc-1ec9157b3339
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641380807 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.1641380807
Directory	/workspace/2.chip_sw_sram_ctrl_execution_main/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1555764447
Short name	T177
Test name
Test status
Simulation time	4891090730 ps
CPU time	814.56 seconds
Started	Jul 24 08:16:13 PM PDT 24
Finished	Jul 24 08:29:49 PM PDT 24
Peak memory	611500 kb
Host	smart-cc3613f5-68f0-4f47-9128-14656773cffd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555764447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.1555764447
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2578560325
Short name	T1287
Test name
Test status
Simulation time	4595864526 ps
CPU time	571.74 seconds
Started	Jul 24 08:16:47 PM PDT 24
Finished	Jul 24 08:26:19 PM PDT 24
Peak memory	611120 kb
Host	smart-80b53111-4124-4169-bbc6-1dfcbfd89f51
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578560325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2578560325
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3448216168
Short name	T1165
Test name
Test status
Simulation time	4193021264 ps
CPU time	641.57 seconds
Started	Jul 24 08:18:05 PM PDT 24
Finished	Jul 24 08:28:47 PM PDT 24
Peak memory	611104 kb
Host	smart-6fc3b254-79ce-45ca-8bfa-61750583ced9
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448216168 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3448216168
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3982201154
Short name	T1244
Test name
Test status
Simulation time	3013256760 ps
CPU time	375.44 seconds
Started	Jul 24 08:20:01 PM PDT 24
Finished	Jul 24 08:26:17 PM PDT 24
Peak memory	610060 kb
Host	smart-984a55a1-8a04-4e09-995d-8b99bcfbab34
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982201154 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3982201154
Directory	/workspace/2.chip_sw_sram_ctrl_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.179313259
Short name	T1436
Test name
Test status
Simulation time	20617341081 ps
CPU time	2770.53 seconds
Started	Jul 24 08:18:03 PM PDT 24
Finished	Jul 24 09:04:14 PM PDT 24
Peak memory	610020 kb
Host	smart-9b5e2539-c715-4d83-95cd-7e441995792a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179313259 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.179313259
Directory	/workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3361220222
Short name	T207
Test name
Test status
Simulation time	4875560962 ps
CPU time	617.14 seconds
Started	Jul 24 08:14:17 PM PDT 24
Finished	Jul 24 08:24:36 PM PDT 24
Peak memory	613940 kb
Host	smart-bcaabd49-727a-4323-8314-5c20bb1c6800
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361220222 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.3361220222
Directory	/workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2250160118
Short name	T203
Test name
Test status
Simulation time	3369261812 ps
CPU time	278.55 seconds
Started	Jul 24 08:15:13 PM PDT 24
Finished	Jul 24 08:19:52 PM PDT 24
Peak memory	613740 kb
Host	smart-4ce4cdfd-6133-448f-9a16-c19ce4067a31
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250160118 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.2250160118
Directory	/workspace/2.chip_sw_sysrst_ctrl_inputs/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.242488121
Short name	T208
Test name
Test status
Simulation time	3134267368 ps
CPU time	375.06 seconds
Started	Jul 24 08:12:59 PM PDT 24
Finished	Jul 24 08:19:14 PM PDT 24
Peak memory	609852 kb
Host	smart-902d960a-c109-4667-aafe-c070865271bf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242488121 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.242488121
Directory	/workspace/2.chip_sw_sysrst_ctrl_outputs/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1902638438
Short name	T23
Test name
Test status
Simulation time	24784069770 ps
CPU time	1493.3 seconds
Started	Jul 24 08:14:01 PM PDT 24
Finished	Jul 24 08:38:55 PM PDT 24
Peak memory	615624 kb
Host	smart-283d4592-75fe-4414-a465-eeccf4605e35
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19026384 38 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.1902638438
Directory	/workspace/2.chip_sw_sysrst_ctrl_reset/latest

---

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.258375096
Short name	T41
Test name
Test status
Simulation time	7152500760 ps
CPU time	690.45 seconds
Started	Jul 24 08:14:11 PM PDT 24
Finished	Jul 24 08:25:42 PM PDT 24
Peak memory	610760 kb
Host	smart-69b7c26a-6344-4f7b-a80a-54b6b66e86e3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258375096 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.258375096
Directory	/workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

---

Test location	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2852864701
Short name	T1355
Test name
Test status
Simulation time	4598535296 ps
CPU time	598.88 seconds
Started	Jul 24 08:10:31 PM PDT 24
Finished	Jul 24 08:20:30 PM PDT 24
Peak memory	619252 kb
Host	smart-a04845a4-7df1-4216-af5d-d1fab6d974c1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2852864701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.2852864701
Directory	/workspace/2.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/2.chip_sw_uart_smoketest.2039436622
Short name	T1227
Test name
Test status
Simulation time	2989843824 ps
CPU time	322.79 seconds
Started	Jul 24 08:21:06 PM PDT 24
Finished	Jul 24 08:26:29 PM PDT 24
Peak memory	617716 kb
Host	smart-67dbe652-58e0-4688-b23e-5b57c35264bf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039436622 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.2039436622
Directory	/workspace/2.chip_sw_uart_smoketest/latest

---

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx.3711775395
Short name	T1400
Test name
Test status
Simulation time	4600252292 ps
CPU time	745.37 seconds
Started	Jul 24 08:12:03 PM PDT 24
Finished	Jul 24 08:24:29 PM PDT 24
Peak memory	625212 kb
Host	smart-120b7527-bc50-46f7-bcf8-fce477bc5571
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711775395 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3711775395
Directory	/workspace/2.chip_sw_uart_tx_rx/latest

---

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3430711713
Short name	T1419
Test name
Test status
Simulation time	13381906450 ps
CPU time	1946.55 seconds
Started	Jul 24 08:09:53 PM PDT 24
Finished	Jul 24 08:42:20 PM PDT 24
Peak memory	619196 kb
Host	smart-beb12202-dfda-47b9-b19e-ebd02095fded
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430711713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.3430711713
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

---

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3701937987
Short name	T315
Test name
Test status
Simulation time	5328294755 ps
CPU time	505.19 seconds
Started	Jul 24 08:11:07 PM PDT 24
Finished	Jul 24 08:19:33 PM PDT 24
Peak memory	625096 kb
Host	smart-4a241e13-b925-4384-a95d-d95d3bfae0f0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701937987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3701937987
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

---

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.4244744545
Short name	T1171
Test name
Test status
Simulation time	79129293480 ps
CPU time	14177 seconds
Started	Jul 24 08:10:11 PM PDT 24
Finished	Jul 25 12:06:30 AM PDT 24
Peak memory	635576 kb
Host	smart-db6499b8-085f-48b5-991e-5a1c5207b4f5
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4244744545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.4244744545
Directory	/workspace/2.chip_sw_uart_tx_rx_bootstrap/latest

---

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1621578224
Short name	T299
Test name
Test status
Simulation time	4211074936 ps
CPU time	673.23 seconds
Started	Jul 24 08:10:29 PM PDT 24
Finished	Jul 24 08:21:43 PM PDT 24
Peak memory	625196 kb
Host	smart-ec6425f7-fa7f-4d16-bbda-c907b19b566a
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621578224 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.1621578224
Directory	/workspace/2.chip_sw_uart_tx_rx_idx1/latest

---

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.39891793
Short name	T1069
Test name
Test status
Simulation time	4996366040 ps
CPU time	760.51 seconds
Started	Jul 24 08:10:13 PM PDT 24
Finished	Jul 24 08:22:54 PM PDT 24
Peak memory	625216 kb
Host	smart-b24b62f2-555e-47fa-8d19-821bf611c7b1
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39891793 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.39891793
Directory	/workspace/2.chip_sw_uart_tx_rx_idx2/latest

---

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3289177725
Short name	T1141
Test name
Test status
Simulation time	4384577956 ps
CPU time	751.93 seconds
Started	Jul 24 08:11:33 PM PDT 24
Finished	Jul 24 08:24:05 PM PDT 24
Peak memory	625172 kb
Host	smart-e523c5da-d38f-4c97-af34-c5b70fdff7e6
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289177725 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.3289177725
Directory	/workspace/2.chip_sw_uart_tx_rx_idx3/latest

---

Test location	/workspace/coverage/default/2.chip_tap_straps_prod.675364988
Short name	T65
Test name
Test status
Simulation time	2484085110 ps
CPU time	150.6 seconds
Started	Jul 24 08:20:38 PM PDT 24
Finished	Jul 24 08:23:09 PM PDT 24
Peak memory	620620 kb
Host	smart-7ef56542-3c47-48e6-b47a-dd94c45d3600
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675364988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.675364988
Directory	/workspace/2.chip_tap_straps_prod/latest

---

Test location	/workspace/coverage/default/2.chip_tap_straps_testunlock0.2015284429
Short name	T1410
Test name
Test status
Simulation time	3589526710 ps
CPU time	312.42 seconds
Started	Jul 24 08:16:46 PM PDT 24
Finished	Jul 24 08:21:58 PM PDT 24
Peak memory	623916 kb
Host	smart-ee682a7a-0694-48ca-be82-e4eee9cca31b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015284429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.2015284429
Directory	/workspace/2.chip_tap_straps_testunlock0/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_dev.1351912679
Short name	T1006
Test name
Test status
Simulation time	15094407886 ps
CPU time	3052.13 seconds
Started	Jul 24 08:26:23 PM PDT 24
Finished	Jul 24 09:17:16 PM PDT 24
Peak memory	610828 kb
Host	smart-4abf15a3-cec9-4c0f-a77e-3ff6214cda86
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351912679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.1351912679
Directory	/workspace/2.rom_e2e_asm_init_dev/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_prod.3889005372
Short name	T1143
Test name
Test status
Simulation time	15766034203 ps
CPU time	3100.45 seconds
Started	Jul 24 08:24:45 PM PDT 24
Finished	Jul 24 09:16:26 PM PDT 24
Peak memory	610508 kb
Host	smart-fee214ca-9e07-4ed3-9b3f-3f513303307c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889005372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.3889005372
Directory	/workspace/2.rom_e2e_asm_init_prod/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3375583289
Short name	T992
Test name
Test status
Simulation time	15423527868 ps
CPU time	3177.47 seconds
Started	Jul 24 08:22:21 PM PDT 24
Finished	Jul 24 09:15:19 PM PDT 24
Peak memory	611856 kb
Host	smart-f336e713-6c19-4e64-9d22-acbd8a2f5a32
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375583289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.3375583289
Directory	/workspace/2.rom_e2e_asm_init_prod_end/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_rma.1051695274
Short name	T1241
Test name
Test status
Simulation time	14552062582 ps
CPU time	2843.15 seconds
Started	Jul 24 08:23:30 PM PDT 24
Finished	Jul 24 09:10:54 PM PDT 24
Peak memory	611800 kb
Host	smart-8c3d12e5-3d40-4954-b91f-bf0c93a90eca
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051695274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.1051695274
Directory	/workspace/2.rom_e2e_asm_init_rma/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3523662503
Short name	T1072
Test name
Test status
Simulation time	11434867315 ps
CPU time	2292.8 seconds
Started	Jul 24 08:23:15 PM PDT 24
Finished	Jul 24 09:01:28 PM PDT 24
Peak memory	610036 kb
Host	smart-fd1971f8-2f31-4448-82c4-a1b6fe519a1d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523662503 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.3523662503
Directory	/workspace/2.rom_e2e_asm_init_test_unlocked0/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1366077581
Short name	T1198
Test name
Test status
Simulation time	14967761960 ps
CPU time	3056.65 seconds
Started	Jul 24 08:23:17 PM PDT 24
Finished	Jul 24 09:14:15 PM PDT 24
Peak memory	610780 kb
Host	smart-c50fa8ca-96d0-458f-9396-243a2b2a61d9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366077581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.1366077581
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1387931685
Short name	T285
Test name
Test status
Simulation time	14291045310 ps
CPU time	3052.53 seconds
Started	Jul 24 08:24:11 PM PDT 24
Finished	Jul 24 09:15:04 PM PDT 24
Peak memory	610644 kb
Host	smart-2325ea30-7ef3-4a74-9497-42130ddb751e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387931685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.1387931685
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_self_hash.2420801824
Short name	T1196
Test name
Test status
Simulation time	26231254322 ps
CPU time	6501.5 seconds
Started	Jul 24 08:24:28 PM PDT 24
Finished	Jul 24 10:12:50 PM PDT 24
Peak memory	610680 kb
Host	smart-89c0fb56-7ee6-4c0f-a298-03ee62034fc1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420801824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.2420801824
Directory	/workspace/2.rom_e2e_self_hash/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.314182133
Short name	T284
Test name
Test status
Simulation time	14551135716 ps
CPU time	3370.17 seconds
Started	Jul 24 08:23:04 PM PDT 24
Finished	Jul 24 09:19:15 PM PDT 24
Peak memory	611740 kb
Host	smart-ef801050-de45-4ad6-bd6b-7819bc93b9b3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314182133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_s hutdown_exception_c.314182133
Directory	/workspace/2.rom_e2e_shutdown_exception_c/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_shutdown_output.3675753094
Short name	T276
Test name
Test status
Simulation time	23744887740 ps
CPU time	2719.97 seconds
Started	Jul 24 08:25:35 PM PDT 24
Finished	Jul 24 09:10:55 PM PDT 24
Peak memory	611440 kb
Host	smart-e789b51f-6706-481c-b430-b327009c9810
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675753094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.3675753094
Directory	/workspace/2.rom_e2e_shutdown_output/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_smoke.511056145
Short name	T1293
Test name
Test status
Simulation time	14813876344 ps
CPU time	3203.58 seconds
Started	Jul 24 08:22:46 PM PDT 24
Finished	Jul 24 09:16:10 PM PDT 24
Peak memory	611432 kb
Host	smart-cf2cf85b-505c-40ce-a364-c79f2352cfb4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=511056145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.511056145
Directory	/workspace/2.rom_e2e_smoke/latest

---

Test location	/workspace/coverage/default/2.rom_e2e_static_critical.1320523049
Short name	T1068
Test name
Test status
Simulation time	16470156004 ps
CPU time	3437.19 seconds
Started	Jul 24 08:22:32 PM PDT 24
Finished	Jul 24 09:19:50 PM PDT 24
Peak memory	610380 kb
Host	smart-53f2042e-d744-4cfe-91e4-77588b168714
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320523049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.1320523049
Directory	/workspace/2.rom_e2e_static_critical/latest

---

Test location	/workspace/coverage/default/2.rom_keymgr_functest.3911882592
Short name	T450
Test name
Test status
Simulation time	4789242384 ps
CPU time	650.72 seconds
Started	Jul 24 08:17:51 PM PDT 24
Finished	Jul 24 08:28:42 PM PDT 24
Peak memory	609956 kb
Host	smart-85d97f87-d8ac-42bb-93e8-9faff6d1c92c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911882592 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.3911882592
Directory	/workspace/2.rom_keymgr_functest/latest

---

Test location	/workspace/coverage/default/2.rom_raw_unlock.2581599805
Short name	T1297
Test name
Test status
Simulation time	6553103925 ps
CPU time	279.66 seconds
Started	Jul 24 08:20:07 PM PDT 24
Finished	Jul 24 08:24:47 PM PDT 24
Peak memory	620820 kb
Host	smart-40b97d9f-49cc-45df-b908-56882e61e408
User	root
Command	/workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2581599805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.2581599805
Directory	/workspace/2.rom_raw_unlock/latest

---

Test location	/workspace/coverage/default/2.rom_volatile_raw_unlock.3224583436
Short name	T765
Test name
Test status
Simulation time	2458105998 ps
CPU time	129.15 seconds
Started	Jul 24 08:18:36 PM PDT 24
Finished	Jul 24 08:20:46 PM PDT 24
Peak memory	623536 kb
Host	smart-aa50779a-ccb3-4f4b-b3e7-7079363f69e1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224583436 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.3224583436
Directory	/workspace/2.rom_volatile_raw_unlock/latest

---

Test location	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1833842345
Short name	T386
Test name
Test status
Simulation time	3150007000 ps
CPU time	375.75 seconds
Started	Jul 24 08:23:53 PM PDT 24
Finished	Jul 24 08:30:09 PM PDT 24
Peak memory	648964 kb
Host	smart-e66d4e7f-56e5-40f3-9371-38398c5c36de
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833842345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1833842345
Directory	/workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/20.chip_sw_all_escalation_resets.1552236432
Short name	T1240
Test name
Test status
Simulation time	6166774092 ps
CPU time	697.08 seconds
Started	Jul 24 08:23:44 PM PDT 24
Finished	Jul 24 08:35:21 PM PDT 24
Peak memory	650560 kb
Host	smart-5cd60230-df98-4e6e-95d6-26dda7a0529b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1552236432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.1552236432
Directory	/workspace/20.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.451873409
Short name	T1106
Test name
Test status
Simulation time	3142993942 ps
CPU time	354.09 seconds
Started	Jul 24 08:25:17 PM PDT 24
Finished	Jul 24 08:31:11 PM PDT 24
Peak memory	649200 kb
Host	smart-c9e93db0-bca0-44ec-b93d-ad7af69c39b0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451873409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_s w_alert_handler_lpg_sleep_mode_alerts.451873409
Directory	/workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/21.chip_sw_all_escalation_resets.3265007635
Short name	T828
Test name
Test status
Simulation time	6663386090 ps
CPU time	637.31 seconds
Started	Jul 24 08:28:31 PM PDT 24
Finished	Jul 24 08:39:09 PM PDT 24
Peak memory	620152 kb
Host	smart-61ba570d-7c37-448a-a739-871ef032e872
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3265007635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3265007635
Directory	/workspace/21.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3805030774
Short name	T1388
Test name
Test status
Simulation time	3946238548 ps
CPU time	462.34 seconds
Started	Jul 24 08:22:48 PM PDT 24
Finished	Jul 24 08:30:30 PM PDT 24
Peak memory	649016 kb
Host	smart-d8830a63-3991-48e5-97c8-a5d7a67e77d9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805030774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3805030774
Directory	/workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/25.chip_sw_all_escalation_resets.718571241
Short name	T810
Test name
Test status
Simulation time	6387209496 ps
CPU time	705.31 seconds
Started	Jul 24 08:24:09 PM PDT 24
Finished	Jul 24 08:35:55 PM PDT 24
Peak memory	650624 kb
Host	smart-de21b177-0da9-4939-8082-36062beee539
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 718571241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.718571241
Directory	/workspace/25.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2654546553
Short name	T842
Test name
Test status
Simulation time	4349741564 ps
CPU time	403.84 seconds
Started	Jul 24 08:31:05 PM PDT 24
Finished	Jul 24 08:37:49 PM PDT 24
Peak memory	649600 kb
Host	smart-956e0a86-4864-4d2a-8394-a9e7e34a6496
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654546553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2654546553
Directory	/workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/26.chip_sw_all_escalation_resets.2396529720
Short name	T164
Test name
Test status
Simulation time	5036207480 ps
CPU time	504.98 seconds
Started	Jul 24 08:30:40 PM PDT 24
Finished	Jul 24 08:39:06 PM PDT 24
Peak memory	620176 kb
Host	smart-13d18e7e-3fc6-42c9-980a-30972f72ca6e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2396529720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.2396529720
Directory	/workspace/26.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3900109751
Short name	T860
Test name
Test status
Simulation time	3902998550 ps
CPU time	334.58 seconds
Started	Jul 24 08:24:45 PM PDT 24
Finished	Jul 24 08:30:20 PM PDT 24
Peak memory	649632 kb
Host	smart-5344b28e-9e03-430a-85bf-a6b0b131a5f4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900109751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3900109751
Directory	/workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.903207211
Short name	T288
Test name
Test status
Simulation time	3523561500 ps
CPU time	340.59 seconds
Started	Jul 24 08:20:04 PM PDT 24
Finished	Jul 24 08:25:45 PM PDT 24
Peak memory	649344 kb
Host	smart-c8300f26-6def-4596-b8b8-5cf418e7311e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903207211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw _alert_handler_lpg_sleep_mode_alerts.903207211
Directory	/workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1249055735
Short name	T1377
Test name
Test status
Simulation time	7217920398 ps
CPU time	545.36 seconds
Started	Jul 24 08:20:48 PM PDT 24
Finished	Jul 24 08:29:54 PM PDT 24
Peak memory	610672 kb
Host	smart-fff789c5-e963-43ad-a760-66f937a43a4c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1249055735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1249055735
Directory	/workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

---

Test location	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1226979594
Short name	T742
Test name
Test status
Simulation time	23598526450 ps
CPU time	4584.9 seconds
Started	Jul 24 08:20:25 PM PDT 24
Finished	Jul 24 09:36:50 PM PDT 24
Peak memory	610100 kb
Host	smart-77988f31-8f3f-4990-81a0-c41ae8c2daea
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226979594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.1226979594
Directory	/workspace/3.chip_sw_csrng_edn_concurrency/latest

---

Test location	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1405485654
Short name	T292
Test name
Test status
Simulation time	6756335304 ps
CPU time	759.46 seconds
Started	Jul 24 08:20:13 PM PDT 24
Finished	Jul 24 08:32:54 PM PDT 24
Peak memory	611164 kb
Host	smart-6582aec4-98e5-4d53-8b26-590ebc5a9701
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1405485654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.1405485654
Directory	/workspace/3.chip_sw_data_integrity_escalation/latest

---

Test location	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.301973838
Short name	T1040
Test name
Test status
Simulation time	4760994664 ps
CPU time	467.57 seconds
Started	Jul 24 08:21:01 PM PDT 24
Finished	Jul 24 08:28:49 PM PDT 24
Peak memory	620836 kb
Host	smart-db84cc14-cc28-4d2d-8377-858af262ffd9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301973838 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.301973838
Directory	/workspace/3.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2113644007
Short name	T129
Test name
Test status
Simulation time	6631509392 ps
CPU time	933.42 seconds
Started	Jul 24 08:19:03 PM PDT 24
Finished	Jul 24 08:34:37 PM PDT 24
Peak memory	610924 kb
Host	smart-147caec6-7c77-46c5-a79d-3c88f8f60bb5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21136440 07 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.2113644007
Directory	/workspace/3.chip_sw_sensor_ctrl_alert/latest

---

Test location	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1946499944
Short name	T1215
Test name
Test status
Simulation time	5015721632 ps
CPU time	661.84 seconds
Started	Jul 24 08:18:54 PM PDT 24
Finished	Jul 24 08:29:57 PM PDT 24
Peak memory	619588 kb
Host	smart-c0463bc1-4810-43fe-a5ef-3e453782ab90
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1946499944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.1946499944
Directory	/workspace/3.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx.3295986932
Short name	T1105
Test name
Test status
Simulation time	4802615800 ps
CPU time	732.25 seconds
Started	Jul 24 08:20:14 PM PDT 24
Finished	Jul 24 08:32:28 PM PDT 24
Peak memory	625212 kb
Host	smart-b4d119f5-2b92-40b3-84fa-5dbcbb8ede49
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295986932 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.3295986932
Directory	/workspace/3.chip_sw_uart_tx_rx/latest

---

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1493282708
Short name	T1381
Test name
Test status
Simulation time	3589906307 ps
CPU time	547.92 seconds
Started	Jul 24 08:18:48 PM PDT 24
Finished	Jul 24 08:27:57 PM PDT 24
Peak memory	618956 kb
Host	smart-dabaed16-b61a-4631-94de-27cdcf331ddd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493282708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.1493282708
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

---

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2988284732
Short name	T1133
Test name
Test status
Simulation time	4745086657 ps
CPU time	435.99 seconds
Started	Jul 24 08:20:13 PM PDT 24
Finished	Jul 24 08:27:30 PM PDT 24
Peak memory	619288 kb
Host	smart-efbe9001-9669-44ec-9507-0b2ccf13bd85
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988284732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2988284732
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

---

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2504895423
Short name	T1158
Test name
Test status
Simulation time	4299051104 ps
CPU time	512.63 seconds
Started	Jul 24 08:23:06 PM PDT 24
Finished	Jul 24 08:31:39 PM PDT 24
Peak memory	625180 kb
Host	smart-6d18b487-9009-4cd1-ac86-1ef7dad0d4ad
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504895423 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.2504895423
Directory	/workspace/3.chip_sw_uart_tx_rx_idx1/latest

---

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1601046544
Short name	T147
Test name
Test status
Simulation time	4323018980 ps
CPU time	687.52 seconds
Started	Jul 24 08:19:10 PM PDT 24
Finished	Jul 24 08:30:38 PM PDT 24
Peak memory	623284 kb
Host	smart-42834cff-99a6-423b-bd9f-af69e0b995f2
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601046544 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.1601046544
Directory	/workspace/3.chip_sw_uart_tx_rx_idx2/latest

---

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2422865468
Short name	T1065
Test name
Test status
Simulation time	3919114864 ps
CPU time	559.56 seconds
Started	Jul 24 08:22:30 PM PDT 24
Finished	Jul 24 08:31:50 PM PDT 24
Peak memory	625208 kb
Host	smart-259a5cae-1bea-4b44-b0d3-259425a8ae1a
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422865468 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.2422865468
Directory	/workspace/3.chip_sw_uart_tx_rx_idx3/latest

---

Test location	/workspace/coverage/default/3.chip_tap_straps_dev.3802798902
Short name	T1027
Test name
Test status
Simulation time	2647008235 ps
CPU time	199.62 seconds
Started	Jul 24 08:19:37 PM PDT 24
Finished	Jul 24 08:22:57 PM PDT 24
Peak memory	620720 kb
Host	smart-56523734-79b3-4e29-b90a-67c103a66a41
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3802798902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.3802798902
Directory	/workspace/3.chip_tap_straps_dev/latest

---

Test location	/workspace/coverage/default/3.chip_tap_straps_prod.1007500591
Short name	T1254
Test name
Test status
Simulation time	2533125017 ps
CPU time	156.31 seconds
Started	Jul 24 08:19:19 PM PDT 24
Finished	Jul 24 08:21:55 PM PDT 24
Peak memory	621824 kb
Host	smart-0c3ceeed-729f-4d20-b36b-5eed98a46ae5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007500591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.1007500591
Directory	/workspace/3.chip_tap_straps_prod/latest

---

Test location	/workspace/coverage/default/3.chip_tap_straps_testunlock0.4291773780
Short name	T63
Test name
Test status
Simulation time	6858606836 ps
CPU time	724.69 seconds
Started	Jul 24 08:18:50 PM PDT 24
Finished	Jul 24 08:30:55 PM PDT 24
Peak memory	621440 kb
Host	smart-db621d60-9b84-40e5-972b-81838b16f250
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291773780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.4291773780
Directory	/workspace/3.chip_tap_straps_testunlock0/latest

---

Test location	/workspace/coverage/default/30.chip_sw_all_escalation_resets.947334889
Short name	T1201
Test name
Test status
Simulation time	6177317590 ps
CPU time	650.65 seconds
Started	Jul 24 08:24:57 PM PDT 24
Finished	Jul 24 08:35:48 PM PDT 24
Peak memory	650420 kb
Host	smart-5d7de732-c2f4-4ba1-8a60-3b98edf2594a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 947334889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.947334889
Directory	/workspace/30.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3501420264
Short name	T318
Test name
Test status
Simulation time	3461165842 ps
CPU time	350.35 seconds
Started	Jul 24 08:24:42 PM PDT 24
Finished	Jul 24 08:30:33 PM PDT 24
Peak memory	649552 kb
Host	smart-d29e8405-4e13-445d-8588-cd420ff7c267
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501420264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3501420264
Directory	/workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/31.chip_sw_all_escalation_resets.1483731550
Short name	T1412
Test name
Test status
Simulation time	5112944500 ps
CPU time	610.59 seconds
Started	Jul 24 08:24:40 PM PDT 24
Finished	Jul 24 08:34:51 PM PDT 24
Peak memory	620012 kb
Host	smart-8c2cf399-5d94-48bc-888c-a0d7880d91fd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1483731550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.1483731550
Directory	/workspace/31.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1588226417
Short name	T1113
Test name
Test status
Simulation time	3521044250 ps
CPU time	363.47 seconds
Started	Jul 24 08:25:06 PM PDT 24
Finished	Jul 24 08:31:10 PM PDT 24
Peak memory	649120 kb
Host	smart-f9c3f34f-0688-4564-9499-dfcc49c7d7b7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588226417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1588226417
Directory	/workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2097366677
Short name	T252
Test name
Test status
Simulation time	3718312942 ps
CPU time	349.37 seconds
Started	Jul 24 08:26:33 PM PDT 24
Finished	Jul 24 08:32:23 PM PDT 24
Peak memory	649232 kb
Host	smart-d2f49d84-4bfb-43c1-ab1d-780f215c4033
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097366677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2097366677
Directory	/workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.732990256
Short name	T1151
Test name
Test status
Simulation time	3604585348 ps
CPU time	355.58 seconds
Started	Jul 24 08:24:37 PM PDT 24
Finished	Jul 24 08:30:33 PM PDT 24
Peak memory	619316 kb
Host	smart-b3779740-b897-4cf9-a734-c3d02af74555
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732990256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_s w_alert_handler_lpg_sleep_mode_alerts.732990256
Directory	/workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2670401964
Short name	T1149
Test name
Test status
Simulation time	3355258198 ps
CPU time	416.25 seconds
Started	Jul 24 08:24:52 PM PDT 24
Finished	Jul 24 08:31:48 PM PDT 24
Peak memory	649568 kb
Host	smart-08dca4dd-5767-4e43-96ee-1dae81462aa6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670401964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2670401964
Directory	/workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/36.chip_sw_all_escalation_resets.2347388145
Short name	T851
Test name
Test status
Simulation time	5228028600 ps
CPU time	656.22 seconds
Started	Jul 24 08:25:11 PM PDT 24
Finished	Jul 24 08:36:08 PM PDT 24
Peak memory	650448 kb
Host	smart-de054b96-75a9-41e0-827f-048dbe424819
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2347388145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.2347388145
Directory	/workspace/36.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1801484867
Short name	T1
Test name
Test status
Simulation time	3293283550 ps
CPU time	387.71 seconds
Started	Jul 24 08:24:32 PM PDT 24
Finished	Jul 24 08:31:00 PM PDT 24
Peak memory	618980 kb
Host	smart-dee71050-5dbe-4b3e-a914-f44cf3b465af
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801484867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1801484867
Directory	/workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1292674110
Short name	T382
Test name
Test status
Simulation time	4189395880 ps
CPU time	528.87 seconds
Started	Jul 24 08:25:37 PM PDT 24
Finished	Jul 24 08:34:26 PM PDT 24
Peak memory	649188 kb
Host	smart-cd022bd7-26cc-41bf-86eb-59ab7500e1ff
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292674110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1292674110
Directory	/workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/39.chip_sw_all_escalation_resets.2847843550
Short name	T159
Test name
Test status
Simulation time	5724423468 ps
CPU time	584.69 seconds
Started	Jul 24 08:25:58 PM PDT 24
Finished	Jul 24 08:35:43 PM PDT 24
Peak memory	620224 kb
Host	smart-e00d3e07-34b0-44f4-8755-e493f28373d4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2847843550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.2847843550
Directory	/workspace/39.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/4.chip_sw_all_escalation_resets.4101921816
Short name	T850
Test name
Test status
Simulation time	4639048400 ps
CPU time	696.1 seconds
Started	Jul 24 08:22:04 PM PDT 24
Finished	Jul 24 08:33:41 PM PDT 24
Peak memory	650384 kb
Host	smart-80d076d0-1bfb-42c5-9093-8c396580a20b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4101921816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.4101921816
Directory	/workspace/4.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1865977828
Short name	T1329
Test name
Test status
Simulation time	7555608722 ps
CPU time	572.24 seconds
Started	Jul 24 08:20:51 PM PDT 24
Finished	Jul 24 08:30:24 PM PDT 24
Peak memory	609936 kb
Host	smart-eebd5e20-1203-4d6d-9ded-d9c37d6e5c51
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1865977828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1865977828
Directory	/workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

---

Test location	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.317009194
Short name	T1443
Test name
Test status
Simulation time	27372522802 ps
CPU time	6482.84 seconds
Started	Jul 24 08:21:03 PM PDT 24
Finished	Jul 24 10:09:07 PM PDT 24
Peak memory	610448 kb
Host	smart-feed7090-c6f8-431d-a831-dc5902357d26
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317009194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.317009194
Directory	/workspace/4.chip_sw_csrng_edn_concurrency/latest

---

Test location	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3016133262
Short name	T1131
Test name
Test status
Simulation time	5540456474 ps
CPU time	478.66 seconds
Started	Jul 24 08:20:11 PM PDT 24
Finished	Jul 24 08:28:09 PM PDT 24
Peak memory	622008 kb
Host	smart-d08a0d5f-f0fc-485e-809b-27b400ff6b0d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016133262 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.3016133262
Directory	/workspace/4.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.158455113
Short name	T128
Test name
Test status
Simulation time	9085837580 ps
CPU time	828.33 seconds
Started	Jul 24 08:22:30 PM PDT 24
Finished	Jul 24 08:36:19 PM PDT 24
Peak memory	610944 kb
Host	smart-f9246eb5-8b2d-4009-96f4-87b051a9605b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15845511 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.158455113
Directory	/workspace/4.chip_sw_sensor_ctrl_alert/latest

---

Test location	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.563952305
Short name	T1221
Test name
Test status
Simulation time	3126476600 ps
CPU time	387.27 seconds
Started	Jul 24 08:21:17 PM PDT 24
Finished	Jul 24 08:27:45 PM PDT 24
Peak memory	618996 kb
Host	smart-245643bd-62ed-4acb-9bf8-f47338fe173a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=563952305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.563952305
Directory	/workspace/4.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3396248432
Short name	T1344
Test name
Test status
Simulation time	8725873247 ps
CPU time	1469.73 seconds
Started	Jul 24 08:22:23 PM PDT 24
Finished	Jul 24 08:46:54 PM PDT 24
Peak memory	619068 kb
Host	smart-c515ccec-7d71-438b-9cd0-c9b79bacbcfc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396248432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.3396248432
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

---

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1533494542
Short name	T1070
Test name
Test status
Simulation time	4129289500 ps
CPU time	595.95 seconds
Started	Jul 24 08:21:09 PM PDT 24
Finished	Jul 24 08:31:05 PM PDT 24
Peak memory	622992 kb
Host	smart-e28b10f1-bbf0-4e8b-a26b-3d21d76329f3
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533494542 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.1533494542
Directory	/workspace/4.chip_sw_uart_tx_rx_idx1/latest

---

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2763402054
Short name	T1321
Test name
Test status
Simulation time	4316688264 ps
CPU time	728.57 seconds
Started	Jul 24 08:20:59 PM PDT 24
Finished	Jul 24 08:33:07 PM PDT 24
Peak memory	625144 kb
Host	smart-a02e6647-0ef8-4a61-989f-66063919ac6f
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763402054 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.2763402054
Directory	/workspace/4.chip_sw_uart_tx_rx_idx2/latest

---

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.712179844
Short name	T326
Test name
Test status
Simulation time	4567776224 ps
CPU time	640.6 seconds
Started	Jul 24 08:23:34 PM PDT 24
Finished	Jul 24 08:34:16 PM PDT 24
Peak memory	625172 kb
Host	smart-ebc142d0-34b6-4eaf-9a7e-b00534b14e41
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712179844 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.712179844
Directory	/workspace/4.chip_sw_uart_tx_rx_idx3/latest

---

Test location	/workspace/coverage/default/4.chip_tap_straps_dev.2704019780
Short name	T1098
Test name
Test status
Simulation time	3509702736 ps
CPU time	227.23 seconds
Started	Jul 24 08:19:24 PM PDT 24
Finished	Jul 24 08:23:12 PM PDT 24
Peak memory	622572 kb
Host	smart-40a96434-0e24-4f78-b6ea-b9cc15297281
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2704019780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.2704019780
Directory	/workspace/4.chip_tap_straps_dev/latest

---

Test location	/workspace/coverage/default/4.chip_tap_straps_prod.1278368725
Short name	T1264
Test name
Test status
Simulation time	3104253740 ps
CPU time	149.47 seconds
Started	Jul 24 08:20:21 PM PDT 24
Finished	Jul 24 08:22:51 PM PDT 24
Peak memory	620624 kb
Host	smart-23cd678d-a436-456e-a1db-812bd0a0a47b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278368725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.1278368725
Directory	/workspace/4.chip_tap_straps_prod/latest

---

Test location	/workspace/coverage/default/4.chip_tap_straps_rma.4261112678
Short name	T1035
Test name
Test status
Simulation time	3039060877 ps
CPU time	198.3 seconds
Started	Jul 24 08:20:20 PM PDT 24
Finished	Jul 24 08:23:39 PM PDT 24
Peak memory	621116 kb
Host	smart-d9b50431-aaec-4bc4-8a7c-44011607ee1f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261112678 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.4261112678
Directory	/workspace/4.chip_tap_straps_rma/latest

---

Test location	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4093950166
Short name	T776
Test name
Test status
Simulation time	3542482130 ps
CPU time	459.37 seconds
Started	Jul 24 08:25:56 PM PDT 24
Finished	Jul 24 08:33:36 PM PDT 24
Peak memory	648876 kb
Host	smart-58fd4af2-0727-47c2-9bbe-d71468ec73ba
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093950166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4093950166
Directory	/workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/40.chip_sw_all_escalation_resets.1202168244
Short name	T826
Test name
Test status
Simulation time	4628198750 ps
CPU time	750.61 seconds
Started	Jul 24 08:24:44 PM PDT 24
Finished	Jul 24 08:37:15 PM PDT 24
Peak memory	650468 kb
Host	smart-f0429de8-9dd7-4540-8b11-d8d77f6de1d6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1202168244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.1202168244
Directory	/workspace/40.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1904558237
Short name	T251
Test name
Test status
Simulation time	3917274644 ps
CPU time	337.06 seconds
Started	Jul 24 08:31:38 PM PDT 24
Finished	Jul 24 08:37:15 PM PDT 24
Peak memory	649116 kb
Host	smart-4bf5fe44-671f-4bf9-a1d4-bd4920ceec59
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904558237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1904558237
Directory	/workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2937690133
Short name	T157
Test name
Test status
Simulation time	5090501992 ps
CPU time	556.21 seconds
Started	Jul 24 08:31:26 PM PDT 24
Finished	Jul 24 08:40:43 PM PDT 24
Peak memory	650440 kb
Host	smart-1c196edc-de4c-4422-809c-c886971188e4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2937690133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2937690133
Directory	/workspace/41.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4030098514
Short name	T94
Test name
Test status
Simulation time	3376897662 ps
CPU time	615.79 seconds
Started	Jul 24 08:24:57 PM PDT 24
Finished	Jul 24 08:35:14 PM PDT 24
Peak memory	648900 kb
Host	smart-245348aa-c234-489b-9b11-151695fc3450
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030098514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4030098514
Directory	/workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2928896820
Short name	T819
Test name
Test status
Simulation time	5757469036 ps
CPU time	642.18 seconds
Started	Jul 24 08:28:18 PM PDT 24
Finished	Jul 24 08:39:00 PM PDT 24
Peak memory	650592 kb
Host	smart-f0ee18c9-b979-470d-87c7-3f937b35372d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2928896820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.2928896820
Directory	/workspace/43.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.744485430
Short name	T847
Test name
Test status
Simulation time	4386302660 ps
CPU time	345.78 seconds
Started	Jul 24 08:24:52 PM PDT 24
Finished	Jul 24 08:30:38 PM PDT 24
Peak memory	649512 kb
Host	smart-aff6a34e-e6b8-42ab-be5e-a5c73e2d7a2d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744485430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_s w_alert_handler_lpg_sleep_mode_alerts.744485430
Directory	/workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/44.chip_sw_all_escalation_resets.214106000
Short name	T806
Test name
Test status
Simulation time	5739660540 ps
CPU time	579.93 seconds
Started	Jul 24 08:26:53 PM PDT 24
Finished	Jul 24 08:36:34 PM PDT 24
Peak memory	650484 kb
Host	smart-f6ded9fb-e416-4b2a-af97-8ea9f662fdd1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 214106000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.214106000
Directory	/workspace/44.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2187221170
Short name	T1371
Test name
Test status
Simulation time	3005745080 ps
CPU time	348.93 seconds
Started	Jul 24 08:26:06 PM PDT 24
Finished	Jul 24 08:31:55 PM PDT 24
Peak memory	649088 kb
Host	smart-4d90cc96-fd2e-4adb-973d-400aede2bb4e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187221170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2187221170
Directory	/workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/45.chip_sw_all_escalation_resets.4128394572
Short name	T1193
Test name
Test status
Simulation time	4805985392 ps
CPU time	784.03 seconds
Started	Jul 24 08:26:01 PM PDT 24
Finished	Jul 24 08:39:06 PM PDT 24
Peak memory	650424 kb
Host	smart-1c33a35b-f90b-4fa5-b4f0-f7d4f650d216
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4128394572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.4128394572
Directory	/workspace/45.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2348025677
Short name	T892
Test name
Test status
Simulation time	3943226830 ps
CPU time	298.7 seconds
Started	Jul 24 08:28:02 PM PDT 24
Finished	Jul 24 08:33:01 PM PDT 24
Peak memory	649268 kb
Host	smart-e56fb0cb-ad04-4732-bfd3-2b1b07cf0d02
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348025677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2348025677
Directory	/workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.865458057
Short name	T836
Test name
Test status
Simulation time	3683060128 ps
CPU time	367.79 seconds
Started	Jul 24 08:26:01 PM PDT 24
Finished	Jul 24 08:32:09 PM PDT 24
Peak memory	649032 kb
Host	smart-865dbab3-ac9c-46b8-82f5-cd46574a8791
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865458057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_s w_alert_handler_lpg_sleep_mode_alerts.865458057
Directory	/workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2149116816
Short name	T281
Test name
Test status
Simulation time	3466571470 ps
CPU time	384.94 seconds
Started	Jul 24 08:25:43 PM PDT 24
Finished	Jul 24 08:32:08 PM PDT 24
Peak memory	649524 kb
Host	smart-05a902ea-700f-4845-83c5-cbaf43a458ab
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149116816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2149116816
Directory	/workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4039606052
Short name	T838
Test name
Test status
Simulation time	4156081174 ps
CPU time	564.15 seconds
Started	Jul 24 08:21:08 PM PDT 24
Finished	Jul 24 08:30:32 PM PDT 24
Peak memory	648972 kb
Host	smart-70c4a8af-a21e-441c-9173-470877d79588
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039606052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.4039606052
Directory	/workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/5.chip_sw_all_escalation_resets.1833593213
Short name	T816
Test name
Test status
Simulation time	4373923950 ps
CPU time	681.53 seconds
Started	Jul 24 08:20:50 PM PDT 24
Finished	Jul 24 08:32:12 PM PDT 24
Peak memory	650336 kb
Host	smart-7f34a5b3-013a-4f44-a776-5cd02edbfb26
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1833593213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.1833593213
Directory	/workspace/5.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3235861540
Short name	T1222
Test name
Test status
Simulation time	12437858616 ps
CPU time	2839.21 seconds
Started	Jul 24 08:23:09 PM PDT 24
Finished	Jul 24 09:10:28 PM PDT 24
Peak memory	610048 kb
Host	smart-ad184ece-9853-4321-babd-a8d2e0c2f7c1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235861540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.3235861540
Directory	/workspace/5.chip_sw_csrng_edn_concurrency/latest

---

Test location	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3128936908
Short name	T289
Test name
Test status
Simulation time	4925251000 ps
CPU time	532.86 seconds
Started	Jul 24 08:22:01 PM PDT 24
Finished	Jul 24 08:30:54 PM PDT 24
Peak memory	611368 kb
Host	smart-c236c81b-6863-4ccd-8122-90899b467a0e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3128936908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.3128936908
Directory	/workspace/5.chip_sw_data_integrity_escalation/latest

---

Test location	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2972799504
Short name	T1136
Test name
Test status
Simulation time	6059041364 ps
CPU time	564.13 seconds
Started	Jul 24 08:23:36 PM PDT 24
Finished	Jul 24 08:33:00 PM PDT 24
Peak memory	620724 kb
Host	smart-473d7e78-17cd-4d12-9c94-fa716e9c04ad
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972799504 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.2972799504
Directory	/workspace/5.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3635171221
Short name	T1271
Test name
Test status
Simulation time	13453743220 ps
CPU time	2417.41 seconds
Started	Jul 24 08:22:29 PM PDT 24
Finished	Jul 24 09:02:47 PM PDT 24
Peak memory	619556 kb
Host	smart-d15374ac-8b18-45c0-b899-891fcf020d75
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3635171221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3635171221
Directory	/workspace/5.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/52.chip_sw_all_escalation_resets.3513247178
Short name	T779
Test name
Test status
Simulation time	5626968796 ps
CPU time	527.55 seconds
Started	Jul 24 08:27:21 PM PDT 24
Finished	Jul 24 08:36:09 PM PDT 24
Peak memory	650364 kb
Host	smart-e298bb0b-cda2-47bf-a924-3e510984b10c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3513247178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.3513247178
Directory	/workspace/52.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2387727894
Short name	T878
Test name
Test status
Simulation time	3516293296 ps
CPU time	457.78 seconds
Started	Jul 24 08:27:50 PM PDT 24
Finished	Jul 24 08:35:28 PM PDT 24
Peak memory	649172 kb
Host	smart-d3aa7393-4119-4d4f-8e68-98f2f58c13c7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387727894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2387727894
Directory	/workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/53.chip_sw_all_escalation_resets.4038890873
Short name	T874
Test name
Test status
Simulation time	5365442920 ps
CPU time	685.87 seconds
Started	Jul 24 08:29:05 PM PDT 24
Finished	Jul 24 08:40:31 PM PDT 24
Peak memory	650264 kb
Host	smart-8870c47f-820a-4e4d-b128-833fe1e24bb7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4038890873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.4038890873
Directory	/workspace/53.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1915973241
Short name	T250
Test name
Test status
Simulation time	4009213156 ps
CPU time	352.67 seconds
Started	Jul 24 08:26:03 PM PDT 24
Finished	Jul 24 08:31:55 PM PDT 24
Peak memory	648932 kb
Host	smart-7ff8be56-3d95-4dc5-b949-a227dcccc481
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915973241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1915973241
Directory	/workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/54.chip_sw_all_escalation_resets.2083965230
Short name	T1277
Test name
Test status
Simulation time	6390279894 ps
CPU time	761.62 seconds
Started	Jul 24 08:26:49 PM PDT 24
Finished	Jul 24 08:39:31 PM PDT 24
Peak memory	650112 kb
Host	smart-009add63-8429-472a-a03e-ade96059408a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2083965230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2083965230
Directory	/workspace/54.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2896129246
Short name	T845
Test name
Test status
Simulation time	4220441368 ps
CPU time	473.04 seconds
Started	Jul 24 08:28:40 PM PDT 24
Finished	Jul 24 08:36:34 PM PDT 24
Peak memory	649220 kb
Host	smart-7fe1913b-00dd-40e8-b0b7-0ba64d8c1db5
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896129246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2896129246
Directory	/workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3611970481
Short name	T818
Test name
Test status
Simulation time	3713365094 ps
CPU time	338.85 seconds
Started	Jul 24 08:28:11 PM PDT 24
Finished	Jul 24 08:33:50 PM PDT 24
Peak memory	649336 kb
Host	smart-3cbfd051-dffb-41a5-9477-852b59a1b72c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611970481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3611970481
Directory	/workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/56.chip_sw_all_escalation_resets.936449397
Short name	T867
Test name
Test status
Simulation time	5181312044 ps
CPU time	657.24 seconds
Started	Jul 24 08:25:29 PM PDT 24
Finished	Jul 24 08:36:26 PM PDT 24
Peak memory	650304 kb
Host	smart-f3adfeeb-c256-482f-a467-520ee76bd841
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 936449397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.936449397
Directory	/workspace/56.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1002867229
Short name	T1423
Test name
Test status
Simulation time	3029455308 ps
CPU time	331.85 seconds
Started	Jul 24 08:26:30 PM PDT 24
Finished	Jul 24 08:32:02 PM PDT 24
Peak memory	648896 kb
Host	smart-36be87f6-76ae-48ae-b3a6-8e23457dc557
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002867229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1002867229
Directory	/workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/58.chip_sw_all_escalation_resets.609559318
Short name	T858
Test name
Test status
Simulation time	5307590330 ps
CPU time	720.02 seconds
Started	Jul 24 08:28:20 PM PDT 24
Finished	Jul 24 08:40:21 PM PDT 24
Peak memory	650736 kb
Host	smart-a603d143-5ec3-42d0-b9fa-7e83259916e4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 609559318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.609559318
Directory	/workspace/58.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3037953400
Short name	T814
Test name
Test status
Simulation time	3492904138 ps
CPU time	371.53 seconds
Started	Jul 24 08:26:25 PM PDT 24
Finished	Jul 24 08:32:37 PM PDT 24
Peak memory	649236 kb
Host	smart-cf624977-7e0a-4934-a925-19c4c2746a0c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037953400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3037953400
Directory	/workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1660820305
Short name	T265
Test name
Test status
Simulation time	4985132600 ps
CPU time	570.48 seconds
Started	Jul 24 08:29:17 PM PDT 24
Finished	Jul 24 08:38:47 PM PDT 24
Peak memory	611364 kb
Host	smart-889fbd6c-92a3-41f3-91d2-57647dc0e693
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1660820305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.1660820305
Directory	/workspace/59.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/6.chip_sw_all_escalation_resets.716104650
Short name	T1394
Test name
Test status
Simulation time	5878444264 ps
CPU time	525.75 seconds
Started	Jul 24 08:24:00 PM PDT 24
Finished	Jul 24 08:32:46 PM PDT 24
Peak memory	620256 kb
Host	smart-72e519bd-3ec1-44af-be1e-bb0febcf76ef
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 716104650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.716104650
Directory	/workspace/6.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2153183053
Short name	T1217
Test name
Test status
Simulation time	15616509140 ps
CPU time	3189.39 seconds
Started	Jul 24 08:21:04 PM PDT 24
Finished	Jul 24 09:14:14 PM PDT 24
Peak memory	610024 kb
Host	smart-da735d35-2710-4129-817c-3f808ccb22ed
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153183053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.2153183053
Directory	/workspace/6.chip_sw_csrng_edn_concurrency/latest

---

Test location	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2963040584
Short name	T1046
Test name
Test status
Simulation time	6837785710 ps
CPU time	618.86 seconds
Started	Jul 24 08:23:21 PM PDT 24
Finished	Jul 24 08:33:40 PM PDT 24
Peak memory	621920 kb
Host	smart-8cacac25-7687-4f4a-ac33-ee871fbf3c7d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963040584 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.2963040584
Directory	/workspace/6.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2678722415
Short name	T357
Test name
Test status
Simulation time	7966851052 ps
CPU time	1210.27 seconds
Started	Jul 24 08:23:45 PM PDT 24
Finished	Jul 24 08:43:56 PM PDT 24
Peak memory	619316 kb
Host	smart-23b86f06-8764-40d9-a42d-d0d8a2d63a30
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2678722415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.2678722415
Directory	/workspace/6.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1779440544
Short name	T100
Test name
Test status
Simulation time	3986872022 ps
CPU time	448.63 seconds
Started	Jul 24 08:32:00 PM PDT 24
Finished	Jul 24 08:39:29 PM PDT 24
Peak memory	649284 kb
Host	smart-26876067-1cf7-4b75-a9eb-4e7f32a59ee7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779440544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1779440544
Directory	/workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.269720205
Short name	T881
Test name
Test status
Simulation time	4127792324 ps
CPU time	431.45 seconds
Started	Jul 24 08:32:04 PM PDT 24
Finished	Jul 24 08:39:16 PM PDT 24
Peak memory	648904 kb
Host	smart-f284716d-9e6c-47f8-8e6c-48a5fbd36d2f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269720205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s w_alert_handler_lpg_sleep_mode_alerts.269720205
Directory	/workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/63.chip_sw_all_escalation_resets.128356509
Short name	T320
Test name
Test status
Simulation time	5054231726 ps
CPU time	665.06 seconds
Started	Jul 24 08:31:31 PM PDT 24
Finished	Jul 24 08:42:36 PM PDT 24
Peak memory	650548 kb
Host	smart-eabd0f62-b93b-4c43-8053-a9eb7d417abf
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 128356509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.128356509
Directory	/workspace/63.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1424943763
Short name	T91
Test name
Test status
Simulation time	4326437976 ps
CPU time	330.29 seconds
Started	Jul 24 08:26:19 PM PDT 24
Finished	Jul 24 08:31:49 PM PDT 24
Peak memory	650056 kb
Host	smart-050828e4-4727-4b26-9f19-1a80072da7c6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424943763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1424943763
Directory	/workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/64.chip_sw_all_escalation_resets.1904663205
Short name	T1442
Test name
Test status
Simulation time	6322469700 ps
CPU time	726.78 seconds
Started	Jul 24 08:31:26 PM PDT 24
Finished	Jul 24 08:43:33 PM PDT 24
Peak memory	650120 kb
Host	smart-1f18c0eb-8b40-42d9-a871-a6f997c94e33
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1904663205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.1904663205
Directory	/workspace/64.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3502677262
Short name	T778
Test name
Test status
Simulation time	3714869624 ps
CPU time	309.25 seconds
Started	Jul 24 08:27:15 PM PDT 24
Finished	Jul 24 08:32:24 PM PDT 24
Peak memory	649192 kb
Host	smart-396a660f-30f9-40bd-a67d-0ee139d7ef1c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502677262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3502677262
Directory	/workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/66.chip_sw_all_escalation_resets.317916734
Short name	T891
Test name
Test status
Simulation time	4184881822 ps
CPU time	602.99 seconds
Started	Jul 24 08:28:04 PM PDT 24
Finished	Jul 24 08:38:08 PM PDT 24
Peak memory	650056 kb
Host	smart-c8120911-bf89-4eee-8965-9fff1afaa4b5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 317916734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.317916734
Directory	/workspace/66.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3134889158
Short name	T884
Test name
Test status
Simulation time	3409435904 ps
CPU time	485.27 seconds
Started	Jul 24 08:33:00 PM PDT 24
Finished	Jul 24 08:41:06 PM PDT 24
Peak memory	649328 kb
Host	smart-db9d3e79-3d90-439e-9a24-aa9a57c069a6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134889158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3134889158
Directory	/workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1693863733
Short name	T298
Test name
Test status
Simulation time	4016161416 ps
CPU time	391.52 seconds
Started	Jul 24 08:32:57 PM PDT 24
Finished	Jul 24 08:39:29 PM PDT 24
Peak memory	648848 kb
Host	smart-b993fbf8-fc3a-49d0-9f12-d2df1cd9d168
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693863733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1693863733
Directory	/workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/69.chip_sw_all_escalation_resets.3085570277
Short name	T843
Test name
Test status
Simulation time	6527152000 ps
CPU time	635.05 seconds
Started	Jul 24 08:28:25 PM PDT 24
Finished	Jul 24 08:39:00 PM PDT 24
Peak memory	650632 kb
Host	smart-132a0039-1f39-40ed-ac63-d9f438582347
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3085570277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.3085570277
Directory	/workspace/69.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2882817910
Short name	T1319
Test name
Test status
Simulation time	16433966132 ps
CPU time	3068.56 seconds
Started	Jul 24 08:21:17 PM PDT 24
Finished	Jul 24 09:12:26 PM PDT 24
Peak memory	610792 kb
Host	smart-2ab7daad-0831-4bf0-837c-1c1e66f9e2b1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882817910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.2882817910
Directory	/workspace/7.chip_sw_csrng_edn_concurrency/latest

---

Test location	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.742328560
Short name	T1382
Test name
Test status
Simulation time	6537127523 ps
CPU time	525.99 seconds
Started	Jul 24 08:21:08 PM PDT 24
Finished	Jul 24 08:29:55 PM PDT 24
Peak memory	621872 kb
Host	smart-5e016bbe-486a-45f1-927a-d9a77e35acad
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742328560 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.742328560
Directory	/workspace/7.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3728993516
Short name	T15
Test name
Test status
Simulation time	8278276040 ps
CPU time	1353.69 seconds
Started	Jul 24 08:23:24 PM PDT 24
Finished	Jul 24 08:45:58 PM PDT 24
Peak memory	619292 kb
Host	smart-a538d2ee-3a3e-4b04-8ee8-cbb4fa5116d7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3728993516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3728993516
Directory	/workspace/7.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2085500520
Short name	T853
Test name
Test status
Simulation time	3692039350 ps
CPU time	301.95 seconds
Started	Jul 24 08:28:41 PM PDT 24
Finished	Jul 24 08:33:44 PM PDT 24
Peak memory	649544 kb
Host	smart-73a610e7-8263-41da-90b7-ab39bfa9cd5c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085500520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2085500520
Directory	/workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/70.chip_sw_all_escalation_resets.3187471976
Short name	T1327
Test name
Test status
Simulation time	4262458268 ps
CPU time	573.54 seconds
Started	Jul 24 08:26:43 PM PDT 24
Finished	Jul 24 08:36:17 PM PDT 24
Peak memory	650072 kb
Host	smart-9eee7421-8d0a-4f18-b0a0-4bb9e6b2fa0e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3187471976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.3187471976
Directory	/workspace/70.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1172548265
Short name	T385
Test name
Test status
Simulation time	4106060406 ps
CPU time	384.39 seconds
Started	Jul 24 08:27:32 PM PDT 24
Finished	Jul 24 08:33:57 PM PDT 24
Peak memory	649372 kb
Host	smart-e4d73aa6-ccc2-49c4-bc32-ed0527b72630
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172548265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1172548265
Directory	/workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/71.chip_sw_all_escalation_resets.107336865
Short name	T404
Test name
Test status
Simulation time	4655970016 ps
CPU time	504.29 seconds
Started	Jul 24 08:28:45 PM PDT 24
Finished	Jul 24 08:37:10 PM PDT 24
Peak memory	650928 kb
Host	smart-05a2ed81-af8a-43dd-ba30-707c4cd9425f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 107336865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.107336865
Directory	/workspace/71.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/72.chip_sw_all_escalation_resets.682203669
Short name	T866
Test name
Test status
Simulation time	5050431030 ps
CPU time	537.44 seconds
Started	Jul 24 08:27:25 PM PDT 24
Finished	Jul 24 08:36:23 PM PDT 24
Peak memory	650540 kb
Host	smart-7f25640a-0550-437f-8c1f-e9c6239c034e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 682203669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.682203669
Directory	/workspace/72.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3415834778
Short name	T807
Test name
Test status
Simulation time	3423489764 ps
CPU time	395.18 seconds
Started	Jul 24 08:28:47 PM PDT 24
Finished	Jul 24 08:35:22 PM PDT 24
Peak memory	648940 kb
Host	smart-8eae4262-6194-46c3-9165-651f6ae99dde
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415834778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3415834778
Directory	/workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/73.chip_sw_all_escalation_resets.3878235844
Short name	T158
Test name
Test status
Simulation time	5219072696 ps
CPU time	480.12 seconds
Started	Jul 24 08:27:23 PM PDT 24
Finished	Jul 24 08:35:24 PM PDT 24
Peak memory	650480 kb
Host	smart-dafd71a7-81a1-421d-9408-0bd748c5912a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3878235844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.3878235844
Directory	/workspace/73.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2559465095
Short name	T775
Test name
Test status
Simulation time	3749060902 ps
CPU time	357.8 seconds
Started	Jul 24 08:27:50 PM PDT 24
Finished	Jul 24 08:33:48 PM PDT 24
Peak memory	649272 kb
Host	smart-e9fa77e6-ac7a-480b-9b44-578eba087da1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559465095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2559465095
Directory	/workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/74.chip_sw_all_escalation_resets.2264952982
Short name	T434
Test name
Test status
Simulation time	5748353040 ps
CPU time	692.91 seconds
Started	Jul 24 08:29:06 PM PDT 24
Finished	Jul 24 08:40:39 PM PDT 24
Peak memory	650168 kb
Host	smart-e52ff0d1-2139-4bf1-a080-2cdbaa8488db
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2264952982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2264952982
Directory	/workspace/74.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1620107121
Short name	T813
Test name
Test status
Simulation time	3697257396 ps
CPU time	357.42 seconds
Started	Jul 24 08:27:47 PM PDT 24
Finished	Jul 24 08:33:45 PM PDT 24
Peak memory	649244 kb
Host	smart-734dbc58-54f8-4ad3-8fdf-73cd3b0b4bcd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620107121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1620107121
Directory	/workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/75.chip_sw_all_escalation_resets.3669324866
Short name	T865
Test name
Test status
Simulation time	6417009634 ps
CPU time	681.9 seconds
Started	Jul 24 08:27:43 PM PDT 24
Finished	Jul 24 08:39:05 PM PDT 24
Peak memory	650508 kb
Host	smart-393adb52-d20d-4006-9b98-6607309a56e9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3669324866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.3669324866
Directory	/workspace/75.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1523672077
Short name	T876
Test name
Test status
Simulation time	3451877642 ps
CPU time	388.74 seconds
Started	Jul 24 08:28:21 PM PDT 24
Finished	Jul 24 08:34:50 PM PDT 24
Peak memory	649092 kb
Host	smart-a737705c-001f-4e02-a5b2-c20ef0594116
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523672077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1523672077
Directory	/workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/76.chip_sw_all_escalation_resets.1805796817
Short name	T266
Test name
Test status
Simulation time	5957291864 ps
CPU time	656.62 seconds
Started	Jul 24 08:33:19 PM PDT 24
Finished	Jul 24 08:44:17 PM PDT 24
Peak memory	650732 kb
Host	smart-5c5118cc-356f-4ae9-9b8f-09dd7e8a18ac
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1805796817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1805796817
Directory	/workspace/76.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1374377480
Short name	T412
Test name
Test status
Simulation time	4195661128 ps
CPU time	642.95 seconds
Started	Jul 24 08:33:45 PM PDT 24
Finished	Jul 24 08:44:29 PM PDT 24
Peak memory	649168 kb
Host	smart-1973cf9a-ed37-495f-8528-ec9a315abebd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374377480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1374377480
Directory	/workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/77.chip_sw_all_escalation_resets.1423677148
Short name	T1209
Test name
Test status
Simulation time	5821389592 ps
CPU time	695.28 seconds
Started	Jul 24 08:33:32 PM PDT 24
Finished	Jul 24 08:45:08 PM PDT 24
Peak memory	619912 kb
Host	smart-0f07e6c0-b75f-4aad-b8d2-dcec7c95bd74
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1423677148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1423677148
Directory	/workspace/77.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3054600423
Short name	T92
Test name
Test status
Simulation time	4687474750 ps
CPU time	430.37 seconds
Started	Jul 24 08:28:08 PM PDT 24
Finished	Jul 24 08:35:18 PM PDT 24
Peak memory	650044 kb
Host	smart-da79ab6d-7a5f-4cf8-9ce0-8890ceecc673
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054600423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3054600423
Directory	/workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3725476779
Short name	T61
Test name
Test status
Simulation time	5894928550 ps
CPU time	574.34 seconds
Started	Jul 24 08:28:27 PM PDT 24
Finished	Jul 24 08:38:02 PM PDT 24
Peak memory	650808 kb
Host	smart-4c97bae9-519f-4f2a-a2e1-123e125deb47
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3725476779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3725476779
Directory	/workspace/79.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/8.chip_sw_all_escalation_resets.3766487831
Short name	T1095
Test name
Test status
Simulation time	5377939832 ps
CPU time	826.43 seconds
Started	Jul 24 08:20:36 PM PDT 24
Finished	Jul 24 08:34:22 PM PDT 24
Peak memory	620156 kb
Host	smart-54768a11-50af-42c8-afff-70dce12c603a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3766487831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3766487831
Directory	/workspace/8.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3184617399
Short name	T1180
Test name
Test status
Simulation time	6730967263 ps
CPU time	423.66 seconds
Started	Jul 24 08:21:23 PM PDT 24
Finished	Jul 24 08:28:27 PM PDT 24
Peak memory	622972 kb
Host	smart-6ec3dbc7-f8bf-470e-a442-986d02587de4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184617399 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3184617399
Directory	/workspace/8.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.679854545
Short name	T369
Test name
Test status
Simulation time	12629015560 ps
CPU time	2073.24 seconds
Started	Jul 24 08:21:13 PM PDT 24
Finished	Jul 24 08:55:46 PM PDT 24
Peak memory	623764 kb
Host	smart-6a45c2ef-f9ab-42d1-a0f4-9a18f41b8e35
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=679854545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.679854545
Directory	/workspace/8.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1894616218
Short name	T781
Test name
Test status
Simulation time	4009070034 ps
CPU time	390.69 seconds
Started	Jul 24 08:28:22 PM PDT 24
Finished	Jul 24 08:34:53 PM PDT 24
Peak memory	649184 kb
Host	smart-5cb1f2d5-a2a2-4065-a683-9f3d371bb592
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894616218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1894616218
Directory	/workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/80.chip_sw_all_escalation_resets.3928555111
Short name	T321
Test name
Test status
Simulation time	5330878996 ps
CPU time	566.71 seconds
Started	Jul 24 08:29:30 PM PDT 24
Finished	Jul 24 08:38:57 PM PDT 24
Peak memory	650532 kb
Host	smart-f7fa7f92-93c9-4f8b-895e-642bfe410054
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3928555111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.3928555111
Directory	/workspace/80.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3325257653
Short name	T83
Test name
Test status
Simulation time	3672358830 ps
CPU time	434.28 seconds
Started	Jul 24 08:27:57 PM PDT 24
Finished	Jul 24 08:35:12 PM PDT 24
Peak memory	649808 kb
Host	smart-7a3039c1-2485-4b58-8fdd-5a49172122d5
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325257653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3325257653
Directory	/workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/81.chip_sw_all_escalation_resets.4160321642
Short name	T1216
Test name
Test status
Simulation time	5889255260 ps
CPU time	631.54 seconds
Started	Jul 24 08:27:57 PM PDT 24
Finished	Jul 24 08:38:29 PM PDT 24
Peak memory	650716 kb
Host	smart-d2489850-c160-45e9-8c44-dd31041e83bd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4160321642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.4160321642
Directory	/workspace/81.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1600952500
Short name	T99
Test name
Test status
Simulation time	3719544908 ps
CPU time	412.85 seconds
Started	Jul 24 08:28:07 PM PDT 24
Finished	Jul 24 08:35:00 PM PDT 24
Peak memory	649572 kb
Host	smart-672868e6-43a6-4738-8f7a-f5aaa26fee6b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600952500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1600952500
Directory	/workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3305708998
Short name	T830
Test name
Test status
Simulation time	5100226632 ps
CPU time	667.73 seconds
Started	Jul 24 08:28:56 PM PDT 24
Finished	Jul 24 08:40:04 PM PDT 24
Peak memory	620212 kb
Host	smart-25497a30-e5f1-4465-b522-26ea527d8986
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3305708998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3305708998
Directory	/workspace/82.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.441013199
Short name	T384
Test name
Test status
Simulation time	2829832432 ps
CPU time	255.91 seconds
Started	Jul 24 08:28:35 PM PDT 24
Finished	Jul 24 08:32:51 PM PDT 24
Peak memory	649248 kb
Host	smart-948b63cb-1871-459e-b71f-4987d4ad1d7b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441013199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_s w_alert_handler_lpg_sleep_mode_alerts.441013199
Directory	/workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/83.chip_sw_all_escalation_resets.461087381
Short name	T264
Test name
Test status
Simulation time	4411187664 ps
CPU time	526.11 seconds
Started	Jul 24 08:29:02 PM PDT 24
Finished	Jul 24 08:37:49 PM PDT 24
Peak memory	611260 kb
Host	smart-c6f3f3a7-5160-43f7-8629-dced8e46abf1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 461087381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.461087381
Directory	/workspace/83.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1480070167
Short name	T772
Test name
Test status
Simulation time	3526593526 ps
CPU time	370.6 seconds
Started	Jul 24 08:27:38 PM PDT 24
Finished	Jul 24 08:33:49 PM PDT 24
Peak memory	648920 kb
Host	smart-9663f2e4-ed14-49ec-9b14-274848f34d51
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480070167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1480070167
Directory	/workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/84.chip_sw_all_escalation_resets.1140203295
Short name	T888
Test name
Test status
Simulation time	4681665030 ps
CPU time	549.04 seconds
Started	Jul 24 08:27:59 PM PDT 24
Finished	Jul 24 08:37:08 PM PDT 24
Peak memory	650344 kb
Host	smart-e1e226a4-b9df-454f-87ee-832f6cbd2668
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1140203295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.1140203295
Directory	/workspace/84.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072111187
Short name	T823
Test name
Test status
Simulation time	3370070216 ps
CPU time	445.57 seconds
Started	Jul 24 08:28:45 PM PDT 24
Finished	Jul 24 08:36:10 PM PDT 24
Peak memory	649180 kb
Host	smart-1cfaaf84-e916-4efb-bcb5-96a2e837a202
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072111187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4072111187
Directory	/workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/85.chip_sw_all_escalation_resets.1716213414
Short name	T844
Test name
Test status
Simulation time	5854858250 ps
CPU time	653.94 seconds
Started	Jul 24 08:27:49 PM PDT 24
Finished	Jul 24 08:38:43 PM PDT 24
Peak memory	650652 kb
Host	smart-b5e5c752-40a8-451f-b084-936870bc0ca4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1716213414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.1716213414
Directory	/workspace/85.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2465035676
Short name	T855
Test name
Test status
Simulation time	3469302210 ps
CPU time	434.01 seconds
Started	Jul 24 08:27:57 PM PDT 24
Finished	Jul 24 08:35:11 PM PDT 24
Peak memory	649500 kb
Host	smart-d3b87214-37c6-4d0d-8365-4e7c003205b2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465035676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2465035676
Directory	/workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/86.chip_sw_all_escalation_resets.2993110481
Short name	T1231
Test name
Test status
Simulation time	5288127506 ps
CPU time	576.8 seconds
Started	Jul 24 08:27:50 PM PDT 24
Finished	Jul 24 08:37:27 PM PDT 24
Peak memory	650496 kb
Host	smart-13d89f48-8805-4a86-9e44-65bfc87968e9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2993110481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.2993110481
Directory	/workspace/86.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2729196945
Short name	T809
Test name
Test status
Simulation time	4019958168 ps
CPU time	346.45 seconds
Started	Jul 24 08:28:24 PM PDT 24
Finished	Jul 24 08:34:11 PM PDT 24
Peak memory	649024 kb
Host	smart-c7a102c1-aa1e-4ae9-ac78-77926857e43b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729196945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2729196945
Directory	/workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3142093859
Short name	T371
Test name
Test status
Simulation time	4514211146 ps
CPU time	498.04 seconds
Started	Jul 24 08:27:53 PM PDT 24
Finished	Jul 24 08:36:12 PM PDT 24
Peak memory	650524 kb
Host	smart-6439c53e-512d-4b7b-b88f-c8a3986ca7fe
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3142093859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.3142093859
Directory	/workspace/87.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1814408969
Short name	T89
Test name
Test status
Simulation time	4089008432 ps
CPU time	474.28 seconds
Started	Jul 24 08:30:58 PM PDT 24
Finished	Jul 24 08:38:53 PM PDT 24
Peak memory	649740 kb
Host	smart-79ab78a7-9455-484e-bac2-89486ffc2a1b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814408969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1814408969
Directory	/workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/88.chip_sw_all_escalation_resets.1561243451
Short name	T815
Test name
Test status
Simulation time	5436435810 ps
CPU time	616 seconds
Started	Jul 24 08:29:51 PM PDT 24
Finished	Jul 24 08:40:07 PM PDT 24
Peak memory	650396 kb
Host	smart-c4ffb04f-d223-4b6b-96a8-c56ada5036b6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1561243451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.1561243451
Directory	/workspace/88.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2195663572
Short name	T893
Test name
Test status
Simulation time	3807754500 ps
CPU time	450.19 seconds
Started	Jul 24 08:31:19 PM PDT 24
Finished	Jul 24 08:38:50 PM PDT 24
Peak memory	649116 kb
Host	smart-87e4764c-1ff1-4fcf-b01b-3c0eb370c009
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195663572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2195663572
Directory	/workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/89.chip_sw_all_escalation_resets.3722456814
Short name	T840
Test name
Test status
Simulation time	5493675806 ps
CPU time	719.5 seconds
Started	Jul 24 08:28:34 PM PDT 24
Finished	Jul 24 08:40:34 PM PDT 24
Peak memory	650436 kb
Host	smart-e52fe4b0-0652-4718-86cf-3211ccef54db
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3722456814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.3722456814
Directory	/workspace/89.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1771181416
Short name	T773
Test name
Test status
Simulation time	3143566850 ps
CPU time	393.53 seconds
Started	Jul 24 08:21:39 PM PDT 24
Finished	Jul 24 08:28:13 PM PDT 24
Peak memory	649228 kb
Host	smart-b6403c95-e60b-46fa-9731-987b9182029a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771181416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.1771181416
Directory	/workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

---

Test location	/workspace/coverage/default/9.chip_sw_all_escalation_resets.2106582466
Short name	T824
Test name
Test status
Simulation time	5777017080 ps
CPU time	610.27 seconds
Started	Jul 24 08:21:54 PM PDT 24
Finished	Jul 24 08:32:05 PM PDT 24
Peak memory	650188 kb
Host	smart-f4c3fc7e-4d05-4122-93ca-7c624ad44c47
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2106582466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.2106582466
Directory	/workspace/9.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4208457238
Short name	T1079
Test name
Test status
Simulation time	22403584630 ps
CPU time	4583.3 seconds
Started	Jul 24 08:22:32 PM PDT 24
Finished	Jul 24 09:38:56 PM PDT 24
Peak memory	609452 kb
Host	smart-03103f94-800f-40ad-9d48-dedfb1b46d13
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208457238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.4208457238
Directory	/workspace/9.chip_sw_csrng_edn_concurrency/latest

---

Test location	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3786130492
Short name	T1232
Test name
Test status
Simulation time	12854184578 ps
CPU time	1076.92 seconds
Started	Jul 24 08:21:34 PM PDT 24
Finished	Jul 24 08:39:32 PM PDT 24
Peak memory	623000 kb
Host	smart-ada57c89-7404-4759-b3b3-7ac42df476e3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786130492 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.3786130492
Directory	/workspace/9.chip_sw_lc_ctrl_transition/latest

---

Test location	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3312738956
Short name	T368
Test name
Test status
Simulation time	4650633144 ps
CPU time	524.23 seconds
Started	Jul 24 08:21:29 PM PDT 24
Finished	Jul 24 08:30:13 PM PDT 24
Peak memory	619272 kb
Host	smart-94a31dcf-4bfe-46b7-a657-57dc872310ce
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3312738956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.3312738956
Directory	/workspace/9.chip_sw_uart_rand_baudrate/latest

---

Test location	/workspace/coverage/default/90.chip_sw_all_escalation_resets.2293692175
Short name	T1325
Test name
Test status
Simulation time	5452201624 ps
CPU time	690.35 seconds
Started	Jul 24 08:35:26 PM PDT 24
Finished	Jul 24 08:46:57 PM PDT 24
Peak memory	620236 kb
Host	smart-dc20ef1b-663d-4bda-9b2c-ed3da4427be7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2293692175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2293692175
Directory	/workspace/90.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/92.chip_sw_all_escalation_resets.774268492
Short name	T1378
Test name
Test status
Simulation time	4569029480 ps
CPU time	497.63 seconds
Started	Jul 24 08:29:30 PM PDT 24
Finished	Jul 24 08:37:48 PM PDT 24
Peak memory	650332 kb
Host	smart-b80d28af-4863-4fd8-8051-b2714231a73b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 774268492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.774268492
Directory	/workspace/92.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/94.chip_sw_all_escalation_resets.1389198632
Short name	T770
Test name
Test status
Simulation time	4831403156 ps
CPU time	450.07 seconds
Started	Jul 24 08:29:04 PM PDT 24
Finished	Jul 24 08:36:35 PM PDT 24
Peak memory	650336 kb
Host	smart-be0cd31e-7f89-4b2a-823e-5c199e91aa9f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1389198632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1389198632
Directory	/workspace/94.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2013467495
Short name	T165
Test name
Test status
Simulation time	6385920358 ps
CPU time	782.33 seconds
Started	Jul 24 08:28:37 PM PDT 24
Finished	Jul 24 08:41:40 PM PDT 24
Peak memory	620148 kb
Host	smart-fc0e4432-b718-4bcc-8cef-ee17f59a2dcf
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2013467495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2013467495
Directory	/workspace/95.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/96.chip_sw_all_escalation_resets.2761687868
Short name	T894
Test name
Test status
Simulation time	4393454956 ps
CPU time	461.3 seconds
Started	Jul 24 08:28:48 PM PDT 24
Finished	Jul 24 08:36:30 PM PDT 24
Peak memory	650356 kb
Host	smart-386de7f2-f5c8-4297-b989-12f14ff578b3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2761687868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2761687868
Directory	/workspace/96.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/default/97.chip_sw_all_escalation_resets.1972180315
Short name	T869
Test name
Test status
Simulation time	4563208100 ps
CPU time	517.57 seconds
Started	Jul 24 08:37:00 PM PDT 24
Finished	Jul 24 08:45:37 PM PDT 24
Peak memory	650416 kb
Host	smart-0484dbd2-3ac3-4687-a556-be638467e5f6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1972180315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1972180315
Directory	/workspace/97.chip_sw_all_escalation_resets/latest

---

Test location	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2640838707
Short name	T192
Test name
Test status
Simulation time	4572684401 ps
CPU time	283.69 seconds
Started	Jul 24 07:32:22 PM PDT 24
Finished	Jul 24 07:37:06 PM PDT 24
Peak memory	652628 kb
Host	smart-37a0def8-72e3-4382-b853-1bc17d1be5b3
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640838707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.2640838707
Directory	/workspace/1.chip_padctrl_attributes/latest

---

Test location	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.174428050
Short name	T191
Test name
Test status
Simulation time	5261410312 ps
CPU time	236.23 seconds
Started	Jul 24 07:32:26 PM PDT 24
Finished	Jul 24 07:36:23 PM PDT 24
Peak memory	649508 kb
Host	smart-df0b63e5-22f7-449f-badf-b52c6d6d0e17
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174428050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 2.chip_padctrl_attributes.174428050
Directory	/workspace/2.chip_padctrl_attributes/latest

---

Test location	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1177625858
Short name	T31
Test name
Test status
Simulation time	4660146344 ps
CPU time	264.8 seconds
Started	Jul 24 07:32:26 PM PDT 24
Finished	Jul 24 07:36:51 PM PDT 24
Peak memory	653936 kb
Host	smart-c688e077-bb57-4745-8969-44a201ab1820
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177625858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.1177625858
Directory	/workspace/3.chip_padctrl_attributes/latest

---

Test location	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1880958590
Short name	T187
Test name
Test status
Simulation time	4849315856 ps
CPU time	321.52 seconds
Started	Jul 24 07:32:26 PM PDT 24
Finished	Jul 24 07:37:47 PM PDT 24
Peak memory	654344 kb
Host	smart-281598ea-c426-4a05-bdcd-718d7887b239
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880958590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.1880958590
Directory	/workspace/4.chip_padctrl_attributes/latest

---

Test location	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.725934641
Short name	T190
Test name
Test status
Simulation time	5552620976 ps
CPU time	291.13 seconds
Started	Jul 24 07:32:22 PM PDT 24
Finished	Jul 24 07:37:13 PM PDT 24
Peak memory	654660 kb
Host	smart-ad3395bc-1919-424f-8a28-4a3270010406
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725934641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.725934641
Directory	/workspace/5.chip_padctrl_attributes/latest

---

Test location	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2407973051
Short name	T188
Test name
Test status
Simulation time	6076629360 ps
CPU time	267.01 seconds
Started	Jul 24 07:32:12 PM PDT 24
Finished	Jul 24 07:36:39 PM PDT 24
Peak memory	657012 kb
Host	smart-a082f0d7-b210-4e0c-963d-b8ec67d14536
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407973051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.2407973051
Directory	/workspace/7.chip_padctrl_attributes/latest

---

Test location	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3368976498
Short name	T193
Test name
Test status
Simulation time	5335617624 ps
CPU time	267.1 seconds
Started	Jul 24 07:32:26 PM PDT 24
Finished	Jul 24 07:36:53 PM PDT 24
Peak memory	641284 kb
Host	smart-3a70e68e-35b2-4f45-bffe-43e321f87100
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368976498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.3368976498
Directory	/workspace/8.chip_padctrl_attributes/latest

---

Test location	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2908096363
Short name	T32
Test name
Test status
Simulation time	4700034104 ps
CPU time	238.56 seconds
Started	Jul 24 07:32:22 PM PDT 24
Finished	Jul 24 07:36:21 PM PDT 24
Peak memory	641292 kb
Host	smart-47fa9ea2-b193-40be-8f18-cb1f276fb2f5
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908096363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.2908096363
Directory	/workspace/9.chip_padctrl_attributes/latest