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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.00 95.37 93.66 95.41 94.47 97.53 99.54


Total test records in report: 2932
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T833 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3410027958 Jul 24 08:24:13 PM PDT 24 Jul 24 08:30:55 PM PDT 24 3416166224 ps
T194 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.748320548 Jul 24 08:05:18 PM PDT 24 Jul 24 08:14:38 PM PDT 24 4637941700 ps
T1120 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3386324816 Jul 24 08:17:36 PM PDT 24 Jul 24 08:27:29 PM PDT 24 6381447480 ps
T836 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.865458057 Jul 24 08:26:01 PM PDT 24 Jul 24 08:32:09 PM PDT 24 3683060128 ps
T217 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.948254836 Jul 24 08:03:04 PM PDT 24 Jul 24 09:05:30 PM PDT 24 20210695399 ps
T1121 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1163138496 Jul 24 08:10:27 PM PDT 24 Jul 24 08:36:51 PM PDT 24 8841219050 ps
T1122 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3237316585 Jul 24 08:15:47 PM PDT 24 Jul 24 08:37:56 PM PDT 24 6191335027 ps
T1123 /workspace/coverage/default/1.chip_sw_otbn_randomness.4091602452 Jul 24 08:06:46 PM PDT 24 Jul 24 08:23:06 PM PDT 24 5890041728 ps
T1124 /workspace/coverage/default/0.chip_sw_uart_tx_rx.4088954524 Jul 24 07:56:12 PM PDT 24 Jul 24 08:09:08 PM PDT 24 4402703988 ps
T377 /workspace/coverage/default/2.chip_sw_hmac_enc.54219615 Jul 24 08:15:44 PM PDT 24 Jul 24 08:21:52 PM PDT 24 2816070016 ps
T767 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3433979333 Jul 24 08:11:52 PM PDT 24 Jul 24 08:13:55 PM PDT 24 2633713776 ps
T1125 /workspace/coverage/default/2.chip_sival_flash_info_access.667829663 Jul 24 08:11:32 PM PDT 24 Jul 24 08:16:08 PM PDT 24 2997482950 ps
T1126 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.54306416 Jul 24 08:05:39 PM PDT 24 Jul 24 09:04:41 PM PDT 24 14820459984 ps
T1127 /workspace/coverage/default/0.rom_e2e_asm_init_dev.683463261 Jul 24 08:07:52 PM PDT 24 Jul 24 09:04:36 PM PDT 24 15746366405 ps
T1128 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3014302263 Jul 24 08:15:11 PM PDT 24 Jul 24 08:25:44 PM PDT 24 18580659256 ps
T50 /workspace/coverage/default/2.chip_sw_alert_test.3523606118 Jul 24 08:16:08 PM PDT 24 Jul 24 08:21:48 PM PDT 24 3268357836 ps
T1129 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.805222648 Jul 24 08:02:17 PM PDT 24 Jul 24 08:08:53 PM PDT 24 3483002720 ps
T1130 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.183513854 Jul 24 08:11:19 PM PDT 24 Jul 24 08:40:03 PM PDT 24 22425964008 ps
T317 /workspace/coverage/default/61.chip_sw_all_escalation_resets.2647955921 Jul 24 08:28:48 PM PDT 24 Jul 24 08:38:11 PM PDT 24 4804824808 ps
T279 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1953476051 Jul 24 08:22:36 PM PDT 24 Jul 24 08:33:20 PM PDT 24 5333526282 ps
T280 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2917358040 Jul 24 08:02:06 PM PDT 24 Jul 24 08:07:44 PM PDT 24 2814158752 ps
T281 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2149116816 Jul 24 08:25:43 PM PDT 24 Jul 24 08:32:08 PM PDT 24 3466571470 ps
T282 /workspace/coverage/default/0.chip_sw_example_rom.2238073260 Jul 24 07:55:26 PM PDT 24 Jul 24 07:57:42 PM PDT 24 3101914472 ps
T283 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1442864261 Jul 24 08:09:24 PM PDT 24 Jul 24 08:12:49 PM PDT 24 2586094856 ps
T284 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.314182133 Jul 24 08:23:04 PM PDT 24 Jul 24 09:19:15 PM PDT 24 14551135716 ps
T285 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1387931685 Jul 24 08:24:11 PM PDT 24 Jul 24 09:15:04 PM PDT 24 14291045310 ps
T286 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.562496233 Jul 24 08:03:29 PM PDT 24 Jul 24 08:12:09 PM PDT 24 7616690106 ps
T287 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1565679428 Jul 24 08:04:08 PM PDT 24 Jul 24 08:14:41 PM PDT 24 9179704576 ps
T288 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.903207211 Jul 24 08:20:04 PM PDT 24 Jul 24 08:25:45 PM PDT 24 3523561500 ps
T1131 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3016133262 Jul 24 08:20:11 PM PDT 24 Jul 24 08:28:09 PM PDT 24 5540456474 ps
T1132 /workspace/coverage/default/0.chip_sw_usbdev_vbus.480243499 Jul 24 07:56:59 PM PDT 24 Jul 24 08:01:28 PM PDT 24 3463833328 ps
T1133 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2988284732 Jul 24 08:20:13 PM PDT 24 Jul 24 08:27:30 PM PDT 24 4745086657 ps
T838 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4039606052 Jul 24 08:21:08 PM PDT 24 Jul 24 08:30:32 PM PDT 24 4156081174 ps
T1134 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.715018136 Jul 24 08:12:58 PM PDT 24 Jul 24 08:20:44 PM PDT 24 4135233252 ps
T267 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.333081540 Jul 24 07:59:54 PM PDT 24 Jul 24 08:11:06 PM PDT 24 6535751776 ps
T1135 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3786444429 Jul 24 07:57:44 PM PDT 24 Jul 24 08:58:15 PM PDT 24 17132791968 ps
T231 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2786759775 Jul 24 08:05:58 PM PDT 24 Jul 24 09:26:09 PM PDT 24 15674118686 ps
T1136 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2972799504 Jul 24 08:23:36 PM PDT 24 Jul 24 08:33:00 PM PDT 24 6059041364 ps
T1137 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1395376578 Jul 24 08:00:52 PM PDT 24 Jul 24 08:17:50 PM PDT 24 5798357458 ps
T401 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2592193447 Jul 24 08:04:28 PM PDT 24 Jul 24 09:35:59 PM PDT 24 24328333900 ps
T318 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3501420264 Jul 24 08:24:42 PM PDT 24 Jul 24 08:30:33 PM PDT 24 3461165842 ps
T874 /workspace/coverage/default/53.chip_sw_all_escalation_resets.4038890873 Jul 24 08:29:05 PM PDT 24 Jul 24 08:40:31 PM PDT 24 5365442920 ps
T26 /workspace/coverage/default/0.chip_sw_usbdev_stream.3762760422 Jul 24 07:57:01 PM PDT 24 Jul 24 09:10:05 PM PDT 24 18121029568 ps
T195 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3112744999 Jul 24 08:01:15 PM PDT 24 Jul 24 08:15:27 PM PDT 24 7232157379 ps
T293 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2653407100 Jul 24 07:57:58 PM PDT 24 Jul 24 08:08:27 PM PDT 24 4877131848 ps
T146 /workspace/coverage/default/0.chip_sw_usbdev_dpi.4203512144 Jul 24 07:58:03 PM PDT 24 Jul 24 08:50:49 PM PDT 24 12231327526 ps
T256 /workspace/coverage/default/1.chip_sw_plic_sw_irq.591468168 Jul 24 08:09:18 PM PDT 24 Jul 24 08:14:48 PM PDT 24 3566053784 ps
T1138 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2964346068 Jul 24 08:02:05 PM PDT 24 Jul 24 08:17:14 PM PDT 24 7023897496 ps
T1139 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.402498613 Jul 24 08:02:33 PM PDT 24 Jul 24 08:12:10 PM PDT 24 3939633204 ps
T755 /workspace/coverage/default/57.chip_sw_all_escalation_resets.4152771232 Jul 24 08:25:42 PM PDT 24 Jul 24 08:34:03 PM PDT 24 4199241592 ps
T1140 /workspace/coverage/default/0.chip_sw_example_concurrency.1722050373 Jul 24 07:57:19 PM PDT 24 Jul 24 08:01:04 PM PDT 24 2934974792 ps
T183 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.134105814 Jul 24 07:56:55 PM PDT 24 Jul 24 09:24:39 PM PDT 24 42803714802 ps
T831 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2629316169 Jul 24 08:22:19 PM PDT 24 Jul 24 08:33:02 PM PDT 24 6111585000 ps
T182 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1108325000 Jul 24 07:57:51 PM PDT 24 Jul 24 08:02:05 PM PDT 24 2112131465 ps
T1141 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3289177725 Jul 24 08:11:33 PM PDT 24 Jul 24 08:24:05 PM PDT 24 4384577956 ps
T1142 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4140970963 Jul 24 08:12:43 PM PDT 24 Jul 24 08:30:28 PM PDT 24 10616184040 ps
T336 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4172139986 Jul 24 08:18:20 PM PDT 24 Jul 24 08:47:13 PM PDT 24 14565260760 ps
T78 /workspace/coverage/default/0.chip_jtag_mem_access.598279964 Jul 24 07:50:15 PM PDT 24 Jul 24 08:14:04 PM PDT 24 13438193864 ps
T1143 /workspace/coverage/default/2.rom_e2e_asm_init_prod.3889005372 Jul 24 08:24:45 PM PDT 24 Jul 24 09:16:26 PM PDT 24 15766034203 ps
T1144 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.93726115 Jul 24 08:05:34 PM PDT 24 Jul 24 08:11:45 PM PDT 24 2541466571 ps
T319 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.639295800 Jul 24 07:56:34 PM PDT 24 Jul 24 08:01:22 PM PDT 24 3383940256 ps
T866 /workspace/coverage/default/72.chip_sw_all_escalation_resets.682203669 Jul 24 08:27:25 PM PDT 24 Jul 24 08:36:23 PM PDT 24 5050431030 ps
T1145 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1060434514 Jul 24 08:03:44 PM PDT 24 Jul 24 09:12:56 PM PDT 24 15760413940 ps
T1146 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1778356494 Jul 24 08:18:55 PM PDT 24 Jul 24 08:27:47 PM PDT 24 5908177720 ps
T1147 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.4012051208 Jul 24 08:04:51 PM PDT 24 Jul 24 08:16:09 PM PDT 24 5048805056 ps
T1148 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.633185210 Jul 24 08:06:30 PM PDT 24 Jul 24 08:14:49 PM PDT 24 4228959040 ps
T252 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2097366677 Jul 24 08:26:33 PM PDT 24 Jul 24 08:32:23 PM PDT 24 3718312942 ps
T1149 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2670401964 Jul 24 08:24:52 PM PDT 24 Jul 24 08:31:48 PM PDT 24 3355258198 ps
T1150 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.671099028 Jul 24 08:02:10 PM PDT 24 Jul 24 08:06:37 PM PDT 24 2988881106 ps
T1151 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.732990256 Jul 24 08:24:37 PM PDT 24 Jul 24 08:30:33 PM PDT 24 3604585348 ps
T352 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.887332129 Jul 24 08:03:29 PM PDT 24 Jul 24 08:15:20 PM PDT 24 4267070220 ps
T876 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1523672077 Jul 24 08:28:21 PM PDT 24 Jul 24 08:34:50 PM PDT 24 3451877642 ps
T161 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2599177260 Jul 24 08:11:50 PM PDT 24 Jul 24 08:15:08 PM PDT 24 2254634994 ps
T1152 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2885517790 Jul 24 08:17:17 PM PDT 24 Jul 24 08:21:25 PM PDT 24 7211284280 ps
T1153 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2705700923 Jul 24 08:08:37 PM PDT 24 Jul 24 08:47:43 PM PDT 24 9466378488 ps
T1154 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3161773836 Jul 24 08:17:28 PM PDT 24 Jul 24 09:07:36 PM PDT 24 21304617687 ps
T1155 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3013956315 Jul 24 08:01:23 PM PDT 24 Jul 24 08:09:53 PM PDT 24 4406744100 ps
T1156 /workspace/coverage/default/0.chip_sw_csrng_kat_test.3806964113 Jul 24 08:01:38 PM PDT 24 Jul 24 08:05:30 PM PDT 24 2560179584 ps
T1157 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1346629511 Jul 24 07:59:24 PM PDT 24 Jul 24 08:04:58 PM PDT 24 3262794696 ps
T1158 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2504895423 Jul 24 08:23:06 PM PDT 24 Jul 24 08:31:39 PM PDT 24 4299051104 ps
T1159 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.741988261 Jul 24 08:09:32 PM PDT 24 Jul 24 08:19:55 PM PDT 24 5369330000 ps
T1160 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1301462289 Jul 24 07:57:40 PM PDT 24 Jul 24 08:06:08 PM PDT 24 3460529346 ps
T344 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4221032327 Jul 24 07:56:26 PM PDT 24 Jul 24 08:11:56 PM PDT 24 5332980572 ps
T90 /workspace/coverage/default/24.chip_sw_all_escalation_resets.848489787 Jul 24 08:24:14 PM PDT 24 Jul 24 08:33:52 PM PDT 24 6157089110 ps
T176 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2313103636 Jul 24 07:57:02 PM PDT 24 Jul 24 07:59:36 PM PDT 24 3195066704 ps
T1161 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.756156317 Jul 24 07:55:51 PM PDT 24 Jul 24 08:01:57 PM PDT 24 6455945974 ps
T350 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1259590262 Jul 24 08:08:42 PM PDT 24 Jul 24 08:16:44 PM PDT 24 3146661492 ps
T198 /workspace/coverage/default/0.chip_jtag_csr_rw.3289409415 Jul 24 07:50:09 PM PDT 24 Jul 24 08:29:58 PM PDT 24 18953799638 ps
T1162 /workspace/coverage/default/0.chip_sw_power_idle_load.3609652066 Jul 24 07:57:51 PM PDT 24 Jul 24 08:08:28 PM PDT 24 4782792908 ps
T240 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1661167315 Jul 24 08:04:09 PM PDT 24 Jul 24 09:25:46 PM PDT 24 46476811260 ps
T1163 /workspace/coverage/default/1.chip_sw_hmac_oneshot.1951601340 Jul 24 08:08:21 PM PDT 24 Jul 24 08:13:18 PM PDT 24 2356836500 ps
T1164 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.81196388 Jul 24 07:56:44 PM PDT 24 Jul 24 08:26:32 PM PDT 24 8822314297 ps
T383 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.846627899 Jul 24 08:22:15 PM PDT 24 Jul 24 08:27:49 PM PDT 24 4025849820 ps
T1165 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3448216168 Jul 24 08:18:05 PM PDT 24 Jul 24 08:28:47 PM PDT 24 4193021264 ps
T160 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1692758362 Jul 24 08:06:06 PM PDT 24 Jul 24 08:12:26 PM PDT 24 3709922451 ps
T1166 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2103580848 Jul 24 08:15:41 PM PDT 24 Jul 24 08:27:04 PM PDT 24 5059523088 ps
T63 /workspace/coverage/default/3.chip_tap_straps_testunlock0.4291773780 Jul 24 08:18:50 PM PDT 24 Jul 24 08:30:55 PM PDT 24 6858606836 ps
T805 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1775024606 Jul 24 08:00:33 PM PDT 24 Jul 24 08:13:28 PM PDT 24 5889927110 ps
T1167 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2925009618 Jul 24 08:08:07 PM PDT 24 Jul 24 08:36:36 PM PDT 24 9605499284 ps
T1168 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.845900041 Jul 24 07:59:52 PM PDT 24 Jul 24 08:05:29 PM PDT 24 3922104990 ps
T378 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2875975985 Jul 24 08:08:36 PM PDT 24 Jul 24 08:15:51 PM PDT 24 6170556884 ps
T1169 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2487969556 Jul 24 08:08:22 PM PDT 24 Jul 24 08:12:49 PM PDT 24 3109038200 ps
T1170 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3948342413 Jul 24 07:59:46 PM PDT 24 Jul 24 08:18:09 PM PDT 24 7740662416 ps
T839 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1788811964 Jul 24 08:20:22 PM PDT 24 Jul 24 08:32:02 PM PDT 24 5216717540 ps
T379 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2064868022 Jul 24 08:00:28 PM PDT 24 Jul 24 08:07:33 PM PDT 24 5618394344 ps
T1171 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.4244744545 Jul 24 08:10:11 PM PDT 24 Jul 25 12:06:30 AM PDT 24 79129293480 ps
T402 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.804557305 Jul 24 08:06:14 PM PDT 24 Jul 24 09:45:52 PM PDT 24 23718261400 ps
T1172 /workspace/coverage/default/1.rom_e2e_asm_init_prod.1717250896 Jul 24 08:12:59 PM PDT 24 Jul 24 09:10:43 PM PDT 24 15355995731 ps
T1173 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.332112616 Jul 24 08:03:27 PM PDT 24 Jul 24 08:21:31 PM PDT 24 6584163827 ps
T1174 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2170207374 Jul 24 07:58:15 PM PDT 24 Jul 24 08:07:42 PM PDT 24 8862398390 ps
T232 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1890423074 Jul 24 08:15:04 PM PDT 24 Jul 24 09:12:07 PM PDT 24 13181316808 ps
T1175 /workspace/coverage/default/1.chip_tap_straps_prod.3788313316 Jul 24 08:13:02 PM PDT 24 Jul 24 08:15:43 PM PDT 24 2906157582 ps
T1176 /workspace/coverage/default/2.chip_sw_kmac_smoketest.1738312468 Jul 24 08:20:16 PM PDT 24 Jul 24 08:24:52 PM PDT 24 2762310952 ps
T1177 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3771324506 Jul 24 08:12:11 PM PDT 24 Jul 24 08:19:19 PM PDT 24 4682133910 ps
T834 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1036228355 Jul 24 08:05:30 PM PDT 24 Jul 24 08:17:02 PM PDT 24 5651021744 ps
T1178 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.136722229 Jul 24 08:14:52 PM PDT 24 Jul 24 08:18:40 PM PDT 24 2308291184 ps
T1179 /workspace/coverage/default/0.chip_sw_edn_sw_mode.2239701304 Jul 24 07:57:21 PM PDT 24 Jul 24 08:37:39 PM PDT 24 9488666472 ps
T1180 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3184617399 Jul 24 08:21:23 PM PDT 24 Jul 24 08:28:27 PM PDT 24 6730967263 ps
T155 /workspace/coverage/default/2.chip_plic_all_irqs_10.3146886087 Jul 24 08:19:39 PM PDT 24 Jul 24 08:30:40 PM PDT 24 4456418622 ps
T36 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1978815016 Jul 24 08:02:19 PM PDT 24 Jul 24 08:07:51 PM PDT 24 3227940472 ps
T1181 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.4162829858 Jul 24 08:25:39 PM PDT 24 Jul 24 08:44:11 PM PDT 24 5983983616 ps
T1182 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2027276337 Jul 24 08:06:28 PM PDT 24 Jul 24 09:05:08 PM PDT 24 15067710710 ps
T1183 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1194269199 Jul 24 08:02:10 PM PDT 24 Jul 24 09:39:52 PM PDT 24 47329749418 ps
T1184 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2696107911 Jul 24 08:14:03 PM PDT 24 Jul 24 08:37:36 PM PDT 24 16120752610 ps
T1185 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1586909440 Jul 24 08:20:30 PM PDT 24 Jul 24 08:27:50 PM PDT 24 5179039248 ps
T1186 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.210341236 Jul 24 08:15:19 PM PDT 24 Jul 24 08:20:34 PM PDT 24 2998564000 ps
T103 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.102696909 Jul 24 08:08:22 PM PDT 24 Jul 24 08:29:13 PM PDT 24 19358161896 ps
T1187 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1541205650 Jul 24 08:05:43 PM PDT 24 Jul 24 09:00:18 PM PDT 24 15136983984 ps
T104 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.513314224 Jul 24 07:59:46 PM PDT 24 Jul 24 08:07:36 PM PDT 24 7735789658 ps
T303 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.890208779 Jul 24 08:07:12 PM PDT 24 Jul 24 08:10:21 PM PDT 24 2384666644 ps
T888 /workspace/coverage/default/84.chip_sw_all_escalation_resets.1140203295 Jul 24 08:27:59 PM PDT 24 Jul 24 08:37:08 PM PDT 24 4681665030 ps
T105 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2443593919 Jul 24 08:19:29 PM PDT 24 Jul 24 08:44:15 PM PDT 24 24878720586 ps
T820 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2615831898 Jul 24 08:23:13 PM PDT 24 Jul 24 08:32:06 PM PDT 24 3104004900 ps
T1188 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3256490962 Jul 24 08:17:52 PM PDT 24 Jul 24 08:38:04 PM PDT 24 8374388408 ps
T1189 /workspace/coverage/default/1.chip_tap_straps_dev.1912668132 Jul 24 08:07:17 PM PDT 24 Jul 24 08:10:58 PM PDT 24 2613248492 ps
T768 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.622995137 Jul 24 08:11:37 PM PDT 24 Jul 24 08:15:05 PM PDT 24 4145257694 ps
T417 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2930642538 Jul 24 08:17:10 PM PDT 24 Jul 24 08:26:21 PM PDT 24 7680376142 ps
T761 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1476705929 Jul 24 08:20:31 PM PDT 24 Jul 24 08:35:21 PM PDT 24 6529003275 ps
T769 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3119740784 Jul 24 08:01:44 PM PDT 24 Jul 24 08:03:31 PM PDT 24 2702895911 ps
T1190 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1270632300 Jul 24 08:08:04 PM PDT 24 Jul 24 08:18:38 PM PDT 24 4198214168 ps
T883 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2241940922 Jul 24 08:21:04 PM PDT 24 Jul 24 08:34:51 PM PDT 24 5086730880 ps
T1191 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2564141314 Jul 24 08:05:06 PM PDT 24 Jul 24 09:07:49 PM PDT 24 17415672952 ps
T1192 /workspace/coverage/default/2.chip_sw_aes_enc.2963954338 Jul 24 08:18:07 PM PDT 24 Jul 24 08:23:44 PM PDT 24 3111871064 ps
T1193 /workspace/coverage/default/45.chip_sw_all_escalation_resets.4128394572 Jul 24 08:26:01 PM PDT 24 Jul 24 08:39:06 PM PDT 24 4805985392 ps
T887 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.844164933 Jul 24 08:25:09 PM PDT 24 Jul 24 08:30:23 PM PDT 24 3727983512 ps
T208 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.242488121 Jul 24 08:12:59 PM PDT 24 Jul 24 08:19:14 PM PDT 24 3134267368 ps
T1194 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3787363233 Jul 24 08:02:06 PM PDT 24 Jul 24 08:11:34 PM PDT 24 5627808522 ps
T1195 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2173252416 Jul 24 08:06:17 PM PDT 24 Jul 24 09:38:40 PM PDT 24 18324614558 ps
T1196 /workspace/coverage/default/2.rom_e2e_self_hash.2420801824 Jul 24 08:24:28 PM PDT 24 Jul 24 10:12:50 PM PDT 24 26231254322 ps
T1197 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1105649910 Jul 24 07:56:49 PM PDT 24 Jul 24 08:03:46 PM PDT 24 5167312900 ps
T1198 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1366077581 Jul 24 08:23:17 PM PDT 24 Jul 24 09:14:15 PM PDT 24 14967761960 ps
T1199 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3481896428 Jul 24 07:59:42 PM PDT 24 Jul 24 09:05:09 PM PDT 24 24722059326 ps
T835 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1250675501 Jul 24 08:10:39 PM PDT 24 Jul 24 08:21:26 PM PDT 24 5099042720 ps
T1200 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2330640555 Jul 24 08:17:19 PM PDT 24 Jul 24 08:28:41 PM PDT 24 4593656304 ps
T1201 /workspace/coverage/default/30.chip_sw_all_escalation_resets.947334889 Jul 24 08:24:57 PM PDT 24 Jul 24 08:35:48 PM PDT 24 6177317590 ps
T1202 /workspace/coverage/default/2.chip_sw_example_rom.3924019203 Jul 24 08:11:36 PM PDT 24 Jul 24 08:13:47 PM PDT 24 2438558222 ps
T1203 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1902554448 Jul 24 08:06:37 PM PDT 24 Jul 24 08:22:20 PM PDT 24 7766973868 ps
T1204 /workspace/coverage/default/0.chip_sw_kmac_entropy.2034698917 Jul 24 07:57:42 PM PDT 24 Jul 24 08:01:25 PM PDT 24 2905658528 ps
T1205 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3364483346 Jul 24 08:01:13 PM PDT 24 Jul 24 08:05:54 PM PDT 24 3607523113 ps
T1206 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2717191861 Jul 24 08:04:06 PM PDT 24 Jul 24 09:16:50 PM PDT 24 14612016305 ps
T442 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1151884217 Jul 24 08:02:47 PM PDT 24 Jul 24 08:38:40 PM PDT 24 27785536199 ps
T1207 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4084980966 Jul 24 08:11:57 PM PDT 24 Jul 24 08:34:24 PM PDT 24 9280824760 ps
T1208 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2643386697 Jul 24 08:15:11 PM PDT 24 Jul 24 08:19:47 PM PDT 24 2547185640 ps
T1209 /workspace/coverage/default/77.chip_sw_all_escalation_resets.1423677148 Jul 24 08:33:32 PM PDT 24 Jul 24 08:45:08 PM PDT 24 5821389592 ps
T1210 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1434961136 Jul 24 08:23:02 PM PDT 24 Jul 24 08:30:51 PM PDT 24 6441039513 ps
T1211 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.763451732 Jul 24 07:57:31 PM PDT 24 Jul 24 07:59:25 PM PDT 24 2292269931 ps
T809 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2729196945 Jul 24 08:28:24 PM PDT 24 Jul 24 08:34:11 PM PDT 24 4019958168 ps
T815 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1561243451 Jul 24 08:29:51 PM PDT 24 Jul 24 08:40:07 PM PDT 24 5436435810 ps
T296 /workspace/coverage/default/28.chip_sw_all_escalation_resets.1635720497 Jul 24 08:24:43 PM PDT 24 Jul 24 08:36:33 PM PDT 24 5364809256 ps
T1212 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1878774325 Jul 24 08:01:06 PM PDT 24 Jul 24 08:02:45 PM PDT 24 2804831363 ps
T1213 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2528660945 Jul 24 08:18:33 PM PDT 24 Jul 24 08:55:11 PM PDT 24 25178182528 ps
T867 /workspace/coverage/default/56.chip_sw_all_escalation_resets.936449397 Jul 24 08:25:29 PM PDT 24 Jul 24 08:36:26 PM PDT 24 5181312044 ps
T431 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.623604792 Jul 24 08:01:22 PM PDT 24 Jul 24 08:34:35 PM PDT 24 26824214354 ps
T1214 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1695114433 Jul 24 08:02:06 PM PDT 24 Jul 24 08:37:35 PM PDT 24 13353511074 ps
T1215 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1946499944 Jul 24 08:18:54 PM PDT 24 Jul 24 08:29:57 PM PDT 24 5015721632 ps
T1216 /workspace/coverage/default/81.chip_sw_all_escalation_resets.4160321642 Jul 24 08:27:57 PM PDT 24 Jul 24 08:38:29 PM PDT 24 5889255260 ps
T1217 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2153183053 Jul 24 08:21:04 PM PDT 24 Jul 24 09:14:14 PM PDT 24 15616509140 ps
T37 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3725968210 Jul 24 08:10:53 PM PDT 24 Jul 24 08:15:02 PM PDT 24 2365904076 ps
T1218 /workspace/coverage/default/2.chip_sw_aes_smoketest.4012996243 Jul 24 08:18:38 PM PDT 24 Jul 24 08:24:19 PM PDT 24 3350458834 ps
T1219 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2646591100 Jul 24 08:06:32 PM PDT 24 Jul 24 09:21:39 PM PDT 24 14711256612 ps
T91 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1424943763 Jul 24 08:26:19 PM PDT 24 Jul 24 08:31:49 PM PDT 24 4326437976 ps
T1220 /workspace/coverage/default/2.chip_sw_kmac_entropy.838757334 Jul 24 08:14:31 PM PDT 24 Jul 24 08:20:02 PM PDT 24 2798374520 ps
T889 /workspace/coverage/default/46.chip_sw_all_escalation_resets.3569723966 Jul 24 08:26:28 PM PDT 24 Jul 24 08:34:46 PM PDT 24 5565712060 ps
T1221 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.563952305 Jul 24 08:21:17 PM PDT 24 Jul 24 08:27:45 PM PDT 24 3126476600 ps
T1222 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3235861540 Jul 24 08:23:09 PM PDT 24 Jul 24 09:10:28 PM PDT 24 12437858616 ps
T800 /workspace/coverage/default/0.chip_sw_pattgen_ios.3730389195 Jul 24 07:56:58 PM PDT 24 Jul 24 08:01:25 PM PDT 24 2702991908 ps
T1223 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2117478079 Jul 24 08:04:00 PM PDT 24 Jul 24 08:23:27 PM PDT 24 10752978241 ps
T1224 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3568582127 Jul 24 08:10:33 PM PDT 24 Jul 24 08:19:17 PM PDT 24 5254821608 ps
T848 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2325404228 Jul 24 08:24:42 PM PDT 24 Jul 24 08:32:46 PM PDT 24 3585975156 ps
T1225 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3602026522 Jul 24 07:58:24 PM PDT 24 Jul 24 08:11:13 PM PDT 24 4618264996 ps
T345 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1975178721 Jul 24 07:57:13 PM PDT 24 Jul 24 08:06:37 PM PDT 24 3611490996 ps
T1226 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1689911173 Jul 24 08:06:17 PM PDT 24 Jul 24 09:22:38 PM PDT 24 15461486284 ps
T817 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3687018504 Jul 24 08:22:20 PM PDT 24 Jul 24 08:28:33 PM PDT 24 3482912696 ps
T167 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3182578734 Jul 24 08:08:27 PM PDT 24 Jul 24 08:19:16 PM PDT 24 5465007440 ps
T1227 /workspace/coverage/default/2.chip_sw_uart_smoketest.2039436622 Jul 24 08:21:06 PM PDT 24 Jul 24 08:26:29 PM PDT 24 2989843824 ps
T1228 /workspace/coverage/default/1.chip_sw_edn_kat.1595795451 Jul 24 08:07:07 PM PDT 24 Jul 24 08:17:54 PM PDT 24 3125145690 ps
T58 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.4146580650 Jul 24 07:57:12 PM PDT 24 Jul 24 08:01:11 PM PDT 24 3804919480 ps
T422 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3270074485 Jul 24 08:15:06 PM PDT 24 Jul 24 08:25:27 PM PDT 24 6103918611 ps
T423 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.491922372 Jul 24 08:00:56 PM PDT 24 Jul 24 08:05:51 PM PDT 24 2960959483 ps
T424 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3628163264 Jul 24 08:03:45 PM PDT 24 Jul 24 08:11:23 PM PDT 24 4565949350 ps
T425 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1932438097 Jul 24 08:06:28 PM PDT 24 Jul 24 08:14:41 PM PDT 24 4205709296 ps
T426 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.961232936 Jul 24 08:14:29 PM PDT 24 Jul 24 08:31:39 PM PDT 24 4995676828 ps
T427 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2905156230 Jul 24 07:59:19 PM PDT 24 Jul 24 08:49:59 PM PDT 24 31022335250 ps
T428 /workspace/coverage/default/29.chip_sw_all_escalation_resets.1695446450 Jul 24 08:23:35 PM PDT 24 Jul 24 08:33:09 PM PDT 24 5078531316 ps
T429 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1893635 Jul 24 08:03:41 PM PDT 24 Jul 24 08:12:14 PM PDT 24 7079495684 ps
T430 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2452127733 Jul 24 08:02:54 PM PDT 24 Jul 24 08:12:40 PM PDT 24 6433183536 ps
T1229 /workspace/coverage/default/1.chip_sw_aes_entropy.125232351 Jul 24 08:05:39 PM PDT 24 Jul 24 08:10:02 PM PDT 24 3182416384 ps
T893 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2195663572 Jul 24 08:31:19 PM PDT 24 Jul 24 08:38:50 PM PDT 24 3807754500 ps
T884 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3134889158 Jul 24 08:33:00 PM PDT 24 Jul 24 08:41:06 PM PDT 24 3409435904 ps
T1230 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.457401035 Jul 24 07:58:37 PM PDT 24 Jul 24 08:02:51 PM PDT 24 2804592154 ps
T1231 /workspace/coverage/default/86.chip_sw_all_escalation_resets.2993110481 Jul 24 08:27:50 PM PDT 24 Jul 24 08:37:27 PM PDT 24 5288127506 ps
T1232 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3786130492 Jul 24 08:21:34 PM PDT 24 Jul 24 08:39:32 PM PDT 24 12854184578 ps
T1233 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3803086324 Jul 24 08:17:00 PM PDT 24 Jul 24 08:21:47 PM PDT 24 2373526535 ps
T1234 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1019416726 Jul 24 08:17:52 PM PDT 24 Jul 24 08:28:27 PM PDT 24 4669026936 ps
T1235 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3630865857 Jul 24 08:05:25 PM PDT 24 Jul 24 08:15:23 PM PDT 24 3850935450 ps
T1236 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.591652709 Jul 24 08:01:32 PM PDT 24 Jul 24 08:06:57 PM PDT 24 2886037292 ps
T1237 /workspace/coverage/default/0.chip_sw_hmac_smoketest.2227143959 Jul 24 08:02:28 PM PDT 24 Jul 24 08:07:35 PM PDT 24 3692030000 ps
T320 /workspace/coverage/default/63.chip_sw_all_escalation_resets.128356509 Jul 24 08:31:31 PM PDT 24 Jul 24 08:42:36 PM PDT 24 5054231726 ps
T380 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2522573741 Jul 24 08:17:17 PM PDT 24 Jul 24 08:24:54 PM PDT 24 5495891030 ps
T321 /workspace/coverage/default/80.chip_sw_all_escalation_resets.3928555111 Jul 24 08:29:30 PM PDT 24 Jul 24 08:38:57 PM PDT 24 5330878996 ps
T1238 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.896312430 Jul 24 08:06:21 PM PDT 24 Jul 24 11:22:11 PM PDT 24 254366646780 ps
T1239 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3097811911 Jul 24 08:00:52 PM PDT 24 Jul 24 08:09:39 PM PDT 24 4087909868 ps
T1240 /workspace/coverage/default/20.chip_sw_all_escalation_resets.1552236432 Jul 24 08:23:44 PM PDT 24 Jul 24 08:35:21 PM PDT 24 6166774092 ps
T1241 /workspace/coverage/default/2.rom_e2e_asm_init_rma.1051695274 Jul 24 08:23:30 PM PDT 24 Jul 24 09:10:54 PM PDT 24 14552062582 ps
T184 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1444437671 Jul 24 08:02:38 PM PDT 24 Jul 24 09:27:08 PM PDT 24 43413735240 ps
T1242 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3530244683 Jul 24 07:57:04 PM PDT 24 Jul 24 09:33:38 PM PDT 24 48998024850 ps
T1243 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2861792655 Jul 24 07:58:31 PM PDT 24 Jul 24 08:03:26 PM PDT 24 2501372472 ps
T853 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2085500520 Jul 24 08:28:41 PM PDT 24 Jul 24 08:33:44 PM PDT 24 3692039350 ps
T1244 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3982201154 Jul 24 08:20:01 PM PDT 24 Jul 24 08:26:17 PM PDT 24 3013256760 ps
T854 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3396339777 Jul 24 08:28:56 PM PDT 24 Jul 24 08:35:35 PM PDT 24 3355976996 ps
T1245 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2137238122 Jul 24 08:12:23 PM PDT 24 Jul 24 08:19:31 PM PDT 24 5819159960 ps
T309 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3199154217 Jul 24 08:04:46 PM PDT 24 Jul 24 08:21:22 PM PDT 24 9202594082 ps
T1246 /workspace/coverage/default/2.chip_sw_flash_init.2541937177 Jul 24 08:14:23 PM PDT 24 Jul 24 08:46:37 PM PDT 24 17078568500 ps
T1247 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2308565596 Jul 24 08:06:44 PM PDT 24 Jul 24 08:15:08 PM PDT 24 3202983872 ps
T1248 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2909859205 Jul 24 08:05:46 PM PDT 24 Jul 24 09:41:45 PM PDT 24 22825026140 ps
T1249 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.286418925 Jul 24 07:59:12 PM PDT 24 Jul 24 08:10:24 PM PDT 24 5819279616 ps
T1250 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.90734902 Jul 24 08:01:16 PM PDT 24 Jul 24 08:12:46 PM PDT 24 8396074720 ps
T1251 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1907965128 Jul 24 08:21:15 PM PDT 24 Jul 24 08:48:56 PM PDT 24 7228966300 ps
T432 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2786644205 Jul 24 08:07:27 PM PDT 24 Jul 24 08:39:27 PM PDT 24 22698123808 ps
T1252 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2730494491 Jul 24 08:18:30 PM PDT 24 Jul 24 08:23:31 PM PDT 24 3170726070 ps
T1253 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1645527284 Jul 24 08:03:56 PM PDT 24 Jul 24 08:13:11 PM PDT 24 4433581946 ps
T1254 /workspace/coverage/default/3.chip_tap_straps_prod.1007500591 Jul 24 08:19:19 PM PDT 24 Jul 24 08:21:55 PM PDT 24 2533125017 ps
T1255 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1695765023 Jul 24 08:00:57 PM PDT 24 Jul 24 08:07:09 PM PDT 24 3275047412 ps
T1256 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3652605272 Jul 24 08:07:38 PM PDT 24 Jul 24 08:11:40 PM PDT 24 3220805955 ps
T1257 /workspace/coverage/default/0.chip_sival_flash_info_access.3132542770 Jul 24 07:59:00 PM PDT 24 Jul 24 08:03:59 PM PDT 24 3049577232 ps
T1258 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3949311725 Jul 24 08:01:19 PM PDT 24 Jul 24 08:09:04 PM PDT 24 4856016000 ps
T1259 /workspace/coverage/default/1.chip_sw_gpio_smoketest.4194686647 Jul 24 08:09:38 PM PDT 24 Jul 24 08:14:21 PM PDT 24 2809998369 ps
T862 /workspace/coverage/default/93.chip_sw_all_escalation_resets.1128913774 Jul 24 08:29:17 PM PDT 24 Jul 24 08:38:47 PM PDT 24 6170967096 ps
T1260 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1069028549 Jul 24 08:23:12 PM PDT 24 Jul 24 08:33:09 PM PDT 24 4221713808 ps
T1261 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.897693624 Jul 24 08:02:40 PM PDT 24 Jul 24 08:07:38 PM PDT 24 3369094839 ps
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