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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.00 95.37 93.66 95.41 94.47 97.53 99.54


Total test records in report: 2932
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T875 /workspace/coverage/default/16.chip_sw_all_escalation_resets.1800198506 Jul 24 08:23:28 PM PDT 24 Jul 24 08:31:06 PM PDT 24 5317549580 ps
T1262 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.370467343 Jul 24 08:04:34 PM PDT 24 Jul 24 08:52:50 PM PDT 24 11571196100 ps
T415 /workspace/coverage/default/1.chip_sw_kmac_app_rom.3182226004 Jul 24 08:05:02 PM PDT 24 Jul 24 08:09:26 PM PDT 24 2751971720 ps
T1263 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2549766755 Jul 24 08:04:03 PM PDT 24 Jul 24 08:35:27 PM PDT 24 26305132239 ps
T763 /workspace/coverage/default/2.chip_tap_straps_dev.3330241651 Jul 24 08:16:52 PM PDT 24 Jul 24 08:44:57 PM PDT 24 15910934528 ps
T168 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3272809357 Jul 24 08:00:11 PM PDT 24 Jul 24 08:10:03 PM PDT 24 4688389632 ps
T1264 /workspace/coverage/default/4.chip_tap_straps_prod.1278368725 Jul 24 08:20:21 PM PDT 24 Jul 24 08:22:51 PM PDT 24 3104253740 ps
T334 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3227031107 Jul 24 08:02:18 PM PDT 24 Jul 24 08:32:01 PM PDT 24 10622450848 ps
T262 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2555739939 Jul 24 08:02:40 PM PDT 24 Jul 24 08:33:24 PM PDT 24 10950425907 ps
T846 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3045882244 Jul 24 08:25:58 PM PDT 24 Jul 24 08:34:48 PM PDT 24 4339864776 ps
T1265 /workspace/coverage/default/1.chip_sw_aes_masking_off.1314277732 Jul 24 08:03:24 PM PDT 24 Jul 24 08:09:41 PM PDT 24 3384775522 ps
T1266 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4249305881 Jul 24 08:16:20 PM PDT 24 Jul 24 08:25:45 PM PDT 24 4875836336 ps
T1267 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1648947638 Jul 24 08:15:05 PM PDT 24 Jul 24 08:34:28 PM PDT 24 5910814406 ps
T1268 /workspace/coverage/default/1.chip_sw_kmac_smoketest.2694699756 Jul 24 08:09:30 PM PDT 24 Jul 24 08:16:19 PM PDT 24 2789350620 ps
T1269 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3181771615 Jul 24 08:01:32 PM PDT 24 Jul 24 08:24:06 PM PDT 24 12305386534 ps
T1270 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1125301654 Jul 24 08:15:18 PM PDT 24 Jul 24 08:23:24 PM PDT 24 6102649914 ps
T1271 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3635171221 Jul 24 08:22:29 PM PDT 24 Jul 24 09:02:47 PM PDT 24 13453743220 ps
T1272 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.4090775276 Jul 24 08:05:58 PM PDT 24 Jul 24 08:09:43 PM PDT 24 2308978378 ps
T1273 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3245018570 Jul 24 08:12:11 PM PDT 24 Jul 24 08:59:20 PM PDT 24 11511441873 ps
T1274 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3541910706 Jul 24 08:23:26 PM PDT 24 Jul 24 08:38:46 PM PDT 24 11681787764 ps
T1275 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2513962839 Jul 24 08:06:12 PM PDT 24 Jul 24 08:10:57 PM PDT 24 3229451392 ps
T1276 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2687498640 Jul 24 07:58:11 PM PDT 24 Jul 24 08:09:46 PM PDT 24 5338607928 ps
T1277 /workspace/coverage/default/54.chip_sw_all_escalation_resets.2083965230 Jul 24 08:26:49 PM PDT 24 Jul 24 08:39:31 PM PDT 24 6390279894 ps
T1278 /workspace/coverage/default/0.chip_sw_rv_timer_irq.985286250 Jul 24 07:57:31 PM PDT 24 Jul 24 08:02:48 PM PDT 24 2707400076 ps
T1279 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3201299293 Jul 24 08:24:46 PM PDT 24 Jul 24 08:51:37 PM PDT 24 8600545802 ps
T1280 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1323599884 Jul 24 08:00:38 PM PDT 24 Jul 24 08:20:39 PM PDT 24 7177164887 ps
T1281 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2713929281 Jul 24 08:17:24 PM PDT 24 Jul 24 08:44:42 PM PDT 24 24380960917 ps
T1282 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.152097851 Jul 24 07:58:15 PM PDT 24 Jul 24 08:26:04 PM PDT 24 8243993548 ps
T1283 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1186388266 Jul 24 08:03:53 PM PDT 24 Jul 24 08:09:26 PM PDT 24 3157345640 ps
T1284 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.4107196301 Jul 24 08:01:25 PM PDT 24 Jul 24 08:08:55 PM PDT 24 5792495000 ps
T1285 /workspace/coverage/default/1.chip_sw_uart_smoketest.213656859 Jul 24 08:08:57 PM PDT 24 Jul 24 08:12:51 PM PDT 24 2604652060 ps
T1286 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4142626602 Jul 24 07:58:06 PM PDT 24 Jul 24 08:10:23 PM PDT 24 18705438992 ps
T841 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2336790302 Jul 24 08:19:32 PM PDT 24 Jul 24 08:43:24 PM PDT 24 13104388976 ps
T1287 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2578560325 Jul 24 08:16:47 PM PDT 24 Jul 24 08:26:19 PM PDT 24 4595864526 ps
T1288 /workspace/coverage/default/1.chip_sw_example_concurrency.295262342 Jul 24 08:04:07 PM PDT 24 Jul 24 08:08:32 PM PDT 24 2954320062 ps
T871 /workspace/coverage/default/27.chip_sw_all_escalation_resets.3179423763 Jul 24 08:25:06 PM PDT 24 Jul 24 08:36:29 PM PDT 24 5885112306 ps
T1289 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.870295749 Jul 24 08:02:10 PM PDT 24 Jul 24 08:12:27 PM PDT 24 5949376004 ps
T1290 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2945607237 Jul 24 08:04:04 PM PDT 24 Jul 24 09:08:46 PM PDT 24 15096560659 ps
T1291 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1573103652 Jul 24 08:07:48 PM PDT 24 Jul 24 08:13:10 PM PDT 24 3071166196 ps
T416 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3280893556 Jul 24 08:06:33 PM PDT 24 Jul 24 08:12:11 PM PDT 24 3291917330 ps
T1292 /workspace/coverage/default/0.chip_sw_aes_entropy.1942622574 Jul 24 07:58:19 PM PDT 24 Jul 24 08:02:55 PM PDT 24 3286487682 ps
T1293 /workspace/coverage/default/2.rom_e2e_smoke.511056145 Jul 24 08:22:46 PM PDT 24 Jul 24 09:16:10 PM PDT 24 14813876344 ps
T1294 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1416297322 Jul 24 08:07:56 PM PDT 24 Jul 24 08:19:32 PM PDT 24 4243883988 ps
T812 /workspace/coverage/default/23.chip_sw_all_escalation_resets.2633523565 Jul 24 08:25:35 PM PDT 24 Jul 24 08:33:27 PM PDT 24 5047298462 ps
T850 /workspace/coverage/default/4.chip_sw_all_escalation_resets.4101921816 Jul 24 08:22:04 PM PDT 24 Jul 24 08:33:41 PM PDT 24 4639048400 ps
T1295 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.506942504 Jul 24 08:03:22 PM PDT 24 Jul 24 08:26:46 PM PDT 24 8676446920 ps
T1296 /workspace/coverage/default/2.chip_sw_rv_timer_irq.3355971181 Jul 24 08:15:05 PM PDT 24 Jul 24 08:18:14 PM PDT 24 3178233688 ps
T1297 /workspace/coverage/default/2.rom_raw_unlock.2581599805 Jul 24 08:20:07 PM PDT 24 Jul 24 08:24:47 PM PDT 24 6553103925 ps
T297 /workspace/coverage/default/19.chip_sw_all_escalation_resets.1126702028 Jul 24 08:25:00 PM PDT 24 Jul 24 08:33:24 PM PDT 24 5489059080 ps
T304 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1564463346 Jul 24 08:13:25 PM PDT 24 Jul 24 08:19:19 PM PDT 24 3605242150 ps
T1298 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3343727596 Jul 24 08:10:11 PM PDT 24 Jul 24 08:17:27 PM PDT 24 3310054116 ps
T1299 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1930276882 Jul 24 07:59:47 PM PDT 24 Jul 24 09:28:33 PM PDT 24 27857714960 ps
T1300 /workspace/coverage/default/1.rom_e2e_self_hash.2772182225 Jul 24 08:13:04 PM PDT 24 Jul 24 09:52:07 PM PDT 24 26213423764 ps
T1301 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1323971929 Jul 24 07:58:06 PM PDT 24 Jul 24 11:13:22 PM PDT 24 254972031914 ps
T313 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.705715914 Jul 24 07:59:06 PM PDT 24 Jul 24 08:10:22 PM PDT 24 5679850216 ps
T1302 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2301582373 Jul 24 08:00:47 PM PDT 24 Jul 24 11:28:09 PM PDT 24 65207384056 ps
T1303 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.15968193 Jul 24 08:04:21 PM PDT 24 Jul 24 10:58:37 PM PDT 24 58272490295 ps
T347 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1581009737 Jul 24 08:00:59 PM PDT 24 Jul 24 08:08:40 PM PDT 24 3888827376 ps
T1304 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1608827838 Jul 24 07:56:51 PM PDT 24 Jul 24 08:10:06 PM PDT 24 4843699440 ps
T1305 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2417781350 Jul 24 08:07:40 PM PDT 24 Jul 24 08:15:20 PM PDT 24 3906447180 ps
T1306 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2391853870 Jul 24 08:13:18 PM PDT 24 Jul 24 08:21:51 PM PDT 24 4494542544 ps
T1307 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2141017852 Jul 24 07:58:23 PM PDT 24 Jul 24 08:07:15 PM PDT 24 4463257208 ps
T1308 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1837728287 Jul 24 08:08:04 PM PDT 24 Jul 24 08:58:29 PM PDT 24 10415828658 ps
T1309 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1084167250 Jul 24 07:56:27 PM PDT 24 Jul 24 08:05:14 PM PDT 24 4371783642 ps
T1310 /workspace/coverage/default/1.rom_raw_unlock.282955214 Jul 24 08:10:01 PM PDT 24 Jul 24 08:14:43 PM PDT 24 5366527877 ps
T1311 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.1120105148 Jul 24 08:16:02 PM PDT 24 Jul 24 08:21:23 PM PDT 24 3651357409 ps
T1312 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1105056077 Jul 24 08:05:36 PM PDT 24 Jul 24 08:10:58 PM PDT 24 2415226140 ps
T1313 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2286185766 Jul 24 08:08:52 PM PDT 24 Jul 24 08:15:20 PM PDT 24 3441932070 ps
T1314 /workspace/coverage/default/2.chip_sw_kmac_app_rom.3512425170 Jul 24 08:16:09 PM PDT 24 Jul 24 08:20:34 PM PDT 24 2803876248 ps
T1315 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3458160367 Jul 24 07:58:06 PM PDT 24 Jul 24 08:27:47 PM PDT 24 7605642212 ps
T787 /workspace/coverage/default/2.chip_sw_plic_sw_irq.232840430 Jul 24 08:16:47 PM PDT 24 Jul 24 08:22:30 PM PDT 24 3006896694 ps
T1316 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3695062838 Jul 24 07:57:17 PM PDT 24 Jul 24 08:26:31 PM PDT 24 21400833419 ps
T1317 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4019235946 Jul 24 08:15:55 PM PDT 24 Jul 24 08:27:44 PM PDT 24 4940506888 ps
T1318 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.118722108 Jul 24 08:12:32 PM PDT 24 Jul 24 08:25:37 PM PDT 24 4534173416 ps
T886 /workspace/coverage/default/12.chip_sw_all_escalation_resets.2140371554 Jul 24 08:22:12 PM PDT 24 Jul 24 08:31:00 PM PDT 24 5883235280 ps
T1319 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2882817910 Jul 24 08:21:17 PM PDT 24 Jul 24 09:12:26 PM PDT 24 16433966132 ps
T1320 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1723886980 Jul 24 08:06:09 PM PDT 24 Jul 24 09:09:53 PM PDT 24 15027257224 ps
T1321 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2763402054 Jul 24 08:20:59 PM PDT 24 Jul 24 08:33:07 PM PDT 24 4316688264 ps
T169 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1645567317 Jul 24 08:17:06 PM PDT 24 Jul 24 08:25:22 PM PDT 24 4645754100 ps
T310 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1641380807 Jul 24 08:16:03 PM PDT 24 Jul 24 08:35:45 PM PDT 24 8895939527 ps
T1322 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3058861689 Jul 24 08:06:40 PM PDT 24 Jul 24 08:27:36 PM PDT 24 6787812360 ps
T807 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3415834778 Jul 24 08:28:47 PM PDT 24 Jul 24 08:35:22 PM PDT 24 3423489764 ps
T1323 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2850915051 Jul 24 08:12:23 PM PDT 24 Jul 24 08:15:40 PM PDT 24 2947803992 ps
T811 /workspace/coverage/default/98.chip_sw_all_escalation_resets.3450649522 Jul 24 08:28:57 PM PDT 24 Jul 24 08:40:11 PM PDT 24 4833850280 ps
T1324 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.49902967 Jul 24 08:20:19 PM PDT 24 Jul 24 08:26:19 PM PDT 24 2946770928 ps
T852 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1031133565 Jul 24 08:27:04 PM PDT 24 Jul 24 08:32:53 PM PDT 24 3555354180 ps
T92 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3054600423 Jul 24 08:28:08 PM PDT 24 Jul 24 08:35:18 PM PDT 24 4687474750 ps
T1325 /workspace/coverage/default/90.chip_sw_all_escalation_resets.2293692175 Jul 24 08:35:26 PM PDT 24 Jul 24 08:46:57 PM PDT 24 5452201624 ps
T1326 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1344203949 Jul 24 08:23:36 PM PDT 24 Jul 24 08:59:34 PM PDT 24 13019485880 ps
T1327 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3187471976 Jul 24 08:26:43 PM PDT 24 Jul 24 08:36:17 PM PDT 24 4262458268 ps
T1328 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3145238208 Jul 24 08:19:40 PM PDT 24 Jul 24 08:28:29 PM PDT 24 4288249610 ps
T1329 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1865977828 Jul 24 08:20:51 PM PDT 24 Jul 24 08:30:24 PM PDT 24 7555608722 ps
T1330 /workspace/coverage/default/0.chip_sw_aes_idle.2971432425 Jul 24 07:57:34 PM PDT 24 Jul 24 08:01:02 PM PDT 24 3322505154 ps
T1331 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3546437534 Jul 24 07:59:22 PM PDT 24 Jul 24 08:18:28 PM PDT 24 4880843064 ps
T43 /workspace/coverage/default/0.chip_sw_spi_device_tpm.2084622503 Jul 24 07:57:29 PM PDT 24 Jul 24 08:03:42 PM PDT 24 3571177570 ps
T363 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.922862736 Jul 24 08:15:45 PM PDT 24 Jul 24 08:26:10 PM PDT 24 4314308830 ps
T1332 /workspace/coverage/default/2.chip_sw_csrng_kat_test.874372472 Jul 24 08:15:17 PM PDT 24 Jul 24 08:19:30 PM PDT 24 2443324004 ps
T51 /workspace/coverage/default/0.chip_sw_alert_test.3567186704 Jul 24 07:59:14 PM PDT 24 Jul 24 08:05:03 PM PDT 24 3141139568 ps
T52 /workspace/coverage/default/2.chip_jtag_csr_rw.181941812 Jul 24 08:09:03 PM PDT 24 Jul 24 08:43:25 PM PDT 24 17347433665 ps
T1333 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1270289965 Jul 24 07:59:32 PM PDT 24 Jul 24 08:03:51 PM PDT 24 2952305809 ps
T1334 /workspace/coverage/default/0.chip_sw_uart_smoketest.4149727613 Jul 24 08:00:40 PM PDT 24 Jul 24 08:04:09 PM PDT 24 2403018172 ps
T1335 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3765975460 Jul 24 08:22:14 PM PDT 24 Jul 24 08:38:59 PM PDT 24 13470280539 ps
T1336 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.110035780 Jul 24 07:57:09 PM PDT 24 Jul 24 08:04:33 PM PDT 24 3498038570 ps
T305 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1023445299 Jul 24 08:18:09 PM PDT 24 Jul 24 08:21:50 PM PDT 24 2368931955 ps
T1337 /workspace/coverage/default/0.chip_sw_kmac_app_rom.4292146426 Jul 24 07:56:12 PM PDT 24 Jul 24 08:00:48 PM PDT 24 3052975420 ps
T1338 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1730897506 Jul 24 08:07:30 PM PDT 24 Jul 24 08:27:37 PM PDT 24 7525981262 ps
T745 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1177176138 Jul 24 08:20:46 PM PDT 24 Jul 24 08:31:06 PM PDT 24 2779502452 ps
T1339 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2599771965 Jul 24 08:12:16 PM PDT 24 Jul 24 08:27:34 PM PDT 24 8825410741 ps
T56 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2596972733 Jul 24 07:58:00 PM PDT 24 Jul 24 08:04:43 PM PDT 24 3690480969 ps
T1340 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3549616103 Jul 24 08:04:02 PM PDT 24 Jul 24 08:52:39 PM PDT 24 11315723348 ps
T813 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1620107121 Jul 24 08:27:47 PM PDT 24 Jul 24 08:33:45 PM PDT 24 3697257396 ps
T1341 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3190485976 Jul 24 08:24:02 PM PDT 24 Jul 24 08:36:25 PM PDT 24 5432844804 ps
T1342 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2410543425 Jul 24 07:56:51 PM PDT 24 Jul 24 08:19:49 PM PDT 24 12980759008 ps
T1343 /workspace/coverage/default/1.rom_e2e_asm_init_rma.458558273 Jul 24 08:19:38 PM PDT 24 Jul 24 09:13:55 PM PDT 24 14496781060 ps
T879 /workspace/coverage/default/91.chip_sw_all_escalation_resets.663775040 Jul 24 08:35:48 PM PDT 24 Jul 24 08:45:21 PM PDT 24 4210372966 ps
T1344 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3396248432 Jul 24 08:22:23 PM PDT 24 Jul 24 08:46:54 PM PDT 24 8725873247 ps
T1345 /workspace/coverage/default/2.chip_sw_otbn_randomness.791823606 Jul 24 08:13:32 PM PDT 24 Jul 24 08:30:55 PM PDT 24 6242084884 ps
T1346 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2055339238 Jul 24 07:59:12 PM PDT 24 Jul 24 08:05:47 PM PDT 24 4481496300 ps
T1347 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3835587317 Jul 24 08:03:52 PM PDT 24 Jul 24 08:36:46 PM PDT 24 15795284432 ps
T1348 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1237306858 Jul 24 07:57:06 PM PDT 24 Jul 24 08:00:41 PM PDT 24 2879990348 ps
T844 /workspace/coverage/default/85.chip_sw_all_escalation_resets.1716213414 Jul 24 08:27:49 PM PDT 24 Jul 24 08:38:43 PM PDT 24 5854858250 ps
T1349 /workspace/coverage/default/2.chip_sw_aes_entropy.1186043654 Jul 24 08:14:39 PM PDT 24 Jul 24 08:19:34 PM PDT 24 3296129160 ps
T1350 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2949136426 Jul 24 08:06:23 PM PDT 24 Jul 24 08:16:19 PM PDT 24 7197992696 ps
T1351 /workspace/coverage/default/1.chip_tap_straps_testunlock0.3881486190 Jul 24 08:11:28 PM PDT 24 Jul 24 08:19:30 PM PDT 24 5570366442 ps
T337 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1581195467 Jul 24 08:14:39 PM PDT 24 Jul 24 08:37:29 PM PDT 24 6368445724 ps
T44 /workspace/coverage/default/2.chip_sw_spi_device_tpm.2712732823 Jul 24 08:11:37 PM PDT 24 Jul 24 08:17:34 PM PDT 24 3665418002 ps
T1352 /workspace/coverage/default/2.chip_sw_power_sleep_load.1768446595 Jul 24 08:17:57 PM PDT 24 Jul 24 08:26:55 PM PDT 24 10146595836 ps
T1353 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2312803682 Jul 24 07:59:51 PM PDT 24 Jul 24 08:06:54 PM PDT 24 5215662960 ps
T1354 /workspace/coverage/default/0.chip_sw_coremark.2859660873 Jul 24 07:58:51 PM PDT 24 Jul 24 11:43:58 PM PDT 24 71681793300 ps
T1355 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2852864701 Jul 24 08:10:31 PM PDT 24 Jul 24 08:20:30 PM PDT 24 4598535296 ps
T1356 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1921706404 Jul 24 08:08:54 PM PDT 24 Jul 24 08:12:52 PM PDT 24 2480140832 ps
T810 /workspace/coverage/default/25.chip_sw_all_escalation_resets.718571241 Jul 24 08:24:09 PM PDT 24 Jul 24 08:35:55 PM PDT 24 6387209496 ps
T249 /workspace/coverage/default/1.chip_sw_alert_test.1215996078 Jul 24 08:04:46 PM PDT 24 Jul 24 08:11:09 PM PDT 24 3212493736 ps
T857 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3509095136 Jul 24 08:25:50 PM PDT 24 Jul 24 08:31:48 PM PDT 24 3541501546 ps
T1357 /workspace/coverage/default/0.chip_sw_hmac_enc.149802469 Jul 24 08:02:08 PM PDT 24 Jul 24 08:06:17 PM PDT 24 2715352400 ps
T1358 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1483375082 Jul 24 08:11:57 PM PDT 24 Jul 24 08:31:24 PM PDT 24 7437630398 ps
T138 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.4233461645 Jul 24 08:17:00 PM PDT 24 Jul 24 08:27:40 PM PDT 24 5951858370 ps
T399 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1854388179 Jul 24 08:03:59 PM PDT 24 Jul 24 08:21:43 PM PDT 24 5045942824 ps
T1359 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1820419357 Jul 24 08:09:32 PM PDT 24 Jul 24 08:16:01 PM PDT 24 5739121604 ps
T1360 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2408376646 Jul 24 08:14:28 PM PDT 24 Jul 24 08:28:18 PM PDT 24 6737681850 ps
T1361 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.278479789 Jul 24 08:13:54 PM PDT 24 Jul 24 08:26:46 PM PDT 24 6029337678 ps
T1362 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.855266906 Jul 24 08:05:18 PM PDT 24 Jul 24 08:30:30 PM PDT 24 7373949680 ps
T1363 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1592566241 Jul 24 08:11:05 PM PDT 24 Jul 24 09:35:15 PM PDT 24 31750441759 ps
T162 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1741063626 Jul 24 08:01:04 PM PDT 24 Jul 24 08:05:57 PM PDT 24 2778731262 ps
T1364 /workspace/coverage/default/0.rom_volatile_raw_unlock.669254629 Jul 24 08:01:45 PM PDT 24 Jul 24 08:03:44 PM PDT 24 2053765478 ps
T1365 /workspace/coverage/default/1.rom_keymgr_functest.1654762498 Jul 24 08:08:53 PM PDT 24 Jul 24 08:19:53 PM PDT 24 4562548100 ps
T890 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1183284477 Jul 24 08:21:28 PM PDT 24 Jul 24 08:28:21 PM PDT 24 3743004050 ps
T64 /workspace/coverage/default/0.chip_tap_straps_rma.1866034838 Jul 24 07:58:42 PM PDT 24 Jul 24 08:05:11 PM PDT 24 4572087262 ps
T196 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2355008148 Jul 24 07:57:33 PM PDT 24 Jul 24 08:11:14 PM PDT 24 6894711793 ps
T1366 /workspace/coverage/default/2.chip_sw_example_manufacturer.3221793755 Jul 24 08:11:44 PM PDT 24 Jul 24 08:15:13 PM PDT 24 2304411540 ps
T1367 /workspace/coverage/default/2.chip_sw_aes_masking_off.3131464407 Jul 24 08:14:40 PM PDT 24 Jul 24 08:20:39 PM PDT 24 3947680756 ps
T1368 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.929279908 Jul 24 08:04:00 PM PDT 24 Jul 24 08:09:43 PM PDT 24 3791717199 ps
T1369 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2979045757 Jul 24 08:10:38 PM PDT 24 Jul 24 08:16:27 PM PDT 24 3407518140 ps
T1370 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1030961683 Jul 24 07:58:21 PM PDT 24 Jul 24 08:12:13 PM PDT 24 6289154900 ps
T1371 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2187221170 Jul 24 08:26:06 PM PDT 24 Jul 24 08:31:55 PM PDT 24 3005745080 ps
T1372 /workspace/coverage/default/0.rom_e2e_asm_init_prod.96552432 Jul 24 08:06:04 PM PDT 24 Jul 24 09:10:28 PM PDT 24 15271222445 ps
T1373 /workspace/coverage/default/0.chip_sw_aes_masking_off.982345784 Jul 24 07:56:36 PM PDT 24 Jul 24 08:01:42 PM PDT 24 3104648710 ps
T859 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2820170300 Jul 24 08:01:34 PM PDT 24 Jul 24 08:14:48 PM PDT 24 6464192688 ps
T1374 /workspace/coverage/default/1.rom_e2e_smoke.1849451019 Jul 24 08:12:21 PM PDT 24 Jul 24 09:05:16 PM PDT 24 15664041340 ps
T1375 /workspace/coverage/default/1.chip_sw_edn_auto_mode.3497031405 Jul 24 08:08:44 PM PDT 24 Jul 24 08:28:04 PM PDT 24 4677590520 ps
T878 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2387727894 Jul 24 08:27:50 PM PDT 24 Jul 24 08:35:28 PM PDT 24 3516293296 ps
T1376 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1962800299 Jul 24 08:01:56 PM PDT 24 Jul 24 08:08:34 PM PDT 24 5313469884 ps
T860 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3900109751 Jul 24 08:24:45 PM PDT 24 Jul 24 08:30:20 PM PDT 24 3902998550 ps
T1377 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1249055735 Jul 24 08:20:48 PM PDT 24 Jul 24 08:29:54 PM PDT 24 7217920398 ps
T1378 /workspace/coverage/default/92.chip_sw_all_escalation_resets.774268492 Jul 24 08:29:30 PM PDT 24 Jul 24 08:37:48 PM PDT 24 4569029480 ps
T1379 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.318227302 Jul 24 08:01:13 PM PDT 24 Jul 24 08:07:15 PM PDT 24 3699741480 ps
T1380 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3150025763 Jul 24 08:06:11 PM PDT 24 Jul 24 08:20:30 PM PDT 24 6637877795 ps
T1381 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1493282708 Jul 24 08:18:48 PM PDT 24 Jul 24 08:27:57 PM PDT 24 3589906307 ps
T1382 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.742328560 Jul 24 08:21:08 PM PDT 24 Jul 24 08:29:55 PM PDT 24 6537127523 ps
T1383 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3670314825 Jul 24 08:00:43 PM PDT 24 Jul 24 08:33:53 PM PDT 24 12554840130 ps
T1384 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.719412550 Jul 24 08:16:04 PM PDT 24 Jul 24 08:26:10 PM PDT 24 8869784412 ps
T1385 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1436446507 Jul 24 08:20:13 PM PDT 24 Jul 24 08:25:26 PM PDT 24 3044616190 ps
T1386 /workspace/coverage/default/0.chip_sw_aes_smoketest.2980685380 Jul 24 08:01:50 PM PDT 24 Jul 24 08:07:30 PM PDT 24 2567866576 ps
T1387 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.4213434430 Jul 24 08:03:15 PM PDT 24 Jul 24 08:14:16 PM PDT 24 7587782934 ps
T1388 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3805030774 Jul 24 08:22:48 PM PDT 24 Jul 24 08:30:30 PM PDT 24 3946238548 ps
T762 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3036133266 Jul 24 08:01:55 PM PDT 24 Jul 24 08:12:01 PM PDT 24 5068418030 ps
T1389 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.39211055 Jul 24 08:24:39 PM PDT 24 Jul 24 08:45:31 PM PDT 24 8117172096 ps
T1390 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3908930083 Jul 24 08:02:19 PM PDT 24 Jul 24 08:08:30 PM PDT 24 3440652204 ps
T1391 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.474369446 Jul 24 08:17:37 PM PDT 24 Jul 24 08:22:24 PM PDT 24 2637412017 ps
T335 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.502012423 Jul 24 08:00:20 PM PDT 24 Jul 24 08:36:12 PM PDT 24 14646589200 ps
T1392 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.459735170 Jul 24 08:03:08 PM PDT 24 Jul 24 08:26:58 PM PDT 24 7759907518 ps
T1393 /workspace/coverage/default/2.chip_sw_all_escalation_resets.1224147185 Jul 24 08:11:40 PM PDT 24 Jul 24 08:23:42 PM PDT 24 4810589518 ps
T1394 /workspace/coverage/default/6.chip_sw_all_escalation_resets.716104650 Jul 24 08:24:00 PM PDT 24 Jul 24 08:32:46 PM PDT 24 5878444264 ps
T1395 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3737325577 Jul 24 08:02:15 PM PDT 24 Jul 24 08:09:42 PM PDT 24 3439543020 ps
T346 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.618358425 Jul 24 07:56:23 PM PDT 24 Jul 24 08:10:08 PM PDT 24 4995150028 ps
T1396 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1595799655 Jul 24 08:11:52 PM PDT 24 Jul 24 08:31:43 PM PDT 24 5325483736 ps
T1397 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3204907833 Jul 24 08:25:46 PM PDT 24 Jul 24 08:32:56 PM PDT 24 3609963050 ps
T1398 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1726704992 Jul 24 08:05:20 PM PDT 24 Jul 24 08:15:01 PM PDT 24 5251172386 ps
T891 /workspace/coverage/default/66.chip_sw_all_escalation_resets.317916734 Jul 24 08:28:04 PM PDT 24 Jul 24 08:38:08 PM PDT 24 4184881822 ps
T1399 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3052742844 Jul 24 08:15:40 PM PDT 24 Jul 24 08:27:21 PM PDT 24 4591916308 ps
T364 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1492377923 Jul 24 08:10:07 PM PDT 24 Jul 24 08:22:22 PM PDT 24 4617382904 ps
T882 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3401944113 Jul 24 08:24:49 PM PDT 24 Jul 24 08:30:48 PM PDT 24 4236232348 ps
T1400 /workspace/coverage/default/2.chip_sw_uart_tx_rx.3711775395 Jul 24 08:12:03 PM PDT 24 Jul 24 08:24:29 PM PDT 24 4600252292 ps
T1401 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1359161820 Jul 24 08:06:19 PM PDT 24 Jul 24 09:12:19 PM PDT 24 15362831712 ps
T1402 /workspace/coverage/default/2.chip_sw_flash_crash_alert.804117604 Jul 24 08:19:16 PM PDT 24 Jul 24 08:34:28 PM PDT 24 4728266280 ps
T1403 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3049823078 Jul 24 08:16:53 PM PDT 24 Jul 24 08:28:19 PM PDT 24 4517188056 ps
T1404 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.384059740 Jul 24 08:06:55 PM PDT 24 Jul 24 08:27:04 PM PDT 24 5957927698 ps
T863 /workspace/coverage/default/49.chip_sw_all_escalation_resets.2615276463 Jul 24 08:26:28 PM PDT 24 Jul 24 08:37:19 PM PDT 24 6223914772 ps
T1405 /workspace/coverage/default/0.chip_sw_otbn_smoketest.3873111609 Jul 24 08:00:41 PM PDT 24 Jul 24 08:24:46 PM PDT 24 6795680350 ps
T1406 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2316936716 Jul 24 08:13:48 PM PDT 24 Jul 24 08:43:35 PM PDT 24 6896218360 ps
T1407 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1523937231 Jul 24 08:05:39 PM PDT 24 Jul 24 08:44:54 PM PDT 24 11047407496 ps
T1408 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2269886677 Jul 24 08:10:58 PM PDT 24 Jul 24 08:16:26 PM PDT 24 3798771960 ps
T1409 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2429265688 Jul 24 08:22:47 PM PDT 24 Jul 24 08:46:24 PM PDT 24 8088703426 ps
T858 /workspace/coverage/default/58.chip_sw_all_escalation_resets.609559318 Jul 24 08:28:20 PM PDT 24 Jul 24 08:40:21 PM PDT 24 5307590330 ps
T1410 /workspace/coverage/default/2.chip_tap_straps_testunlock0.2015284429 Jul 24 08:16:46 PM PDT 24 Jul 24 08:21:58 PM PDT 24 3589526710 ps
T55 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3171057683 Jul 24 07:56:28 PM PDT 24 Jul 24 08:01:40 PM PDT 24 3049938804 ps
T885 /workspace/coverage/default/55.chip_sw_all_escalation_resets.1976283341 Jul 24 08:26:08 PM PDT 24 Jul 24 08:37:26 PM PDT 24 5548867660 ps
T1411 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2104719342 Jul 24 07:57:41 PM PDT 24 Jul 24 08:36:55 PM PDT 24 24681330296 ps
T1412 /workspace/coverage/default/31.chip_sw_all_escalation_resets.1483731550 Jul 24 08:24:40 PM PDT 24 Jul 24 08:34:51 PM PDT 24 5112944500 ps
T38 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3066947521 Jul 24 07:58:31 PM PDT 24 Jul 24 08:02:48 PM PDT 24 3547983496 ps
T1413 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2403346645 Jul 24 08:02:33 PM PDT 24 Jul 24 09:20:18 PM PDT 24 24015612836 ps
T1414 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.259562447 Jul 24 07:57:56 PM PDT 24 Jul 24 08:19:52 PM PDT 24 6344940153 ps
T1415 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1036522158 Jul 24 07:57:44 PM PDT 24 Jul 24 08:07:56 PM PDT 24 4469635864 ps
T1416 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1223289259 Jul 24 08:15:39 PM PDT 24 Jul 24 08:24:46 PM PDT 24 4166095824 ps
T1417 /workspace/coverage/default/2.chip_sw_kmac_idle.3669589648 Jul 24 08:15:47 PM PDT 24 Jul 24 08:19:49 PM PDT 24 3429314720 ps
T353 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1575531468 Jul 24 07:57:07 PM PDT 24 Jul 24 08:08:04 PM PDT 24 4903143000 ps
T1418 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2089564487 Jul 24 08:12:57 PM PDT 24 Jul 24 09:08:04 PM PDT 24 14698898805 ps
T1419 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3430711713 Jul 24 08:09:53 PM PDT 24 Jul 24 08:42:20 PM PDT 24 13381906450 ps
T197 /workspace/coverage/default/1.chip_jtag_mem_access.536298783 Jul 24 07:59:39 PM PDT 24 Jul 24 08:26:10 PM PDT 24 13861224729 ps
T1420 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.4060343232 Jul 24 08:00:07 PM PDT 24 Jul 24 08:04:22 PM PDT 24 3321972784 ps
T864 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4186164496 Jul 24 08:25:38 PM PDT 24 Jul 24 08:32:24 PM PDT 24 4376176660 ps
T877 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3123831843 Jul 24 08:22:28 PM PDT 24 Jul 24 08:28:16 PM PDT 24 3828264936 ps
T1421 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2955066166 Jul 24 08:08:21 PM PDT 24 Jul 24 09:14:24 PM PDT 24 14640492844 ps
T1422 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1751964125 Jul 24 08:04:39 PM PDT 24 Jul 24 08:07:41 PM PDT 24 3093069824 ps
T880 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2919811668 Jul 24 08:26:26 PM PDT 24 Jul 24 08:31:38 PM PDT 24 3955692334 ps
T1423 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1002867229 Jul 24 08:26:30 PM PDT 24 Jul 24 08:32:02 PM PDT 24 3029455308 ps
T1424 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3910168899 Jul 24 08:00:13 PM PDT 24 Jul 24 08:08:39 PM PDT 24 4884316470 ps
T333 /workspace/coverage/default/0.chip_plic_all_irqs_0.137669682 Jul 24 07:59:05 PM PDT 24 Jul 24 08:23:29 PM PDT 24 6425220756 ps
T1425 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1891863215 Jul 24 08:19:06 PM PDT 24 Jul 24 08:23:22 PM PDT 24 3328788922 ps
T1426 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1552845651 Jul 24 08:17:44 PM PDT 24 Jul 24 08:21:54 PM PDT 24 2747540911 ps
T1427 /workspace/coverage/default/0.chip_sw_edn_kat.3342894084 Jul 24 07:59:35 PM PDT 24 Jul 24 08:09:58 PM PDT 24 3418142820 ps
T1428 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2751860263 Jul 24 08:13:59 PM PDT 24 Jul 24 09:09:46 PM PDT 24 14390899450 ps
T788 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1720556788 Jul 24 07:58:36 PM PDT 24 Jul 24 08:03:48 PM PDT 24 3062317136 ps
T1429 /workspace/coverage/default/2.chip_sw_otbn_smoketest.1302504128 Jul 24 08:19:42 PM PDT 24 Jul 24 08:49:26 PM PDT 24 11590657312 ps
T861 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3649731507 Jul 24 08:26:10 PM PDT 24 Jul 24 08:33:16 PM PDT 24 3614962850 ps
T375 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2845703732 Jul 24 08:18:52 PM PDT 24 Jul 24 08:29:51 PM PDT 24 5174705189 ps
T1430 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2626763063 Jul 24 07:58:54 PM PDT 24 Jul 24 08:25:11 PM PDT 24 8547052280 ps
T1431 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1513586837 Jul 24 08:04:41 PM PDT 24 Jul 24 09:07:25 PM PDT 24 32648066231 ps
T1432 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.546261317 Jul 24 07:59:22 PM PDT 24 Jul 24 08:07:55 PM PDT 24 5586108169 ps
T1433 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2427740982 Jul 24 08:01:34 PM PDT 24 Jul 24 08:11:57 PM PDT 24 4482703960 ps
T847 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.744485430 Jul 24 08:24:52 PM PDT 24 Jul 24 08:30:38 PM PDT 24 4386302660 ps
T1434 /workspace/coverage/default/2.chip_sw_power_idle_load.2397408860 Jul 24 08:18:44 PM PDT 24 Jul 24 08:29:40 PM PDT 24 4498333350 ps
T370 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2634723451 Jul 24 08:03:44 PM PDT 24 Jul 24 08:19:16 PM PDT 24 4723048796 ps
T1435 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.513603478 Jul 24 08:02:33 PM PDT 24 Jul 24 08:07:15 PM PDT 24 2925162120 ps
T57 /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1456740261 Jul 24 08:06:28 PM PDT 24 Jul 24 08:12:43 PM PDT 24 4121920239 ps
T1436 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.179313259 Jul 24 08:18:03 PM PDT 24 Jul 24 09:04:14 PM PDT 24 20617341081 ps
T1437 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2906691820 Jul 24 07:59:39 PM PDT 24 Jul 24 08:25:16 PM PDT 24 6249162554 ps
T1438 /workspace/coverage/default/0.rom_e2e_self_hash.2877703156 Jul 24 08:05:47 PM PDT 24 Jul 24 09:43:53 PM PDT 24 26361659288 ps
T1439 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1666726953 Jul 24 07:59:48 PM PDT 24 Jul 24 08:25:55 PM PDT 24 12820546928 ps
T881 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.269720205 Jul 24 08:32:04 PM PDT 24 Jul 24 08:39:16 PM PDT 24 4127792324 ps
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