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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.09 95.46 93.86 95.44 94.60 97.53 99.61


Total test records in report: 2935
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T709 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.730730984 Aug 09 08:24:17 PM PDT 24 Aug 09 08:39:38 PM PDT 24 5168507978 ps
T350 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3065741723 Aug 09 08:30:25 PM PDT 24 Aug 09 08:42:44 PM PDT 24 4058092140 ps
T921 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2139068694 Aug 09 08:31:14 PM PDT 24 Aug 09 08:49:08 PM PDT 24 7016566278 ps
T246 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1818761779 Aug 09 08:48:07 PM PDT 24 Aug 09 09:00:10 PM PDT 24 5488337000 ps
T78 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2867673534 Aug 09 08:24:39 PM PDT 24 Aug 09 08:59:52 PM PDT 24 11932071792 ps
T922 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.481132287 Aug 09 08:28:44 PM PDT 24 Aug 09 09:32:47 PM PDT 24 12550113458 ps
T794 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1615782101 Aug 09 08:52:37 PM PDT 24 Aug 09 08:58:33 PM PDT 24 3111114674 ps
T923 /workspace/coverage/default/0.chip_sw_kmac_smoketest.51011417 Aug 09 08:24:49 PM PDT 24 Aug 09 08:30:40 PM PDT 24 3285065556 ps
T87 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1569076956 Aug 09 08:20:01 PM PDT 24 Aug 09 08:25:38 PM PDT 24 3520000626 ps
T924 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2936123359 Aug 09 08:25:15 PM PDT 24 Aug 09 08:33:06 PM PDT 24 4823477912 ps
T699 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2203604657 Aug 09 08:28:57 PM PDT 24 Aug 09 08:33:04 PM PDT 24 2563718936 ps
T276 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1167563731 Aug 09 08:29:37 PM PDT 24 Aug 09 09:27:35 PM PDT 24 13646490366 ps
T925 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2716084027 Aug 09 08:31:44 PM PDT 24 Aug 09 09:18:22 PM PDT 24 11845012504 ps
T750 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3405035869 Aug 09 08:50:05 PM PDT 24 Aug 09 08:57:54 PM PDT 24 3295595456 ps
T459 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2934830816 Aug 09 08:27:25 PM PDT 24 Aug 09 08:38:52 PM PDT 24 7095785665 ps
T303 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.793625284 Aug 09 08:34:15 PM PDT 24 Aug 09 08:40:50 PM PDT 24 3646553400 ps
T339 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.543838664 Aug 09 08:51:59 PM PDT 24 Aug 09 09:03:54 PM PDT 24 4942309876 ps
T926 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3218168456 Aug 09 08:23:20 PM PDT 24 Aug 09 08:27:59 PM PDT 24 3111016912 ps
T927 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.483711366 Aug 09 08:22:01 PM PDT 24 Aug 09 08:32:44 PM PDT 24 4161296976 ps
T928 /workspace/coverage/default/2.chip_sw_power_sleep_load.1502260052 Aug 09 08:45:31 PM PDT 24 Aug 09 08:56:10 PM PDT 24 11519827816 ps
T929 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.987192350 Aug 09 08:34:26 PM PDT 24 Aug 09 08:38:42 PM PDT 24 2846106480 ps
T930 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2102835170 Aug 09 08:29:46 PM PDT 24 Aug 09 09:09:03 PM PDT 24 10224086436 ps
T240 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.738440064 Aug 09 08:21:30 PM PDT 24 Aug 09 08:54:54 PM PDT 24 23615399463 ps
T258 /workspace/coverage/default/0.chip_sw_plic_sw_irq.944804777 Aug 09 08:21:32 PM PDT 24 Aug 09 08:26:40 PM PDT 24 2971264784 ps
T758 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3025894961 Aug 09 08:47:51 PM PDT 24 Aug 09 08:53:31 PM PDT 24 3524232386 ps
T21 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2419853137 Aug 09 08:39:05 PM PDT 24 Aug 09 09:08:09 PM PDT 24 21113705560 ps
T931 /workspace/coverage/default/1.chip_sw_kmac_idle.3460986545 Aug 09 08:30:45 PM PDT 24 Aug 09 08:34:27 PM PDT 24 2674359690 ps
T932 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1699977835 Aug 09 08:47:25 PM PDT 24 Aug 09 08:58:01 PM PDT 24 5550413223 ps
T179 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1335735952 Aug 09 08:46:10 PM PDT 24 Aug 09 09:00:14 PM PDT 24 10584549487 ps
T933 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1871085649 Aug 09 08:27:21 PM PDT 24 Aug 09 08:31:51 PM PDT 24 2647504820 ps
T683 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.123506462 Aug 09 08:20:43 PM PDT 24 Aug 09 08:37:34 PM PDT 24 5798961485 ps
T748 /workspace/coverage/default/48.chip_sw_all_escalation_resets.2924011541 Aug 09 08:51:53 PM PDT 24 Aug 09 09:00:22 PM PDT 24 4180397820 ps
T726 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1661705063 Aug 09 08:45:43 PM PDT 24 Aug 09 08:57:51 PM PDT 24 5952709688 ps
T333 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2600020778 Aug 09 08:37:55 PM PDT 24 Aug 09 08:50:04 PM PDT 24 5271679876 ps
T934 /workspace/coverage/default/0.chip_sw_hmac_multistream.4100555659 Aug 09 08:25:07 PM PDT 24 Aug 09 08:55:31 PM PDT 24 7830648400 ps
T71 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3127782077 Aug 09 08:22:37 PM PDT 24 Aug 09 08:31:19 PM PDT 24 3520808448 ps
T25 /workspace/coverage/default/2.chip_sw_gpio.1889302964 Aug 09 08:38:40 PM PDT 24 Aug 09 08:47:57 PM PDT 24 3607507434 ps
T935 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3918480509 Aug 09 08:21:54 PM PDT 24 Aug 09 08:41:09 PM PDT 24 6740090860 ps
T49 /workspace/coverage/default/0.chip_sw_alert_test.1900915217 Aug 09 08:21:27 PM PDT 24 Aug 09 08:27:07 PM PDT 24 3306783960 ps
T936 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2457154079 Aug 09 08:24:19 PM PDT 24 Aug 09 08:28:57 PM PDT 24 2987736566 ps
T220 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3238866361 Aug 09 08:50:51 PM PDT 24 Aug 09 09:14:53 PM PDT 24 8395322760 ps
T937 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.563653255 Aug 09 08:25:21 PM PDT 24 Aug 09 09:23:02 PM PDT 24 15606372996 ps
T66 /workspace/coverage/default/0.chip_tap_straps_testunlock0.2703696357 Aug 09 08:20:27 PM PDT 24 Aug 09 08:28:57 PM PDT 24 5507330942 ps
T938 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.500732141 Aug 09 08:29:14 PM PDT 24 Aug 09 08:59:25 PM PDT 24 15588449699 ps
T939 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1419090317 Aug 09 08:22:58 PM PDT 24 Aug 09 08:32:20 PM PDT 24 5984667380 ps
T940 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.4274845452 Aug 09 08:40:37 PM PDT 24 Aug 09 09:12:37 PM PDT 24 25571754790 ps
T708 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.797976083 Aug 09 08:41:42 PM PDT 24 Aug 09 08:50:22 PM PDT 24 6175066694 ps
T162 /workspace/coverage/default/0.chip_plic_all_irqs_10.3021835665 Aug 09 08:21:52 PM PDT 24 Aug 09 08:32:35 PM PDT 24 3893963160 ps
T283 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3078701553 Aug 09 08:20:23 PM PDT 24 Aug 09 08:28:27 PM PDT 24 3220754068 ps
T786 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2382837864 Aug 09 08:52:03 PM PDT 24 Aug 09 09:00:16 PM PDT 24 4041052116 ps
T941 /workspace/coverage/default/0.chip_sw_example_rom.50785127 Aug 09 08:20:00 PM PDT 24 Aug 09 08:21:57 PM PDT 24 2579488860 ps
T340 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1583638712 Aug 09 08:26:10 PM PDT 24 Aug 09 08:40:06 PM PDT 24 4416852252 ps
T352 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3903998033 Aug 09 08:36:48 PM PDT 24 Aug 09 08:46:20 PM PDT 24 4610927530 ps
T942 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.643865444 Aug 09 08:24:45 PM PDT 24 Aug 09 08:46:43 PM PDT 24 8551494939 ps
T943 /workspace/coverage/default/0.chip_sw_edn_kat.3194876126 Aug 09 08:22:25 PM PDT 24 Aug 09 08:35:36 PM PDT 24 3463309288 ps
T50 /workspace/coverage/default/2.chip_sw_alert_test.3331379259 Aug 09 08:39:40 PM PDT 24 Aug 09 08:45:18 PM PDT 24 2536778428 ps
T363 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1183794767 Aug 09 08:47:35 PM PDT 24 Aug 09 08:57:45 PM PDT 24 4094483354 ps
T216 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4262699734 Aug 09 08:20:12 PM PDT 24 Aug 09 08:31:12 PM PDT 24 4165146510 ps
T944 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3344706539 Aug 09 08:39:38 PM PDT 24 Aug 09 08:45:00 PM PDT 24 3010718078 ps
T945 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2252697789 Aug 09 08:43:08 PM PDT 24 Aug 09 09:00:39 PM PDT 24 6802712564 ps
T36 /workspace/coverage/default/0.chip_sw_spi_device_tpm.2398850503 Aug 09 08:23:42 PM PDT 24 Aug 09 08:30:51 PM PDT 24 4131165072 ps
T946 /workspace/coverage/default/2.chip_tap_straps_rma.4085058992 Aug 09 08:42:08 PM PDT 24 Aug 09 08:45:37 PM PDT 24 3213313487 ps
T177 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.4221472310 Aug 09 08:38:03 PM PDT 24 Aug 09 10:06:35 PM PDT 24 47648841284 ps
T947 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3586051758 Aug 09 08:48:32 PM PDT 24 Aug 09 08:57:49 PM PDT 24 3859986344 ps
T948 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1468773139 Aug 09 08:29:09 PM PDT 24 Aug 09 08:40:13 PM PDT 24 4336551964 ps
T949 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3080692496 Aug 09 08:25:29 PM PDT 24 Aug 09 08:29:11 PM PDT 24 2241439380 ps
T79 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3780954874 Aug 09 08:38:05 PM PDT 24 Aug 09 11:30:41 PM PDT 24 58851688850 ps
T950 /workspace/coverage/default/2.chip_sw_edn_kat.201832795 Aug 09 08:40:05 PM PDT 24 Aug 09 08:50:57 PM PDT 24 3429057780 ps
T951 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.146672348 Aug 09 08:32:58 PM PDT 24 Aug 09 08:42:23 PM PDT 24 5740901248 ps
T952 /workspace/coverage/default/2.chip_sw_otbn_randomness.4119331017 Aug 09 08:39:03 PM PDT 24 Aug 09 08:56:22 PM PDT 24 5903908526 ps
T158 /workspace/coverage/default/2.rom_raw_unlock.3418353761 Aug 09 08:45:35 PM PDT 24 Aug 09 08:50:08 PM PDT 24 5838634042 ps
T745 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3067549501 Aug 09 08:53:24 PM PDT 24 Aug 09 08:59:56 PM PDT 24 4346766136 ps
T360 /workspace/coverage/default/2.chip_sw_hmac_enc.3152070330 Aug 09 08:41:12 PM PDT 24 Aug 09 08:46:54 PM PDT 24 2923889114 ps
T217 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1766669059 Aug 09 08:41:40 PM PDT 24 Aug 09 08:46:44 PM PDT 24 2922624785 ps
T953 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2357862750 Aug 09 08:40:27 PM PDT 24 Aug 09 08:52:52 PM PDT 24 4245328952 ps
T284 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3661355289 Aug 09 08:41:01 PM PDT 24 Aug 09 08:48:55 PM PDT 24 3564430044 ps
T720 /workspace/coverage/default/23.chip_sw_all_escalation_resets.439741117 Aug 09 08:49:55 PM PDT 24 Aug 09 08:59:42 PM PDT 24 5354856730 ps
T954 /workspace/coverage/default/0.chip_sw_aes_enc.266423578 Aug 09 08:20:30 PM PDT 24 Aug 09 08:25:12 PM PDT 24 2902118604 ps
T955 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.569750449 Aug 09 08:42:45 PM PDT 24 Aug 09 08:54:11 PM PDT 24 5674817168 ps
T171 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4206648453 Aug 09 08:25:51 PM PDT 24 Aug 09 08:36:05 PM PDT 24 6064501592 ps
T956 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2430735491 Aug 09 08:27:45 PM PDT 24 Aug 09 08:45:08 PM PDT 24 5900413472 ps
T738 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2441153706 Aug 09 08:48:28 PM PDT 24 Aug 09 08:55:41 PM PDT 24 3549034676 ps
T957 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1220556171 Aug 09 08:19:20 PM PDT 24 Aug 09 08:46:18 PM PDT 24 8206512200 ps
T958 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.863492083 Aug 09 08:35:01 PM PDT 24 Aug 09 08:40:31 PM PDT 24 3072334345 ps
T192 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.67559417 Aug 09 08:40:01 PM PDT 24 Aug 09 08:51:43 PM PDT 24 6862624204 ps
T959 /workspace/coverage/default/2.rom_keymgr_functest.2440194505 Aug 09 08:43:32 PM PDT 24 Aug 09 08:55:50 PM PDT 24 5513712940 ps
T960 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.108257107 Aug 09 08:30:56 PM PDT 24 Aug 09 08:35:17 PM PDT 24 3060791092 ps
T961 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1693926952 Aug 09 08:38:47 PM PDT 24 Aug 09 08:42:39 PM PDT 24 2877961534 ps
T962 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3992970535 Aug 09 08:46:29 PM PDT 24 Aug 09 10:16:02 PM PDT 24 19223719890 ps
T224 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.58864293 Aug 09 08:23:40 PM PDT 24 Aug 09 08:35:47 PM PDT 24 5065638037 ps
T218 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3882553087 Aug 09 08:20:06 PM PDT 24 Aug 09 08:25:10 PM PDT 24 3285392930 ps
T963 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1583568824 Aug 09 08:40:08 PM PDT 24 Aug 09 08:43:46 PM PDT 24 2922093104 ps
T722 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3804566823 Aug 09 08:51:05 PM PDT 24 Aug 09 08:56:39 PM PDT 24 3898392492 ps
T752 /workspace/coverage/default/92.chip_sw_all_escalation_resets.1256017343 Aug 09 08:54:34 PM PDT 24 Aug 09 09:03:12 PM PDT 24 4970834824 ps
T964 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.64670583 Aug 09 08:24:04 PM PDT 24 Aug 09 08:27:30 PM PDT 24 2551999137 ps
T213 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.488923677 Aug 09 08:23:28 PM PDT 24 Aug 10 12:03:11 AM PDT 24 78720901050 ps
T761 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2973468361 Aug 09 08:53:58 PM PDT 24 Aug 09 09:00:53 PM PDT 24 4199942520 ps
T185 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3606653996 Aug 09 08:21:52 PM PDT 24 Aug 09 08:31:38 PM PDT 24 5042789464 ps
T965 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1668160168 Aug 09 08:54:28 PM PDT 24 Aug 09 09:05:10 PM PDT 24 6366425722 ps
T230 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.720405775 Aug 09 08:28:15 PM PDT 24 Aug 09 08:33:37 PM PDT 24 3748126816 ps
T966 /workspace/coverage/default/1.rom_e2e_asm_init_prod.3956261934 Aug 09 08:39:09 PM PDT 24 Aug 09 09:47:21 PM PDT 24 15916545551 ps
T967 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1577397863 Aug 09 08:26:14 PM PDT 24 Aug 09 08:30:55 PM PDT 24 3310743534 ps
T277 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1542072268 Aug 09 08:30:51 PM PDT 24 Aug 09 09:41:14 PM PDT 24 15455601950 ps
T968 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2841265440 Aug 09 08:45:47 PM PDT 24 Aug 09 08:53:53 PM PDT 24 4766728510 ps
T248 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2801897951 Aug 09 08:30:19 PM PDT 24 Aug 09 08:41:51 PM PDT 24 6591230528 ps
T361 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3617311222 Aug 09 08:35:18 PM PDT 24 Aug 09 08:39:19 PM PDT 24 2824000181 ps
T969 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1342521077 Aug 09 08:47:33 PM PDT 24 Aug 09 09:03:33 PM PDT 24 10526389499 ps
T338 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2481933536 Aug 09 08:21:47 PM PDT 24 Aug 09 08:47:34 PM PDT 24 7557486212 ps
T970 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.207961204 Aug 09 08:22:30 PM PDT 24 Aug 09 08:31:21 PM PDT 24 4464678200 ps
T971 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1784966891 Aug 09 08:45:26 PM PDT 24 Aug 09 08:50:54 PM PDT 24 3065839616 ps
T972 /workspace/coverage/default/0.chip_sw_hmac_oneshot.2036720880 Aug 09 08:24:37 PM PDT 24 Aug 09 08:31:28 PM PDT 24 3090355800 ps
T973 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1942600219 Aug 09 08:42:17 PM PDT 24 Aug 09 08:45:18 PM PDT 24 2708149050 ps
T225 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1250394993 Aug 09 08:20:50 PM PDT 24 Aug 09 08:30:11 PM PDT 24 6272188898 ps
T974 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2789829688 Aug 09 08:41:31 PM PDT 24 Aug 09 08:48:56 PM PDT 24 4709295336 ps
T214 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2612667316 Aug 09 08:21:46 PM PDT 24 Aug 10 12:01:58 AM PDT 24 78431310400 ps
T975 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1096589716 Aug 09 08:39:45 PM PDT 24 Aug 09 08:44:01 PM PDT 24 2804013780 ps
T159 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.627037124 Aug 09 08:27:43 PM PDT 24 Aug 09 11:17:48 PM PDT 24 59156112424 ps
T148 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3395723628 Aug 09 08:47:47 PM PDT 24 Aug 09 08:55:22 PM PDT 24 3536920596 ps
T976 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2807293400 Aug 09 08:39:39 PM PDT 24 Aug 09 08:49:40 PM PDT 24 5261043382 ps
T351 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2740658998 Aug 09 08:21:53 PM PDT 24 Aug 09 08:32:57 PM PDT 24 4640771205 ps
T730 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1554496837 Aug 09 08:51:27 PM PDT 24 Aug 09 09:04:30 PM PDT 24 5255880546 ps
T231 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1862739359 Aug 09 08:28:49 PM PDT 24 Aug 09 09:08:20 PM PDT 24 12191826919 ps
T37 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1205423792 Aug 09 08:36:21 PM PDT 24 Aug 09 08:42:14 PM PDT 24 3506447064 ps
T328 /workspace/coverage/default/1.chip_plic_all_irqs_20.101501220 Aug 09 08:32:47 PM PDT 24 Aug 09 08:46:09 PM PDT 24 4166128618 ps
T232 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2916857462 Aug 09 08:41:23 PM PDT 24 Aug 09 09:04:54 PM PDT 24 7431239016 ps
T977 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.581752434 Aug 09 08:49:10 PM PDT 24 Aug 09 09:21:42 PM PDT 24 12839690664 ps
T344 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2122691615 Aug 09 08:24:17 PM PDT 24 Aug 09 08:31:44 PM PDT 24 3826434608 ps
T978 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.16454092 Aug 09 08:31:30 PM PDT 24 Aug 09 09:34:40 PM PDT 24 15160276472 ps
T767 /workspace/coverage/default/21.chip_sw_all_escalation_resets.3328406088 Aug 09 08:54:16 PM PDT 24 Aug 09 09:04:53 PM PDT 24 5846988520 ps
T979 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.650634163 Aug 09 08:30:52 PM PDT 24 Aug 09 08:41:02 PM PDT 24 4691306650 ps
T980 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.187621637 Aug 09 08:24:50 PM PDT 24 Aug 09 08:40:04 PM PDT 24 8099092200 ps
T981 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2923602648 Aug 09 08:19:49 PM PDT 24 Aug 09 08:36:50 PM PDT 24 6128576930 ps
T156 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1947287038 Aug 09 08:25:05 PM PDT 24 Aug 09 09:19:34 PM PDT 24 17132222676 ps
T22 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1895519956 Aug 09 08:30:18 PM PDT 24 Aug 09 08:37:57 PM PDT 24 3136905968 ps
T982 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1868170467 Aug 09 08:40:59 PM PDT 24 Aug 09 08:53:35 PM PDT 24 20026442552 ps
T264 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2886373793 Aug 09 08:32:37 PM PDT 24 Aug 09 08:41:28 PM PDT 24 5258699028 ps
T983 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3463920932 Aug 09 08:38:54 PM PDT 24 Aug 09 09:01:48 PM PDT 24 8252632360 ps
T984 /workspace/coverage/default/1.chip_sw_example_rom.3741799374 Aug 09 08:23:32 PM PDT 24 Aug 09 08:25:39 PM PDT 24 3057735464 ps
T157 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3532358779 Aug 09 08:40:33 PM PDT 24 Aug 09 09:36:22 PM PDT 24 18272407700 ps
T136 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2121427257 Aug 09 08:43:56 PM PDT 24 Aug 09 08:54:28 PM PDT 24 5927569000 ps
T754 /workspace/coverage/default/54.chip_sw_all_escalation_resets.1682523246 Aug 09 08:52:57 PM PDT 24 Aug 09 09:00:17 PM PDT 24 4671440302 ps
T985 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3136262457 Aug 09 08:45:46 PM PDT 24 Aug 09 08:53:07 PM PDT 24 5057218843 ps
T986 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2667100460 Aug 09 08:26:23 PM PDT 24 Aug 09 08:45:56 PM PDT 24 5679259726 ps
T80 /workspace/coverage/default/2.chip_jtag_csr_rw.1996419223 Aug 09 08:34:29 PM PDT 24 Aug 09 08:50:40 PM PDT 24 10614425800 ps
T370 /workspace/coverage/default/64.chip_sw_all_escalation_resets.1716558141 Aug 09 08:54:19 PM PDT 24 Aug 09 09:04:54 PM PDT 24 5339267500 ps
T987 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3541808768 Aug 09 08:30:39 PM PDT 24 Aug 09 08:44:49 PM PDT 24 7028201630 ps
T988 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1283791303 Aug 09 08:32:44 PM PDT 24 Aug 09 08:40:26 PM PDT 24 4200803960 ps
T989 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2996175053 Aug 09 08:41:02 PM PDT 24 Aug 09 08:53:25 PM PDT 24 4017437778 ps
T824 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4159615451 Aug 09 08:56:05 PM PDT 24 Aug 09 09:04:15 PM PDT 24 4629869856 ps
T233 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.107989878 Aug 09 08:28:29 PM PDT 24 Aug 09 08:52:41 PM PDT 24 7267639336 ps
T990 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2711040318 Aug 09 08:30:22 PM PDT 24 Aug 09 08:34:43 PM PDT 24 2841884305 ps
T238 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.6236752 Aug 09 08:42:47 PM PDT 24 Aug 09 10:10:50 PM PDT 24 48501318195 ps
T991 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3588018166 Aug 09 08:36:55 PM PDT 24 Aug 09 09:22:44 PM PDT 24 13526033616 ps
T992 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.4287263642 Aug 09 08:39:25 PM PDT 24 Aug 09 08:57:23 PM PDT 24 6117450296 ps
T278 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.536973892 Aug 09 08:24:01 PM PDT 24 Aug 09 08:25:47 PM PDT 24 2909779598 ps
T219 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3133535784 Aug 09 08:41:35 PM PDT 24 Aug 09 08:53:13 PM PDT 24 4500201576 ps
T993 /workspace/coverage/default/2.chip_sw_example_concurrency.2672868288 Aug 09 08:35:38 PM PDT 24 Aug 09 08:39:39 PM PDT 24 2471178432 ps
T994 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3455889613 Aug 09 08:27:48 PM PDT 24 Aug 09 09:29:42 PM PDT 24 15384920290 ps
T995 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2105528782 Aug 09 08:48:12 PM PDT 24 Aug 09 08:59:09 PM PDT 24 3704764820 ps
T996 /workspace/coverage/default/0.chip_sw_flash_crash_alert.3116744 Aug 09 08:21:10 PM PDT 24 Aug 09 08:33:05 PM PDT 24 4799923660 ps
T997 /workspace/coverage/default/2.chip_sw_flash_crash_alert.695993512 Aug 09 08:42:20 PM PDT 24 Aug 09 08:54:49 PM PDT 24 6259678252 ps
T998 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1983031911 Aug 09 08:22:54 PM PDT 24 Aug 09 08:44:55 PM PDT 24 5720039752 ps
T739 /workspace/coverage/default/10.chip_sw_all_escalation_resets.4260193795 Aug 09 08:47:44 PM PDT 24 Aug 09 08:58:37 PM PDT 24 6248236152 ps
T999 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.841236071 Aug 09 08:43:53 PM PDT 24 Aug 09 08:53:41 PM PDT 24 3561449886 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_config_host.248112531 Aug 09 08:21:32 PM PDT 24 Aug 09 08:55:44 PM PDT 24 9020750940 ps
T762 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3420234272 Aug 09 08:50:27 PM PDT 24 Aug 09 09:01:46 PM PDT 24 6175267992 ps
T1000 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2353363304 Aug 09 08:22:53 PM PDT 24 Aug 09 08:31:23 PM PDT 24 5246267252 ps
T357 /workspace/coverage/default/24.chip_sw_all_escalation_resets.2192683415 Aug 09 08:50:38 PM PDT 24 Aug 09 09:00:20 PM PDT 24 5862909958 ps
T1001 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1794854173 Aug 09 08:32:12 PM PDT 24 Aug 09 08:43:50 PM PDT 24 4686553384 ps
T792 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2010406198 Aug 09 08:54:57 PM PDT 24 Aug 09 09:01:20 PM PDT 24 3348724696 ps
T1002 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.150395337 Aug 09 08:38:47 PM PDT 24 Aug 09 08:57:14 PM PDT 24 5977993361 ps
T1003 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3379671204 Aug 09 08:20:59 PM PDT 24 Aug 09 08:25:45 PM PDT 24 2553338384 ps
T1004 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.662799570 Aug 09 08:41:19 PM PDT 24 Aug 09 08:54:46 PM PDT 24 3935003880 ps
T1005 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2060705312 Aug 09 08:27:49 PM PDT 24 Aug 09 08:57:28 PM PDT 24 8558070770 ps
T174 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2825572140 Aug 09 08:43:19 PM PDT 24 Aug 09 08:55:06 PM PDT 24 4639151670 ps
T1006 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3708517430 Aug 09 08:26:17 PM PDT 24 Aug 09 09:37:40 PM PDT 24 25743883525 ps
T140 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1043009570 Aug 09 08:22:00 PM PDT 24 Aug 09 08:33:37 PM PDT 24 6468235592 ps
T407 /workspace/coverage/default/1.chip_sw_kmac_app_rom.2802477242 Aug 09 08:30:12 PM PDT 24 Aug 09 08:34:06 PM PDT 24 2922145480 ps
T24 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.997626044 Aug 09 08:23:57 PM PDT 24 Aug 09 08:34:41 PM PDT 24 3930327500 ps
T1007 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.320504310 Aug 09 08:53:00 PM PDT 24 Aug 09 10:04:29 PM PDT 24 15299564078 ps
T1008 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.154231493 Aug 09 08:47:40 PM PDT 24 Aug 09 09:10:18 PM PDT 24 7939689064 ps
T1009 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1727561874 Aug 09 08:45:23 PM PDT 24 Aug 09 08:56:07 PM PDT 24 3982203624 ps
T1010 /workspace/coverage/default/3.chip_tap_straps_prod.3934635711 Aug 09 08:46:01 PM PDT 24 Aug 09 08:48:37 PM PDT 24 2684254399 ps
T358 /workspace/coverage/default/95.chip_sw_all_escalation_resets.58396329 Aug 09 08:55:07 PM PDT 24 Aug 09 09:05:46 PM PDT 24 6744570970 ps
T775 /workspace/coverage/default/16.chip_sw_all_escalation_resets.4200411293 Aug 09 08:49:40 PM PDT 24 Aug 09 08:59:22 PM PDT 24 5472803152 ps
T1011 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1018668673 Aug 09 08:22:23 PM PDT 24 Aug 09 08:34:52 PM PDT 24 4694340936 ps
T1012 /workspace/coverage/default/1.rom_e2e_self_hash.2613888445 Aug 09 08:43:03 PM PDT 24 Aug 09 10:21:45 PM PDT 24 26775972888 ps
T1013 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.202707847 Aug 09 08:41:02 PM PDT 24 Aug 09 08:56:49 PM PDT 24 4632440448 ps
T796 /workspace/coverage/default/0.chip_sw_all_escalation_resets.142051698 Aug 09 08:20:06 PM PDT 24 Aug 09 08:31:48 PM PDT 24 4548951040 ps
T335 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2104766726 Aug 09 08:20:24 PM PDT 24 Aug 09 08:49:18 PM PDT 24 9248320080 ps
T759 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2705468248 Aug 09 08:55:28 PM PDT 24 Aug 09 09:00:51 PM PDT 24 3513695816 ps
T798 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1776537325 Aug 09 08:22:30 PM PDT 24 Aug 09 08:28:55 PM PDT 24 3635023558 ps
T241 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2488944395 Aug 09 08:32:46 PM PDT 24 Aug 09 09:07:45 PM PDT 24 24978827286 ps
T821 /workspace/coverage/default/26.chip_sw_all_escalation_resets.4233354615 Aug 09 08:50:27 PM PDT 24 Aug 09 09:04:43 PM PDT 24 5491402694 ps
T1014 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4120297369 Aug 09 08:28:54 PM PDT 24 Aug 09 09:23:57 PM PDT 24 17001429090 ps
T1015 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.545136716 Aug 09 08:21:01 PM PDT 24 Aug 09 09:59:42 PM PDT 24 49649538040 ps
T756 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3400460035 Aug 09 08:51:23 PM PDT 24 Aug 09 08:57:06 PM PDT 24 4106464668 ps
T183 /workspace/coverage/default/2.rom_e2e_shutdown_output.3873303032 Aug 09 08:47:25 PM PDT 24 Aug 09 09:38:16 PM PDT 24 23982032018 ps
T822 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1364825097 Aug 09 08:54:31 PM PDT 24 Aug 09 09:00:06 PM PDT 24 3341650264 ps
T329 /workspace/coverage/default/0.chip_plic_all_irqs_20.1391372246 Aug 09 08:21:42 PM PDT 24 Aug 09 08:34:18 PM PDT 24 4751824400 ps
T1016 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3601811819 Aug 09 08:42:37 PM PDT 24 Aug 09 08:52:19 PM PDT 24 7837477500 ps
T1017 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.71621507 Aug 09 08:30:20 PM PDT 24 Aug 09 09:02:44 PM PDT 24 10163007268 ps
T764 /workspace/coverage/default/39.chip_sw_all_escalation_resets.551858888 Aug 09 08:53:31 PM PDT 24 Aug 09 09:04:43 PM PDT 24 5084833720 ps
T72 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2801904551 Aug 09 08:19:22 PM PDT 24 Aug 09 10:14:49 PM PDT 24 31398371360 ps
T1018 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1882414664 Aug 09 08:37:28 PM PDT 24 Aug 09 09:01:36 PM PDT 24 23554235900 ps
T88 /workspace/coverage/default/0.chip_sw_gpio_smoketest.2863415262 Aug 09 08:25:58 PM PDT 24 Aug 09 08:29:59 PM PDT 24 2657183805 ps
T1019 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1343827643 Aug 09 08:41:34 PM PDT 24 Aug 09 08:49:26 PM PDT 24 3290010816 ps
T740 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2976708907 Aug 09 08:55:04 PM PDT 24 Aug 09 09:03:05 PM PDT 24 4984731520 ps
T1020 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2424982006 Aug 09 08:19:49 PM PDT 24 Aug 09 11:21:23 PM PDT 24 59829782738 ps
T109 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1170235293 Aug 09 08:32:41 PM PDT 24 Aug 09 08:41:42 PM PDT 24 3621501798 ps
T1021 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4224234561 Aug 09 08:24:15 PM PDT 24 Aug 09 08:43:25 PM PDT 24 7081560420 ps
T1022 /workspace/coverage/default/2.chip_sival_flash_info_access.1215482817 Aug 09 08:36:47 PM PDT 24 Aug 09 08:40:55 PM PDT 24 3414728968 ps
T190 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2595058024 Aug 09 08:38:07 PM PDT 24 Aug 09 10:04:35 PM PDT 24 44533808680 ps
T1023 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3449768016 Aug 09 08:24:37 PM PDT 24 Aug 09 08:29:25 PM PDT 24 2542379245 ps
T684 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4053661844 Aug 09 08:33:45 PM PDT 24 Aug 09 08:45:56 PM PDT 24 4525699878 ps
T243 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1709819753 Aug 09 08:20:24 PM PDT 24 Aug 09 10:02:17 PM PDT 24 46607844833 ps
T1024 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1078708530 Aug 09 08:47:58 PM PDT 24 Aug 09 09:20:04 PM PDT 24 13441164498 ps
T1025 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3588064392 Aug 09 08:20:46 PM PDT 24 Aug 09 08:41:55 PM PDT 24 6648752190 ps
T744 /workspace/coverage/default/58.chip_sw_all_escalation_resets.1048754436 Aug 09 08:57:13 PM PDT 24 Aug 09 09:07:43 PM PDT 24 5758319200 ps
T763 /workspace/coverage/default/63.chip_sw_all_escalation_resets.925164181 Aug 09 08:55:00 PM PDT 24 Aug 09 09:05:39 PM PDT 24 5321643774 ps
T1026 /workspace/coverage/default/0.rom_e2e_smoke.686703296 Aug 09 08:29:14 PM PDT 24 Aug 09 09:38:54 PM PDT 24 15283629816 ps
T776 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3642736523 Aug 09 08:52:56 PM PDT 24 Aug 09 09:00:21 PM PDT 24 3286237840 ps
T1027 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1291740414 Aug 09 08:28:10 PM PDT 24 Aug 09 08:49:02 PM PDT 24 10712171231 ps
T137 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3701123038 Aug 09 08:45:23 PM PDT 24 Aug 09 08:53:34 PM PDT 24 4807791210 ps
T769 /workspace/coverage/default/17.chip_sw_all_escalation_resets.3116236796 Aug 09 08:50:37 PM PDT 24 Aug 09 08:58:54 PM PDT 24 4589576940 ps
T1028 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4246165019 Aug 09 08:41:25 PM PDT 24 Aug 09 08:53:00 PM PDT 24 5585457116 ps
T346 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2138550314 Aug 09 08:19:26 PM PDT 24 Aug 09 08:30:43 PM PDT 24 4784699160 ps
T1029 /workspace/coverage/default/1.chip_sw_otbn_smoketest.3308952484 Aug 09 08:34:43 PM PDT 24 Aug 09 09:09:45 PM PDT 24 10736236680 ps
T305 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1446045949 Aug 09 08:22:02 PM PDT 24 Aug 09 08:35:25 PM PDT 24 6864934372 ps
T1030 /workspace/coverage/default/33.chip_sw_all_escalation_resets.32140138 Aug 09 08:49:34 PM PDT 24 Aug 09 08:59:36 PM PDT 24 5532865730 ps
T367 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1217717416 Aug 09 08:34:47 PM PDT 24 Aug 09 08:49:53 PM PDT 24 5745289081 ps
T1031 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3705524234 Aug 09 08:30:18 PM PDT 24 Aug 09 08:55:45 PM PDT 24 8204778880 ps
T718 /workspace/coverage/default/84.chip_sw_all_escalation_resets.355136268 Aug 09 08:55:39 PM PDT 24 Aug 09 09:07:17 PM PDT 24 4800235592 ps
T1032 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1171561500 Aug 09 08:29:44 PM PDT 24 Aug 09 10:01:26 PM PDT 24 22983084862 ps
T186 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.323926708 Aug 09 08:23:34 PM PDT 24 Aug 09 08:32:56 PM PDT 24 4683237428 ps
T1033 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1931224297 Aug 09 08:42:15 PM PDT 24 Aug 09 08:46:26 PM PDT 24 2615343480 ps
T1034 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2544963684 Aug 09 08:27:14 PM PDT 24 Aug 09 08:31:26 PM PDT 24 3312635223 ps
T815 /workspace/coverage/default/42.chip_sw_all_escalation_resets.2622132065 Aug 09 08:52:45 PM PDT 24 Aug 09 09:01:27 PM PDT 24 4436717800 ps
T1035 /workspace/coverage/default/2.chip_sw_edn_sw_mode.2239032183 Aug 09 08:40:23 PM PDT 24 Aug 09 09:06:47 PM PDT 24 9686938864 ps
T1036 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4256196980 Aug 09 08:23:28 PM PDT 24 Aug 09 08:38:11 PM PDT 24 4943459250 ps
T1037 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.236745439 Aug 09 08:28:47 PM PDT 24 Aug 09 09:27:30 PM PDT 24 19551778003 ps
T688 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2302881715 Aug 09 08:23:26 PM PDT 24 Aug 09 08:25:31 PM PDT 24 2542378656 ps
T1038 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1617787817 Aug 09 08:50:41 PM PDT 24 Aug 09 08:57:11 PM PDT 24 7074621785 ps
T138 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.701041402 Aug 09 08:47:01 PM PDT 24 Aug 09 08:55:46 PM PDT 24 4959113440 ps
T180 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1872680110 Aug 09 08:19:58 PM PDT 24 Aug 09 08:22:53 PM PDT 24 3083964474 ps
T1039 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2389883132 Aug 09 08:40:12 PM PDT 24 Aug 09 08:55:35 PM PDT 24 5564605784 ps
T1040 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3107007118 Aug 09 08:22:35 PM PDT 24 Aug 09 08:33:21 PM PDT 24 4242204254 ps
T1041 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3945097033 Aug 09 08:38:07 PM PDT 24 Aug 09 09:00:45 PM PDT 24 8007261028 ps
T1042 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3078980511 Aug 09 08:20:50 PM PDT 24 Aug 09 11:32:48 PM PDT 24 65431600468 ps
T92 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1098377558 Aug 09 08:48:38 PM PDT 24 Aug 09 08:54:13 PM PDT 24 4258507408 ps
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