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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.09 95.46 93.86 95.44 94.60 97.53 99.61


Total test records in report: 2935
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T279 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3212670442 Aug 09 08:31:10 PM PDT 24 Aug 09 09:23:40 PM PDT 24 11292914281 ps
T1043 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2621325118 Aug 09 08:34:11 PM PDT 24 Aug 09 08:44:45 PM PDT 24 4587384550 ps
T804 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2688329071 Aug 09 08:52:12 PM PDT 24 Aug 09 08:58:06 PM PDT 24 3618285792 ps
T1044 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1771297506 Aug 09 08:20:19 PM PDT 24 Aug 09 09:01:29 PM PDT 24 26647354548 ps
T1045 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.4266703276 Aug 09 08:37:39 PM PDT 24 Aug 09 08:42:53 PM PDT 24 4711908548 ps
T1046 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1781211974 Aug 09 08:52:05 PM PDT 24 Aug 09 09:43:44 PM PDT 24 11338513426 ps
T141 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2372418498 Aug 09 08:32:17 PM PDT 24 Aug 09 08:40:48 PM PDT 24 5136424150 ps
T1047 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1586239836 Aug 09 08:27:16 PM PDT 24 Aug 09 08:51:43 PM PDT 24 9220682312 ps
T1048 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2720400055 Aug 09 08:25:16 PM PDT 24 Aug 09 08:32:37 PM PDT 24 5589474330 ps
T167 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1662965163 Aug 09 08:25:26 PM PDT 24 Aug 09 08:27:02 PM PDT 24 2381496052 ps
T1049 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1427443106 Aug 09 08:30:02 PM PDT 24 Aug 09 08:34:27 PM PDT 24 3124099860 ps
T800 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1505506959 Aug 09 08:55:33 PM PDT 24 Aug 09 09:02:51 PM PDT 24 4344857090 ps
T116 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3925174810 Aug 09 08:23:21 PM PDT 24 Aug 09 11:42:27 PM PDT 24 89162201244 ps
T285 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3093891146 Aug 09 08:35:06 PM PDT 24 Aug 09 08:45:03 PM PDT 24 6261741150 ps
T755 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2714816293 Aug 09 08:56:08 PM PDT 24 Aug 09 09:07:37 PM PDT 24 5381815860 ps
T757 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2380634062 Aug 09 08:51:06 PM PDT 24 Aug 09 08:58:04 PM PDT 24 3682463666 ps
T1050 /workspace/coverage/default/1.chip_sw_example_manufacturer.270864088 Aug 09 08:24:31 PM PDT 24 Aug 09 08:28:03 PM PDT 24 3342979080 ps
T324 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1173163125 Aug 09 08:27:01 PM PDT 24 Aug 09 08:32:50 PM PDT 24 3464389763 ps
T1051 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2533575781 Aug 09 08:22:52 PM PDT 24 Aug 09 08:29:04 PM PDT 24 5426582636 ps
T1052 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3118395590 Aug 09 08:52:10 PM PDT 24 Aug 09 08:57:06 PM PDT 24 3145436112 ps
T1053 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1671718106 Aug 09 08:26:00 PM PDT 24 Aug 09 09:35:23 PM PDT 24 15845993206 ps
T711 /workspace/coverage/default/0.rom_raw_unlock.1726456712 Aug 09 08:27:03 PM PDT 24 Aug 09 08:31:34 PM PDT 24 6022879923 ps
T813 /workspace/coverage/default/36.chip_sw_all_escalation_resets.1139339075 Aug 09 08:51:09 PM PDT 24 Aug 09 08:58:27 PM PDT 24 5913217400 ps
T1054 /workspace/coverage/default/0.chip_sw_coremark.566189585 Aug 09 08:25:52 PM PDT 24 Aug 10 12:13:57 AM PDT 24 71533932512 ps
T51 /workspace/coverage/default/1.chip_sw_alert_test.3422913500 Aug 09 08:28:45 PM PDT 24 Aug 09 08:35:19 PM PDT 24 3298166334 ps
T1055 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2612722138 Aug 09 08:37:12 PM PDT 24 Aug 09 09:03:10 PM PDT 24 9835777018 ps
T1056 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1196949901 Aug 09 08:34:37 PM PDT 24 Aug 09 08:38:50 PM PDT 24 2948939359 ps
T689 /workspace/coverage/default/1.rom_volatile_raw_unlock.3081526888 Aug 09 08:37:25 PM PDT 24 Aug 09 08:39:33 PM PDT 24 3014303955 ps
T33 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.143746386 Aug 09 08:23:15 PM PDT 24 Aug 09 08:34:33 PM PDT 24 7254616570 ps
T1057 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3288514132 Aug 09 08:36:17 PM PDT 24 Aug 09 08:46:52 PM PDT 24 4436404668 ps
T254 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860910500 Aug 09 08:54:40 PM PDT 24 Aug 09 09:01:04 PM PDT 24 3573181116 ps
T1058 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1278887934 Aug 09 08:20:24 PM PDT 24 Aug 09 08:39:43 PM PDT 24 7329361788 ps
T1059 /workspace/coverage/default/1.chip_sw_aes_entropy.3904019032 Aug 09 08:28:10 PM PDT 24 Aug 09 08:32:43 PM PDT 24 3651953302 ps
T789 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1500154224 Aug 09 08:52:55 PM PDT 24 Aug 09 08:59:49 PM PDT 24 3302823010 ps
T93 /workspace/coverage/default/47.chip_sw_all_escalation_resets.2302711844 Aug 09 08:52:12 PM PDT 24 Aug 09 09:02:39 PM PDT 24 4751189532 ps
T1060 /workspace/coverage/default/2.chip_sw_uart_tx_rx.494390840 Aug 09 08:38:00 PM PDT 24 Aug 09 08:49:54 PM PDT 24 4565061090 ps
T40 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1402531111 Aug 09 08:30:18 PM PDT 24 Aug 09 08:46:51 PM PDT 24 8021608544 ps
T151 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.504921333 Aug 09 08:31:15 PM PDT 24 Aug 09 08:36:27 PM PDT 24 3045282083 ps
T103 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2278058085 Aug 09 08:32:56 PM PDT 24 Aug 09 09:00:26 PM PDT 24 24854683832 ps
T104 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1626047685 Aug 09 08:27:06 PM PDT 24 Aug 09 08:52:47 PM PDT 24 23611627120 ps
T1061 /workspace/coverage/default/2.chip_sw_aon_timer_irq.3782858042 Aug 09 08:40:07 PM PDT 24 Aug 09 08:45:38 PM PDT 24 4636868360 ps
T1062 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.114627987 Aug 09 08:47:49 PM PDT 24 Aug 09 09:42:31 PM PDT 24 16090593099 ps
T777 /workspace/coverage/default/79.chip_sw_all_escalation_resets.3894183808 Aug 09 08:58:01 PM PDT 24 Aug 09 09:06:37 PM PDT 24 4996260626 ps
T1063 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1592505336 Aug 09 08:42:58 PM PDT 24 Aug 09 08:52:01 PM PDT 24 6374072299 ps
T1064 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3939884029 Aug 09 08:31:06 PM PDT 24 Aug 09 08:42:42 PM PDT 24 4295205210 ps
T819 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1046564797 Aug 09 08:55:13 PM PDT 24 Aug 09 09:01:35 PM PDT 24 3587537734 ps
T1065 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3090007401 Aug 09 08:21:18 PM PDT 24 Aug 09 08:27:24 PM PDT 24 3679490772 ps
T1066 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3065297798 Aug 09 08:35:32 PM PDT 24 Aug 09 08:40:54 PM PDT 24 2553329054 ps
T686 /workspace/coverage/default/4.chip_tap_straps_dev.678481797 Aug 09 08:46:26 PM PDT 24 Aug 09 09:04:37 PM PDT 24 11359981438 ps
T685 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3844451269 Aug 09 08:43:41 PM PDT 24 Aug 09 08:54:19 PM PDT 24 4285616357 ps
T110 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.35707607 Aug 09 08:42:43 PM PDT 24 Aug 09 08:48:44 PM PDT 24 4036335850 ps
T371 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3743575907 Aug 09 08:49:41 PM PDT 24 Aug 09 08:56:25 PM PDT 24 4145112498 ps
T205 /workspace/coverage/default/0.chip_sw_power_virus.2970885710 Aug 09 08:27:28 PM PDT 24 Aug 09 08:53:57 PM PDT 24 5802216952 ps
T1067 /workspace/coverage/default/29.chip_sw_all_escalation_resets.2648970717 Aug 09 08:50:04 PM PDT 24 Aug 09 09:01:36 PM PDT 24 6076681040 ps
T222 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2672627859 Aug 09 08:20:38 PM PDT 24 Aug 09 09:23:31 PM PDT 24 20935518527 ps
T1068 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1838977808 Aug 09 08:47:28 PM PDT 24 Aug 09 08:57:37 PM PDT 24 7634389800 ps
T311 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.746449849 Aug 09 08:49:59 PM PDT 24 Aug 09 08:57:40 PM PDT 24 4077053248 ps
T1069 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.681472425 Aug 09 08:23:17 PM PDT 24 Aug 09 09:32:17 PM PDT 24 19258103266 ps
T690 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1770343905 Aug 09 08:21:59 PM PDT 24 Aug 09 08:24:02 PM PDT 24 2424390064 ps
T807 /workspace/coverage/default/65.chip_sw_all_escalation_resets.2875687228 Aug 09 08:54:36 PM PDT 24 Aug 09 09:08:41 PM PDT 24 5909830178 ps
T1070 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3556256843 Aug 09 08:27:22 PM PDT 24 Aug 09 08:40:51 PM PDT 24 4705388824 ps
T286 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2134560344 Aug 09 08:28:33 PM PDT 24 Aug 09 08:44:28 PM PDT 24 6222974960 ps
T721 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3359217058 Aug 09 08:50:52 PM PDT 24 Aug 09 08:56:56 PM PDT 24 4353499982 ps
T1071 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3165480 Aug 09 08:48:03 PM PDT 24 Aug 09 10:07:44 PM PDT 24 24138018876 ps
T1072 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1584931335 Aug 09 08:48:49 PM PDT 24 Aug 09 08:52:51 PM PDT 24 2888780152 ps
T1073 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3303829592 Aug 09 08:20:46 PM PDT 24 Aug 09 08:40:08 PM PDT 24 6350240406 ps
T1074 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3617575183 Aug 09 08:20:26 PM PDT 24 Aug 09 08:48:01 PM PDT 24 7913757744 ps
T1075 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3167653481 Aug 09 08:25:10 PM PDT 24 Aug 09 08:48:05 PM PDT 24 6434074200 ps
T1076 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1874849686 Aug 09 08:25:03 PM PDT 24 Aug 09 08:31:47 PM PDT 24 4195631432 ps
T53 /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3851795393 Aug 09 08:37:19 PM PDT 24 Aug 09 08:42:43 PM PDT 24 3623407597 ps
T1077 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2258782664 Aug 09 08:28:44 PM PDT 24 Aug 09 09:29:46 PM PDT 24 15265753014 ps
T242 /workspace/coverage/default/1.chip_sw_flash_init.1275436014 Aug 09 08:26:29 PM PDT 24 Aug 09 08:55:58 PM PDT 24 20602372650 ps
T362 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2764405982 Aug 09 08:40:51 PM PDT 24 Aug 09 08:47:21 PM PDT 24 3048022150 ps
T1078 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1223148793 Aug 09 08:31:11 PM PDT 24 Aug 09 09:31:21 PM PDT 24 13700225240 ps
T1079 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4096883427 Aug 09 08:34:24 PM PDT 24 Aug 09 08:38:13 PM PDT 24 2888396740 ps
T1080 /workspace/coverage/default/2.chip_sw_example_rom.1321837527 Aug 09 08:35:02 PM PDT 24 Aug 09 08:37:19 PM PDT 24 3116154032 ps
T1081 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2134601482 Aug 09 08:26:23 PM PDT 24 Aug 09 08:35:46 PM PDT 24 4437249242 ps
T1082 /workspace/coverage/default/0.chip_sw_uart_smoketest.3130704326 Aug 09 08:24:57 PM PDT 24 Aug 09 08:29:15 PM PDT 24 2775815398 ps
T781 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.652786893 Aug 09 08:53:04 PM PDT 24 Aug 09 08:58:39 PM PDT 24 3546972920 ps
T234 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3937549169 Aug 09 08:24:50 PM PDT 24 Aug 09 08:45:35 PM PDT 24 7534011474 ps
T782 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3566820264 Aug 09 08:55:00 PM PDT 24 Aug 09 09:01:32 PM PDT 24 4151487842 ps
T181 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2511518510 Aug 09 08:39:08 PM PDT 24 Aug 09 09:22:58 PM PDT 24 24762760494 ps
T1083 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2241752162 Aug 09 08:20:32 PM PDT 24 Aug 09 08:39:30 PM PDT 24 10901513710 ps
T341 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4041945709 Aug 09 08:21:13 PM PDT 24 Aug 09 08:36:48 PM PDT 24 4591467120 ps
T1084 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3353054731 Aug 09 08:43:44 PM PDT 24 Aug 09 09:37:43 PM PDT 24 25415127591 ps
T1085 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1519902334 Aug 09 08:35:52 PM PDT 24 Aug 09 08:45:16 PM PDT 24 3925024180 ps
T1086 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.220214148 Aug 09 08:38:11 PM PDT 24 Aug 09 09:02:49 PM PDT 24 11894784788 ps
T330 /workspace/coverage/default/2.chip_plic_all_irqs_20.392502563 Aug 09 08:41:14 PM PDT 24 Aug 09 08:53:45 PM PDT 24 5169261100 ps
T38 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1960687768 Aug 09 08:28:49 PM PDT 24 Aug 09 08:35:55 PM PDT 24 3668723533 ps
T1087 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.956494505 Aug 09 08:27:42 PM PDT 24 Aug 09 08:35:44 PM PDT 24 4532432470 ps
T408 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2873222503 Aug 09 08:41:23 PM PDT 24 Aug 09 08:50:09 PM PDT 24 9376626796 ps
T143 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3492165550 Aug 09 08:22:56 PM PDT 24 Aug 09 08:29:26 PM PDT 24 5359018048 ps
T1088 /workspace/coverage/default/1.chip_sw_aes_smoketest.3940346793 Aug 09 08:34:50 PM PDT 24 Aug 09 08:38:50 PM PDT 24 2182448514 ps
T395 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2304673583 Aug 09 08:40:59 PM PDT 24 Aug 09 08:52:11 PM PDT 24 3166666392 ps
T765 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2607218162 Aug 09 08:49:23 PM PDT 24 Aug 09 08:55:28 PM PDT 24 3202136808 ps
T1089 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.82512480 Aug 09 08:46:18 PM PDT 24 Aug 09 08:57:57 PM PDT 24 3371862200 ps
T1090 /workspace/coverage/default/2.chip_sw_power_idle_load.28381572 Aug 09 08:44:09 PM PDT 24 Aug 09 08:54:36 PM PDT 24 4496494802 ps
T1091 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.737038238 Aug 09 08:39:57 PM PDT 24 Aug 09 09:09:40 PM PDT 24 10055741000 ps
T1092 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3157343344 Aug 09 08:35:40 PM PDT 24 Aug 09 08:47:42 PM PDT 24 3656797720 ps
T244 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1741937150 Aug 09 08:20:10 PM PDT 24 Aug 09 09:55:17 PM PDT 24 46828704836 ps
T381 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2060511703 Aug 09 08:26:41 PM PDT 24 Aug 09 08:37:12 PM PDT 24 5595901728 ps
T287 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1794953970 Aug 09 08:40:59 PM PDT 24 Aug 09 08:49:51 PM PDT 24 5049314270 ps
T1093 /workspace/coverage/default/1.chip_sw_aes_enc.1396250880 Aug 09 08:25:42 PM PDT 24 Aug 09 08:28:47 PM PDT 24 2541100280 ps
T342 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2789397436 Aug 09 08:20:09 PM PDT 24 Aug 09 08:28:04 PM PDT 24 4576406400 ps
T771 /workspace/coverage/default/22.chip_sw_all_escalation_resets.819767050 Aug 09 08:50:48 PM PDT 24 Aug 09 09:03:05 PM PDT 24 6182359950 ps
T1094 /workspace/coverage/default/2.chip_sw_otbn_smoketest.1362214344 Aug 09 08:46:57 PM PDT 24 Aug 09 09:00:44 PM PDT 24 5720232168 ps
T117 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2653472815 Aug 09 08:33:30 PM PDT 24 Aug 09 09:43:23 PM PDT 24 25506899546 ps
T1095 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.608314529 Aug 09 08:26:49 PM PDT 24 Aug 09 09:39:39 PM PDT 24 20715107924 ps
T312 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3577018454 Aug 09 08:54:21 PM PDT 24 Aug 09 09:05:36 PM PDT 24 5217848224 ps
T1096 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3029638680 Aug 09 08:43:19 PM PDT 24 Aug 09 08:51:37 PM PDT 24 7925021402 ps
T1097 /workspace/coverage/default/2.rom_e2e_static_critical.3806560650 Aug 09 08:53:03 PM PDT 24 Aug 09 10:00:50 PM PDT 24 17572989966 ps
T1098 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3008253392 Aug 09 08:28:47 PM PDT 24 Aug 09 08:55:59 PM PDT 24 11463500386 ps
T1099 /workspace/coverage/default/2.rom_e2e_asm_init_rma.867741031 Aug 09 08:47:41 PM PDT 24 Aug 09 09:33:49 PM PDT 24 14258575304 ps
T1100 /workspace/coverage/default/0.chip_sw_aes_entropy.1275792303 Aug 09 08:21:42 PM PDT 24 Aug 09 08:27:10 PM PDT 24 2853549970 ps
T1101 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1841497284 Aug 09 08:42:36 PM PDT 24 Aug 09 08:49:30 PM PDT 24 3681088632 ps
T1102 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3999765050 Aug 09 08:45:59 PM PDT 24 Aug 09 08:59:52 PM PDT 24 8458570725 ps
T797 /workspace/coverage/default/78.chip_sw_all_escalation_resets.4140683978 Aug 09 08:54:28 PM PDT 24 Aug 09 09:04:01 PM PDT 24 4968185896 ps
T1103 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1189457828 Aug 09 08:29:58 PM PDT 24 Aug 09 09:16:12 PM PDT 24 11427219951 ps
T1104 /workspace/coverage/default/2.chip_sw_example_flash.4258178763 Aug 09 08:35:38 PM PDT 24 Aug 09 08:39:52 PM PDT 24 2942035224 ps
T1105 /workspace/coverage/default/2.chip_sw_gpio_smoketest.601520918 Aug 09 08:47:22 PM PDT 24 Aug 09 08:51:56 PM PDT 24 2722623219 ps
T742 /workspace/coverage/default/97.chip_sw_all_escalation_resets.1046451451 Aug 09 08:55:57 PM PDT 24 Aug 09 09:04:10 PM PDT 24 5016092936 ps
T1106 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1910630657 Aug 09 08:24:42 PM PDT 24 Aug 09 08:35:04 PM PDT 24 4827596876 ps
T1107 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2907692175 Aug 09 08:19:41 PM PDT 24 Aug 09 08:43:14 PM PDT 24 11144587217 ps
T288 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2833007069 Aug 09 08:31:20 PM PDT 24 Aug 09 08:43:23 PM PDT 24 5496170520 ps
T409 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.4160139767 Aug 09 08:20:27 PM PDT 24 Aug 09 08:28:40 PM PDT 24 8936430995 ps
T1108 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4137358176 Aug 09 08:43:39 PM PDT 24 Aug 09 08:48:03 PM PDT 24 2781251958 ps
T1109 /workspace/coverage/default/0.chip_sw_example_concurrency.227306600 Aug 09 08:19:46 PM PDT 24 Aug 09 08:24:46 PM PDT 24 3112127148 ps
T235 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.4048384624 Aug 09 08:32:33 PM PDT 24 Aug 09 09:32:04 PM PDT 24 13803527384 ps
T823 /workspace/coverage/default/91.chip_sw_all_escalation_resets.1055834507 Aug 09 08:55:52 PM PDT 24 Aug 09 09:02:36 PM PDT 24 4841586550 ps
T353 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1086107406 Aug 09 08:37:08 PM PDT 24 Aug 09 08:49:58 PM PDT 24 5505701334 ps
T1110 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.4262705783 Aug 09 08:44:28 PM PDT 24 Aug 09 08:51:54 PM PDT 24 6202508886 ps
T1111 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1515581480 Aug 09 08:22:49 PM PDT 24 Aug 09 08:48:11 PM PDT 24 7344395624 ps
T1112 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1387365847 Aug 09 08:31:40 PM PDT 24 Aug 09 10:19:42 PM PDT 24 23238413533 ps
T1113 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.886866332 Aug 09 08:44:45 PM PDT 24 Aug 09 08:49:42 PM PDT 24 3432547074 ps
T265 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.4268286043 Aug 09 08:25:27 PM PDT 24 Aug 09 09:03:25 PM PDT 24 10364665887 ps
T382 /workspace/coverage/default/82.chip_sw_all_escalation_resets.1717830573 Aug 09 08:55:35 PM PDT 24 Aug 09 09:03:13 PM PDT 24 5405684928 ps
T1114 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3727822986 Aug 09 08:20:15 PM PDT 24 Aug 09 08:26:22 PM PDT 24 3656819080 ps
T719 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3916511464 Aug 09 08:51:42 PM PDT 24 Aug 09 08:59:30 PM PDT 24 3917880866 ps
T741 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3259727916 Aug 09 08:45:24 PM PDT 24 Aug 09 08:51:43 PM PDT 24 3591311996 ps
T1115 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.517639490 Aug 09 08:36:32 PM PDT 24 Aug 09 08:41:41 PM PDT 24 2447036072 ps
T105 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.396822054 Aug 09 08:42:25 PM PDT 24 Aug 09 08:49:06 PM PDT 24 6811800040 ps
T802 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1336104813 Aug 09 08:57:13 PM PDT 24 Aug 09 09:03:12 PM PDT 24 3533543324 ps
T1116 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2148200796 Aug 09 08:25:49 PM PDT 24 Aug 09 08:50:51 PM PDT 24 24121096188 ps
T289 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.943380463 Aug 09 08:41:18 PM PDT 24 Aug 09 08:54:24 PM PDT 24 5798018130 ps
T1117 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3389448211 Aug 09 08:41:48 PM PDT 24 Aug 09 08:48:23 PM PDT 24 3327425318 ps
T106 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.755025366 Aug 09 08:33:19 PM PDT 24 Aug 09 08:39:56 PM PDT 24 7421378140 ps
T1118 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2743563666 Aug 09 08:25:04 PM PDT 24 Aug 09 08:29:23 PM PDT 24 2758809984 ps
T1119 /workspace/coverage/default/49.chip_sw_all_escalation_resets.1946260502 Aug 09 08:52:07 PM PDT 24 Aug 09 09:01:26 PM PDT 24 5625379768 ps
T751 /workspace/coverage/default/56.chip_sw_all_escalation_resets.605163507 Aug 09 08:52:54 PM PDT 24 Aug 09 09:02:29 PM PDT 24 4844831094 ps
T1120 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.981707227 Aug 09 08:23:19 PM PDT 24 Aug 09 08:33:57 PM PDT 24 8724202500 ps
T1121 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.251728377 Aug 09 08:43:05 PM PDT 24 Aug 09 08:52:03 PM PDT 24 5116724472 ps
T1122 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3134497937 Aug 09 08:29:57 PM PDT 24 Aug 09 09:12:57 PM PDT 24 26866625163 ps
T26 /workspace/coverage/default/0.chip_sw_gpio.3308477119 Aug 09 08:20:39 PM PDT 24 Aug 09 08:28:03 PM PDT 24 3383063800 ps
T1123 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1368527116 Aug 09 08:26:02 PM PDT 24 Aug 09 08:35:15 PM PDT 24 3707621191 ps
T1124 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2384021899 Aug 09 08:28:33 PM PDT 24 Aug 09 09:38:44 PM PDT 24 14896876794 ps
T1125 /workspace/coverage/default/0.chip_sw_usbdev_vbus.3061341764 Aug 09 08:21:05 PM PDT 24 Aug 09 08:24:48 PM PDT 24 2772757864 ps
T1126 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2952378011 Aug 09 08:26:42 PM PDT 24 Aug 09 08:31:28 PM PDT 24 2651612260 ps
T1127 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1698605351 Aug 09 08:24:48 PM PDT 24 Aug 09 08:44:48 PM PDT 24 5916479180 ps
T787 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2367951363 Aug 09 08:55:01 PM PDT 24 Aug 09 09:03:40 PM PDT 24 4219767516 ps
T1128 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4066490178 Aug 09 08:52:31 PM PDT 24 Aug 09 09:11:16 PM PDT 24 7983544232 ps
T1129 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1705699438 Aug 09 08:24:25 PM PDT 24 Aug 09 08:36:06 PM PDT 24 4417781110 ps
T1130 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3007374482 Aug 09 08:23:44 PM PDT 24 Aug 09 08:44:54 PM PDT 24 9734775520 ps
T182 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.88038084 Aug 09 08:21:27 PM PDT 24 Aug 09 08:25:30 PM PDT 24 3689489557 ps
T1131 /workspace/coverage/default/1.chip_sw_kmac_entropy.131143725 Aug 09 08:29:19 PM PDT 24 Aug 09 08:33:42 PM PDT 24 2653285740 ps
T1132 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2573215425 Aug 09 08:37:40 PM PDT 24 Aug 09 08:44:50 PM PDT 24 5304786748 ps
T1133 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.4023019116 Aug 09 08:46:55 PM PDT 24 Aug 09 10:12:47 PM PDT 24 23978761400 ps
T313 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.259664709 Aug 09 08:39:22 PM PDT 24 Aug 09 08:46:41 PM PDT 24 3964321498 ps
T1134 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2238267777 Aug 09 08:26:31 PM PDT 24 Aug 09 11:36:53 PM PDT 24 63367175230 ps
T1135 /workspace/coverage/default/2.chip_sw_aes_entropy.365457055 Aug 09 08:39:39 PM PDT 24 Aug 09 08:44:09 PM PDT 24 3099167632 ps
T809 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3029457090 Aug 09 08:53:15 PM PDT 24 Aug 09 08:58:52 PM PDT 24 2942132072 ps
T1136 /workspace/coverage/default/0.chip_sw_usbdev_dpi.1299877871 Aug 09 08:19:10 PM PDT 24 Aug 09 09:12:23 PM PDT 24 12399683148 ps
T1137 /workspace/coverage/default/1.chip_sival_flash_info_access.2246118464 Aug 09 08:25:50 PM PDT 24 Aug 09 08:29:52 PM PDT 24 2600913496 ps
T691 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2597293333 Aug 09 08:37:07 PM PDT 24 Aug 09 08:39:20 PM PDT 24 3276533779 ps
T760 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1249037813 Aug 09 08:54:14 PM PDT 24 Aug 09 08:59:46 PM PDT 24 3722088510 ps
T1138 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.426975427 Aug 09 08:31:02 PM PDT 24 Aug 09 08:42:07 PM PDT 24 5173586850 ps
T1139 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4052870882 Aug 09 08:36:59 PM PDT 24 Aug 09 08:39:24 PM PDT 24 2452497305 ps
T57 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1221370899 Aug 09 08:26:23 PM PDT 24 Aug 09 08:32:50 PM PDT 24 6089330116 ps
T421 /workspace/coverage/default/0.chip_sw_edn_sw_mode.35600810 Aug 09 08:22:40 PM PDT 24 Aug 09 08:45:53 PM PDT 24 6049325062 ps
T422 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1954701154 Aug 09 08:30:20 PM PDT 24 Aug 09 08:39:53 PM PDT 24 4886200600 ps
T354 /workspace/coverage/default/2.chip_sw_pattgen_ios.4136063563 Aug 09 08:35:24 PM PDT 24 Aug 09 08:40:07 PM PDT 24 2798095736 ps
T423 /workspace/coverage/default/2.chip_sw_kmac_entropy.3585438236 Aug 09 08:37:33 PM PDT 24 Aug 09 08:40:56 PM PDT 24 3356832840 ps
T424 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1036783390 Aug 09 08:47:22 PM PDT 24 Aug 09 08:53:36 PM PDT 24 3205933792 ps
T425 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2275270860 Aug 09 08:42:18 PM PDT 24 Aug 09 09:05:11 PM PDT 24 11451760231 ps
T426 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2935792966 Aug 09 08:49:50 PM PDT 24 Aug 09 08:58:42 PM PDT 24 3095404088 ps
T427 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.748747439 Aug 09 08:30:04 PM PDT 24 Aug 09 09:29:59 PM PDT 24 15497893382 ps
T112 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2289749571 Aug 09 08:33:00 PM PDT 24 Aug 09 08:57:51 PM PDT 24 21656433230 ps
T785 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2730032017 Aug 09 08:53:03 PM PDT 24 Aug 09 09:00:42 PM PDT 24 4335044006 ps
T1140 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1573683856 Aug 09 08:20:41 PM PDT 24 Aug 09 08:30:01 PM PDT 24 5871809216 ps
T1141 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3116433122 Aug 09 08:24:42 PM PDT 24 Aug 09 08:44:34 PM PDT 24 8437504480 ps
T1142 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2371228175 Aug 09 08:28:43 PM PDT 24 Aug 09 08:45:05 PM PDT 24 5465770692 ps
T1143 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.4039267338 Aug 09 08:48:33 PM PDT 24 Aug 09 09:00:02 PM PDT 24 5528953817 ps
T31 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2796057398 Aug 09 08:25:10 PM PDT 24 Aug 09 08:29:45 PM PDT 24 2486953776 ps
T816 /workspace/coverage/default/96.chip_sw_all_escalation_resets.2217711352 Aug 09 08:54:42 PM PDT 24 Aug 09 09:03:37 PM PDT 24 6007309776 ps
T1144 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1032096183 Aug 09 08:22:59 PM PDT 24 Aug 09 08:28:55 PM PDT 24 3591266713 ps
T1145 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.618251723 Aug 09 08:26:20 PM PDT 24 Aug 09 08:44:16 PM PDT 24 5501186451 ps
T322 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3689582609 Aug 09 08:29:01 PM PDT 24 Aug 09 08:38:49 PM PDT 24 5899588086 ps
T1146 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2937111303 Aug 09 08:52:39 PM PDT 24 Aug 09 09:42:01 PM PDT 24 14810848912 ps
T1147 /workspace/coverage/default/93.chip_sw_all_escalation_resets.3564436666 Aug 09 08:55:42 PM PDT 24 Aug 09 09:04:44 PM PDT 24 4867711280 ps
T1148 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1078273276 Aug 09 08:41:26 PM PDT 24 Aug 09 11:50:35 PM PDT 24 255315765384 ps
T1149 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2516611948 Aug 09 08:21:19 PM PDT 24 Aug 09 08:36:14 PM PDT 24 11011290359 ps
T1150 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3145450912 Aug 09 08:31:03 PM PDT 24 Aug 09 09:11:32 PM PDT 24 13380300620 ps
T81 /workspace/coverage/default/2.chip_jtag_mem_access.317802732 Aug 09 08:34:29 PM PDT 24 Aug 09 08:57:59 PM PDT 24 13627935412 ps
T1151 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2437200721 Aug 09 08:21:31 PM PDT 24 Aug 09 09:50:03 PM PDT 24 27443005520 ps
T1152 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3421637392 Aug 09 08:22:25 PM PDT 24 Aug 09 08:25:44 PM PDT 24 3165219818 ps
T1153 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1376352539 Aug 09 08:39:55 PM PDT 24 Aug 09 08:47:01 PM PDT 24 7798700778 ps
T1154 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3863476144 Aug 09 08:41:39 PM PDT 24 Aug 09 08:52:16 PM PDT 24 4409187390 ps
T1155 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3994531397 Aug 09 08:24:06 PM PDT 24 Aug 09 08:31:01 PM PDT 24 3397140832 ps
T676 /workspace/coverage/default/0.chip_sw_edn_boot_mode.786999133 Aug 09 08:25:26 PM PDT 24 Aug 09 08:37:04 PM PDT 24 3236903880 ps
T55 /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2367032554 Aug 09 08:27:46 PM PDT 24 Aug 09 08:32:43 PM PDT 24 3781868896 ps
T712 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3078316996 Aug 09 08:23:32 PM PDT 24 Aug 09 08:50:11 PM PDT 24 10929417864 ps
T795 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1897231150 Aug 09 08:54:55 PM PDT 24 Aug 09 09:01:20 PM PDT 24 4368181000 ps
T1156 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3370246362 Aug 09 08:31:00 PM PDT 24 Aug 09 08:53:11 PM PDT 24 6663914640 ps
T749 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1963816612 Aug 09 08:49:56 PM PDT 24 Aug 09 08:55:53 PM PDT 24 4159740428 ps
T191 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2732611700 Aug 09 08:25:02 PM PDT 24 Aug 09 09:43:15 PM PDT 24 42453391024 ps
T1157 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4148360007 Aug 09 08:27:46 PM PDT 24 Aug 09 08:29:48 PM PDT 24 2618123850 ps
T1158 /workspace/coverage/default/2.chip_sw_hmac_multistream.1714576837 Aug 09 08:42:03 PM PDT 24 Aug 09 09:09:24 PM PDT 24 7987033448 ps
T1159 /workspace/coverage/default/1.chip_sw_example_flash.3477361339 Aug 09 08:26:15 PM PDT 24 Aug 09 08:29:56 PM PDT 24 2607866408 ps
T1160 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1143983800 Aug 09 08:41:26 PM PDT 24 Aug 09 09:37:35 PM PDT 24 14743306224 ps
T825 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2855531336 Aug 09 08:53:56 PM PDT 24 Aug 09 09:02:21 PM PDT 24 4810665160 ps
T1161 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3867991488 Aug 09 08:28:14 PM PDT 24 Aug 09 08:35:09 PM PDT 24 2833110840 ps
T1162 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2571868289 Aug 09 08:39:23 PM PDT 24 Aug 09 09:29:11 PM PDT 24 17502679450 ps
T1163 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1847364732 Aug 09 08:24:44 PM PDT 24 Aug 09 08:35:36 PM PDT 24 4078059160 ps
T355 /workspace/coverage/default/0.chip_sw_pattgen_ios.330717555 Aug 09 08:20:36 PM PDT 24 Aug 09 08:25:05 PM PDT 24 2924246712 ps
T811 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2054263367 Aug 09 08:54:35 PM PDT 24 Aug 09 09:00:57 PM PDT 24 4488028512 ps
T1164 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2774997837 Aug 09 08:38:47 PM PDT 24 Aug 09 09:30:22 PM PDT 24 31100249384 ps
T1165 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2160204966 Aug 09 08:30:25 PM PDT 24 Aug 09 08:51:01 PM PDT 24 7405964017 ps
T323 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2664064388 Aug 09 08:43:26 PM PDT 24 Aug 09 08:50:15 PM PDT 24 4384705674 ps
T52 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1339045986 Aug 09 08:19:32 PM PDT 24 Aug 09 08:24:33 PM PDT 24 3187473808 ps
T1166 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.794212455 Aug 09 08:21:40 PM PDT 24 Aug 09 08:25:21 PM PDT 24 3609095299 ps
T1167 /workspace/coverage/default/1.chip_sw_aon_timer_irq.1344255273 Aug 09 08:29:49 PM PDT 24 Aug 09 08:36:40 PM PDT 24 4287121900 ps
T56 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.674936821 Aug 09 08:20:14 PM PDT 24 Aug 09 08:23:54 PM PDT 24 2817820905 ps
T1168 /workspace/coverage/default/2.chip_sw_kmac_app_rom.1919880763 Aug 09 08:40:55 PM PDT 24 Aug 09 08:43:41 PM PDT 24 2358951186 ps
T348 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.378708216 Aug 09 08:34:38 PM PDT 24 Aug 09 08:41:15 PM PDT 24 4123396370 ps
T1169 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.478900422 Aug 09 08:26:44 PM PDT 24 Aug 09 08:33:22 PM PDT 24 3950422300 ps
T1170 /workspace/coverage/default/1.chip_sw_hmac_oneshot.185466051 Aug 09 08:30:14 PM PDT 24 Aug 09 08:37:47 PM PDT 24 2832646432 ps
T772 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1293122072 Aug 09 08:50:13 PM PDT 24 Aug 09 08:56:11 PM PDT 24 3652920132 ps
T814 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.794304750 Aug 09 08:48:24 PM PDT 24 Aug 09 08:55:27 PM PDT 24 3908372240 ps
T1171 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1942077174 Aug 09 08:49:15 PM PDT 24 Aug 09 09:00:19 PM PDT 24 3885664608 ps
T1172 /workspace/coverage/default/81.chip_sw_all_escalation_resets.2292486281 Aug 09 08:59:45 PM PDT 24 Aug 09 09:10:23 PM PDT 24 4729306320 ps
T111 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3116394568 Aug 09 08:36:03 PM PDT 24 Aug 09 08:44:16 PM PDT 24 6633052654 ps
T430 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.945134017 Aug 09 08:47:58 PM PDT 24 Aug 09 09:12:40 PM PDT 24 8084359812 ps
T32 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1632016043 Aug 09 08:37:11 PM PDT 24 Aug 09 08:43:27 PM PDT 24 3372226400 ps
T431 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3892711891 Aug 09 08:40:37 PM PDT 24 Aug 09 09:12:24 PM PDT 24 10646167985 ps
T432 /workspace/coverage/default/2.rom_e2e_self_hash.3920272808 Aug 09 08:49:02 PM PDT 24 Aug 09 10:22:19 PM PDT 24 26642936352 ps
T433 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2292008995 Aug 09 08:35:59 PM PDT 24 Aug 09 08:47:10 PM PDT 24 5367117862 ps
T304 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3548851742 Aug 09 08:43:21 PM PDT 24 Aug 09 08:48:35 PM PDT 24 3016907490 ps
T434 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3712859111 Aug 09 08:41:58 PM PDT 24 Aug 09 08:48:14 PM PDT 24 3408621618 ps
T435 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1450038603 Aug 09 08:41:34 PM PDT 24 Aug 09 08:47:32 PM PDT 24 3051575416 ps
T436 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.585737971 Aug 09 08:27:17 PM PDT 24 Aug 09 08:37:06 PM PDT 24 6245576750 ps
T1173 /workspace/coverage/default/1.chip_sw_otbn_randomness.4077754102 Aug 09 08:31:08 PM PDT 24 Aug 09 08:50:00 PM PDT 24 5910221540 ps
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