| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.09 | 95.46 | 93.86 | 95.44 | 94.60 | 97.53 | 99.61 |
| T2763 | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.2713930072 | Aug 09 08:04:28 PM PDT 24 | Aug 09 08:05:15 PM PDT 24 | 1339384131 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.479558971 | Aug 09 08:04:38 PM PDT 24 | Aug 09 08:06:11 PM PDT 24 | 9629106856 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/19.xbar_error_random.1843243876 | Aug 09 07:59:58 PM PDT 24 | Aug 09 08:01:14 PM PDT 24 | 2400748871 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3855044453 | Aug 09 08:05:54 PM PDT 24 | Aug 09 08:06:28 PM PDT 24 | 108465575 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/86.xbar_random.67846792 | Aug 09 08:09:58 PM PDT 24 | Aug 09 08:10:29 PM PDT 24 | 395068966 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/13.chip_tl_errors.2428421214 | Aug 09 07:59:04 PM PDT 24 | Aug 09 08:00:30 PM PDT 24 | 2703168205 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/49.xbar_random.3238753723 | Aug 09 08:04:39 PM PDT 24 | Aug 09 08:05:26 PM PDT 24 | 459755953 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.907978617 | Aug 09 08:10:41 PM PDT 24 | Aug 09 08:19:16 PM PDT 24 | 4301718065 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/94.xbar_same_source.3028909221 | Aug 09 08:11:12 PM PDT 24 | Aug 09 08:11:46 PM PDT 24 | 1284400579 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1918389376 | Aug 09 07:59:22 PM PDT 24 | Aug 09 08:00:10 PM PDT 24 | 2947509431 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.2919104230 | Aug 09 08:09:27 PM PDT 24 | Aug 09 08:09:46 PM PDT 24 | 150999866 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3235182522 | Aug 09 07:58:57 PM PDT 24 | Aug 09 08:58:44 PM PDT 24 | 28965340918 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3294229609 | Aug 09 08:08:45 PM PDT 24 | Aug 09 08:08:54 PM PDT 24 | 72602859 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.21518289 | Aug 09 08:09:32 PM PDT 24 | Aug 09 08:09:38 PM PDT 24 | 44322628 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.475445342 | Aug 09 08:06:14 PM PDT 24 | Aug 09 08:06:40 PM PDT 24 | 224293568 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2320785577 | Aug 09 08:07:34 PM PDT 24 | Aug 09 08:22:10 PM PDT 24 | 79213198224 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/67.xbar_random.2024138585 | Aug 09 08:07:19 PM PDT 24 | Aug 09 08:08:09 PM PDT 24 | 1541957405 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.3788695773 | Aug 09 08:01:07 PM PDT 24 | Aug 09 08:01:48 PM PDT 24 | 3990275969 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.4272609469 | Aug 09 08:09:59 PM PDT 24 | Aug 09 08:13:19 PM PDT 24 | 2726199537 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2486022163 | Aug 09 08:00:52 PM PDT 24 | Aug 09 08:03:42 PM PDT 24 | 4338191060 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2202669622 | Aug 09 08:07:57 PM PDT 24 | Aug 09 08:08:03 PM PDT 24 | 42876054 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.1943763048 | Aug 09 08:11:46 PM PDT 24 | Aug 09 08:12:49 PM PDT 24 | 835488485 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/1.xbar_stress_all.1602929175 | Aug 09 07:57:35 PM PDT 24 | Aug 09 08:02:37 PM PDT 24 | 8441752790 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3111646471 | Aug 09 07:59:12 PM PDT 24 | Aug 09 07:59:18 PM PDT 24 | 47107708 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.411741530 | Aug 09 07:58:13 PM PDT 24 | Aug 09 08:08:58 PM PDT 24 | 59643887759 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3023431778 | Aug 09 08:06:34 PM PDT 24 | Aug 09 08:14:05 PM PDT 24 | 14394121433 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/75.xbar_error_random.115516121 | Aug 09 08:08:27 PM PDT 24 | Aug 09 08:08:53 PM PDT 24 | 688772222 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.918632335 | Aug 09 08:09:31 PM PDT 24 | Aug 09 08:10:03 PM PDT 24 | 312872112 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1018168011 | Aug 09 08:12:08 PM PDT 24 | Aug 09 08:12:33 PM PDT 24 | 202349540 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.791943804 | Aug 09 07:58:10 PM PDT 24 | Aug 09 08:07:47 PM PDT 24 | 33875458725 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.3374579696 | Aug 09 08:10:34 PM PDT 24 | Aug 09 08:11:20 PM PDT 24 | 583947176 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.1008733948 | Aug 09 08:10:30 PM PDT 24 | Aug 09 08:16:22 PM PDT 24 | 10485668717 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/50.xbar_smoke.3125589718 | Aug 09 08:04:51 PM PDT 24 | Aug 09 08:05:00 PM PDT 24 | 188959996 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1248348729 | Aug 09 07:57:52 PM PDT 24 | Aug 09 07:59:32 PM PDT 24 | 6009138748 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2228440169 | Aug 09 08:00:22 PM PDT 24 | Aug 09 08:00:29 PM PDT 24 | 55049311 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/95.xbar_error_random.3315629696 | Aug 09 08:11:24 PM PDT 24 | Aug 09 08:12:02 PM PDT 24 | 1101857414 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/14.xbar_error_random.2409460360 | Aug 09 07:59:08 PM PDT 24 | Aug 09 08:00:27 PM PDT 24 | 2214893701 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.4212792957 | Aug 09 08:07:57 PM PDT 24 | Aug 09 08:08:17 PM PDT 24 | 177823970 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2629396180 | Aug 09 08:02:03 PM PDT 24 | Aug 09 08:02:10 PM PDT 24 | 49555522 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1230672574 | Aug 09 08:10:02 PM PDT 24 | Aug 09 08:11:41 PM PDT 24 | 2403322641 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/29.xbar_same_source.3560216425 | Aug 09 08:01:31 PM PDT 24 | Aug 09 08:02:38 PM PDT 24 | 2576458135 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.252622365 | Aug 09 07:57:52 PM PDT 24 | Aug 09 07:58:14 PM PDT 24 | 425167432 ps | ||
| T698 | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.970368259 | Aug 09 08:03:37 PM PDT 24 | Aug 09 08:15:57 PM PDT 24 | 8006744687 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3225466861 | Aug 09 08:07:05 PM PDT 24 | Aug 09 08:07:10 PM PDT 24 | 22143364 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2363207400 | Aug 09 08:05:20 PM PDT 24 | Aug 09 08:05:38 PM PDT 24 | 127926798 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.1744702439 | Aug 09 08:07:55 PM PDT 24 | Aug 09 08:08:18 PM PDT 24 | 536704195 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/91.xbar_smoke.3339335775 | Aug 09 08:10:43 PM PDT 24 | Aug 09 08:10:49 PM PDT 24 | 39839617 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3071242184 | Aug 09 08:08:40 PM PDT 24 | Aug 09 08:48:08 PM PDT 24 | 123763756477 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.2777632670 | Aug 09 07:58:28 PM PDT 24 | Aug 09 07:58:57 PM PDT 24 | 319048833 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.528733899 | Aug 09 08:05:54 PM PDT 24 | Aug 09 08:06:01 PM PDT 24 | 55533010 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/48.xbar_smoke.1287229442 | Aug 09 08:04:23 PM PDT 24 | Aug 09 08:04:33 PM PDT 24 | 198133984 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.1664558362 | Aug 09 08:09:22 PM PDT 24 | Aug 09 08:14:26 PM PDT 24 | 9148496815 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2207276577 | Aug 09 07:59:57 PM PDT 24 | Aug 09 08:00:37 PM PDT 24 | 476712410 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/9.xbar_stress_all.3345629875 | Aug 09 07:58:05 PM PDT 24 | Aug 09 07:59:07 PM PDT 24 | 1611751207 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.1918571941 | Aug 09 08:07:58 PM PDT 24 | Aug 09 08:09:28 PM PDT 24 | 8979461200 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/39.xbar_same_source.501758634 | Aug 09 08:03:09 PM PDT 24 | Aug 09 08:03:19 PM PDT 24 | 221632653 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.897512888 | Aug 09 08:10:01 PM PDT 24 | Aug 09 08:10:11 PM PDT 24 | 56665519 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.277646037 | Aug 09 07:57:58 PM PDT 24 | Aug 09 08:03:49 PM PDT 24 | 20886079518 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.4117959732 | Aug 09 08:00:22 PM PDT 24 | Aug 09 08:00:29 PM PDT 24 | 38035247 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/78.xbar_stress_all.2037889152 | Aug 09 08:08:55 PM PDT 24 | Aug 09 08:12:04 PM PDT 24 | 4543280625 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/0.xbar_same_source.1899322790 | Aug 09 07:57:32 PM PDT 24 | Aug 09 07:57:47 PM PDT 24 | 194380649 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.919946154 | Aug 09 07:58:09 PM PDT 24 | Aug 09 08:35:43 PM PDT 24 | 15457789271 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.269077687 | Aug 09 08:03:02 PM PDT 24 | Aug 09 08:04:34 PM PDT 24 | 5110353347 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.868408775 | Aug 09 07:58:15 PM PDT 24 | Aug 09 07:58:31 PM PDT 24 | 116364366 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.3952431908 | Aug 09 08:02:32 PM PDT 24 | Aug 09 08:03:02 PM PDT 24 | 795073086 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1022537057 | Aug 09 08:08:47 PM PDT 24 | Aug 09 08:14:44 PM PDT 24 | 2107036250 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.344286950 | Aug 09 08:10:34 PM PDT 24 | Aug 09 08:11:51 PM PDT 24 | 4601312410 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.743329686 | Aug 09 08:10:53 PM PDT 24 | Aug 09 08:11:28 PM PDT 24 | 458522210 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/60.xbar_stress_all.1589294347 | Aug 09 08:06:20 PM PDT 24 | Aug 09 08:11:25 PM PDT 24 | 8321114127 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2734327735 | Aug 09 08:05:19 PM PDT 24 | Aug 09 08:08:46 PM PDT 24 | 2237374061 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/61.xbar_smoke.1185843542 | Aug 09 08:06:28 PM PDT 24 | Aug 09 08:06:37 PM PDT 24 | 197523818 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.1723658934 | Aug 09 08:11:12 PM PDT 24 | Aug 09 08:11:18 PM PDT 24 | 40016665 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/68.xbar_same_source.1540485330 | Aug 09 08:07:26 PM PDT 24 | Aug 09 08:07:49 PM PDT 24 | 297310008 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2099766434 | Aug 09 08:10:16 PM PDT 24 | Aug 09 08:14:04 PM PDT 24 | 2286675535 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.2136674629 | Aug 09 08:10:30 PM PDT 24 | Aug 09 08:10:43 PM PDT 24 | 93817723 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.4243725003 | Aug 09 08:11:36 PM PDT 24 | Aug 09 08:12:23 PM PDT 24 | 532728782 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2856534955 | Aug 09 07:57:31 PM PDT 24 | Aug 09 07:58:46 PM PDT 24 | 198622854 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.900968153 | Aug 09 08:11:14 PM PDT 24 | Aug 09 08:46:50 PM PDT 24 | 118084462876 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/72.xbar_same_source.3019750431 | Aug 09 08:08:05 PM PDT 24 | Aug 09 08:08:38 PM PDT 24 | 535360034 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1547645949 | Aug 09 08:11:23 PM PDT 24 | Aug 09 08:14:13 PM PDT 24 | 9587172460 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1293170005 | Aug 09 08:10:20 PM PDT 24 | Aug 09 08:10:26 PM PDT 24 | 38225174 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.3288873060 | Aug 09 07:58:12 PM PDT 24 | Aug 09 07:58:37 PM PDT 24 | 337955479 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.603279341 | Aug 09 08:05:54 PM PDT 24 | Aug 09 08:06:28 PM PDT 24 | 414630080 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.838777095 | Aug 09 08:07:19 PM PDT 24 | Aug 09 08:15:23 PM PDT 24 | 42021940871 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.371438632 | Aug 09 08:10:44 PM PDT 24 | Aug 09 08:10:50 PM PDT 24 | 41724821 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/73.xbar_smoke.3210800509 | Aug 09 08:08:03 PM PDT 24 | Aug 09 08:08:11 PM PDT 24 | 152384445 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.3390251856 | Aug 09 08:04:12 PM PDT 24 | Aug 09 08:08:14 PM PDT 24 | 8186499443 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/98.xbar_same_source.2164544896 | Aug 09 08:11:55 PM PDT 24 | Aug 09 08:12:18 PM PDT 24 | 733100293 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1392190304 | Aug 09 07:58:27 PM PDT 24 | Aug 09 08:11:06 PM PDT 24 | 73326592131 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2106327270 | Aug 09 08:01:39 PM PDT 24 | Aug 09 08:02:04 PM PDT 24 | 244346154 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.546969237 | Aug 09 07:59:31 PM PDT 24 | Aug 09 08:07:15 PM PDT 24 | 11894212081 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/73.xbar_stress_all.3427079232 | Aug 09 08:08:14 PM PDT 24 | Aug 09 08:11:00 PM PDT 24 | 4802030335 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2366343142 | Aug 09 08:07:41 PM PDT 24 | Aug 09 08:08:21 PM PDT 24 | 857413588 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.917009228 | Aug 09 08:05:27 PM PDT 24 | Aug 09 08:07:12 PM PDT 24 | 6185324821 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.1774312983 | Aug 09 07:59:38 PM PDT 24 | Aug 09 08:01:37 PM PDT 24 | 2608944659 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/5.xbar_same_source.3723110206 | Aug 09 07:57:53 PM PDT 24 | Aug 09 07:58:43 PM PDT 24 | 1548628537 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.4061223356 | Aug 09 08:02:33 PM PDT 24 | Aug 09 08:03:10 PM PDT 24 | 1010608233 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/18.xbar_error_random.1444296328 | Aug 09 07:59:50 PM PDT 24 | Aug 09 08:00:16 PM PDT 24 | 297555595 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.134446843 | Aug 09 08:11:56 PM PDT 24 | Aug 09 08:14:21 PM PDT 24 | 1976765860 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.1493876543 | Aug 09 08:01:33 PM PDT 24 | Aug 09 08:02:33 PM PDT 24 | 1480041011 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/2.xbar_smoke.2435443645 | Aug 09 07:57:41 PM PDT 24 | Aug 09 07:57:49 PM PDT 24 | 211177999 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2382512773 | Aug 09 08:00:40 PM PDT 24 | Aug 09 08:16:36 PM PDT 24 | 58146958626 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/67.xbar_same_source.4067701462 | Aug 09 08:07:18 PM PDT 24 | Aug 09 08:07:32 PM PDT 24 | 328548564 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2635057655 | Aug 09 07:59:05 PM PDT 24 | Aug 09 08:00:13 PM PDT 24 | 4204347981 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2409143384 | Aug 09 08:04:07 PM PDT 24 | Aug 09 08:05:29 PM PDT 24 | 7355019309 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/65.xbar_same_source.3229480706 | Aug 09 08:07:01 PM PDT 24 | Aug 09 08:07:22 PM PDT 24 | 649684758 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2342300411 | Aug 09 08:08:38 PM PDT 24 | Aug 09 08:08:49 PM PDT 24 | 99472111 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2542161270 | Aug 09 08:06:37 PM PDT 24 | Aug 09 08:26:42 PM PDT 24 | 74306812425 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.264686055 | Aug 09 08:06:46 PM PDT 24 | Aug 09 08:08:51 PM PDT 24 | 3469329831 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.38891475 | Aug 09 08:06:18 PM PDT 24 | Aug 09 08:09:11 PM PDT 24 | 10596076310 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/83.xbar_error_random.228939201 | Aug 09 08:09:51 PM PDT 24 | Aug 09 08:10:15 PM PDT 24 | 643949526 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.4136818110 | Aug 09 07:57:49 PM PDT 24 | Aug 09 07:58:32 PM PDT 24 | 1325062249 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/24.xbar_stress_all.2871975119 | Aug 09 08:00:50 PM PDT 24 | Aug 09 08:10:04 PM PDT 24 | 14842353849 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.370136413 | Aug 09 08:10:52 PM PDT 24 | Aug 09 08:14:46 PM PDT 24 | 7680033738 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.4285436432 | Aug 09 08:02:17 PM PDT 24 | Aug 09 08:03:36 PM PDT 24 | 988984097 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.4175376115 | Aug 09 08:06:14 PM PDT 24 | Aug 09 08:15:14 PM PDT 24 | 9785447320 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.840321353 | Aug 09 08:10:53 PM PDT 24 | Aug 09 08:10:59 PM PDT 24 | 39514013 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1211351976 | Aug 09 08:00:37 PM PDT 24 | Aug 09 08:10:04 PM PDT 24 | 52155305234 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.256875051 | Aug 09 08:06:56 PM PDT 24 | Aug 09 08:07:24 PM PDT 24 | 101798890 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/80.xbar_smoke.851761519 | Aug 09 08:09:02 PM PDT 24 | Aug 09 08:09:08 PM PDT 24 | 37616301 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.455915029 | Aug 09 08:04:25 PM PDT 24 | Aug 09 08:04:33 PM PDT 24 | 49175897 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.3230072513 | Aug 09 08:09:56 PM PDT 24 | Aug 09 08:11:13 PM PDT 24 | 7626441653 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/36.xbar_same_source.2616374552 | Aug 09 08:02:38 PM PDT 24 | Aug 09 08:04:00 PM PDT 24 | 2598431422 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2861830986 | Aug 09 07:57:58 PM PDT 24 | Aug 09 07:58:04 PM PDT 24 | 55032979 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/56.xbar_smoke.969069190 | Aug 09 08:05:39 PM PDT 24 | Aug 09 08:05:50 PM PDT 24 | 246943875 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.3789698031 | Aug 09 08:05:51 PM PDT 24 | Aug 09 08:07:02 PM PDT 24 | 1910519180 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.2134183084 | Aug 09 08:10:52 PM PDT 24 | Aug 09 08:11:07 PM PDT 24 | 338907849 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/21.xbar_same_source.376080663 | Aug 09 08:00:23 PM PDT 24 | Aug 09 08:00:33 PM PDT 24 | 124793240 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2367300393 | Aug 09 07:58:07 PM PDT 24 | Aug 09 07:58:13 PM PDT 24 | 45833957 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.168528492 | Aug 09 08:03:19 PM PDT 24 | Aug 09 08:33:16 PM PDT 24 | 97521536728 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/57.xbar_stress_all.3612725555 | Aug 09 08:05:58 PM PDT 24 | Aug 09 08:10:47 PM PDT 24 | 3660684767 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1466505926 | Aug 09 07:59:34 PM PDT 24 | Aug 09 08:07:40 PM PDT 24 | 2445132068 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.71994838 | Aug 09 07:59:25 PM PDT 24 | Aug 09 08:12:44 PM PDT 24 | 79409088386 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2509203092 | Aug 09 08:08:54 PM PDT 24 | Aug 09 08:11:12 PM PDT 24 | 3519035798 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/38.xbar_random.1043317288 | Aug 09 08:03:02 PM PDT 24 | Aug 09 08:03:53 PM PDT 24 | 579670471 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2487328723 | Aug 09 08:04:18 PM PDT 24 | Aug 09 08:04:46 PM PDT 24 | 272362029 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.843098889 | Aug 09 08:07:01 PM PDT 24 | Aug 09 08:07:07 PM PDT 24 | 50022380 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.802280147 | Aug 09 08:09:20 PM PDT 24 | Aug 09 08:16:47 PM PDT 24 | 8817277887 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3088916932 | Aug 09 08:02:39 PM PDT 24 | Aug 09 08:21:05 PM PDT 24 | 62010930728 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.3474194673 | Aug 09 08:10:57 PM PDT 24 | Aug 09 08:11:24 PM PDT 24 | 806793553 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.208126885 | Aug 09 08:02:17 PM PDT 24 | Aug 09 08:07:54 PM PDT 24 | 887192138 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1763318302 | Aug 09 07:58:00 PM PDT 24 | Aug 09 07:58:51 PM PDT 24 | 388684959 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.642993228 | Aug 09 08:02:14 PM PDT 24 | Aug 09 08:20:38 PM PDT 24 | 60642737781 ps | ||
| T640 | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1555452070 | Aug 09 08:07:58 PM PDT 24 | Aug 09 08:16:14 PM PDT 24 | 6248764788 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.1180482827 | Aug 09 08:05:12 PM PDT 24 | Aug 09 08:06:52 PM PDT 24 | 9783657508 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/9.xbar_same_source.1032973485 | Aug 09 07:58:05 PM PDT 24 | Aug 09 07:58:46 PM PDT 24 | 1435282075 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/12.xbar_random.1884402456 | Aug 09 07:58:40 PM PDT 24 | Aug 09 07:59:25 PM PDT 24 | 460603827 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/27.xbar_stress_all.2598341352 | Aug 09 08:01:09 PM PDT 24 | Aug 09 08:04:47 PM PDT 24 | 6039279985 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3951591717 | Aug 09 07:57:44 PM PDT 24 | Aug 09 08:11:19 PM PDT 24 | 11612592576 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.3617770264 | Aug 09 08:05:23 PM PDT 24 | Aug 09 08:06:41 PM PDT 24 | 7813192145 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.2641771336 | Aug 09 08:09:13 PM PDT 24 | Aug 09 08:09:46 PM PDT 24 | 807421104 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.3261616334 | Aug 09 08:02:49 PM PDT 24 | Aug 09 08:03:17 PM PDT 24 | 287468810 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.2869722361 | Aug 09 07:58:04 PM PDT 24 | Aug 09 08:04:21 PM PDT 24 | 38963227348 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/34.xbar_smoke.317431758 | Aug 09 08:02:17 PM PDT 24 | Aug 09 08:02:25 PM PDT 24 | 150498549 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3409522357 | Aug 09 07:59:10 PM PDT 24 | Aug 09 08:00:46 PM PDT 24 | 9626178779 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/10.xbar_error_random.360727200 | Aug 09 07:58:14 PM PDT 24 | Aug 09 07:58:37 PM PDT 24 | 278714530 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.4043523408 | Aug 09 07:59:17 PM PDT 24 | Aug 09 08:13:46 PM PDT 24 | 55731439482 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.1132733349 | Aug 09 08:00:51 PM PDT 24 | Aug 09 08:06:32 PM PDT 24 | 19691415275 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2458654728 | Aug 09 08:05:52 PM PDT 24 | Aug 09 08:11:55 PM PDT 24 | 10285347482 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.3948420671 | Aug 09 08:07:09 PM PDT 24 | Aug 09 08:07:46 PM PDT 24 | 895214876 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1934953193 | Aug 09 07:58:18 PM PDT 24 | Aug 09 08:04:48 PM PDT 24 | 6903475140 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/80.xbar_same_source.739729192 | Aug 09 08:09:08 PM PDT 24 | Aug 09 08:09:52 PM PDT 24 | 1519324854 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2407687466 | Aug 09 08:06:00 PM PDT 24 | Aug 09 08:10:00 PM PDT 24 | 793999101 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/49.xbar_stress_all.3393364773 | Aug 09 08:04:45 PM PDT 24 | Aug 09 08:19:39 PM PDT 24 | 22380929027 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/23.xbar_smoke.332904621 | Aug 09 08:00:30 PM PDT 24 | Aug 09 08:00:40 PM PDT 24 | 223147209 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/84.xbar_smoke.1876545148 | Aug 09 08:09:48 PM PDT 24 | Aug 09 08:09:56 PM PDT 24 | 203607548 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.3629200355 | Aug 09 07:59:29 PM PDT 24 | Aug 09 07:59:56 PM PDT 24 | 637077269 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1972149733 | Aug 09 08:02:17 PM PDT 24 | Aug 09 08:07:48 PM PDT 24 | 7349064572 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3185537836 | Aug 09 08:01:52 PM PDT 24 | Aug 09 08:02:09 PM PDT 24 | 373429779 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1422166242 | Aug 09 07:58:26 PM PDT 24 | Aug 09 08:03:59 PM PDT 24 | 20675156043 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.4164565605 | Aug 09 08:04:51 PM PDT 24 | Aug 09 08:05:49 PM PDT 24 | 3595476188 ps | ||
| T2932 | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.90960554 | Aug 09 08:12:09 PM PDT 24 | Aug 09 08:13:07 PM PDT 24 | 203480919 ps | ||
| T2933 | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.114599935 | Aug 09 08:02:17 PM PDT 24 | Aug 09 08:12:04 PM PDT 24 | 34127922345 ps | ||
| T2934 | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3139896077 | Aug 09 08:05:54 PM PDT 24 | Aug 09 08:12:22 PM PDT 24 | 6573872952 ps | ||
| T2935 | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.830762771 | Aug 09 07:59:55 PM PDT 24 | Aug 09 08:00:36 PM PDT 24 | 969775740 ps | ||
| T27 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.210577794 | Aug 09 07:57:28 PM PDT 24 | Aug 09 08:01:31 PM PDT 24 | 5049151128 ps | ||
| T28 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2678158112 | Aug 09 07:57:28 PM PDT 24 | Aug 09 08:01:16 PM PDT 24 | 3823052766 ps | ||
| T29 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1914711186 | Aug 09 07:57:27 PM PDT 24 | Aug 09 08:01:27 PM PDT 24 | 3966143481 ps | ||
| T193 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1960929871 | Aug 09 07:57:27 PM PDT 24 | Aug 09 08:03:10 PM PDT 24 | 4976513276 ps | ||
| T194 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3652435712 | Aug 09 07:57:32 PM PDT 24 | Aug 09 08:00:54 PM PDT 24 | 4296296873 ps | ||
| T195 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2595356250 | Aug 09 07:57:31 PM PDT 24 | Aug 09 08:01:51 PM PDT 24 | 4790551840 ps | ||
| T196 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2552194750 | Aug 09 07:57:30 PM PDT 24 | Aug 09 08:00:04 PM PDT 24 | 4188772340 ps | ||
| T201 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.756915525 | Aug 09 07:57:26 PM PDT 24 | Aug 09 08:01:18 PM PDT 24 | 4123780694 ps | ||
| T202 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3141855507 | Aug 09 07:57:28 PM PDT 24 | Aug 09 08:01:38 PM PDT 24 | 5258844045 ps | ||
| T197 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3904754670 | Aug 09 07:57:29 PM PDT 24 | Aug 09 08:01:02 PM PDT 24 | 3902336320 ps |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3479084001 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 11928900520 ps |
| CPU time | 1322.55 seconds |
| Started | Aug 09 08:40:06 PM PDT 24 |
| Finished | Aug 09 09:02:09 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-597b3617-5f2b-4eb3-ace7-4fe7077a2e81 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479084001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.3479084001 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.707397891 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 14516069379 ps |
| CPU time | 1756.8 seconds |
| Started | Aug 09 07:59:47 PM PDT 24 |
| Finished | Aug 09 08:29:05 PM PDT 24 |
| Peak memory | 593544 kb |
| Host | smart-e2339285-3378-44f0-926f-bf58576dcc59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707397891 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.chip_same_csr_outstanding.707397891 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.3586267302 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5934551100 ps |
| CPU time | 1165.27 seconds |
| Started | Aug 09 08:23:03 PM PDT 24 |
| Finished | Aug 09 08:42:28 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-7e4ea032-e0a2-4237-a8da-cce6649dfb93 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586267302 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.3586267302 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2175210043 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 100932782014 ps |
| CPU time | 2002.61 seconds |
| Started | Aug 09 08:06:47 PM PDT 24 |
| Finished | Aug 09 08:40:10 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-e73af03f-ce39-4599-9187-c03e07987adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175210043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.2175210043 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1080734244 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 133296182818 ps |
| CPU time | 2204.66 seconds |
| Started | Aug 09 08:05:28 PM PDT 24 |
| Finished | Aug 09 08:42:13 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-31b5a702-5970-468e-b2e2-769938a36058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080734244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.1080734244 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.210577794 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5049151128 ps |
| CPU time | 243.15 seconds |
| Started | Aug 09 07:57:28 PM PDT 24 |
| Finished | Aug 09 08:01:31 PM PDT 24 |
| Peak memory | 657204 kb |
| Host | smart-3bd2db63-174d-4b8d-afd1-5e017bcc2447 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210577794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 3.chip_padctrl_attributes.210577794 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.234914223 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 152157403346 ps |
| CPU time | 2705.97 seconds |
| Started | Aug 09 08:07:59 PM PDT 24 |
| Finished | Aug 09 08:53:05 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-1c104d94-bcf9-4148-9282-9cc705299290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234914223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_d evice_slow_rsp.234914223 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.2444336659 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1665299777 ps |
| CPU time | 128.5 seconds |
| Started | Aug 09 08:07:22 PM PDT 24 |
| Finished | Aug 09 08:09:31 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-f2dc4cb9-ea82-40b2-abf1-917fc8284da9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444336659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.2444336659 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_virus.920903027 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5940250968 ps |
| CPU time | 1397.8 seconds |
| Started | Aug 09 08:38:08 PM PDT 24 |
| Finished | Aug 09 09:01:26 PM PDT 24 |
| Peak memory | 624880 kb |
| Host | smart-2cb3ac12-d7fc-48eb-8696-53fd4554cd9a |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=920903027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.920903027 |
| Directory | /workspace/1.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3443806527 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 7188820829 ps |
| CPU time | 1046.52 seconds |
| Started | Aug 09 08:33:10 PM PDT 24 |
| Finished | Aug 09 08:50:36 PM PDT 24 |
| Peak memory | 618000 kb |
| Host | smart-7f84d32c-492e-4448-b100-df2c5d31505e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3443806527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3443806527 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1303466581 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3560171940 ps |
| CPU time | 357.83 seconds |
| Started | Aug 09 08:35:57 PM PDT 24 |
| Finished | Aug 09 08:41:55 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-67e5c9a0-16e1-4e46-a734-9ca23c528c14 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303 466581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.1303466581 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2796982861 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 127453837674 ps |
| CPU time | 2188.8 seconds |
| Started | Aug 09 08:01:43 PM PDT 24 |
| Finished | Aug 09 08:38:12 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-261341d2-0c43-4ec1-9e6d-e31f36101817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796982861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.2796982861 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2684673292 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 9262470706 ps |
| CPU time | 1052.46 seconds |
| Started | Aug 09 08:37:18 PM PDT 24 |
| Finished | Aug 09 08:54:51 PM PDT 24 |
| Peak memory | 620212 kb |
| Host | smart-f1e4f3f2-917a-41f4-b184-87c5bace26f1 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684673292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.2684673292 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2620075579 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 20974559024 ps |
| CPU time | 1678.49 seconds |
| Started | Aug 09 08:41:21 PM PDT 24 |
| Finished | Aug 09 09:09:20 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-e650934f-3ded-4721-8d6e-3cfc9e1d9c39 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2620075579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2620075579 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3402733181 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3017315048 ps |
| CPU time | 305.5 seconds |
| Started | Aug 09 08:21:37 PM PDT 24 |
| Finished | Aug 09 08:26:43 PM PDT 24 |
| Peak memory | 608512 kb |
| Host | smart-aee8e1a2-0fa8-4d1a-ace9-0241e98ad123 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3402733181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.3402733181 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.2857229793 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5009944760 ps |
| CPU time | 621.98 seconds |
| Started | Aug 09 08:52:51 PM PDT 24 |
| Finished | Aug 09 09:03:13 PM PDT 24 |
| Peak memory | 619948 kb |
| Host | smart-1ec1f025-09a4-42b0-84f8-69fedb031418 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2857229793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.2857229793 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.3338165857 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 51409769714 ps |
| CPU time | 911.59 seconds |
| Started | Aug 09 07:58:07 PM PDT 24 |
| Finished | Aug 09 08:13:19 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-c243e5d7-e68d-4722-b0ab-87397a03fe01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338165857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.3338165857 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1190652912 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 10523240720 ps |
| CPU time | 773.08 seconds |
| Started | Aug 09 07:57:56 PM PDT 24 |
| Finished | Aug 09 08:10:49 PM PDT 24 |
| Peak memory | 653156 kb |
| Host | smart-49e36738-ac1c-42b1-8543-2991a166ad49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190652912 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.1190652912 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.101501220 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4166128618 ps |
| CPU time | 801.43 seconds |
| Started | Aug 09 08:32:47 PM PDT 24 |
| Finished | Aug 09 08:46:09 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-0672b691-8271-4668-b698-b7299ca96060 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101501220 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_20.101501220 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2869413981 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2747638906 ps |
| CPU time | 185.93 seconds |
| Started | Aug 09 08:09:32 PM PDT 24 |
| Finished | Aug 09 08:12:38 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-05479ff7-3c73-4bd3-96f5-e6af37a96fef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869413981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.2869413981 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1839984396 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 24447022926 ps |
| CPU time | 6392.13 seconds |
| Started | Aug 09 08:29:09 PM PDT 24 |
| Finished | Aug 09 10:15:42 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-2c94cef0-bde6-4c44-a5ac-2ec7eb87cc9c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1839984396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1839984396 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2916857462 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 7431239016 ps |
| CPU time | 1411.28 seconds |
| Started | Aug 09 08:41:23 PM PDT 24 |
| Finished | Aug 09 09:04:54 PM PDT 24 |
| Peak memory | 611096 kb |
| Host | smart-0dd2e3f4-db45-4eae-8882-47c6eebab8b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291685 7462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2916857462 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2114507391 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 147551496286 ps |
| CPU time | 2637.89 seconds |
| Started | Aug 09 08:07:58 PM PDT 24 |
| Finished | Aug 09 08:51:56 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-97c3cbf0-533a-499f-af1e-3b8911552e0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114507391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.2114507391 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.1968980155 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 19406966250 ps |
| CPU time | 2515.21 seconds |
| Started | Aug 09 08:37:38 PM PDT 24 |
| Finished | Aug 09 09:19:34 PM PDT 24 |
| Peak memory | 613528 kb |
| Host | smart-fa314ee4-5335-40e2-83bd-a24441ca040f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968980155 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.1968980155 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.3021835665 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 3893963160 ps |
| CPU time | 641.75 seconds |
| Started | Aug 09 08:21:52 PM PDT 24 |
| Finished | Aug 09 08:32:35 PM PDT 24 |
| Peak memory | 609100 kb |
| Host | smart-acfe12e8-191a-4ca3-b2fc-8d57384f241c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021835665 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.3021835665 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.1215986847 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4709406520 ps |
| CPU time | 393.76 seconds |
| Started | Aug 09 07:57:50 PM PDT 24 |
| Finished | Aug 09 08:04:24 PM PDT 24 |
| Peak memory | 598868 kb |
| Host | smart-3753362e-2862-4b1a-9704-d8c49faec401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215986847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.1215986847 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.1889302964 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3607507434 ps |
| CPU time | 556.98 seconds |
| Started | Aug 09 08:38:40 PM PDT 24 |
| Finished | Aug 09 08:47:57 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-0c379028-c8ca-4f68-9bf8-15bcfe430dad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889302964 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.1889302964 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.146134904 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1179778981 ps |
| CPU time | 93.67 seconds |
| Started | Aug 09 08:03:36 PM PDT 24 |
| Finished | Aug 09 08:05:10 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-c4e643fa-cfa5-4e83-85d2-871ec8454ceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146134904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device. 146134904 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.2152176491 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11038787240 ps |
| CPU time | 1025.1 seconds |
| Started | Aug 09 08:24:27 PM PDT 24 |
| Finished | Aug 09 08:41:34 PM PDT 24 |
| Peak memory | 607900 kb |
| Host | smart-30792b1c-f9c1-465b-b141-2b3fef79f4a5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152176491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.2152176491 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2265927495 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 5566884576 ps |
| CPU time | 1310.7 seconds |
| Started | Aug 09 08:31:50 PM PDT 24 |
| Finished | Aug 09 08:53:41 PM PDT 24 |
| Peak memory | 609088 kb |
| Host | smart-fbcf2444-258b-443a-86c7-2ff3e3c5c532 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2265927495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.2265927495 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.743180332 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 48889369240 ps |
| CPU time | 5289.73 seconds |
| Started | Aug 09 08:26:37 PM PDT 24 |
| Finished | Aug 09 09:54:47 PM PDT 24 |
| Peak memory | 620492 kb |
| Host | smart-4a236832-b0f7-4a65-a0df-fd427bd0fb67 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743180332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_dev.743180332 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3492165550 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 5359018048 ps |
| CPU time | 389.56 seconds |
| Started | Aug 09 08:22:56 PM PDT 24 |
| Finished | Aug 09 08:29:26 PM PDT 24 |
| Peak memory | 608836 kb |
| Host | smart-041f9444-a466-421d-95fa-cac61f61f25d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34921655 50 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3492165550 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2123558002 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2851775246 ps |
| CPU time | 271.72 seconds |
| Started | Aug 09 08:27:14 PM PDT 24 |
| Finished | Aug 09 08:31:46 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-ed6b0e9d-2400-4feb-9175-64c5ff5af33b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123 558002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.2123558002 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.1900915217 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3306783960 ps |
| CPU time | 338.9 seconds |
| Started | Aug 09 08:21:27 PM PDT 24 |
| Finished | Aug 09 08:27:07 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-8a1e0fdb-31ae-4afe-a463-3b31e13e35e5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900915217 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.1900915217 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.782771365 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 6620075043 ps |
| CPU time | 67.32 seconds |
| Started | Aug 09 08:06:13 PM PDT 24 |
| Finished | Aug 09 08:07:20 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-3f3806d7-882c-4594-be1f-0d2b511cb196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782771365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.782771365 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.2912372213 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 4627412590 ps |
| CPU time | 337.25 seconds |
| Started | Aug 09 07:59:52 PM PDT 24 |
| Finished | Aug 09 08:05:29 PM PDT 24 |
| Peak memory | 600900 kb |
| Host | smart-1defebcb-9ae9-4676-b9b0-03ac3b33ab0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912372213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.2912372213 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2419853137 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 21113705560 ps |
| CPU time | 1742.82 seconds |
| Started | Aug 09 08:39:05 PM PDT 24 |
| Finished | Aug 09 09:08:09 PM PDT 24 |
| Peak memory | 614684 kb |
| Host | smart-cd49f42d-ac37-4146-ae6c-be36fabf58cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24198531 37 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.2419853137 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3606653996 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5042789464 ps |
| CPU time | 585.08 seconds |
| Started | Aug 09 08:21:52 PM PDT 24 |
| Finished | Aug 09 08:31:38 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-af700787-2903-471c-a7b0-faee56d4fc05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606653996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.3606653996 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3869773043 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2658709512 ps |
| CPU time | 230.56 seconds |
| Started | Aug 09 08:19:00 PM PDT 24 |
| Finished | Aug 09 08:22:51 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-f0002cd5-c8d5-40ad-8dff-eb078b821b1b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869 773043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.3869773043 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.157770217 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 43800812448 ps |
| CPU time | 4953.48 seconds |
| Started | Aug 09 08:24:11 PM PDT 24 |
| Finished | Aug 09 09:46:45 PM PDT 24 |
| Peak memory | 621912 kb |
| Host | smart-ea2260d6-bb61-4456-a494-819e659ae6c8 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=157770217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.157770217 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.2026639130 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 13549515686 ps |
| CPU time | 466.66 seconds |
| Started | Aug 09 08:08:20 PM PDT 24 |
| Finished | Aug 09 08:16:06 PM PDT 24 |
| Peak memory | 577100 kb |
| Host | smart-e1a608b9-9fa9-4963-b7ce-a9865b76ffba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026639130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2026639130 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.3252414729 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 61206572 ps |
| CPU time | 7.81 seconds |
| Started | Aug 09 08:09:56 PM PDT 24 |
| Finished | Aug 09 08:10:04 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-bc604055-2179-4b3d-b2f9-bfe7e58ba58e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252414729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .3252414729 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.71512892 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 5552874824 ps |
| CPU time | 1054.92 seconds |
| Started | Aug 09 08:44:31 PM PDT 24 |
| Finished | Aug 09 09:02:07 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-69f6f683-abdf-4ad3-ad06-f2bc1bfb387e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=71512892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.71512892 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.674936821 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2817820905 ps |
| CPU time | 220.28 seconds |
| Started | Aug 09 08:20:14 PM PDT 24 |
| Finished | Aug 09 08:23:54 PM PDT 24 |
| Peak memory | 618576 kb |
| Host | smart-1e44df80-3fe6-4eab-b677-352b1ef2b526 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674936821 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.674936821 |
| Directory | /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.1755841693 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 30250354916 ps |
| CPU time | 4204.92 seconds |
| Started | Aug 09 07:57:48 PM PDT 24 |
| Finished | Aug 09 09:07:54 PM PDT 24 |
| Peak memory | 593568 kb |
| Host | smart-92599d22-06ca-4907-a3b0-b754fd2ca439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755841693 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.1755841693 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.883656162 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3897724672 ps |
| CPU time | 585.29 seconds |
| Started | Aug 09 08:46:16 PM PDT 24 |
| Finished | Aug 09 08:56:01 PM PDT 24 |
| Peak memory | 623684 kb |
| Host | smart-a805ff53-b4ae-4b4e-9ec0-6f6b751a0818 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883656162 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.883656162 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.3997580795 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 4964844566 ps |
| CPU time | 689.64 seconds |
| Started | Aug 09 08:56:42 PM PDT 24 |
| Finished | Aug 09 09:08:12 PM PDT 24 |
| Peak memory | 650472 kb |
| Host | smart-b7208e8e-6e27-4c84-843e-0d5537aa436f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3997580795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.3997580795 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.188747557 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1573671038 ps |
| CPU time | 331.48 seconds |
| Started | Aug 09 08:01:59 PM PDT 24 |
| Finished | Aug 09 08:07:31 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-d8bc08ab-50fc-4a98-90b0-7e8110ef4988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188747557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.188747557 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2593967938 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3407064362 ps |
| CPU time | 143.51 seconds |
| Started | Aug 09 08:21:38 PM PDT 24 |
| Finished | Aug 09 08:24:02 PM PDT 24 |
| Peak memory | 619828 kb |
| Host | smart-ab6c3cdc-b154-40af-9f46-b095534e5c33 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25939679 38 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2593967938 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.1864346936 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 3860267400 ps |
| CPU time | 255.57 seconds |
| Started | Aug 09 07:58:25 PM PDT 24 |
| Finished | Aug 09 08:02:40 PM PDT 24 |
| Peak memory | 598888 kb |
| Host | smart-a03eca2f-f41b-4146-9af5-b7ed7a6c9df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864346936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.1864346936 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.2060511703 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 5595901728 ps |
| CPU time | 630.73 seconds |
| Started | Aug 09 08:26:41 PM PDT 24 |
| Finished | Aug 09 08:37:12 PM PDT 24 |
| Peak memory | 649856 kb |
| Host | smart-4bb1fb07-bc05-49c7-ae15-e81b28c4e65f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2060511703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.2060511703 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.4243920124 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 5984363644 ps |
| CPU time | 667.95 seconds |
| Started | Aug 09 08:55:12 PM PDT 24 |
| Finished | Aug 09 09:06:20 PM PDT 24 |
| Peak memory | 650096 kb |
| Host | smart-cdd08d8b-80c9-4f1d-bb92-b7bbe8f0b62c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4243920124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.4243920124 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.663714871 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 5887361304 ps |
| CPU time | 589.71 seconds |
| Started | Aug 09 08:49:56 PM PDT 24 |
| Finished | Aug 09 08:59:46 PM PDT 24 |
| Peak memory | 650300 kb |
| Host | smart-8941879c-c748-476d-b3a3-a2ce8f02d0df |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 663714871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.663714871 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.2302711844 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 4751189532 ps |
| CPU time | 626.87 seconds |
| Started | Aug 09 08:52:12 PM PDT 24 |
| Finished | Aug 09 09:02:39 PM PDT 24 |
| Peak memory | 650704 kb |
| Host | smart-a92e7b77-f482-4433-a064-45fcd493c7bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2302711844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2302711844 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.67559417 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 6862624204 ps |
| CPU time | 701.81 seconds |
| Started | Aug 09 08:40:01 PM PDT 24 |
| Finished | Aug 09 08:51:43 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-050f7eef-65da-44b0-ace0-37d7f84be0a1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67559417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc _hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng _lc_hw_debug_en_test.67559417 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.54095477 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4647485802 ps |
| CPU time | 522.43 seconds |
| Started | Aug 09 08:21:01 PM PDT 24 |
| Finished | Aug 09 08:29:43 PM PDT 24 |
| Peak memory | 633004 kb |
| Host | smart-97f85ce8-a855-42ad-9ac1-0928cda7d99a |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54095477 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.54095477 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.964876469 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3794690880 ps |
| CPU time | 300.06 seconds |
| Started | Aug 09 08:36:33 PM PDT 24 |
| Finished | Aug 09 08:41:33 PM PDT 24 |
| Peak memory | 609068 kb |
| Host | smart-d07c474d-8ec0-487b-9512-99b9d05eecb8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964876469 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.964876469 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.641920635 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 5494590040 ps |
| CPU time | 1182.64 seconds |
| Started | Aug 09 08:30:24 PM PDT 24 |
| Finished | Aug 09 08:50:07 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-4dd86d06-24ff-426a-8a5d-a7fc2b80e160 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641920635 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_plic_all_irqs_0.641920635 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.2456931153 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3113029949 ps |
| CPU time | 114.25 seconds |
| Started | Aug 09 08:08:48 PM PDT 24 |
| Finished | Aug 09 08:10:43 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-98432539-1b1b-4b1a-9dbb-95b8ced78381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456931153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.2456931153 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2912216585 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 6405383722 ps |
| CPU time | 382.21 seconds |
| Started | Aug 09 07:57:42 PM PDT 24 |
| Finished | Aug 09 08:04:04 PM PDT 24 |
| Peak memory | 664576 kb |
| Host | smart-c2536d2e-49de-4fa3-a0c2-c046e1044a93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912216585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.2912216585 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.720405775 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 3748126816 ps |
| CPU time | 321.55 seconds |
| Started | Aug 09 08:28:15 PM PDT 24 |
| Finished | Aug 09 08:33:37 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-9fdf7190-2891-4995-ba14-5d3e8e31f6ff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72 0405775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.720405775 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1043009570 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 6468235592 ps |
| CPU time | 697.08 seconds |
| Started | Aug 09 08:22:00 PM PDT 24 |
| Finished | Aug 09 08:33:37 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-66bce31d-b13c-4502-85ff-c6010b1496fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10430095 70 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.1043009570 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.1956490630 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3404594071 ps |
| CPU time | 138.08 seconds |
| Started | Aug 09 08:08:08 PM PDT 24 |
| Finished | Aug 09 08:10:26 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-fccc1d05-1a48-4c76-9828-123ad6bd99c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956490630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .1956490630 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1221370899 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 6089330116 ps |
| CPU time | 384.85 seconds |
| Started | Aug 09 08:26:23 PM PDT 24 |
| Finished | Aug 09 08:32:50 PM PDT 24 |
| Peak memory | 610872 kb |
| Host | smart-4552b032-9acd-43e6-9abe-8e0c27a888a3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221370899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1221370899 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3116394568 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 6633052654 ps |
| CPU time | 491.97 seconds |
| Started | Aug 09 08:36:03 PM PDT 24 |
| Finished | Aug 09 08:44:16 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-d87a0ef3-c505-4cdf-9e18-7465f86e9b20 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116394568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3116394568 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3734272177 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5762543896 ps |
| CPU time | 421.36 seconds |
| Started | Aug 09 08:19:34 PM PDT 24 |
| Finished | Aug 09 08:26:36 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-05076137-ad03-4f63-92b7-8e2037f6a302 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734272177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.3734272177 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.449700493 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 79023938988 ps |
| CPU time | 13117.1 seconds |
| Started | Aug 09 08:35:54 PM PDT 24 |
| Finished | Aug 10 12:14:32 AM PDT 24 |
| Peak memory | 634812 kb |
| Host | smart-d8ba4c73-6212-4967-aac2-92d329ad2f33 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=449700493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.449700493 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3412161804 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 5771733821 ps |
| CPU time | 485.52 seconds |
| Started | Aug 09 08:10:03 PM PDT 24 |
| Finished | Aug 09 08:18:08 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-8c02b0af-ca21-4b42-9c0c-6e4ff8ef192c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412161804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.3412161804 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3127782077 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3520808448 ps |
| CPU time | 521.72 seconds |
| Started | Aug 09 08:22:37 PM PDT 24 |
| Finished | Aug 09 08:31:19 PM PDT 24 |
| Peak memory | 609556 kb |
| Host | smart-a96cad64-a820-480d-af6d-63c6cbd0b9ab |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312778 2077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3127782077 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.462596027 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 7190241506 ps |
| CPU time | 655.7 seconds |
| Started | Aug 09 08:22:10 PM PDT 24 |
| Finished | Aug 09 08:33:06 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-b910fc4c-fd30-4229-b75d-b79c1b2b8525 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462596027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_ sram_ret_contents_scramble.462596027 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.2637379684 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 4070672744 ps |
| CPU time | 327.03 seconds |
| Started | Aug 09 07:58:27 PM PDT 24 |
| Finished | Aug 09 08:03:54 PM PDT 24 |
| Peak memory | 599180 kb |
| Host | smart-8e323f8d-97fd-4a1f-a347-e56151243790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637379684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.2637379684 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2595058024 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 44533808680 ps |
| CPU time | 5185.37 seconds |
| Started | Aug 09 08:38:07 PM PDT 24 |
| Finished | Aug 09 10:04:35 PM PDT 24 |
| Peak memory | 622040 kb |
| Host | smart-665c3e9c-c303-412e-8706-fc1728141833 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2595058024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.2595058024 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.726548065 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 5250751593 ps |
| CPU time | 317.31 seconds |
| Started | Aug 09 08:09:52 PM PDT 24 |
| Finished | Aug 09 08:15:09 PM PDT 24 |
| Peak memory | 577324 kb |
| Host | smart-f4c990f0-92f3-4b5a-8c46-2ab032512963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726548065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_ with_rand_reset.726548065 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.392502563 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5169261100 ps |
| CPU time | 750.99 seconds |
| Started | Aug 09 08:41:14 PM PDT 24 |
| Finished | Aug 09 08:53:45 PM PDT 24 |
| Peak memory | 608616 kb |
| Host | smart-0f2a4d9e-765c-4e33-8e8a-544afceb36b6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392502563 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_20.392502563 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3734902907 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 697317365 ps |
| CPU time | 250.23 seconds |
| Started | Aug 09 08:08:29 PM PDT 24 |
| Finished | Aug 09 08:12:40 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-e72497d1-dbf5-48a7-acd5-6a545d934055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734902907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.3734902907 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2936025652 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 108188070363 ps |
| CPU time | 2065.04 seconds |
| Started | Aug 09 08:10:17 PM PDT 24 |
| Finished | Aug 09 08:44:43 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-ce0f9b0a-0739-44f8-8d6c-9900a872812e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936025652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.2936025652 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3165822853 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 12144020281 ps |
| CPU time | 662.75 seconds |
| Started | Aug 09 07:57:57 PM PDT 24 |
| Finished | Aug 09 08:09:00 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-056418bd-3135-48bb-aa04-3cdabc988857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165822853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.3165822853 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.1930964876 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 13350382510 ps |
| CPU time | 460.54 seconds |
| Started | Aug 09 07:59:17 PM PDT 24 |
| Finished | Aug 09 08:06:58 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-d1248c9f-e95e-48cb-9c9c-f1f95111ef01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930964876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1930964876 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1228640500 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 567823872 ps |
| CPU time | 174.96 seconds |
| Started | Aug 09 07:59:49 PM PDT 24 |
| Finished | Aug 09 08:02:44 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-18cf7fc5-e8f7-4c50-8363-8139e8749c7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228640500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.1228640500 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3148726878 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 8435330057 ps |
| CPU time | 2012.1 seconds |
| Started | Aug 09 08:22:32 PM PDT 24 |
| Finished | Aug 09 08:56:06 PM PDT 24 |
| Peak memory | 624548 kb |
| Host | smart-12ff758c-9821-4360-9e09-7807f77dbd84 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148726878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.3148726878 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1985388191 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 5469521086 ps |
| CPU time | 547.42 seconds |
| Started | Aug 09 08:37:55 PM PDT 24 |
| Finished | Aug 09 08:47:03 PM PDT 24 |
| Peak memory | 616396 kb |
| Host | smart-34bda2c4-211c-42ab-b8ca-1774b2a5070e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1985388191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1985388191 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3395723628 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 3536920596 ps |
| CPU time | 455.54 seconds |
| Started | Aug 09 08:47:47 PM PDT 24 |
| Finished | Aug 09 08:55:22 PM PDT 24 |
| Peak memory | 608728 kb |
| Host | smart-875d7f3e-ef8c-4d24-81ff-6758e7877133 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33957236 28 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3395723628 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3904754670 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3902336320 ps |
| CPU time | 212.75 seconds |
| Started | Aug 09 07:57:29 PM PDT 24 |
| Finished | Aug 09 08:01:02 PM PDT 24 |
| Peak memory | 649056 kb |
| Host | smart-0604eb71-9c26-499a-b966-40c0c5799085 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904754670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.3904754670 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.4155299496 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3574437396 ps |
| CPU time | 669 seconds |
| Started | Aug 09 08:42:34 PM PDT 24 |
| Finished | Aug 09 08:53:44 PM PDT 24 |
| Peak memory | 608296 kb |
| Host | smart-e10a5140-635b-4f8b-a246-d53c8315cf34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155299496 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.4155299496 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.198646831 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5127121048 ps |
| CPU time | 640.45 seconds |
| Started | Aug 09 08:30:48 PM PDT 24 |
| Finished | Aug 09 08:41:29 PM PDT 24 |
| Peak memory | 609504 kb |
| Host | smart-c1e96238-12da-496a-8383-9930f5506bf5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19864683 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.198646831 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.487932506 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 6328869340 ps |
| CPU time | 407.72 seconds |
| Started | Aug 09 08:00:53 PM PDT 24 |
| Finished | Aug 09 08:07:40 PM PDT 24 |
| Peak memory | 577160 kb |
| Host | smart-43bd792c-2a7a-455f-9ec9-d2480dbaf70f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487932506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_reset_error.487932506 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2876339614 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 23766568892 ps |
| CPU time | 5303.18 seconds |
| Started | Aug 09 08:31:42 PM PDT 24 |
| Finished | Aug 09 10:00:06 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-43ae4631-aeed-431c-b059-a827b7001af8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2876339614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.2876339614 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.584950160 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 32614619096 ps |
| CPU time | 6633.68 seconds |
| Started | Aug 09 08:48:12 PM PDT 24 |
| Finished | Aug 09 10:38:47 PM PDT 24 |
| Peak memory | 610252 kb |
| Host | smart-49c172eb-2e68-4832-95aa-c011feb3648c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584950160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.584950160 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.3724280764 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 6312139144 ps |
| CPU time | 1076.33 seconds |
| Started | Aug 09 08:40:36 PM PDT 24 |
| Finished | Aug 09 08:58:33 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-9e68730c-5c1c-47d2-811b-343b7bf4a2e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724280764 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.3724280764 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.3835973357 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3757359182 ps |
| CPU time | 232.43 seconds |
| Started | Aug 09 07:57:38 PM PDT 24 |
| Finished | Aug 09 08:01:31 PM PDT 24 |
| Peak memory | 598904 kb |
| Host | smart-6f42b92c-ce81-4b19-b012-9fb3d1b5344d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835973357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3835973357 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3680465992 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4361365400 ps |
| CPU time | 531.76 seconds |
| Started | Aug 09 08:22:59 PM PDT 24 |
| Finished | Aug 09 08:31:51 PM PDT 24 |
| Peak memory | 619648 kb |
| Host | smart-9d25d821-1ae9-4068-8969-7f3f632ec9d3 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 680465992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.3680465992 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.736796653 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 25074142232 ps |
| CPU time | 4115 seconds |
| Started | Aug 09 08:25:57 PM PDT 24 |
| Finished | Aug 09 09:34:33 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-2983e2f8-ad7b-41a9-9a2b-21eefa1c5376 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736796653 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.736796653 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.1391372246 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4751824400 ps |
| CPU time | 755.96 seconds |
| Started | Aug 09 08:21:42 PM PDT 24 |
| Finished | Aug 09 08:34:18 PM PDT 24 |
| Peak memory | 608620 kb |
| Host | smart-1f98724e-d89f-4f3e-b8b9-3d9447fd51f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391372246 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.1391372246 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4256196980 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 4943459250 ps |
| CPU time | 882.75 seconds |
| Started | Aug 09 08:23:28 PM PDT 24 |
| Finished | Aug 09 08:38:11 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-64fbfe71-f7d7-4a28-9962-a2993fb06328 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=4256196980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4256196980 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3140147614 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 9652511094 ps |
| CPU time | 590.03 seconds |
| Started | Aug 09 08:05:39 PM PDT 24 |
| Finished | Aug 09 08:15:29 PM PDT 24 |
| Peak memory | 577356 kb |
| Host | smart-b7d6f720-85b9-4f19-9046-f117c0351e8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140147614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.3140147614 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2325690952 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 9832431008 ps |
| CPU time | 589.46 seconds |
| Started | Aug 09 07:57:57 PM PDT 24 |
| Finished | Aug 09 08:07:47 PM PDT 24 |
| Peak memory | 577152 kb |
| Host | smart-48d99829-3dd0-4a16-8443-1b1654674317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325690952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.2325690952 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1709819753 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 46607844833 ps |
| CPU time | 6111.86 seconds |
| Started | Aug 09 08:20:24 PM PDT 24 |
| Finished | Aug 09 10:02:17 PM PDT 24 |
| Peak memory | 620476 kb |
| Host | smart-694cf1ec-1796-4832-a7ca-a5d54151088f |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709819753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.1709819753 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1662965163 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2381496052 ps |
| CPU time | 95.24 seconds |
| Started | Aug 09 08:25:26 PM PDT 24 |
| Finished | Aug 09 08:27:02 PM PDT 24 |
| Peak memory | 622776 kb |
| Host | smart-3683ee82-1d9b-4f61-b738-03a4d53cdd47 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662965163 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.1662965163 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.2077736524 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 3597944070 ps |
| CPU time | 244.16 seconds |
| Started | Aug 09 07:59:15 PM PDT 24 |
| Finished | Aug 09 08:03:20 PM PDT 24 |
| Peak memory | 603924 kb |
| Host | smart-d52d15d0-0b08-443c-a980-3859cc289990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077736524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.2077736524 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.483711366 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 4161296976 ps |
| CPU time | 642.04 seconds |
| Started | Aug 09 08:22:01 PM PDT 24 |
| Finished | Aug 09 08:32:44 PM PDT 24 |
| Peak memory | 611916 kb |
| Host | smart-b9df4696-afd2-4e20-b621-24f198a6939c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483711366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.483711366 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2243496705 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 534352508 ps |
| CPU time | 174.76 seconds |
| Started | Aug 09 08:10:58 PM PDT 24 |
| Finished | Aug 09 08:13:53 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-1d35e296-c57d-44a9-a2aa-6c0a21a55cee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243496705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.2243496705 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3926043285 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2269226539 ps |
| CPU time | 116.16 seconds |
| Started | Aug 09 08:26:19 PM PDT 24 |
| Finished | Aug 09 08:28:16 PM PDT 24 |
| Peak memory | 622832 kb |
| Host | smart-f773702a-d7a5-45c1-8daa-9b224598f4f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926043285 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.3926043285 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.3263184190 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 95984600269 ps |
| CPU time | 1058.37 seconds |
| Started | Aug 09 08:01:15 PM PDT 24 |
| Finished | Aug 09 08:18:54 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-01d58db8-21c3-4d50-97ad-922967632e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263184190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3263184190 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.3308477119 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3383063800 ps |
| CPU time | 443.27 seconds |
| Started | Aug 09 08:20:39 PM PDT 24 |
| Finished | Aug 09 08:28:03 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-b95d5596-e2c5-4eaf-93fa-a5250b1515f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308477119 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.3308477119 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2789397436 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4576406400 ps |
| CPU time | 474.58 seconds |
| Started | Aug 09 08:20:09 PM PDT 24 |
| Finished | Aug 09 08:28:04 PM PDT 24 |
| Peak memory | 623980 kb |
| Host | smart-ce4dd74e-24ef-4204-ad01-f71695440cf8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789397436 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2789397436 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.4268286043 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 10364665887 ps |
| CPU time | 2276.81 seconds |
| Started | Aug 09 08:25:27 PM PDT 24 |
| Finished | Aug 09 09:03:25 PM PDT 24 |
| Peak memory | 624420 kb |
| Host | smart-5b277676-9ac2-4098-af1a-3a20d05d2f27 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42682 86043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.4268286043 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2016535055 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 4192439024 ps |
| CPU time | 680.54 seconds |
| Started | Aug 09 08:11:52 PM PDT 24 |
| Finished | Aug 09 08:23:13 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-90c8834f-f603-49a0-a53b-2140719daac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016535055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.2016535055 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.1115485953 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 5628961056 ps |
| CPU time | 614.16 seconds |
| Started | Aug 09 08:53:10 PM PDT 24 |
| Finished | Aug 09 09:03:24 PM PDT 24 |
| Peak memory | 649924 kb |
| Host | smart-889d1e49-166c-40d2-8e35-91feea190d8f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1115485953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.1115485953 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2732611700 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 42453391024 ps |
| CPU time | 4691.72 seconds |
| Started | Aug 09 08:25:02 PM PDT 24 |
| Finished | Aug 09 09:43:15 PM PDT 24 |
| Peak memory | 621072 kb |
| Host | smart-c2f30ef4-9f05-4923-8707-c765dfea5e32 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2732611700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.2732611700 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.248112531 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9020750940 ps |
| CPU time | 2051.78 seconds |
| Started | Aug 09 08:21:32 PM PDT 24 |
| Finished | Aug 09 08:55:44 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-bf8a478b-6c32-4831-ba50-f1b0eee8d175 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24811 2531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.248112531 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.613982097 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 7796449882 ps |
| CPU time | 305.24 seconds |
| Started | Aug 09 08:06:01 PM PDT 24 |
| Finished | Aug 09 08:11:07 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-861a1dc0-763c-4bef-8f8a-458534fd6e20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613982097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.613982097 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1895519956 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3136905968 ps |
| CPU time | 457.52 seconds |
| Started | Aug 09 08:30:18 PM PDT 24 |
| Finished | Aug 09 08:37:57 PM PDT 24 |
| Peak memory | 609412 kb |
| Host | smart-a11af387-dc88-4a10-a163-ac53c40963e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895519956 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.1895519956 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2126647280 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 5848978218 ps |
| CPU time | 311.18 seconds |
| Started | Aug 09 07:57:38 PM PDT 24 |
| Finished | Aug 09 08:02:49 PM PDT 24 |
| Peak memory | 661160 kb |
| Host | smart-8950b9e3-b763-41c6-8633-ae07bbf9471c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126647280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.2126647280 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.944804777 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2971264784 ps |
| CPU time | 307.95 seconds |
| Started | Aug 09 08:21:32 PM PDT 24 |
| Finished | Aug 09 08:26:40 PM PDT 24 |
| Peak memory | 609096 kb |
| Host | smart-9a6b53dc-dec8-4f21-a383-19e4baec5a25 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944804777 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_plic_sw_irq.944804777 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.3555069489 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3957330569 ps |
| CPU time | 224.56 seconds |
| Started | Aug 09 08:00:13 PM PDT 24 |
| Finished | Aug 09 08:03:58 PM PDT 24 |
| Peak memory | 598940 kb |
| Host | smart-737ed522-b788-42c6-b169-fa551b17ad1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555069489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.3555069489 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.1411110122 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 4838457870 ps |
| CPU time | 339.44 seconds |
| Started | Aug 09 07:58:11 PM PDT 24 |
| Finished | Aug 09 08:03:50 PM PDT 24 |
| Peak memory | 604004 kb |
| Host | smart-947c8e0d-f94c-4e65-8db1-2e879ebb61a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411110122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1411110122 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2104766726 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 9248320080 ps |
| CPU time | 1733.11 seconds |
| Started | Aug 09 08:20:24 PM PDT 24 |
| Finished | Aug 09 08:49:18 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-1f700552-1612-4aa6-8a84-bf1b6c86b915 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2104766726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.2104766726 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.412695433 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2851619707 ps |
| CPU time | 340.33 seconds |
| Started | Aug 09 08:47:38 PM PDT 24 |
| Finished | Aug 09 08:53:19 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-24055edf-8971-417a-bb4b-8d396e541114 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126954 33 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.412695433 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.4183825602 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2880112527 ps |
| CPU time | 230.35 seconds |
| Started | Aug 09 07:59:01 PM PDT 24 |
| Finished | Aug 09 08:02:52 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-b6324a6b-5eb8-4975-a8c3-2144a7f95c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183825602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.4183825602 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.3340261500 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1158180054 ps |
| CPU time | 100.74 seconds |
| Started | Aug 09 08:01:19 PM PDT 24 |
| Finished | Aug 09 08:03:00 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-25d557fe-1a6a-4809-bb38-6a1bfd3372e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340261500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3340261500 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.4055112458 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 12557197162 ps |
| CPU time | 404.74 seconds |
| Started | Aug 09 08:06:13 PM PDT 24 |
| Finished | Aug 09 08:12:58 PM PDT 24 |
| Peak memory | 577076 kb |
| Host | smart-ecb02e12-5c10-468d-a3ed-5fc5d8984665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055112458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.4055112458 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1632016043 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3372226400 ps |
| CPU time | 375.87 seconds |
| Started | Aug 09 08:37:11 PM PDT 24 |
| Finished | Aug 09 08:43:27 PM PDT 24 |
| Peak memory | 608792 kb |
| Host | smart-a398e197-2dcd-4f46-a0cd-5f4c0f2d82c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632016043 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.1632016043 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.3977511421 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3802053335 ps |
| CPU time | 302.39 seconds |
| Started | Aug 09 07:58:15 PM PDT 24 |
| Finished | Aug 09 08:03:17 PM PDT 24 |
| Peak memory | 600900 kb |
| Host | smart-32aaf6c2-af11-43de-b9c4-0f9a4e9509a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977511421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.3977511421 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1463906938 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 681721818 ps |
| CPU time | 164.83 seconds |
| Started | Aug 09 07:59:01 PM PDT 24 |
| Finished | Aug 09 08:01:46 PM PDT 24 |
| Peak memory | 577096 kb |
| Host | smart-b250e5a6-c78d-47f4-973f-5f70a1ba66d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463906938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.1463906938 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1776537325 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 3635023558 ps |
| CPU time | 383.47 seconds |
| Started | Aug 09 08:22:30 PM PDT 24 |
| Finished | Aug 09 08:28:55 PM PDT 24 |
| Peak memory | 648640 kb |
| Host | smart-0916952d-c210-4fa0-92fd-424c4860d128 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776537325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.1776537325 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.142051698 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 4548951040 ps |
| CPU time | 701.58 seconds |
| Started | Aug 09 08:20:06 PM PDT 24 |
| Finished | Aug 09 08:31:48 PM PDT 24 |
| Peak memory | 649844 kb |
| Host | smart-d91b3f80-0b95-4e09-8d37-a2abe41a25da |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 142051698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.142051698 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4177434270 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 4204321260 ps |
| CPU time | 328.61 seconds |
| Started | Aug 09 08:29:11 PM PDT 24 |
| Finished | Aug 09 08:34:40 PM PDT 24 |
| Peak memory | 649192 kb |
| Host | smart-8a036be9-8f65-486d-9faa-1c0a6468add9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177434270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.4177434270 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1098377558 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 4258507408 ps |
| CPU time | 335.59 seconds |
| Started | Aug 09 08:48:38 PM PDT 24 |
| Finished | Aug 09 08:54:13 PM PDT 24 |
| Peak memory | 649176 kb |
| Host | smart-6661f7cf-9ff0-4ca6-9aa0-946da18fae79 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098377558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1098377558 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.4260193795 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 6248236152 ps |
| CPU time | 652.12 seconds |
| Started | Aug 09 08:47:44 PM PDT 24 |
| Finished | Aug 09 08:58:37 PM PDT 24 |
| Peak memory | 650304 kb |
| Host | smart-b3757285-d0a6-473b-b2db-613dd95d36a1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4260193795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.4260193795 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.794304750 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 3908372240 ps |
| CPU time | 422.27 seconds |
| Started | Aug 09 08:48:24 PM PDT 24 |
| Finished | Aug 09 08:55:27 PM PDT 24 |
| Peak memory | 649104 kb |
| Host | smart-9756de40-cd8b-43a7-9266-7b16e8a47c38 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794304750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_s w_alert_handler_lpg_sleep_mode_alerts.794304750 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3400460035 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4106464668 ps |
| CPU time | 342.29 seconds |
| Started | Aug 09 08:51:23 PM PDT 24 |
| Finished | Aug 09 08:57:06 PM PDT 24 |
| Peak memory | 647448 kb |
| Host | smart-85adf3e1-8e71-4a7d-be30-6264648369b4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400460035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3400460035 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.1152666848 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 5815690208 ps |
| CPU time | 521.44 seconds |
| Started | Aug 09 08:50:59 PM PDT 24 |
| Finished | Aug 09 08:59:40 PM PDT 24 |
| Peak memory | 649872 kb |
| Host | smart-9d2f494c-b49b-4a6e-a2a7-cc1b394aaf6a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1152666848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.1152666848 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2607218162 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 3202136808 ps |
| CPU time | 364.59 seconds |
| Started | Aug 09 08:49:23 PM PDT 24 |
| Finished | Aug 09 08:55:28 PM PDT 24 |
| Peak memory | 648984 kb |
| Host | smart-831b41bb-29fe-42d8-8477-7501f26fb0e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607218162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2607218162 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.746449849 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4077053248 ps |
| CPU time | 460.76 seconds |
| Started | Aug 09 08:49:59 PM PDT 24 |
| Finished | Aug 09 08:57:40 PM PDT 24 |
| Peak memory | 648860 kb |
| Host | smart-e78991a3-a4d8-4ffe-bb59-73f6fdfac303 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746449849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_s w_alert_handler_lpg_sleep_mode_alerts.746449849 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.2483495459 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 5130643792 ps |
| CPU time | 624.38 seconds |
| Started | Aug 09 08:49:32 PM PDT 24 |
| Finished | Aug 09 08:59:57 PM PDT 24 |
| Peak memory | 650056 kb |
| Host | smart-0b77b2d5-9070-4f1a-ad77-c456518b1d21 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2483495459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.2483495459 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1133713633 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 4530841258 ps |
| CPU time | 409.58 seconds |
| Started | Aug 09 08:49:48 PM PDT 24 |
| Finished | Aug 09 08:56:38 PM PDT 24 |
| Peak memory | 649320 kb |
| Host | smart-e6c03149-78f9-4b62-9168-dac080aa70e3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133713633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1133713633 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.3116236796 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4589576940 ps |
| CPU time | 496.35 seconds |
| Started | Aug 09 08:50:37 PM PDT 24 |
| Finished | Aug 09 08:58:54 PM PDT 24 |
| Peak memory | 649796 kb |
| Host | smart-30968e32-b3d4-4eb6-b697-6f5f003896d2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3116236796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.3116236796 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3494287354 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 4504240000 ps |
| CPU time | 325.45 seconds |
| Started | Aug 09 08:49:43 PM PDT 24 |
| Finished | Aug 09 08:55:09 PM PDT 24 |
| Peak memory | 649412 kb |
| Host | smart-28fc91a0-aa08-4100-9089-fb77191174a9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494287354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3494287354 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.2809049403 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 5440726520 ps |
| CPU time | 703.05 seconds |
| Started | Aug 09 08:49:19 PM PDT 24 |
| Finished | Aug 09 09:01:02 PM PDT 24 |
| Peak memory | 650076 kb |
| Host | smart-3fac157c-eeeb-4174-8bd3-d634fb2dd49e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2809049403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2809049403 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3405035869 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3295595456 ps |
| CPU time | 469.36 seconds |
| Started | Aug 09 08:50:05 PM PDT 24 |
| Finished | Aug 09 08:57:54 PM PDT 24 |
| Peak memory | 648720 kb |
| Host | smart-d1131177-0b0a-4a9c-af95-d9ffcc18b10a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405035869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3405035869 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.2548942893 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 4666764360 ps |
| CPU time | 697.26 seconds |
| Started | Aug 09 08:36:47 PM PDT 24 |
| Finished | Aug 09 08:48:25 PM PDT 24 |
| Peak memory | 650288 kb |
| Host | smart-3a4c5844-cf12-40bd-8ce2-040d832efead |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2548942893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.2548942893 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3743575907 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4145112498 ps |
| CPU time | 403.61 seconds |
| Started | Aug 09 08:49:41 PM PDT 24 |
| Finished | Aug 09 08:56:25 PM PDT 24 |
| Peak memory | 648972 kb |
| Host | smart-810cfd86-0731-409c-b85d-843ab349b075 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743575907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3743575907 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2458448313 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3537190760 ps |
| CPU time | 389.73 seconds |
| Started | Aug 09 08:50:44 PM PDT 24 |
| Finished | Aug 09 08:57:14 PM PDT 24 |
| Peak memory | 648632 kb |
| Host | smart-a659df73-55b6-478b-8ffd-c6c91bdbd3c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458448313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2458448313 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.3328406088 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5846988520 ps |
| CPU time | 637.13 seconds |
| Started | Aug 09 08:54:16 PM PDT 24 |
| Finished | Aug 09 09:04:53 PM PDT 24 |
| Peak memory | 650172 kb |
| Host | smart-3569780c-3205-4290-baa6-da47d814ea1b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3328406088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3328406088 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1172245340 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4122318056 ps |
| CPU time | 343.9 seconds |
| Started | Aug 09 08:49:57 PM PDT 24 |
| Finished | Aug 09 08:55:41 PM PDT 24 |
| Peak memory | 648672 kb |
| Host | smart-5464c8c5-cd2c-48ac-83a1-eac2c7717f37 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172245340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1172245340 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1293122072 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3652920132 ps |
| CPU time | 358.12 seconds |
| Started | Aug 09 08:50:13 PM PDT 24 |
| Finished | Aug 09 08:56:11 PM PDT 24 |
| Peak memory | 648716 kb |
| Host | smart-59dd79ef-ee70-41ec-bc48-163a2517d576 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293122072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1293122072 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.2192683415 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 5862909958 ps |
| CPU time | 580.9 seconds |
| Started | Aug 09 08:50:38 PM PDT 24 |
| Finished | Aug 09 09:00:20 PM PDT 24 |
| Peak memory | 650140 kb |
| Host | smart-a81e35b2-432c-4de5-878b-605b219f2abf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2192683415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.2192683415 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.355537548 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 5226782352 ps |
| CPU time | 496.69 seconds |
| Started | Aug 09 08:50:00 PM PDT 24 |
| Finished | Aug 09 08:58:17 PM PDT 24 |
| Peak memory | 650040 kb |
| Host | smart-f41e4398-70d5-4b33-9724-1ed0224e2fa2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 355537548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.355537548 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.4233354615 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 5491402694 ps |
| CPU time | 856.1 seconds |
| Started | Aug 09 08:50:27 PM PDT 24 |
| Finished | Aug 09 09:04:43 PM PDT 24 |
| Peak memory | 650220 kb |
| Host | smart-c87a4b94-a4e6-4006-8465-bb4a5bf9dcff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4233354615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.4233354615 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1963816612 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4159740428 ps |
| CPU time | 356.3 seconds |
| Started | Aug 09 08:49:56 PM PDT 24 |
| Finished | Aug 09 08:55:53 PM PDT 24 |
| Peak memory | 648780 kb |
| Host | smart-1a6f3ba6-ce0a-4557-8087-eda8c729d8e2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963816612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1963816612 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.2688442455 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 5352959192 ps |
| CPU time | 651.45 seconds |
| Started | Aug 09 08:49:31 PM PDT 24 |
| Finished | Aug 09 09:00:23 PM PDT 24 |
| Peak memory | 649816 kb |
| Host | smart-3a41baea-6e93-4581-8aea-b3e35859e3a9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2688442455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2688442455 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2935792966 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 3095404088 ps |
| CPU time | 531.57 seconds |
| Started | Aug 09 08:49:50 PM PDT 24 |
| Finished | Aug 09 08:58:42 PM PDT 24 |
| Peak memory | 649352 kb |
| Host | smart-d296db93-399f-4941-b75c-f393e7c4634a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935792966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2935792966 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.1676056577 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4483800420 ps |
| CPU time | 736.08 seconds |
| Started | Aug 09 08:54:42 PM PDT 24 |
| Finished | Aug 09 09:06:59 PM PDT 24 |
| Peak memory | 650172 kb |
| Host | smart-a213e325-8e42-4ada-8e8f-1a51af0e6d49 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1676056577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1676056577 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2058494147 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3907924568 ps |
| CPU time | 340.62 seconds |
| Started | Aug 09 08:49:48 PM PDT 24 |
| Finished | Aug 09 08:55:29 PM PDT 24 |
| Peak memory | 649000 kb |
| Host | smart-9a48aa1f-147d-40d7-972a-7aa029c60e50 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058494147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2058494147 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.1661705063 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5952709688 ps |
| CPU time | 727.28 seconds |
| Started | Aug 09 08:45:43 PM PDT 24 |
| Finished | Aug 09 08:57:51 PM PDT 24 |
| Peak memory | 650288 kb |
| Host | smart-8284e27c-6dc0-4e20-80a9-208bcac1985d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1661705063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.1661705063 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2081085688 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 4051540376 ps |
| CPU time | 472.58 seconds |
| Started | Aug 09 08:50:39 PM PDT 24 |
| Finished | Aug 09 08:58:32 PM PDT 24 |
| Peak memory | 648984 kb |
| Host | smart-fbe283ed-40e9-4fa8-a5a3-4bc44a9bdf8c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081085688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2081085688 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.1927914172 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 5414057228 ps |
| CPU time | 538.38 seconds |
| Started | Aug 09 08:50:04 PM PDT 24 |
| Finished | Aug 09 08:59:02 PM PDT 24 |
| Peak memory | 650076 kb |
| Host | smart-eb1893b5-a73f-401f-ac94-44afa74196f9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1927914172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.1927914172 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278161563 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 3831901208 ps |
| CPU time | 265.82 seconds |
| Started | Aug 09 08:51:39 PM PDT 24 |
| Finished | Aug 09 08:56:05 PM PDT 24 |
| Peak memory | 649036 kb |
| Host | smart-b535d6c5-fa42-4e99-8efc-6b029d06f3a8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278161563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2278161563 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2382837864 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 4041052116 ps |
| CPU time | 493.4 seconds |
| Started | Aug 09 08:52:03 PM PDT 24 |
| Finished | Aug 09 09:00:16 PM PDT 24 |
| Peak memory | 648748 kb |
| Host | smart-d20a6585-431f-4776-b014-f0307ee3d786 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382837864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2382837864 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3804566823 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3898392492 ps |
| CPU time | 333.53 seconds |
| Started | Aug 09 08:51:05 PM PDT 24 |
| Finished | Aug 09 08:56:39 PM PDT 24 |
| Peak memory | 648940 kb |
| Host | smart-83845c0e-5e3e-42ad-8966-c4634838b0b2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804566823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3804566823 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.1554496837 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 5255880546 ps |
| CPU time | 782.84 seconds |
| Started | Aug 09 08:51:27 PM PDT 24 |
| Finished | Aug 09 09:04:30 PM PDT 24 |
| Peak memory | 650216 kb |
| Host | smart-3fc0f4de-0ee8-4039-81f0-c5cf5d996167 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1554496837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.1554496837 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1791949946 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3912371904 ps |
| CPU time | 353.71 seconds |
| Started | Aug 09 08:46:12 PM PDT 24 |
| Finished | Aug 09 08:52:06 PM PDT 24 |
| Peak memory | 648952 kb |
| Host | smart-f151354c-b0b9-4ee0-99ae-65b980510a64 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791949946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.1791949946 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3916511464 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3917880866 ps |
| CPU time | 467.31 seconds |
| Started | Aug 09 08:51:42 PM PDT 24 |
| Finished | Aug 09 08:59:30 PM PDT 24 |
| Peak memory | 648940 kb |
| Host | smart-cdc7c2bd-f51e-4e1d-9aa0-dab60181b5da |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916511464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3916511464 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2334097652 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3231945172 ps |
| CPU time | 380.01 seconds |
| Started | Aug 09 08:52:24 PM PDT 24 |
| Finished | Aug 09 08:58:44 PM PDT 24 |
| Peak memory | 648692 kb |
| Host | smart-5587f7c9-402e-4a81-b930-0880ef1dc203 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334097652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2334097652 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.2622132065 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 4436717800 ps |
| CPU time | 522 seconds |
| Started | Aug 09 08:52:45 PM PDT 24 |
| Finished | Aug 09 09:01:27 PM PDT 24 |
| Peak memory | 649848 kb |
| Host | smart-6e0f513f-4b98-42b8-b6b1-2b79c0e3afcc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2622132065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.2622132065 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.591303066 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 5464874208 ps |
| CPU time | 600.11 seconds |
| Started | Aug 09 08:51:25 PM PDT 24 |
| Finished | Aug 09 09:01:25 PM PDT 24 |
| Peak memory | 650108 kb |
| Host | smart-1642065f-a883-42fc-b183-d11054d3783e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 591303066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.591303066 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.83747589 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3315456382 ps |
| CPU time | 441.37 seconds |
| Started | Aug 09 08:51:38 PM PDT 24 |
| Finished | Aug 09 08:59:00 PM PDT 24 |
| Peak memory | 648920 kb |
| Host | smart-a63b4687-9bb6-4be2-9535-92b5f45ada80 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83747589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw _alert_handler_lpg_sleep_mode_alerts.83747589 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.4196794407 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 5235273492 ps |
| CPU time | 739.64 seconds |
| Started | Aug 09 08:52:39 PM PDT 24 |
| Finished | Aug 09 09:04:59 PM PDT 24 |
| Peak memory | 650196 kb |
| Host | smart-75321bb3-6cca-4c69-b8c1-41322e6107cc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4196794407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.4196794407 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2252804455 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3940919630 ps |
| CPU time | 420.14 seconds |
| Started | Aug 09 08:52:30 PM PDT 24 |
| Finished | Aug 09 08:59:31 PM PDT 24 |
| Peak memory | 648652 kb |
| Host | smart-dcff85d0-5e7d-4d65-bf5f-037a1fa95880 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252804455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2252804455 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1897231150 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4368181000 ps |
| CPU time | 384.28 seconds |
| Started | Aug 09 08:54:55 PM PDT 24 |
| Finished | Aug 09 09:01:20 PM PDT 24 |
| Peak memory | 649236 kb |
| Host | smart-2c37d510-ef23-48c7-905b-b87588b4bc7a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897231150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1897231150 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3574766774 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 3724260222 ps |
| CPU time | 316.7 seconds |
| Started | Aug 09 08:52:08 PM PDT 24 |
| Finished | Aug 09 08:57:25 PM PDT 24 |
| Peak memory | 648724 kb |
| Host | smart-770a0d1f-8393-40ab-956d-8f18cd941fa0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574766774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3574766774 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.1314782399 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 6575474358 ps |
| CPU time | 664.74 seconds |
| Started | Aug 09 08:47:04 PM PDT 24 |
| Finished | Aug 09 08:58:09 PM PDT 24 |
| Peak memory | 650256 kb |
| Host | smart-fa21d3a2-b425-4b7b-9fde-2b69dc0f020f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1314782399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.1314782399 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1500154224 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3302823010 ps |
| CPU time | 413.85 seconds |
| Started | Aug 09 08:52:55 PM PDT 24 |
| Finished | Aug 09 08:59:49 PM PDT 24 |
| Peak memory | 649136 kb |
| Host | smart-140bbc40-bb08-4eec-b45d-0f08ece10a26 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500154224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1500154224 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3029457090 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 2942132072 ps |
| CPU time | 336.56 seconds |
| Started | Aug 09 08:53:15 PM PDT 24 |
| Finished | Aug 09 08:58:52 PM PDT 24 |
| Peak memory | 648772 kb |
| Host | smart-50417417-9234-47d5-9026-41de62790e66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029457090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3029457090 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2688329071 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 3618285792 ps |
| CPU time | 354.01 seconds |
| Started | Aug 09 08:52:12 PM PDT 24 |
| Finished | Aug 09 08:58:06 PM PDT 24 |
| Peak memory | 648840 kb |
| Host | smart-e9d667d6-6fde-490e-b32d-665681c0d3d3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688329071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2688329071 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3067549501 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4346766136 ps |
| CPU time | 391.01 seconds |
| Started | Aug 09 08:53:24 PM PDT 24 |
| Finished | Aug 09 08:59:56 PM PDT 24 |
| Peak memory | 649244 kb |
| Host | smart-7d39e091-9a3d-4d4d-ae2d-6d5a72cb67a4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067549501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3067549501 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.1682523246 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4671440302 ps |
| CPU time | 439.85 seconds |
| Started | Aug 09 08:52:57 PM PDT 24 |
| Finished | Aug 09 09:00:17 PM PDT 24 |
| Peak memory | 650396 kb |
| Host | smart-69ba8398-f0c8-47ef-ae3d-28b69206a2eb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1682523246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.1682523246 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2730032017 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 4335044006 ps |
| CPU time | 458.79 seconds |
| Started | Aug 09 08:53:03 PM PDT 24 |
| Finished | Aug 09 09:00:42 PM PDT 24 |
| Peak memory | 649088 kb |
| Host | smart-837c0a01-b189-4c2d-84c7-f77c92a76477 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730032017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2730032017 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3003197443 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3155647974 ps |
| CPU time | 413.94 seconds |
| Started | Aug 09 08:52:32 PM PDT 24 |
| Finished | Aug 09 08:59:26 PM PDT 24 |
| Peak memory | 648684 kb |
| Host | smart-26f58714-7748-4666-89db-da66344cd97a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003197443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3003197443 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.1048754436 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 5758319200 ps |
| CPU time | 630.3 seconds |
| Started | Aug 09 08:57:13 PM PDT 24 |
| Finished | Aug 09 09:07:43 PM PDT 24 |
| Peak memory | 650140 kb |
| Host | smart-7700196c-f25e-4b72-9551-07770851358f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1048754436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1048754436 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4272111816 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 3904364326 ps |
| CPU time | 359.84 seconds |
| Started | Aug 09 08:53:11 PM PDT 24 |
| Finished | Aug 09 08:59:11 PM PDT 24 |
| Peak memory | 648884 kb |
| Host | smart-4361c493-c9df-4d59-98de-82794867943a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272111816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4272111816 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4159615451 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 4629869856 ps |
| CPU time | 490.5 seconds |
| Started | Aug 09 08:56:05 PM PDT 24 |
| Finished | Aug 09 09:04:15 PM PDT 24 |
| Peak memory | 649332 kb |
| Host | smart-dae6b9c2-f284-4857-a4c1-79f5c99b25f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159615451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4159615451 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1944304706 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 3722838196 ps |
| CPU time | 355.34 seconds |
| Started | Aug 09 08:53:41 PM PDT 24 |
| Finished | Aug 09 08:59:37 PM PDT 24 |
| Peak memory | 648976 kb |
| Host | smart-57c81542-be37-42e5-9227-bd26a6615295 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944304706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1944304706 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.925164181 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 5321643774 ps |
| CPU time | 639 seconds |
| Started | Aug 09 08:55:00 PM PDT 24 |
| Finished | Aug 09 09:05:39 PM PDT 24 |
| Peak memory | 650372 kb |
| Host | smart-fe694ee1-93ce-443f-8089-4e68bed4bc72 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 925164181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.925164181 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1364825097 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 3341650264 ps |
| CPU time | 334.54 seconds |
| Started | Aug 09 08:54:31 PM PDT 24 |
| Finished | Aug 09 09:00:06 PM PDT 24 |
| Peak memory | 648876 kb |
| Host | smart-bc04f75d-9adb-45be-a9e9-5b79c04a78f6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364825097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1364825097 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.2875687228 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 5909830178 ps |
| CPU time | 844.7 seconds |
| Started | Aug 09 08:54:36 PM PDT 24 |
| Finished | Aug 09 09:08:41 PM PDT 24 |
| Peak memory | 649944 kb |
| Host | smart-14502bad-b973-4694-82b1-f3fdc4326b7f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2875687228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.2875687228 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3586826208 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 4573791094 ps |
| CPU time | 429.71 seconds |
| Started | Aug 09 08:56:09 PM PDT 24 |
| Finished | Aug 09 09:03:19 PM PDT 24 |
| Peak memory | 649348 kb |
| Host | smart-c8366a12-d0f3-4bad-88d4-b968941aaf80 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586826208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3586826208 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.302307295 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 6350879544 ps |
| CPU time | 567.36 seconds |
| Started | Aug 09 08:54:47 PM PDT 24 |
| Finished | Aug 09 09:04:15 PM PDT 24 |
| Peak memory | 650000 kb |
| Host | smart-513188c4-9e03-4dbe-96b3-8692f05c7e9d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 302307295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.302307295 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1249037813 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3722088510 ps |
| CPU time | 332.17 seconds |
| Started | Aug 09 08:54:14 PM PDT 24 |
| Finished | Aug 09 08:59:46 PM PDT 24 |
| Peak memory | 649252 kb |
| Host | smart-5dc0a0a4-560b-4f78-b4e1-0a06d1387942 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249037813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1249037813 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2010406198 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3348724696 ps |
| CPU time | 382.9 seconds |
| Started | Aug 09 08:54:57 PM PDT 24 |
| Finished | Aug 09 09:01:20 PM PDT 24 |
| Peak memory | 648912 kb |
| Host | smart-c25a3d5e-9741-49bb-bf61-50b8c9975c60 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010406198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2010406198 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.571691882 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 3980289050 ps |
| CPU time | 298.15 seconds |
| Started | Aug 09 08:58:04 PM PDT 24 |
| Finished | Aug 09 09:03:02 PM PDT 24 |
| Peak memory | 648912 kb |
| Host | smart-21f9929c-ed1e-45b2-975c-bd01ae7db0b5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571691882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_s w_alert_handler_lpg_sleep_mode_alerts.571691882 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2705468248 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3513695816 ps |
| CPU time | 323.33 seconds |
| Started | Aug 09 08:55:28 PM PDT 24 |
| Finished | Aug 09 09:00:51 PM PDT 24 |
| Peak memory | 649284 kb |
| Host | smart-46be85b7-3788-4601-a1af-730bda614682 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705468248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2705468248 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.1046451451 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 5016092936 ps |
| CPU time | 492.45 seconds |
| Started | Aug 09 08:55:57 PM PDT 24 |
| Finished | Aug 09 09:04:10 PM PDT 24 |
| Peak memory | 650184 kb |
| Host | smart-2b5b3d0e-fb7b-4471-bedc-41bde3915b7f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1046451451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1046451451 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3602761406 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 30982617346 ps |
| CPU time | 4312.55 seconds |
| Started | Aug 09 07:57:37 PM PDT 24 |
| Finished | Aug 09 09:09:30 PM PDT 24 |
| Peak memory | 593956 kb |
| Host | smart-814ec957-0655-4f0a-a595-b949a70233d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602761406 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.3602761406 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1696522153 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 6322453824 ps |
| CPU time | 436.96 seconds |
| Started | Aug 09 08:27:01 PM PDT 24 |
| Finished | Aug 09 08:34:18 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-3d4a5b40-a1af-48e7-a158-ae0945a2e49d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1696522153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1696522153 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1584156223 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4109954104 ps |
| CPU time | 406.17 seconds |
| Started | Aug 09 08:43:08 PM PDT 24 |
| Finished | Aug 09 08:49:55 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-8f01aa1f-20f3-47cb-af7b-cf97ed912da6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584156223 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1584156223 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.2703696357 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5507330942 ps |
| CPU time | 509.77 seconds |
| Started | Aug 09 08:20:27 PM PDT 24 |
| Finished | Aug 09 08:28:57 PM PDT 24 |
| Peak memory | 632740 kb |
| Host | smart-16e769e5-886e-4a29-89eb-dca39571dcb4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703696357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.2703696357 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.938891582 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 5246692048 ps |
| CPU time | 767.09 seconds |
| Started | Aug 09 08:53:07 PM PDT 24 |
| Finished | Aug 09 09:05:55 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-a3a5412b-42b5-4cbc-8476-73785556412f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 938891582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.938891582 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1446045949 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 6864934372 ps |
| CPU time | 802.62 seconds |
| Started | Aug 09 08:22:02 PM PDT 24 |
| Finished | Aug 09 08:35:25 PM PDT 24 |
| Peak memory | 609568 kb |
| Host | smart-60808117-e6e4-49b8-8c11-83ae454f70be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446045949 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1446045949 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2459298516 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 3254393984 ps |
| CPU time | 368.71 seconds |
| Started | Aug 09 08:37:39 PM PDT 24 |
| Finished | Aug 09 08:43:48 PM PDT 24 |
| Peak memory | 622404 kb |
| Host | smart-fc3ec81a-b0d7-46bd-8d71-17b86a925548 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459298516 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.2459298516 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3804112699 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 22422848396 ps |
| CPU time | 1085.88 seconds |
| Started | Aug 09 08:25:06 PM PDT 24 |
| Finished | Aug 09 08:43:12 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-eddb5b7e-8cbf-425b-9816-14d79712e125 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3804112699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3804112699 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.58864293 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 5065638037 ps |
| CPU time | 726.61 seconds |
| Started | Aug 09 08:23:40 PM PDT 24 |
| Finished | Aug 09 08:35:47 PM PDT 24 |
| Peak memory | 621548 kb |
| Host | smart-7fcfd6ff-ef9f-461b-a250-4ce2d78bde62 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58864293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.58864293 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.4233956898 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 6020443102 ps |
| CPU time | 678 seconds |
| Started | Aug 09 08:21:31 PM PDT 24 |
| Finished | Aug 09 08:32:51 PM PDT 24 |
| Peak memory | 620860 kb |
| Host | smart-6e06164e-6075-4cf4-846c-940d693fc6fb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4233956898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.4233956898 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1302410202 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 115980519795 ps |
| CPU time | 2226.27 seconds |
| Started | Aug 09 07:59:33 PM PDT 24 |
| Finished | Aug 09 08:36:40 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-58783f55-37cd-4dcc-b468-a80bc95fcbca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302410202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.1302410202 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2157239900 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 3252346149 ps |
| CPU time | 417.68 seconds |
| Started | Aug 09 07:59:38 PM PDT 24 |
| Finished | Aug 09 08:06:35 PM PDT 24 |
| Peak memory | 577140 kb |
| Host | smart-2fb1d887-1bd0-4c56-ad15-2ca5f6490085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157239900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.2157239900 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.416448358 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 5453742410 ps |
| CPU time | 869.93 seconds |
| Started | Aug 09 08:23:32 PM PDT 24 |
| Finished | Aug 09 08:38:03 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-fabdd53e-ea34-4e4b-a7d8-c7914f00d962 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416448358 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.416448358 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.714265855 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3523053448 ps |
| CPU time | 714.79 seconds |
| Started | Aug 09 08:37:00 PM PDT 24 |
| Finished | Aug 09 08:48:55 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-f57447ec-86e2-4a2d-aaa0-907ab686483f |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714265855 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.714265855 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3320424940 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 19292176792 ps |
| CPU time | 438.39 seconds |
| Started | Aug 09 08:21:41 PM PDT 24 |
| Finished | Aug 09 08:29:02 PM PDT 24 |
| Peak memory | 619576 kb |
| Host | smart-e5043178-f6d3-460a-8309-174342bb5f1b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3320424940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3320424940 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3303829592 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 6350240406 ps |
| CPU time | 1160.82 seconds |
| Started | Aug 09 08:20:46 PM PDT 24 |
| Finished | Aug 09 08:40:08 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-84b6c82b-5c2f-498a-a98e-98edc9a75777 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303829592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.3303829592 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1781987095 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 4271254582 ps |
| CPU time | 411.64 seconds |
| Started | Aug 09 08:24:10 PM PDT 24 |
| Finished | Aug 09 08:31:02 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-5a83a67c-e955-40f0-ae38-24ebd80cd00e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1781987095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1781987095 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.2924188657 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3240686374 ps |
| CPU time | 181.3 seconds |
| Started | Aug 09 07:57:28 PM PDT 24 |
| Finished | Aug 09 08:00:30 PM PDT 24 |
| Peak memory | 598924 kb |
| Host | smart-aafebf2e-298f-4ffa-b4ed-0cf7ad58df52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924188657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2924188657 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.2007012921 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3597283003 ps |
| CPU time | 197.73 seconds |
| Started | Aug 09 08:00:17 PM PDT 24 |
| Finished | Aug 09 08:03:35 PM PDT 24 |
| Peak memory | 604048 kb |
| Host | smart-aa6c0c37-a87e-44a1-be3e-725054f40334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007012921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.2007012921 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3102540064 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 13830301153 ps |
| CPU time | 788.87 seconds |
| Started | Aug 09 08:00:49 PM PDT 24 |
| Finished | Aug 09 08:13:58 PM PDT 24 |
| Peak memory | 579740 kb |
| Host | smart-cae3fba2-5539-474f-bccb-5a611b79cc1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102540064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.3102540064 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.970368259 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 8006744687 ps |
| CPU time | 739.89 seconds |
| Started | Aug 09 08:03:37 PM PDT 24 |
| Finished | Aug 09 08:15:57 PM PDT 24 |
| Peak memory | 577140 kb |
| Host | smart-63d3fd7e-4528-4201-8bd6-d1e50344eca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970368259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_reset_error.970368259 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.119324720 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3562372634 ps |
| CPU time | 330.68 seconds |
| Started | Aug 09 08:05:08 PM PDT 24 |
| Finished | Aug 09 08:10:39 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-8e9ec316-56fd-40b3-ba34-b6f12872c914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119324720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_reset_error.119324720 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1555452070 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 6248764788 ps |
| CPU time | 494.98 seconds |
| Started | Aug 09 08:07:58 PM PDT 24 |
| Finished | Aug 09 08:16:14 PM PDT 24 |
| Peak memory | 577168 kb |
| Host | smart-b718c66b-cefb-4b60-964b-0e2e5e897c8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555452070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.1555452070 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.884120457 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 3872674522 ps |
| CPU time | 269.13 seconds |
| Started | Aug 09 07:58:06 PM PDT 24 |
| Finished | Aug 09 08:02:35 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-de7f95d2-9bcb-4007-85d2-89274c1bc294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884120457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.884120457 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.196604423 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 3239456096 ps |
| CPU time | 254.53 seconds |
| Started | Aug 09 08:09:27 PM PDT 24 |
| Finished | Aug 09 08:13:42 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-d9dac67c-1f18-4955-877c-927b53c35ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196604423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.196604423 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3304493242 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4063449560 ps |
| CPU time | 511.58 seconds |
| Started | Aug 09 08:19:14 PM PDT 24 |
| Finished | Aug 09 08:27:46 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-2296e576-fe4e-4e51-9994-744b471d97cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304493242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.3304493242 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.1293372623 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 3476313744 ps |
| CPU time | 357.16 seconds |
| Started | Aug 09 08:24:45 PM PDT 24 |
| Finished | Aug 09 08:30:43 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-91ca6289-f857-4100-93c0-493d1ba95cfb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293372623 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.1293372623 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.330717555 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2924246712 ps |
| CPU time | 268 seconds |
| Started | Aug 09 08:20:36 PM PDT 24 |
| Finished | Aug 09 08:25:05 PM PDT 24 |
| Peak memory | 612216 kb |
| Host | smart-8df3d0bb-425c-4757-9109-d272b29066f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330717555 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.330717555 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3027353257 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3395116050 ps |
| CPU time | 445.24 seconds |
| Started | Aug 09 08:23:35 PM PDT 24 |
| Finished | Aug 09 08:31:01 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-711652fe-b95f-4178-bd2e-415d69f662f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027353257 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.3027353257 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.730730984 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 5168507978 ps |
| CPU time | 920.44 seconds |
| Started | Aug 09 08:24:17 PM PDT 24 |
| Finished | Aug 09 08:39:38 PM PDT 24 |
| Peak memory | 608756 kb |
| Host | smart-4c5358a8-4025-4791-b3ac-c39216eda494 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73073 0984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.730730984 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3377127880 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 12840009640 ps |
| CPU time | 1541.58 seconds |
| Started | Aug 09 08:37:52 PM PDT 24 |
| Finished | Aug 09 09:03:34 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-adaba0cc-f76f-4218-b6a3-958229adac8a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3377127880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.3377127880 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1222592144 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 13981376894 ps |
| CPU time | 619.51 seconds |
| Started | Aug 09 07:57:29 PM PDT 24 |
| Finished | Aug 09 08:07:48 PM PDT 24 |
| Peak memory | 591612 kb |
| Host | smart-f5c39be2-dabb-4326-9bbd-4720971383ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222592144 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.1222592144 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.1874849686 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 4195631432 ps |
| CPU time | 404.22 seconds |
| Started | Aug 09 08:25:03 PM PDT 24 |
| Finished | Aug 09 08:31:47 PM PDT 24 |
| Peak memory | 609080 kb |
| Host | smart-a1daa8b0-7c03-41ca-915f-595a4d4aee8d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874849686 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.1874849686 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3925174810 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 89162201244 ps |
| CPU time | 11945.7 seconds |
| Started | Aug 09 08:23:21 PM PDT 24 |
| Finished | Aug 09 11:42:27 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-e9ef98ca-fe00-46dc-b17d-b3acbde4fb7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3925174810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.3925174810 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.786999133 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3236903880 ps |
| CPU time | 697.11 seconds |
| Started | Aug 09 08:25:26 PM PDT 24 |
| Finished | Aug 09 08:37:04 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-ba362867-94ab-4190-8b19-13cae43f409b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786999133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_b oot_mode.786999133 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2443598046 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 12523588900 ps |
| CPU time | 3338.42 seconds |
| Started | Aug 09 08:22:51 PM PDT 24 |
| Finished | Aug 09 09:18:30 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-f7132df3-5423-4f33-9271-7c77b3ae2bd0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24435 98046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2443598046 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3541704252 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2828370816 ps |
| CPU time | 209.48 seconds |
| Started | Aug 09 08:42:56 PM PDT 24 |
| Finished | Aug 09 08:46:26 PM PDT 24 |
| Peak memory | 617160 kb |
| Host | smart-b397edbe-e425-4004-840b-c8f355c00347 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541704252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.3541704252 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3723542410 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 29821249581 ps |
| CPU time | 5032.64 seconds |
| Started | Aug 09 07:57:27 PM PDT 24 |
| Finished | Aug 09 09:21:20 PM PDT 24 |
| Peak memory | 594480 kb |
| Host | smart-0ff330cd-50c5-4bf0-9c99-cee97bdf7a93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723542410 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.3723542410 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2803148929 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 30860162360 ps |
| CPU time | 3725.71 seconds |
| Started | Aug 09 07:57:30 PM PDT 24 |
| Finished | Aug 09 08:59:37 PM PDT 24 |
| Peak memory | 590852 kb |
| Host | smart-f0fa471c-812f-4eb4-82b8-4c7ce464ae82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803148929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.2803148929 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.779767766 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4831661523 ps |
| CPU time | 244.93 seconds |
| Started | Aug 09 07:57:32 PM PDT 24 |
| Finished | Aug 09 08:01:37 PM PDT 24 |
| Peak memory | 663008 kb |
| Host | smart-a6662b9c-b0c2-4798-bd94-6d45408f5741 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779767766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_re set.779767766 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3558456786 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 12102808800 ps |
| CPU time | 873.55 seconds |
| Started | Aug 09 07:57:41 PM PDT 24 |
| Finished | Aug 09 08:12:15 PM PDT 24 |
| Peak memory | 642832 kb |
| Host | smart-1baa00ec-32e5-4e87-b9ff-4c1397fd7971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558456786 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.3558456786 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.2354748208 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 4220948560 ps |
| CPU time | 247.11 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 08:01:59 PM PDT 24 |
| Peak memory | 599164 kb |
| Host | smart-98014905-8481-491a-85e4-c2d92573d1bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354748208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.2354748208 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.811151027 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 6783674348 ps |
| CPU time | 322.91 seconds |
| Started | Aug 09 07:57:30 PM PDT 24 |
| Finished | Aug 09 08:02:53 PM PDT 24 |
| Peak memory | 591740 kb |
| Host | smart-7a48a698-6dea-4519-b836-2cfa570fc980 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811151027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .chip_prim_tl_access.811151027 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3641917274 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 29030472151 ps |
| CPU time | 3233.61 seconds |
| Started | Aug 09 07:57:29 PM PDT 24 |
| Finished | Aug 09 08:51:23 PM PDT 24 |
| Peak memory | 593636 kb |
| Host | smart-ae0c9f23-3f20-403e-aa9b-610053695513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641917274 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.3641917274 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2263162968 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 45636105 ps |
| CPU time | 9.34 seconds |
| Started | Aug 09 07:57:29 PM PDT 24 |
| Finished | Aug 09 07:57:39 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-af5e2bf7-d950-42c3-a467-685f1d01fde7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263162968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 2263162968 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.996756936 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 92103965993 ps |
| CPU time | 1664.89 seconds |
| Started | Aug 09 07:57:34 PM PDT 24 |
| Finished | Aug 09 08:25:19 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-6a4e28b9-be3d-4d45-bb69-f26984c2f48d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996756936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_de vice_slow_rsp.996756936 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1886114927 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 534731715 ps |
| CPU time | 23.71 seconds |
| Started | Aug 09 07:57:31 PM PDT 24 |
| Finished | Aug 09 07:57:55 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-e771e5fb-480b-4f6f-ac6d-3dcf401db1d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886114927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .1886114927 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.2215971000 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 237762990 ps |
| CPU time | 18.12 seconds |
| Started | Aug 09 07:57:34 PM PDT 24 |
| Finished | Aug 09 07:57:52 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-b5fa5cf9-5e92-4f7d-bc14-b529a912ee21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215971000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2215971000 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.2746251320 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 519016406 ps |
| CPU time | 18.16 seconds |
| Started | Aug 09 07:57:28 PM PDT 24 |
| Finished | Aug 09 07:57:46 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-237e798b-b24e-43b0-a471-46ebc03412d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746251320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.2746251320 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1374380537 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 28222245941 ps |
| CPU time | 271.82 seconds |
| Started | Aug 09 07:57:36 PM PDT 24 |
| Finished | Aug 09 08:02:08 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-78f453a7-0536-47d3-a437-2f4ba599f537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374380537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1374380537 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2171688759 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 57521132927 ps |
| CPU time | 915.71 seconds |
| Started | Aug 09 07:57:36 PM PDT 24 |
| Finished | Aug 09 08:12:52 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-04918aa1-6b34-4f78-9bbf-aca86cb01afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171688759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2171688759 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2211545083 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 291099748 ps |
| CPU time | 22.7 seconds |
| Started | Aug 09 07:57:35 PM PDT 24 |
| Finished | Aug 09 07:57:58 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-3436b59b-bc75-4538-a380-d1a5179606cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211545083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.2211545083 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.1899322790 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 194380649 ps |
| CPU time | 14.66 seconds |
| Started | Aug 09 07:57:32 PM PDT 24 |
| Finished | Aug 09 07:57:47 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-addb059b-d544-439b-a68b-759d23214372 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899322790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1899322790 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.3109354366 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 203576119 ps |
| CPU time | 8.32 seconds |
| Started | Aug 09 07:57:28 PM PDT 24 |
| Finished | Aug 09 07:57:37 PM PDT 24 |
| Peak memory | 574828 kb |
| Host | smart-8260589c-d230-4a00-b319-b572f3680d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109354366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3109354366 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1582877391 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 8098726485 ps |
| CPU time | 85.22 seconds |
| Started | Aug 09 07:57:34 PM PDT 24 |
| Finished | Aug 09 07:58:59 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-1fc3b0b5-a0a2-488c-b3f7-dbebf1235d3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582877391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1582877391 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1692491509 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 4153232260 ps |
| CPU time | 66.99 seconds |
| Started | Aug 09 07:57:34 PM PDT 24 |
| Finished | Aug 09 07:58:41 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-55d41a5b-c09d-423b-8fa6-9cdbe061ed22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692491509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1692491509 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1353124229 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 42241237 ps |
| CPU time | 5.74 seconds |
| Started | Aug 09 07:57:28 PM PDT 24 |
| Finished | Aug 09 07:57:34 PM PDT 24 |
| Peak memory | 574872 kb |
| Host | smart-addef1f7-63cf-41d9-9c60-6922d94384b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353124229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .1353124229 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.3238831136 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 2506395942 ps |
| CPU time | 214.93 seconds |
| Started | Aug 09 07:57:29 PM PDT 24 |
| Finished | Aug 09 08:01:04 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-35309508-3a05-414a-ab23-217e8e62ca7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238831136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3238831136 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1653229150 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 7722608812 ps |
| CPU time | 268.14 seconds |
| Started | Aug 09 07:57:29 PM PDT 24 |
| Finished | Aug 09 08:01:58 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-d60fac58-15ed-4bec-aaf7-e189d847d530 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653229150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1653229150 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2856534955 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 198622854 ps |
| CPU time | 74.75 seconds |
| Started | Aug 09 07:57:31 PM PDT 24 |
| Finished | Aug 09 07:58:46 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-3c546394-db6d-43a7-a519-41a4f6e5b07e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856534955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.2856534955 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3180507891 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 326472772 ps |
| CPU time | 102.64 seconds |
| Started | Aug 09 07:57:33 PM PDT 24 |
| Finished | Aug 09 07:59:16 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-92c70bc5-1684-4cbe-9f1a-c96dccb693bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180507891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.3180507891 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1491447673 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 234514334 ps |
| CPU time | 11.67 seconds |
| Started | Aug 09 07:57:34 PM PDT 24 |
| Finished | Aug 09 07:57:46 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-f6fcc4b1-8657-4070-a865-b5291a4591ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491447673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1491447673 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.63044220 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 39747199347 ps |
| CPU time | 6202.55 seconds |
| Started | Aug 09 07:57:46 PM PDT 24 |
| Finished | Aug 09 09:41:09 PM PDT 24 |
| Peak memory | 594524 kb |
| Host | smart-ed995d3c-6754-4f32-ba8c-335c35560ee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63044220 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.chip_csr_aliasing.63044220 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.470478431 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 59944788372 ps |
| CPU time | 6566.15 seconds |
| Started | Aug 09 07:57:43 PM PDT 24 |
| Finished | Aug 09 09:47:10 PM PDT 24 |
| Peak memory | 592916 kb |
| Host | smart-6e4e6789-652c-4dc1-a777-b00140b5cb78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470478431 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.470478431 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3951591717 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 11612592576 ps |
| CPU time | 814.93 seconds |
| Started | Aug 09 07:57:44 PM PDT 24 |
| Finished | Aug 09 08:11:19 PM PDT 24 |
| Peak memory | 653240 kb |
| Host | smart-8552abb9-45ba-444e-a07e-d6f6ea265082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951591717 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.3951591717 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.1527345844 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 5971589968 ps |
| CPU time | 527.6 seconds |
| Started | Aug 09 07:57:39 PM PDT 24 |
| Finished | Aug 09 08:06:27 PM PDT 24 |
| Peak memory | 599076 kb |
| Host | smart-b0ee2066-16a9-45cc-8d8f-80060cdaafad |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527345844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.1527345844 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3700505821 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 8465890050 ps |
| CPU time | 292.01 seconds |
| Started | Aug 09 07:57:39 PM PDT 24 |
| Finished | Aug 09 08:02:31 PM PDT 24 |
| Peak memory | 590240 kb |
| Host | smart-6bbaf2f4-f8c6-4909-ad89-5b1656432aa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700505821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.3700505821 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2450672628 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 9573937310 ps |
| CPU time | 347.11 seconds |
| Started | Aug 09 07:57:39 PM PDT 24 |
| Finished | Aug 09 08:03:26 PM PDT 24 |
| Peak memory | 599800 kb |
| Host | smart-802ae094-7db4-4d45-831e-f939db3b517b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450672628 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.2450672628 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.1286190700 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 2517844909 ps |
| CPU time | 111.81 seconds |
| Started | Aug 09 07:57:43 PM PDT 24 |
| Finished | Aug 09 07:59:35 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-c025f48b-3f23-4d64-9d01-44e982d2111b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286190700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 1286190700 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1645915429 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 166370731524 ps |
| CPU time | 2861.93 seconds |
| Started | Aug 09 07:57:41 PM PDT 24 |
| Finished | Aug 09 08:45:24 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-d4666aaf-95c8-4154-bd9e-c2003e5ff71e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645915429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.1645915429 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.354061934 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 951484952 ps |
| CPU time | 33.75 seconds |
| Started | Aug 09 07:57:36 PM PDT 24 |
| Finished | Aug 09 07:58:10 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-249085cf-381a-4713-851b-d192a1abbb84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354061934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr. 354061934 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.3377686511 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 306646791 ps |
| CPU time | 23.08 seconds |
| Started | Aug 09 07:57:45 PM PDT 24 |
| Finished | Aug 09 07:58:08 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-1c5dc623-29dc-4e9a-bc7a-d32e65e2dcf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377686511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3377686511 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.975346909 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 482918743 ps |
| CPU time | 39.8 seconds |
| Started | Aug 09 07:57:38 PM PDT 24 |
| Finished | Aug 09 07:58:18 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-7ed91f6a-8daf-462a-bf18-8248e48e87f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975346909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.975346909 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2653755132 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 40235826069 ps |
| CPU time | 379 seconds |
| Started | Aug 09 07:57:43 PM PDT 24 |
| Finished | Aug 09 08:04:02 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-fe047764-9af3-44a4-91d1-be36298e1ae6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653755132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2653755132 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1351492984 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 38640804224 ps |
| CPU time | 662.69 seconds |
| Started | Aug 09 07:57:37 PM PDT 24 |
| Finished | Aug 09 08:08:40 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-af558a26-f46f-4d27-a84e-9c6b55db0afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351492984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1351492984 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.800147914 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 454236037 ps |
| CPU time | 39.96 seconds |
| Started | Aug 09 07:57:39 PM PDT 24 |
| Finished | Aug 09 07:58:19 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-334c13e9-bda2-4bca-b2eb-feb7690451c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800147914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delay s.800147914 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.3746028235 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 240256321 ps |
| CPU time | 20.03 seconds |
| Started | Aug 09 07:57:41 PM PDT 24 |
| Finished | Aug 09 07:58:01 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-ae33baa6-49e8-4346-ba9f-2ce72b9ef2a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746028235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3746028235 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.4005538418 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 51008332 ps |
| CPU time | 5.89 seconds |
| Started | Aug 09 07:57:46 PM PDT 24 |
| Finished | Aug 09 07:57:52 PM PDT 24 |
| Peak memory | 574792 kb |
| Host | smart-732d9168-f420-45c8-8c63-823d4a275bcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005538418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.4005538418 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2020528687 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 8656643663 ps |
| CPU time | 88.77 seconds |
| Started | Aug 09 07:57:36 PM PDT 24 |
| Finished | Aug 09 07:59:05 PM PDT 24 |
| Peak memory | 574860 kb |
| Host | smart-c1ee1bb5-0232-461e-a3b4-4816d21f1ce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020528687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2020528687 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2606102217 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 5118752922 ps |
| CPU time | 91.87 seconds |
| Started | Aug 09 07:57:47 PM PDT 24 |
| Finished | Aug 09 07:59:19 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-e7a8d453-ffa7-41ab-9762-2969df1159b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606102217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2606102217 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1313483323 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 46705124 ps |
| CPU time | 6.59 seconds |
| Started | Aug 09 07:57:42 PM PDT 24 |
| Finished | Aug 09 07:57:48 PM PDT 24 |
| Peak memory | 574800 kb |
| Host | smart-8544d574-c327-4f7d-9413-aaf1df73829c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313483323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .1313483323 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.1602929175 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 8441752790 ps |
| CPU time | 302.33 seconds |
| Started | Aug 09 07:57:35 PM PDT 24 |
| Finished | Aug 09 08:02:37 PM PDT 24 |
| Peak memory | 577100 kb |
| Host | smart-474e8adb-b6ec-41cb-8ddc-1afd8823f89f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602929175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1602929175 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.4204572978 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 16201422094 ps |
| CPU time | 512.83 seconds |
| Started | Aug 09 07:57:37 PM PDT 24 |
| Finished | Aug 09 08:06:10 PM PDT 24 |
| Peak memory | 577160 kb |
| Host | smart-513bcc7c-0073-4cc0-9a60-cb12caaea582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204572978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.4204572978 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3670220105 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 10083579254 ps |
| CPU time | 584.02 seconds |
| Started | Aug 09 07:57:49 PM PDT 24 |
| Finished | Aug 09 08:07:34 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-0e96c6c9-4e13-4954-9162-0741d1f78934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670220105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.3670220105 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.413214736 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 234054487 ps |
| CPU time | 49.89 seconds |
| Started | Aug 09 07:57:39 PM PDT 24 |
| Finished | Aug 09 07:58:29 PM PDT 24 |
| Peak memory | 576988 kb |
| Host | smart-675e3d9f-44b7-4ef3-a4a1-433b481f0e34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413214736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_reset_error.413214736 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.393268290 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 614224803 ps |
| CPU time | 25.27 seconds |
| Started | Aug 09 07:57:39 PM PDT 24 |
| Finished | Aug 09 07:58:04 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-628e54c1-bfb6-4507-8e39-82fdb7b4f2d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393268290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.393268290 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3645468003 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 6156743878 ps |
| CPU time | 406.13 seconds |
| Started | Aug 09 07:58:14 PM PDT 24 |
| Finished | Aug 09 08:05:00 PM PDT 24 |
| Peak memory | 644468 kb |
| Host | smart-1d2159f0-66b3-434c-8922-e2555ff9a3b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645468003 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.3645468003 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.3706901405 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 3806732915 ps |
| CPU time | 283.25 seconds |
| Started | Aug 09 07:58:15 PM PDT 24 |
| Finished | Aug 09 08:02:58 PM PDT 24 |
| Peak memory | 597760 kb |
| Host | smart-75dd48bf-8179-41d0-ba7f-d06d14485b3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706901405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.3706901405 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1876730930 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 27492436894 ps |
| CPU time | 3905.05 seconds |
| Started | Aug 09 07:58:15 PM PDT 24 |
| Finished | Aug 09 09:03:20 PM PDT 24 |
| Peak memory | 593416 kb |
| Host | smart-8ef229b7-fbaf-4778-955b-b73fb5da4a73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876730930 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.1876730930 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.2777632670 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 319048833 ps |
| CPU time | 29.06 seconds |
| Started | Aug 09 07:58:28 PM PDT 24 |
| Finished | Aug 09 07:58:57 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-b32455ba-dd1e-4baf-8ff9-a6e27978ae0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777632670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .2777632670 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3185232595 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 38898057563 ps |
| CPU time | 615.3 seconds |
| Started | Aug 09 07:58:15 PM PDT 24 |
| Finished | Aug 09 08:08:30 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-40111cb4-4a3e-40d1-8075-f154dcf93ea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185232595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.3185232595 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1366483704 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 1103122289 ps |
| CPU time | 45.35 seconds |
| Started | Aug 09 07:58:14 PM PDT 24 |
| Finished | Aug 09 07:58:59 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-d85c50da-fba5-4e9e-be0d-2afe466bdc23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366483704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.1366483704 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.360727200 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 278714530 ps |
| CPU time | 23.24 seconds |
| Started | Aug 09 07:58:14 PM PDT 24 |
| Finished | Aug 09 07:58:37 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-130e9751-6c86-4182-a4b8-e863ae14b993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360727200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.360727200 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.2970881541 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 305131041 ps |
| CPU time | 12.7 seconds |
| Started | Aug 09 07:58:16 PM PDT 24 |
| Finished | Aug 09 07:58:29 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-75287dad-e7eb-47fc-a3c7-50894fd1a606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970881541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2970881541 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.884517554 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 32928761356 ps |
| CPU time | 355.41 seconds |
| Started | Aug 09 07:58:16 PM PDT 24 |
| Finished | Aug 09 08:04:12 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-4cef3017-d4c2-4c78-824e-23eb27f2bc5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884517554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.884517554 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.704133301 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 20053913533 ps |
| CPU time | 334.67 seconds |
| Started | Aug 09 07:58:16 PM PDT 24 |
| Finished | Aug 09 08:03:51 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-137d72c3-da45-4b9f-8b14-5954aa2055f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704133301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.704133301 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.290079193 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 300524921 ps |
| CPU time | 28.41 seconds |
| Started | Aug 09 07:58:14 PM PDT 24 |
| Finished | Aug 09 07:58:42 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-371354ab-6a7e-4d14-8f91-81b85ff5d5cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290079193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela ys.290079193 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.3255779792 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 273428954 ps |
| CPU time | 19.89 seconds |
| Started | Aug 09 07:58:19 PM PDT 24 |
| Finished | Aug 09 07:58:39 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-638fdc19-cff3-455e-ad96-a71846c1489c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255779792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3255779792 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.349813647 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 161379382 ps |
| CPU time | 7.95 seconds |
| Started | Aug 09 07:58:19 PM PDT 24 |
| Finished | Aug 09 07:58:27 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-8a26feff-c1c0-46ce-b041-a60f56a67ac6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349813647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.349813647 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1923084038 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 8997908867 ps |
| CPU time | 95.23 seconds |
| Started | Aug 09 07:58:18 PM PDT 24 |
| Finished | Aug 09 07:59:53 PM PDT 24 |
| Peak memory | 574888 kb |
| Host | smart-36caee47-81c5-442a-9ebb-571c20f7170e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923084038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1923084038 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1713147544 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 5803019354 ps |
| CPU time | 102.67 seconds |
| Started | Aug 09 07:58:16 PM PDT 24 |
| Finished | Aug 09 07:59:58 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-6bf14dcb-14d4-4e95-8907-c0fc0d1bea28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713147544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1713147544 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1400941614 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 57306061 ps |
| CPU time | 6.39 seconds |
| Started | Aug 09 07:58:28 PM PDT 24 |
| Finished | Aug 09 07:58:34 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-d9034119-f085-4a57-b76b-9760955d8e48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400941614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.1400941614 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.3482865097 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 37304322 ps |
| CPU time | 7.04 seconds |
| Started | Aug 09 07:58:16 PM PDT 24 |
| Finished | Aug 09 07:58:23 PM PDT 24 |
| Peak memory | 574980 kb |
| Host | smart-50c6feff-631e-4f4a-b5ec-193cd5283c96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482865097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3482865097 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.285675455 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 4354930128 ps |
| CPU time | 133.34 seconds |
| Started | Aug 09 07:58:17 PM PDT 24 |
| Finished | Aug 09 08:00:30 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-0f46c94a-defb-4431-90a1-6610ccf0a99f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285675455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.285675455 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1303713586 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 4377106351 ps |
| CPU time | 538.08 seconds |
| Started | Aug 09 07:58:15 PM PDT 24 |
| Finished | Aug 09 08:07:14 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-902dd077-7816-4d0f-8327-eecd02671bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303713586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.1303713586 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2984198049 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 6640296536 ps |
| CPU time | 354.9 seconds |
| Started | Aug 09 07:58:16 PM PDT 24 |
| Finished | Aug 09 08:04:11 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-344eb90a-a8c7-4777-b579-dbcf1800b35b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984198049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.2984198049 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.868408775 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 116364366 ps |
| CPU time | 16.04 seconds |
| Started | Aug 09 07:58:15 PM PDT 24 |
| Finished | Aug 09 07:58:31 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-ffded1c7-8a60-45da-9e08-e759fe35ce68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868408775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.868408775 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.110143087 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 7571328770 ps |
| CPU time | 443.65 seconds |
| Started | Aug 09 07:58:41 PM PDT 24 |
| Finished | Aug 09 08:06:05 PM PDT 24 |
| Peak memory | 639264 kb |
| Host | smart-8c864214-fc47-40de-ab7d-9332a24e2d16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110143087 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.110143087 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.831911739 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 4759845440 ps |
| CPU time | 312.62 seconds |
| Started | Aug 09 07:58:33 PM PDT 24 |
| Finished | Aug 09 08:03:45 PM PDT 24 |
| Peak memory | 597856 kb |
| Host | smart-1ace0f66-60fd-4cb0-8805-d0bd9bbb4ecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831911739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.831911739 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1884852282 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 28444931142 ps |
| CPU time | 4316.81 seconds |
| Started | Aug 09 07:58:23 PM PDT 24 |
| Finished | Aug 09 09:10:21 PM PDT 24 |
| Peak memory | 593764 kb |
| Host | smart-5322c27f-34a0-4857-bec1-8f7f55f4469a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884852282 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.1884852282 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.2556133073 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 2231785059 ps |
| CPU time | 86.45 seconds |
| Started | Aug 09 07:58:23 PM PDT 24 |
| Finished | Aug 09 07:59:50 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-c4def3c7-292e-4dec-a4d9-1c4ff77cecb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556133073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .2556133073 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2809717200 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 57621639550 ps |
| CPU time | 877.03 seconds |
| Started | Aug 09 07:58:32 PM PDT 24 |
| Finished | Aug 09 08:13:09 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-205db2e8-873e-4e26-bd20-7a4e3f19c1b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809717200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.2809717200 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3747140848 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 152720957 ps |
| CPU time | 17.59 seconds |
| Started | Aug 09 07:58:34 PM PDT 24 |
| Finished | Aug 09 07:58:52 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-77f7fb8c-54ab-45f9-8fa2-e4f0ff283673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747140848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.3747140848 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.3652808387 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 233528993 ps |
| CPU time | 23 seconds |
| Started | Aug 09 07:58:39 PM PDT 24 |
| Finished | Aug 09 07:59:02 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-51fde506-6caf-4802-9d3c-67bb3331baba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652808387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3652808387 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.3524996248 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 171839581 ps |
| CPU time | 18.94 seconds |
| Started | Aug 09 07:58:32 PM PDT 24 |
| Finished | Aug 09 07:58:51 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-a5e9e367-4d83-4aad-82aa-cdb24080a59b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524996248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.3524996248 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1392190304 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 73326592131 ps |
| CPU time | 758.98 seconds |
| Started | Aug 09 07:58:27 PM PDT 24 |
| Finished | Aug 09 08:11:06 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-8021bde2-9545-4e60-b8d9-18089e135ca3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392190304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1392190304 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2102953956 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 55861580508 ps |
| CPU time | 899.69 seconds |
| Started | Aug 09 07:58:27 PM PDT 24 |
| Finished | Aug 09 08:13:27 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-e5b25cdb-81c5-4f32-b61a-1d87fe438976 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102953956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2102953956 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3052380395 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 194494254 ps |
| CPU time | 16.83 seconds |
| Started | Aug 09 07:58:25 PM PDT 24 |
| Finished | Aug 09 07:58:42 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-c43f77dc-ce8f-40e8-9934-4c795e622dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052380395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.3052380395 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.4238700879 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 1370374219 ps |
| CPU time | 37.79 seconds |
| Started | Aug 09 07:58:39 PM PDT 24 |
| Finished | Aug 09 07:59:17 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-981be35d-54f0-4306-b8d0-3dc2e833a6ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238700879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.4238700879 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.2864470149 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 39809960 ps |
| CPU time | 5.76 seconds |
| Started | Aug 09 07:58:24 PM PDT 24 |
| Finished | Aug 09 07:58:30 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-f4a7877a-d5d6-4ae2-bc87-2d6e6a3790fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864470149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2864470149 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1035130575 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 8579869327 ps |
| CPU time | 89.67 seconds |
| Started | Aug 09 07:58:32 PM PDT 24 |
| Finished | Aug 09 08:00:02 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-ee497d19-ac3f-411c-932b-b1d3e5a26750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035130575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1035130575 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1551935961 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 4399893260 ps |
| CPU time | 77.13 seconds |
| Started | Aug 09 07:58:22 PM PDT 24 |
| Finished | Aug 09 07:59:40 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-3c6e11dc-566f-471f-b73c-996c5b4742f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551935961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1551935961 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2369059151 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 59462220 ps |
| CPU time | 7.42 seconds |
| Started | Aug 09 07:58:32 PM PDT 24 |
| Finished | Aug 09 07:58:40 PM PDT 24 |
| Peak memory | 574844 kb |
| Host | smart-2da10f57-bdf7-4e82-825b-e7d9fd9af756 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369059151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.2369059151 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.680237671 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 2796228865 ps |
| CPU time | 240 seconds |
| Started | Aug 09 07:58:32 PM PDT 24 |
| Finished | Aug 09 08:02:32 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-257096c5-8bfe-4ed9-bcea-e721f573dc15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680237671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.680237671 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3185398103 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 48313214 ps |
| CPU time | 6.09 seconds |
| Started | Aug 09 07:58:33 PM PDT 24 |
| Finished | Aug 09 07:58:39 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-744b8f85-9f31-4b2e-b124-c9897c08d704 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185398103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3185398103 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3509590157 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 2755125020 ps |
| CPU time | 293.65 seconds |
| Started | Aug 09 07:58:34 PM PDT 24 |
| Finished | Aug 09 08:03:27 PM PDT 24 |
| Peak memory | 577164 kb |
| Host | smart-90de26dd-12d0-431e-88f1-6339bbf17492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509590157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.3509590157 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2150972063 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 6897851389 ps |
| CPU time | 378.76 seconds |
| Started | Aug 09 07:58:35 PM PDT 24 |
| Finished | Aug 09 08:04:53 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-586cd699-21cc-4950-8141-e6fd655e920f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150972063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.2150972063 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1095966783 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 345238617 ps |
| CPU time | 42.22 seconds |
| Started | Aug 09 07:58:33 PM PDT 24 |
| Finished | Aug 09 07:59:15 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-2a54d51a-4083-476c-8c1f-6e627f5f27b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095966783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1095966783 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3783625412 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 5856505684 ps |
| CPU time | 475 seconds |
| Started | Aug 09 07:58:53 PM PDT 24 |
| Finished | Aug 09 08:06:48 PM PDT 24 |
| Peak memory | 638736 kb |
| Host | smart-e04cb972-b1d4-4acc-84ef-b707fb1cb15a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783625412 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.3783625412 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.1880537179 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 5525211415 ps |
| CPU time | 526.04 seconds |
| Started | Aug 09 07:58:59 PM PDT 24 |
| Finished | Aug 09 08:07:46 PM PDT 24 |
| Peak memory | 598412 kb |
| Host | smart-ca3ba1d1-f21b-4b44-aebd-2b24acf858fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880537179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.1880537179 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2451606687 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 27502608103 ps |
| CPU time | 4641.77 seconds |
| Started | Aug 09 07:58:42 PM PDT 24 |
| Finished | Aug 09 09:16:04 PM PDT 24 |
| Peak memory | 593520 kb |
| Host | smart-f6ad7a99-cf99-448d-bfce-080f31f7d813 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451606687 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.2451606687 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.1445935622 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 4346777004 ps |
| CPU time | 283.53 seconds |
| Started | Aug 09 07:58:41 PM PDT 24 |
| Finished | Aug 09 08:03:25 PM PDT 24 |
| Peak memory | 598796 kb |
| Host | smart-2943a717-1b68-4d60-9d37-7bbacc41e56a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445935622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.1445935622 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.2709173677 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 815644983 ps |
| CPU time | 30.63 seconds |
| Started | Aug 09 07:58:47 PM PDT 24 |
| Finished | Aug 09 07:59:17 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-8a1b6a06-0815-4b0f-bbc6-0bcea6d5eefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709173677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .2709173677 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1763850738 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 107316828306 ps |
| CPU time | 1708.32 seconds |
| Started | Aug 09 07:58:46 PM PDT 24 |
| Finished | Aug 09 08:27:15 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-00bbac64-ede1-4990-a684-97c745cd0a4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763850738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.1763850738 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.4178274935 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 860378775 ps |
| CPU time | 34.21 seconds |
| Started | Aug 09 07:59:00 PM PDT 24 |
| Finished | Aug 09 07:59:34 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-0d3e56a5-8e0a-4623-a983-36ffac1dcbeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178274935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.4178274935 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.2420344066 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 543397025 ps |
| CPU time | 39.73 seconds |
| Started | Aug 09 07:58:46 PM PDT 24 |
| Finished | Aug 09 07:59:25 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-2b12b125-a676-409e-9d5d-0e953f275d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420344066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2420344066 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.1884402456 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 460603827 ps |
| CPU time | 44.26 seconds |
| Started | Aug 09 07:58:40 PM PDT 24 |
| Finished | Aug 09 07:59:25 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-f85af0f1-c21c-46fd-9a08-899ab23b94dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884402456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1884402456 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1569774705 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 104599217638 ps |
| CPU time | 1072.49 seconds |
| Started | Aug 09 07:58:47 PM PDT 24 |
| Finished | Aug 09 08:16:40 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-6676255b-cb02-4097-b32f-80886bef44bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569774705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1569774705 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2488766440 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 70242936435 ps |
| CPU time | 1277.75 seconds |
| Started | Aug 09 07:58:46 PM PDT 24 |
| Finished | Aug 09 08:20:04 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-db4bfb9d-f140-4600-bb83-d4d2a1c46d2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488766440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2488766440 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.588595451 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 130618679 ps |
| CPU time | 13.47 seconds |
| Started | Aug 09 07:58:41 PM PDT 24 |
| Finished | Aug 09 07:58:54 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-a92112e1-ce33-4aa1-b573-4d1284bc0abc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588595451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_dela ys.588595451 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.3897400343 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 437980487 ps |
| CPU time | 14.59 seconds |
| Started | Aug 09 07:58:46 PM PDT 24 |
| Finished | Aug 09 07:59:01 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-60260d28-3e94-447f-b113-a84f59c77158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897400343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3897400343 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.3162185758 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 201679032 ps |
| CPU time | 8.53 seconds |
| Started | Aug 09 07:58:42 PM PDT 24 |
| Finished | Aug 09 07:58:50 PM PDT 24 |
| Peak memory | 574812 kb |
| Host | smart-27456610-8f4c-42a6-bc34-c1b8c023e162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162185758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3162185758 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.999207021 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 8776515813 ps |
| CPU time | 87.55 seconds |
| Started | Aug 09 07:58:42 PM PDT 24 |
| Finished | Aug 09 08:00:09 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-23ec3d31-9d72-4e85-9205-25fcb80aa93b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999207021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.999207021 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3772503889 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 5668233669 ps |
| CPU time | 94.68 seconds |
| Started | Aug 09 07:58:39 PM PDT 24 |
| Finished | Aug 09 08:00:14 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-411a7137-e200-4b3e-a544-e831d3389471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772503889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3772503889 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.691110983 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 58463151 ps |
| CPU time | 6.88 seconds |
| Started | Aug 09 07:58:40 PM PDT 24 |
| Finished | Aug 09 07:58:47 PM PDT 24 |
| Peak memory | 574784 kb |
| Host | smart-a4c8c0af-3baa-4eb1-882c-e55868494006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691110983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays .691110983 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.1702693972 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 1089239509 ps |
| CPU time | 73.44 seconds |
| Started | Aug 09 07:58:55 PM PDT 24 |
| Finished | Aug 09 08:00:08 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-675a3a1d-fefa-4074-b97e-ca3afe2fe0f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702693972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1702693972 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.33007366 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 6615379187 ps |
| CPU time | 241.59 seconds |
| Started | Aug 09 07:58:52 PM PDT 24 |
| Finished | Aug 09 08:02:54 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-c10030e3-dbf8-42ea-b640-47918c55ac30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33007366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.33007366 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1602702806 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 274022494 ps |
| CPU time | 75.71 seconds |
| Started | Aug 09 07:58:53 PM PDT 24 |
| Finished | Aug 09 08:00:09 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-83ebf7c8-914b-419a-ad06-223e4cd0165f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602702806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.1602702806 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1000919873 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 738028459 ps |
| CPU time | 108.45 seconds |
| Started | Aug 09 07:58:53 PM PDT 24 |
| Finished | Aug 09 08:00:42 PM PDT 24 |
| Peak memory | 577072 kb |
| Host | smart-757189d9-ee37-4e80-b81e-cd9f7d623fa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000919873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.1000919873 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1219205684 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 129543104 ps |
| CPU time | 15.19 seconds |
| Started | Aug 09 07:58:59 PM PDT 24 |
| Finished | Aug 09 07:59:14 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-4e17158c-27e1-433d-9399-20c28b88c4c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219205684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1219205684 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2847020352 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 8415246294 ps |
| CPU time | 818.48 seconds |
| Started | Aug 09 07:59:04 PM PDT 24 |
| Finished | Aug 09 08:12:43 PM PDT 24 |
| Peak memory | 646004 kb |
| Host | smart-dca0d721-701b-445a-904c-5bbdbcdd5461 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847020352 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.2847020352 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.3032618673 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 6099120878 ps |
| CPU time | 709.1 seconds |
| Started | Aug 09 07:59:11 PM PDT 24 |
| Finished | Aug 09 08:11:00 PM PDT 24 |
| Peak memory | 599132 kb |
| Host | smart-ef489126-8a58-4156-8196-24dab490e512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032618673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.3032618673 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3235182522 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 28965340918 ps |
| CPU time | 3586.12 seconds |
| Started | Aug 09 07:58:57 PM PDT 24 |
| Finished | Aug 09 08:58:44 PM PDT 24 |
| Peak memory | 593648 kb |
| Host | smart-8037aca2-bf3a-4010-9a07-ae29c11ada5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235182522 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.3235182522 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.2428421214 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 2703168205 ps |
| CPU time | 86.37 seconds |
| Started | Aug 09 07:59:04 PM PDT 24 |
| Finished | Aug 09 08:00:30 PM PDT 24 |
| Peak memory | 603992 kb |
| Host | smart-5e4d24fb-7b48-4aae-b8ea-1d2edfcd3a2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428421214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.2428421214 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.72888418 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 2652280637 ps |
| CPU time | 91.95 seconds |
| Started | Aug 09 07:59:00 PM PDT 24 |
| Finished | Aug 09 08:00:32 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-4a755474-f2b2-4236-b1c3-92ab0340841c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72888418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.72888418 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1326915389 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 61195050107 ps |
| CPU time | 1084.78 seconds |
| Started | Aug 09 07:59:02 PM PDT 24 |
| Finished | Aug 09 08:17:07 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-9ca2b41d-917e-4113-99c0-7dbe275e7cee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326915389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.1326915389 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3350070672 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 1230080302 ps |
| CPU time | 47.35 seconds |
| Started | Aug 09 07:58:59 PM PDT 24 |
| Finished | Aug 09 07:59:47 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-d0210eb7-5b95-46e2-ba91-9be14fb0584d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350070672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.3350070672 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.1952160263 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 118236456 ps |
| CPU time | 10.83 seconds |
| Started | Aug 09 07:59:03 PM PDT 24 |
| Finished | Aug 09 07:59:14 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-f26353d0-f2ce-412f-b1f8-0e5795c9d600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952160263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1952160263 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.97562555 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1531682812 ps |
| CPU time | 54.54 seconds |
| Started | Aug 09 07:59:02 PM PDT 24 |
| Finished | Aug 09 07:59:56 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-9b17c51d-50c5-4572-99a3-4147d05e30c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97562555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.97562555 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1160772997 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 40980264939 ps |
| CPU time | 424.08 seconds |
| Started | Aug 09 07:59:01 PM PDT 24 |
| Finished | Aug 09 08:06:05 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-650c3186-67aa-4849-b589-47b9623aac8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160772997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1160772997 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1788898984 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 62068592949 ps |
| CPU time | 1065.57 seconds |
| Started | Aug 09 07:59:01 PM PDT 24 |
| Finished | Aug 09 08:16:47 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-556d4dd1-44ec-4096-b3e1-befbc39754c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788898984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1788898984 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3320637188 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 273752045 ps |
| CPU time | 25.23 seconds |
| Started | Aug 09 07:59:01 PM PDT 24 |
| Finished | Aug 09 07:59:26 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-844884d5-59d8-42b3-b2b3-92d0f49cab71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320637188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.3320637188 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.610469524 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 389524756 ps |
| CPU time | 26.22 seconds |
| Started | Aug 09 07:59:01 PM PDT 24 |
| Finished | Aug 09 07:59:28 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-b137f017-acc2-4226-b176-27d17d1f6387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610469524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.610469524 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.4274557330 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 50599017 ps |
| CPU time | 6.36 seconds |
| Started | Aug 09 07:58:59 PM PDT 24 |
| Finished | Aug 09 07:59:05 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-40a9b233-a0bd-4fff-b1a8-02a1ae95f4d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274557330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4274557330 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.4225281794 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 6948391029 ps |
| CPU time | 66.07 seconds |
| Started | Aug 09 07:59:02 PM PDT 24 |
| Finished | Aug 09 08:00:08 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-f206f895-5457-43e0-9589-85c872c59fee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225281794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.4225281794 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1210986698 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 4796395938 ps |
| CPU time | 83.21 seconds |
| Started | Aug 09 07:59:01 PM PDT 24 |
| Finished | Aug 09 08:00:24 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-b9fd72de-242b-45c0-a6a7-dc95cd9bc2d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210986698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1210986698 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3986149014 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 47307980 ps |
| CPU time | 5.72 seconds |
| Started | Aug 09 07:58:59 PM PDT 24 |
| Finished | Aug 09 07:59:05 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-96864c60-f644-4224-94e3-8c940e60f001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986149014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.3986149014 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3355443565 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 10147615038 ps |
| CPU time | 361.02 seconds |
| Started | Aug 09 07:59:03 PM PDT 24 |
| Finished | Aug 09 08:05:04 PM PDT 24 |
| Peak memory | 577092 kb |
| Host | smart-15ddc626-bbed-48bc-b2f9-506f0b8cbad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355443565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3355443565 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.931127317 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 195046487 ps |
| CPU time | 66.14 seconds |
| Started | Aug 09 07:59:02 PM PDT 24 |
| Finished | Aug 09 08:00:08 PM PDT 24 |
| Peak memory | 577052 kb |
| Host | smart-f2928add-db40-49ec-bc78-6231538c3f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931127317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_ with_rand_reset.931127317 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1344746106 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 1303817281 ps |
| CPU time | 59.03 seconds |
| Started | Aug 09 07:59:02 PM PDT 24 |
| Finished | Aug 09 08:00:01 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-c524dc71-5a37-4d6d-911e-3da5f5734857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344746106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1344746106 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2479570582 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 7350621966 ps |
| CPU time | 427.04 seconds |
| Started | Aug 09 07:59:10 PM PDT 24 |
| Finished | Aug 09 08:06:17 PM PDT 24 |
| Peak memory | 644644 kb |
| Host | smart-0efab08f-a904-4a9f-8294-6a167ebbf66e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479570582 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.2479570582 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.3166817429 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 4458677978 ps |
| CPU time | 353.34 seconds |
| Started | Aug 09 07:59:12 PM PDT 24 |
| Finished | Aug 09 08:05:06 PM PDT 24 |
| Peak memory | 598548 kb |
| Host | smart-e06722e1-1254-4d4d-9aef-fe8f348837b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166817429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.3166817429 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3372512669 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 13704233996 ps |
| CPU time | 1713.77 seconds |
| Started | Aug 09 07:59:06 PM PDT 24 |
| Finished | Aug 09 08:27:40 PM PDT 24 |
| Peak memory | 593544 kb |
| Host | smart-e125897b-9afb-4635-b117-0340dcd12d9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372512669 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.3372512669 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.3019307680 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4092772522 ps |
| CPU time | 234.16 seconds |
| Started | Aug 09 07:59:08 PM PDT 24 |
| Finished | Aug 09 08:03:02 PM PDT 24 |
| Peak memory | 604032 kb |
| Host | smart-1e457c63-7186-4abe-8c4b-ab60af70fa50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019307680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.3019307680 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.2329116842 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 79110866 ps |
| CPU time | 8.19 seconds |
| Started | Aug 09 07:59:05 PM PDT 24 |
| Finished | Aug 09 07:59:13 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-d8daf246-f3b1-45e0-8567-05dba2efa92f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329116842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .2329116842 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1365918350 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 17299985740 ps |
| CPU time | 277.94 seconds |
| Started | Aug 09 07:59:05 PM PDT 24 |
| Finished | Aug 09 08:03:43 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-bf720b13-7831-4d70-99e6-cc6c2a671c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365918350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.1365918350 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3205025279 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 314688853 ps |
| CPU time | 30.3 seconds |
| Started | Aug 09 07:59:10 PM PDT 24 |
| Finished | Aug 09 07:59:41 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-1f875628-a70d-43b9-bcac-4ef774bcfedf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205025279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.3205025279 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.2409460360 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 2214893701 ps |
| CPU time | 78.89 seconds |
| Started | Aug 09 07:59:08 PM PDT 24 |
| Finished | Aug 09 08:00:27 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-b770c6bc-1061-4a03-a8eb-0fc06657c109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409460360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2409460360 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.1932467696 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 1686555329 ps |
| CPU time | 65.16 seconds |
| Started | Aug 09 07:59:08 PM PDT 24 |
| Finished | Aug 09 08:00:13 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-a1ff329e-1ac3-4eea-b0dd-6379730fd470 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932467696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.1932467696 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.256949653 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 22920284324 ps |
| CPU time | 240.87 seconds |
| Started | Aug 09 07:59:07 PM PDT 24 |
| Finished | Aug 09 08:03:08 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-c4b1a0b4-2f1d-4997-8d4c-41ac344066ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256949653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.256949653 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1178133633 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 58193188091 ps |
| CPU time | 1033.44 seconds |
| Started | Aug 09 07:59:07 PM PDT 24 |
| Finished | Aug 09 08:16:21 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-fb43adc6-b546-4d68-a574-f6367e452363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178133633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1178133633 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.470201887 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 190218151 ps |
| CPU time | 19.97 seconds |
| Started | Aug 09 07:59:05 PM PDT 24 |
| Finished | Aug 09 07:59:25 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-5dcdcaa7-8dbc-4eb3-9718-f36ae2d43a55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470201887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_dela ys.470201887 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.979256014 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1452795809 ps |
| CPU time | 39.38 seconds |
| Started | Aug 09 07:59:11 PM PDT 24 |
| Finished | Aug 09 07:59:50 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-bcb10869-b9ff-4845-b742-53dbebdd3298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979256014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.979256014 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.230673968 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 49184396 ps |
| CPU time | 6.07 seconds |
| Started | Aug 09 07:59:04 PM PDT 24 |
| Finished | Aug 09 07:59:10 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-96e6974f-2157-49c1-a1b9-c089ff9647a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230673968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.230673968 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3342866621 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 10136504317 ps |
| CPU time | 106.11 seconds |
| Started | Aug 09 07:59:09 PM PDT 24 |
| Finished | Aug 09 08:00:55 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-d7526a6a-aff5-4437-847c-39cfd1d1140b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342866621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3342866621 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2635057655 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 4204347981 ps |
| CPU time | 67.12 seconds |
| Started | Aug 09 07:59:05 PM PDT 24 |
| Finished | Aug 09 08:00:13 PM PDT 24 |
| Peak memory | 574828 kb |
| Host | smart-ef7056c0-5794-4247-9665-21058839bf49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635057655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2635057655 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3111646471 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 47107708 ps |
| CPU time | 5.87 seconds |
| Started | Aug 09 07:59:12 PM PDT 24 |
| Finished | Aug 09 07:59:18 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-718d3d03-39f9-43d9-b749-d4b2e9afcbf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111646471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.3111646471 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.2658874104 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 2241149313 ps |
| CPU time | 88.6 seconds |
| Started | Aug 09 07:59:11 PM PDT 24 |
| Finished | Aug 09 08:00:39 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-17915395-81ed-4f58-bcbe-87cbacac591b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658874104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2658874104 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3530641447 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 521954508 ps |
| CPU time | 47.59 seconds |
| Started | Aug 09 07:59:10 PM PDT 24 |
| Finished | Aug 09 07:59:58 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-998c7bef-8275-488d-b9d1-31aa294e7695 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530641447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3530641447 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1311616443 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 187921517 ps |
| CPU time | 51.22 seconds |
| Started | Aug 09 07:59:16 PM PDT 24 |
| Finished | Aug 09 08:00:07 PM PDT 24 |
| Peak memory | 577016 kb |
| Host | smart-2c513a39-8143-44e7-99cd-15e63e23dd4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311616443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.1311616443 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3387067238 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 194880695 ps |
| CPU time | 81.79 seconds |
| Started | Aug 09 07:59:11 PM PDT 24 |
| Finished | Aug 09 08:00:33 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-8b0d5736-e3b7-4311-b1e8-cb5926ec07ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387067238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.3387067238 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2671819148 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 159809571 ps |
| CPU time | 9.28 seconds |
| Started | Aug 09 07:59:11 PM PDT 24 |
| Finished | Aug 09 07:59:21 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-fdb41ba8-ab05-4607-af49-4a27e277a21c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671819148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2671819148 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.848295642 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 10732194610 ps |
| CPU time | 799.17 seconds |
| Started | Aug 09 07:59:19 PM PDT 24 |
| Finished | Aug 09 08:12:38 PM PDT 24 |
| Peak memory | 648112 kb |
| Host | smart-15a2f590-341b-4424-b11d-8131618bf2a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848295642 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.848295642 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.1459128076 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 3823404318 ps |
| CPU time | 224.26 seconds |
| Started | Aug 09 07:59:15 PM PDT 24 |
| Finished | Aug 09 08:02:59 PM PDT 24 |
| Peak memory | 597484 kb |
| Host | smart-f2556e0d-dad5-437e-b275-2e75096c2f35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459128076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.1459128076 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3169108879 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 27890228069 ps |
| CPU time | 3845.53 seconds |
| Started | Aug 09 07:59:15 PM PDT 24 |
| Finished | Aug 09 09:03:21 PM PDT 24 |
| Peak memory | 593608 kb |
| Host | smart-8aa60c8a-8a56-4e06-a39f-55fe3763bf40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169108879 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3169108879 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.2945670145 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 164188828 ps |
| CPU time | 15.33 seconds |
| Started | Aug 09 07:59:19 PM PDT 24 |
| Finished | Aug 09 07:59:34 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-37b8e5a1-5ded-4e73-98c8-b60c4f460ab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945670145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .2945670145 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.4043523408 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 55731439482 ps |
| CPU time | 867.97 seconds |
| Started | Aug 09 07:59:17 PM PDT 24 |
| Finished | Aug 09 08:13:46 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-8c5a9e1a-8647-4efd-b744-bafd818b7327 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043523408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.4043523408 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.242851034 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 84459067 ps |
| CPU time | 12.69 seconds |
| Started | Aug 09 07:59:18 PM PDT 24 |
| Finished | Aug 09 07:59:31 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-525800a8-d1c6-4338-8899-8e64c89a04bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242851034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr .242851034 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.2744446067 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 265182535 ps |
| CPU time | 11.32 seconds |
| Started | Aug 09 07:59:18 PM PDT 24 |
| Finished | Aug 09 07:59:30 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-9823781a-2629-4414-b019-a768d946a127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744446067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2744446067 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.953385091 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 287679942 ps |
| CPU time | 13.61 seconds |
| Started | Aug 09 07:59:11 PM PDT 24 |
| Finished | Aug 09 07:59:25 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-7a35bf94-153d-4868-bbb4-d9ee92ec9d96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953385091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.953385091 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2353350679 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 42585377403 ps |
| CPU time | 457.24 seconds |
| Started | Aug 09 07:59:16 PM PDT 24 |
| Finished | Aug 09 08:06:54 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-218474cc-241e-4e97-92eb-f465fec0b4d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353350679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2353350679 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.712482626 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 53936409999 ps |
| CPU time | 932.31 seconds |
| Started | Aug 09 07:59:18 PM PDT 24 |
| Finished | Aug 09 08:14:51 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-f25c8648-07f4-4b63-aa11-a11c58f1b582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712482626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.712482626 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.2202704033 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 136922626 ps |
| CPU time | 14.58 seconds |
| Started | Aug 09 07:59:16 PM PDT 24 |
| Finished | Aug 09 07:59:31 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-5aadc4df-bd40-4265-b1f2-51bd77f1c5b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202704033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.2202704033 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.1897394625 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 413881735 ps |
| CPU time | 29.16 seconds |
| Started | Aug 09 07:59:15 PM PDT 24 |
| Finished | Aug 09 07:59:45 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-aaee5f69-6f8c-4018-9301-f9d65d023538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897394625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1897394625 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.4127944733 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 49600958 ps |
| CPU time | 6.54 seconds |
| Started | Aug 09 07:59:16 PM PDT 24 |
| Finished | Aug 09 07:59:23 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-218c8390-b5b9-49f6-bf75-d0664f70441c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127944733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.4127944733 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3409522357 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 9626178779 ps |
| CPU time | 95.42 seconds |
| Started | Aug 09 07:59:10 PM PDT 24 |
| Finished | Aug 09 08:00:46 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-d5535510-d8cd-4c88-8706-7fd8aa836130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409522357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3409522357 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.22163595 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 4584798247 ps |
| CPU time | 78.01 seconds |
| Started | Aug 09 07:59:15 PM PDT 24 |
| Finished | Aug 09 08:00:33 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-f5d6df3b-c47e-4e15-8628-1bce54ef03b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22163595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.22163595 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1054012079 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 44425409 ps |
| CPU time | 6.21 seconds |
| Started | Aug 09 07:59:09 PM PDT 24 |
| Finished | Aug 09 07:59:16 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-f984a17f-13ce-494a-b687-7b26213cd0f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054012079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.1054012079 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3747372748 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 17330920269 ps |
| CPU time | 637.67 seconds |
| Started | Aug 09 07:59:17 PM PDT 24 |
| Finished | Aug 09 08:09:55 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-b393a65e-ffa8-42e6-9eae-5583259473f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747372748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3747372748 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2087440858 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 636423762 ps |
| CPU time | 305.09 seconds |
| Started | Aug 09 07:59:18 PM PDT 24 |
| Finished | Aug 09 08:04:23 PM PDT 24 |
| Peak memory | 577060 kb |
| Host | smart-9925d9c7-096b-42cd-9fd8-935f36c1a331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087440858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.2087440858 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1568037269 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 597317032 ps |
| CPU time | 211.96 seconds |
| Started | Aug 09 07:59:15 PM PDT 24 |
| Finished | Aug 09 08:02:47 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-838a1ff6-e2e2-4df0-9679-f5db755920ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568037269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.1568037269 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2648387748 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 1045766919 ps |
| CPU time | 40.42 seconds |
| Started | Aug 09 07:59:18 PM PDT 24 |
| Finished | Aug 09 07:59:58 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-077529db-3f2d-45c6-bb42-3469f96df0fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648387748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2648387748 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.7001895 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 11835701548 ps |
| CPU time | 787.93 seconds |
| Started | Aug 09 07:59:32 PM PDT 24 |
| Finished | Aug 09 08:12:40 PM PDT 24 |
| Peak memory | 649240 kb |
| Host | smart-fb8bef03-5d08-47ed-8c1a-f63fa2646a09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7001895 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.7001895 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.1730396360 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 5129905205 ps |
| CPU time | 334.59 seconds |
| Started | Aug 09 07:59:29 PM PDT 24 |
| Finished | Aug 09 08:05:04 PM PDT 24 |
| Peak memory | 597644 kb |
| Host | smart-0917276f-2651-47fc-ae8a-0948b811d7f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730396360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.1730396360 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.659161256 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 14666814103 ps |
| CPU time | 2029.08 seconds |
| Started | Aug 09 07:59:16 PM PDT 24 |
| Finished | Aug 09 08:33:05 PM PDT 24 |
| Peak memory | 593624 kb |
| Host | smart-d1aedbad-c629-44ac-9886-473936c9c59c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659161256 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.chip_same_csr_outstanding.659161256 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.2466474224 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 4031588542 ps |
| CPU time | 367.22 seconds |
| Started | Aug 09 07:59:18 PM PDT 24 |
| Finished | Aug 09 08:05:25 PM PDT 24 |
| Peak memory | 604036 kb |
| Host | smart-7f0fd062-e3ed-47e4-8275-5e8978e9ff60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466474224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.2466474224 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.1690326245 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 518348377 ps |
| CPU time | 20.8 seconds |
| Started | Aug 09 07:59:24 PM PDT 24 |
| Finished | Aug 09 07:59:45 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-701ce45c-c7dc-48de-9d05-5a36d80447ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690326245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .1690326245 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1204471126 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 855032771 ps |
| CPU time | 33.27 seconds |
| Started | Aug 09 07:59:30 PM PDT 24 |
| Finished | Aug 09 08:00:04 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-68ae78ab-1e16-4664-9653-c4580e04eb2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204471126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.1204471126 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.2364711961 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 815381564 ps |
| CPU time | 26.83 seconds |
| Started | Aug 09 07:59:30 PM PDT 24 |
| Finished | Aug 09 07:59:57 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-9821a5b0-64ae-4ede-9b95-fbec2799d591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364711961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2364711961 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.4214743119 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 555914334 ps |
| CPU time | 23.91 seconds |
| Started | Aug 09 07:59:25 PM PDT 24 |
| Finished | Aug 09 07:59:49 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-bf32fcc1-2038-46c1-bab1-d051b8c4392d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214743119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.4214743119 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.71994838 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 79409088386 ps |
| CPU time | 798.78 seconds |
| Started | Aug 09 07:59:25 PM PDT 24 |
| Finished | Aug 09 08:12:44 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-9d899489-7044-4485-867e-37d844c2a09b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71994838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.71994838 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1918389376 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 2947509431 ps |
| CPU time | 47.74 seconds |
| Started | Aug 09 07:59:22 PM PDT 24 |
| Finished | Aug 09 08:00:10 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-01254f86-9073-4a40-8da8-614df9fea215 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918389376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1918389376 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3521921140 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 391409724 ps |
| CPU time | 40.7 seconds |
| Started | Aug 09 07:59:23 PM PDT 24 |
| Finished | Aug 09 08:00:04 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-f3ef40af-5108-4ece-98d0-a7e12b7ddc04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521921140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.3521921140 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.3071264396 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 2002890386 ps |
| CPU time | 59.14 seconds |
| Started | Aug 09 07:59:33 PM PDT 24 |
| Finished | Aug 09 08:00:32 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-5a0688a1-1b37-4b5b-9724-0819d358f15d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071264396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3071264396 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.858726769 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 182495174 ps |
| CPU time | 8.68 seconds |
| Started | Aug 09 07:59:23 PM PDT 24 |
| Finished | Aug 09 07:59:32 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-fb5feb86-8ab1-4742-8d27-05809ff153a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858726769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.858726769 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.3460373980 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 6419424608 ps |
| CPU time | 65.27 seconds |
| Started | Aug 09 07:59:25 PM PDT 24 |
| Finished | Aug 09 08:00:30 PM PDT 24 |
| Peak memory | 574864 kb |
| Host | smart-f36861f6-bf11-44f7-bb0f-bef63005e7a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460373980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3460373980 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.3868183959 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 4287704593 ps |
| CPU time | 73.2 seconds |
| Started | Aug 09 07:59:23 PM PDT 24 |
| Finished | Aug 09 08:00:36 PM PDT 24 |
| Peak memory | 574904 kb |
| Host | smart-33872701-2922-4154-80cf-393fe8bbb48a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868183959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3868183959 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.977273173 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 41250151 ps |
| CPU time | 6.17 seconds |
| Started | Aug 09 07:59:22 PM PDT 24 |
| Finished | Aug 09 07:59:28 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-d8b68fdb-afbd-42ab-a692-d1faef726e3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977273173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays .977273173 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.605123675 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 2978023878 ps |
| CPU time | 217.14 seconds |
| Started | Aug 09 07:59:36 PM PDT 24 |
| Finished | Aug 09 08:03:14 PM PDT 24 |
| Peak memory | 577100 kb |
| Host | smart-225fde23-317d-4aa2-92b2-fcff74e814cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605123675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.605123675 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.546969237 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 11894212081 ps |
| CPU time | 463.9 seconds |
| Started | Aug 09 07:59:31 PM PDT 24 |
| Finished | Aug 09 08:07:15 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-55d596d4-9f0f-4605-a6b3-253266301b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546969237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.546969237 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1466505926 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 2445132068 ps |
| CPU time | 486.43 seconds |
| Started | Aug 09 07:59:34 PM PDT 24 |
| Finished | Aug 09 08:07:40 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-d0324cc2-9fc9-47c9-81e3-072e7a43479d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466505926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.1466505926 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2980360511 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 432318470 ps |
| CPU time | 111.03 seconds |
| Started | Aug 09 07:59:33 PM PDT 24 |
| Finished | Aug 09 08:01:24 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-c9b54af9-bc92-4d88-9514-676dac93dca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980360511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.2980360511 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.3629200355 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 637077269 ps |
| CPU time | 27.08 seconds |
| Started | Aug 09 07:59:29 PM PDT 24 |
| Finished | Aug 09 07:59:56 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-fca4f4cc-5e18-4229-8695-5c87151cb114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629200355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3629200355 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.362019017 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 6994169035 ps |
| CPU time | 422.22 seconds |
| Started | Aug 09 07:59:42 PM PDT 24 |
| Finished | Aug 09 08:06:44 PM PDT 24 |
| Peak memory | 638808 kb |
| Host | smart-0df75fbb-c08f-4bdf-8568-aa2f8f23f72f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362019017 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.362019017 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.234336703 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 3786350575 ps |
| CPU time | 299.14 seconds |
| Started | Aug 09 07:59:42 PM PDT 24 |
| Finished | Aug 09 08:04:41 PM PDT 24 |
| Peak memory | 597288 kb |
| Host | smart-1f40271f-4b26-40df-9153-0ee61c418bfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234336703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.234336703 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3430813041 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 32633204183 ps |
| CPU time | 4156.5 seconds |
| Started | Aug 09 07:59:38 PM PDT 24 |
| Finished | Aug 09 09:08:55 PM PDT 24 |
| Peak memory | 593908 kb |
| Host | smart-0e5f87aa-2936-4a18-9e1d-27c75ece6cef |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430813041 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.3430813041 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.2284320503 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 4396770442 ps |
| CPU time | 304.59 seconds |
| Started | Aug 09 07:59:36 PM PDT 24 |
| Finished | Aug 09 08:04:41 PM PDT 24 |
| Peak memory | 603924 kb |
| Host | smart-9c6140ad-4988-4160-a942-ebdbd814f66d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284320503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.2284320503 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.1774312983 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 2608944659 ps |
| CPU time | 118.87 seconds |
| Started | Aug 09 07:59:38 PM PDT 24 |
| Finished | Aug 09 08:01:37 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-5a432bc9-0512-4909-acf4-fdd0be90cfae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774312983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .1774312983 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3773194790 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 125672888495 ps |
| CPU time | 2042.76 seconds |
| Started | Aug 09 07:59:37 PM PDT 24 |
| Finished | Aug 09 08:33:40 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-280a6245-d2e7-413a-9fb6-6b634d10006d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773194790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.3773194790 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.420760386 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 1374760260 ps |
| CPU time | 55.97 seconds |
| Started | Aug 09 07:59:46 PM PDT 24 |
| Finished | Aug 09 08:00:42 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-04d61850-3145-49f8-b4b9-8f184630c10f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420760386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr .420760386 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.2844131357 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 542541749 ps |
| CPU time | 48.33 seconds |
| Started | Aug 09 07:59:46 PM PDT 24 |
| Finished | Aug 09 08:00:35 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-58444dd6-da0d-4bcf-b916-826619816cd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844131357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2844131357 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.975247057 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 1428190306 ps |
| CPU time | 51.77 seconds |
| Started | Aug 09 07:59:39 PM PDT 24 |
| Finished | Aug 09 08:00:31 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-5125de24-a53f-44c6-acdd-b6bce9ef6dd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975247057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.975247057 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.2648434903 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 76748961840 ps |
| CPU time | 817.78 seconds |
| Started | Aug 09 07:59:38 PM PDT 24 |
| Finished | Aug 09 08:13:16 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-de07a8b6-ad36-42b7-947d-c3c469eb03dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648434903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2648434903 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.568607159 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 26284469795 ps |
| CPU time | 407.26 seconds |
| Started | Aug 09 07:59:37 PM PDT 24 |
| Finished | Aug 09 08:06:24 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-6bbcb80b-5707-4a73-9287-f74bbb71a520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568607159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.568607159 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.3257513110 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 215015845 ps |
| CPU time | 19.02 seconds |
| Started | Aug 09 07:59:41 PM PDT 24 |
| Finished | Aug 09 08:00:00 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-7fc26c0f-60b3-4192-85ab-8c015e1384f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257513110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.3257513110 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.1419080543 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 325358047 ps |
| CPU time | 13.1 seconds |
| Started | Aug 09 07:59:46 PM PDT 24 |
| Finished | Aug 09 07:59:59 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-7d18cf54-dcdf-488a-bf95-9f4694647093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419080543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1419080543 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.631449441 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 52332953 ps |
| CPU time | 6.25 seconds |
| Started | Aug 09 07:59:30 PM PDT 24 |
| Finished | Aug 09 07:59:36 PM PDT 24 |
| Peak memory | 574844 kb |
| Host | smart-2014915c-bfed-4e0f-ac9b-030ad2f4eb14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631449441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.631449441 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.293577908 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 10004365151 ps |
| CPU time | 100.06 seconds |
| Started | Aug 09 07:59:32 PM PDT 24 |
| Finished | Aug 09 08:01:12 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-be50c0e4-e121-4aba-920c-b8a92826c3e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293577908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.293577908 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3818713260 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 3754076172 ps |
| CPU time | 64.1 seconds |
| Started | Aug 09 07:59:30 PM PDT 24 |
| Finished | Aug 09 08:00:34 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-d1f14ca7-70af-424d-a936-ff5781997bcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818713260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3818713260 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2989298121 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 50135340 ps |
| CPU time | 6.35 seconds |
| Started | Aug 09 07:59:36 PM PDT 24 |
| Finished | Aug 09 07:59:42 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-a2c4f6af-2288-44d4-b642-f4b4a53c165e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989298121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.2989298121 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.625119577 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 8526274553 ps |
| CPU time | 337.04 seconds |
| Started | Aug 09 07:59:47 PM PDT 24 |
| Finished | Aug 09 08:05:24 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-b0bc1402-d3bb-4eed-837b-7360484b997f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625119577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.625119577 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.3738846398 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 1071326456 ps |
| CPU time | 33.69 seconds |
| Started | Aug 09 07:59:38 PM PDT 24 |
| Finished | Aug 09 08:00:11 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-a318b674-5a0d-4446-bde2-e99b35116120 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738846398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3738846398 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1298363443 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 10633904312 ps |
| CPU time | 532.92 seconds |
| Started | Aug 09 07:59:43 PM PDT 24 |
| Finished | Aug 09 08:08:36 PM PDT 24 |
| Peak memory | 577164 kb |
| Host | smart-f6248210-19d9-4a08-9a78-82244a5e8994 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298363443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.1298363443 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3337834365 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 132615374 ps |
| CPU time | 14.33 seconds |
| Started | Aug 09 07:59:41 PM PDT 24 |
| Finished | Aug 09 07:59:56 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-2e372356-bc81-4602-9ee7-71509e746af3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337834365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3337834365 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.749931779 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 5658582925 ps |
| CPU time | 404.63 seconds |
| Started | Aug 09 07:59:54 PM PDT 24 |
| Finished | Aug 09 08:06:39 PM PDT 24 |
| Peak memory | 639880 kb |
| Host | smart-f6b24938-1f83-4b06-8ade-f94dca339af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749931779 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.749931779 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.860463862 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 6690229764 ps |
| CPU time | 611.86 seconds |
| Started | Aug 09 07:59:52 PM PDT 24 |
| Finished | Aug 09 08:10:04 PM PDT 24 |
| Peak memory | 598948 kb |
| Host | smart-b8293fcf-903f-4cdb-b278-a28bd7e2669c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860463862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.860463862 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.694657166 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 31250062390 ps |
| CPU time | 4405.14 seconds |
| Started | Aug 09 07:59:44 PM PDT 24 |
| Finished | Aug 09 09:13:10 PM PDT 24 |
| Peak memory | 593724 kb |
| Host | smart-837f44a9-2932-47a4-8e7d-3bd39581104b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694657166 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.chip_same_csr_outstanding.694657166 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.2195400755 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 3522958880 ps |
| CPU time | 211.91 seconds |
| Started | Aug 09 07:59:46 PM PDT 24 |
| Finished | Aug 09 08:03:18 PM PDT 24 |
| Peak memory | 604140 kb |
| Host | smart-c46587ad-4a9c-4c91-ab67-aac072c3f5de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195400755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.2195400755 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.3274513966 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 1019226785 ps |
| CPU time | 69.22 seconds |
| Started | Aug 09 07:59:46 PM PDT 24 |
| Finished | Aug 09 08:00:55 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-0372469c-dbb2-40bf-8c6e-4780b07d5be4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274513966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .3274513966 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2212155622 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 113341039627 ps |
| CPU time | 1919.06 seconds |
| Started | Aug 09 07:59:52 PM PDT 24 |
| Finished | Aug 09 08:31:51 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-15f026f8-f762-41ae-b231-d03d62c6a3bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212155622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.2212155622 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.4063985602 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 765614598 ps |
| CPU time | 29.16 seconds |
| Started | Aug 09 07:59:49 PM PDT 24 |
| Finished | Aug 09 08:00:18 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-f98c1a14-5d64-4cfa-a492-39e89bcb109c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063985602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.4063985602 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.1444296328 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 297555595 ps |
| CPU time | 25.89 seconds |
| Started | Aug 09 07:59:50 PM PDT 24 |
| Finished | Aug 09 08:00:16 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-84ed9a7a-df2c-423e-97fd-f67f075f4790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444296328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1444296328 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.161193158 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1900344450 ps |
| CPU time | 70.36 seconds |
| Started | Aug 09 07:59:44 PM PDT 24 |
| Finished | Aug 09 08:00:54 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-51fd1e64-b958-42bd-86d6-11aa39b33d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161193158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.161193158 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.3455225156 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 96887124187 ps |
| CPU time | 952.66 seconds |
| Started | Aug 09 07:59:42 PM PDT 24 |
| Finished | Aug 09 08:15:35 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-b8f130bb-403c-4dcf-85ae-ea6c63c5cc63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455225156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3455225156 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1849084855 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 32768877559 ps |
| CPU time | 591.34 seconds |
| Started | Aug 09 07:59:43 PM PDT 24 |
| Finished | Aug 09 08:09:34 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-bf8f7cbb-9a0c-47cb-9007-80ad8b0ee07d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849084855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1849084855 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3254282303 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 213757424 ps |
| CPU time | 19.61 seconds |
| Started | Aug 09 07:59:44 PM PDT 24 |
| Finished | Aug 09 08:00:03 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-12489897-5e52-498f-9598-d8ccdbba2b79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254282303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.3254282303 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.2539927986 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 567134240 ps |
| CPU time | 36.52 seconds |
| Started | Aug 09 07:59:52 PM PDT 24 |
| Finished | Aug 09 08:00:29 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-a646c1d5-2aac-49af-9e84-ffffb3889739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539927986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2539927986 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.3403300911 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 180449050 ps |
| CPU time | 7.61 seconds |
| Started | Aug 09 07:59:42 PM PDT 24 |
| Finished | Aug 09 07:59:50 PM PDT 24 |
| Peak memory | 574856 kb |
| Host | smart-b90000e2-a83d-4c29-8bea-6be71e0bb467 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403300911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3403300911 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.2287374482 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 6654482905 ps |
| CPU time | 63.81 seconds |
| Started | Aug 09 07:59:46 PM PDT 24 |
| Finished | Aug 09 08:00:50 PM PDT 24 |
| Peak memory | 574892 kb |
| Host | smart-5a55e449-e948-491c-9eb3-01c2e8e99a3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287374482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2287374482 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1820177711 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 4683005052 ps |
| CPU time | 68.67 seconds |
| Started | Aug 09 07:59:44 PM PDT 24 |
| Finished | Aug 09 08:00:52 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-adcb2df0-e3ed-4aaf-bccd-6ede59510a95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820177711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1820177711 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1119582519 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 51798593 ps |
| CPU time | 6.01 seconds |
| Started | Aug 09 07:59:45 PM PDT 24 |
| Finished | Aug 09 07:59:51 PM PDT 24 |
| Peak memory | 574840 kb |
| Host | smart-d1c4a597-6868-4a76-830e-ec879c13baf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119582519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.1119582519 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.4103329129 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 2133776349 ps |
| CPU time | 163.62 seconds |
| Started | Aug 09 07:59:54 PM PDT 24 |
| Finished | Aug 09 08:02:37 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-c8fc62f9-3a42-4420-a44b-d893b424d6fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103329129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.4103329129 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3034481350 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 4606908449 ps |
| CPU time | 161.87 seconds |
| Started | Aug 09 07:59:50 PM PDT 24 |
| Finished | Aug 09 08:02:32 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-2c9efd5d-6129-408b-af6c-70e9788d914c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034481350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3034481350 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3842611151 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 5137162376 ps |
| CPU time | 263.14 seconds |
| Started | Aug 09 07:59:49 PM PDT 24 |
| Finished | Aug 09 08:04:12 PM PDT 24 |
| Peak memory | 577136 kb |
| Host | smart-4dea6f9d-e3d0-4704-9a57-694995ffb6b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842611151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.3842611151 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.4045885539 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 115114632 ps |
| CPU time | 16.6 seconds |
| Started | Aug 09 07:59:50 PM PDT 24 |
| Finished | Aug 09 08:00:06 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-f33a320c-d83a-4ad3-b5ee-432da580b61c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045885539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.4045885539 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.445540094 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 5989291670 ps |
| CPU time | 542.79 seconds |
| Started | Aug 09 08:00:04 PM PDT 24 |
| Finished | Aug 09 08:09:09 PM PDT 24 |
| Peak memory | 638536 kb |
| Host | smart-cc281201-6a54-42f1-bc64-d17ec55eda24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445540094 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.445540094 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.2398643941 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 6031297508 ps |
| CPU time | 545.24 seconds |
| Started | Aug 09 08:00:02 PM PDT 24 |
| Finished | Aug 09 08:09:11 PM PDT 24 |
| Peak memory | 599280 kb |
| Host | smart-6b69038f-12f0-432b-ab80-eadb6bf57e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398643941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.2398643941 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.2206615049 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 670725091 ps |
| CPU time | 30.07 seconds |
| Started | Aug 09 07:59:58 PM PDT 24 |
| Finished | Aug 09 08:00:29 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-1b8bd638-1515-4f94-9fff-81fcd0556f1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206615049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .2206615049 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.54142527 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 10811441872 ps |
| CPU time | 187.85 seconds |
| Started | Aug 09 07:59:57 PM PDT 24 |
| Finished | Aug 09 08:03:05 PM PDT 24 |
| Peak memory | 574860 kb |
| Host | smart-1fea9d08-fa3f-44d7-9c55-bfef5d03a4a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54142527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_de vice_slow_rsp.54142527 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1585094357 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 42909582 ps |
| CPU time | 7.33 seconds |
| Started | Aug 09 08:00:03 PM PDT 24 |
| Finished | Aug 09 08:00:13 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-1a355e6e-a513-45d6-9a00-433413a8d811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585094357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.1585094357 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.1843243876 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 2400748871 ps |
| CPU time | 75.25 seconds |
| Started | Aug 09 07:59:58 PM PDT 24 |
| Finished | Aug 09 08:01:14 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-55d1dd22-09d8-4062-8172-87b3e08ea4ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843243876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1843243876 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.2292797515 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 424393499 ps |
| CPU time | 36.52 seconds |
| Started | Aug 09 07:59:57 PM PDT 24 |
| Finished | Aug 09 08:00:33 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-90cfa8a8-c252-4abb-8f3a-4345a2e76b4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292797515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.2292797515 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2323503140 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 61110005720 ps |
| CPU time | 593.43 seconds |
| Started | Aug 09 07:59:57 PM PDT 24 |
| Finished | Aug 09 08:09:50 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-e3214479-faf4-47f4-b5df-88416a632923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323503140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2323503140 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2636353325 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 16896168686 ps |
| CPU time | 292.63 seconds |
| Started | Aug 09 07:59:55 PM PDT 24 |
| Finished | Aug 09 08:04:47 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-aac04894-87f6-44e8-ba5e-106e9b74aeed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636353325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2636353325 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2207276577 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 476712410 ps |
| CPU time | 39.28 seconds |
| Started | Aug 09 07:59:57 PM PDT 24 |
| Finished | Aug 09 08:00:37 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-ddeba8e0-80a6-49d8-a831-949272f0c5e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207276577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.2207276577 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.3860592505 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 2710023418 ps |
| CPU time | 78.69 seconds |
| Started | Aug 09 07:59:58 PM PDT 24 |
| Finished | Aug 09 08:01:16 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-bc4acbfc-9bf0-427a-93c8-8061973df730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860592505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3860592505 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.2054055409 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 48257229 ps |
| CPU time | 5.9 seconds |
| Started | Aug 09 07:59:51 PM PDT 24 |
| Finished | Aug 09 07:59:57 PM PDT 24 |
| Peak memory | 574820 kb |
| Host | smart-291c28db-d1f1-4349-8d14-d26c7dd691bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054055409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2054055409 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.3137673331 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 9256229223 ps |
| CPU time | 90.97 seconds |
| Started | Aug 09 07:59:50 PM PDT 24 |
| Finished | Aug 09 08:01:21 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-4c30eb06-a3a2-4598-8e3c-f94450bf4b67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137673331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3137673331 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3878343209 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 6584806823 ps |
| CPU time | 112.76 seconds |
| Started | Aug 09 07:59:53 PM PDT 24 |
| Finished | Aug 09 08:01:46 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-a0513369-33f9-49a3-ad71-fc409edae0ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878343209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3878343209 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3452910903 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 53234849 ps |
| CPU time | 6.49 seconds |
| Started | Aug 09 07:59:54 PM PDT 24 |
| Finished | Aug 09 08:00:01 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-699d8974-dfd8-441a-bb48-914c6bab01f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452910903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.3452910903 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.198347728 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 6956747790 ps |
| CPU time | 261.47 seconds |
| Started | Aug 09 08:00:02 PM PDT 24 |
| Finished | Aug 09 08:04:27 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-c270d1b2-d79c-4434-b5aa-a53158b08785 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198347728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.198347728 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.2329626370 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 3295278952 ps |
| CPU time | 271.35 seconds |
| Started | Aug 09 08:00:04 PM PDT 24 |
| Finished | Aug 09 08:04:37 PM PDT 24 |
| Peak memory | 577144 kb |
| Host | smart-3c224c8d-d71f-4e64-8664-8d4af72ac511 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329626370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2329626370 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.632282820 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 1937584551 ps |
| CPU time | 302.6 seconds |
| Started | Aug 09 08:00:04 PM PDT 24 |
| Finished | Aug 09 08:05:08 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-1bbb71c0-7d8a-45b6-a8a8-b9afc9a4f9a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632282820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_ with_rand_reset.632282820 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3968449438 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 580483451 ps |
| CPU time | 140.47 seconds |
| Started | Aug 09 08:00:04 PM PDT 24 |
| Finished | Aug 09 08:02:26 PM PDT 24 |
| Peak memory | 577032 kb |
| Host | smart-11a74b3e-7db9-48e0-af55-80942075667d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968449438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.3968449438 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.830762771 |
| Short name | T2935 |
| Test name | |
| Test status | |
| Simulation time | 969775740 ps |
| CPU time | 41.01 seconds |
| Started | Aug 09 07:59:55 PM PDT 24 |
| Finished | Aug 09 08:00:36 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-77da7875-869d-4695-9b85-acc4dd352639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830762771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.830762771 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.303613942 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 32893724030 ps |
| CPU time | 5466.83 seconds |
| Started | Aug 09 07:57:38 PM PDT 24 |
| Finished | Aug 09 09:28:45 PM PDT 24 |
| Peak memory | 594392 kb |
| Host | smart-f1193cf4-8d7c-4f70-a581-58bc6c6ce874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303613942 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.chip_csr_aliasing.303613942 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.221701089 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 6325625920 ps |
| CPU time | 440.34 seconds |
| Started | Aug 09 07:57:37 PM PDT 24 |
| Finished | Aug 09 08:04:58 PM PDT 24 |
| Peak memory | 592840 kb |
| Host | smart-0feaa880-3bbf-4443-b819-a92aa6296016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221701089 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.221701089 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.426320145 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 8388657936 ps |
| CPU time | 754.96 seconds |
| Started | Aug 09 07:57:46 PM PDT 24 |
| Finished | Aug 09 08:10:21 PM PDT 24 |
| Peak memory | 650432 kb |
| Host | smart-9ec7a07d-3223-471b-be21-c7f1d47322d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426320145 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.426320145 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.3584058248 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 4908557940 ps |
| CPU time | 365.43 seconds |
| Started | Aug 09 07:57:46 PM PDT 24 |
| Finished | Aug 09 08:03:52 PM PDT 24 |
| Peak memory | 598372 kb |
| Host | smart-410db37d-c0d5-45e6-960f-211ebaed105a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584058248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3584058248 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.1982747359 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 9473615730 ps |
| CPU time | 479.32 seconds |
| Started | Aug 09 07:57:41 PM PDT 24 |
| Finished | Aug 09 08:05:40 PM PDT 24 |
| Peak memory | 590852 kb |
| Host | smart-eea0cda5-4616-4c6c-b15a-92ba067a4d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982747359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.1982747359 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.800347258 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 11920224741 ps |
| CPU time | 488.61 seconds |
| Started | Aug 09 07:57:41 PM PDT 24 |
| Finished | Aug 09 08:05:50 PM PDT 24 |
| Peak memory | 599776 kb |
| Host | smart-83346354-19eb-4e62-b47b-3034cf570c4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800347258 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.chip_rv_dm_lc_disabled.800347258 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2777392672 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 30060778556 ps |
| CPU time | 3744.23 seconds |
| Started | Aug 09 07:57:40 PM PDT 24 |
| Finished | Aug 09 09:00:05 PM PDT 24 |
| Peak memory | 593252 kb |
| Host | smart-9d77a7c5-3dba-487e-96fc-c900762aec1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777392672 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2777392672 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.235789954 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 2132592510 ps |
| CPU time | 84 seconds |
| Started | Aug 09 07:57:40 PM PDT 24 |
| Finished | Aug 09 07:59:04 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-04252ea2-1bb6-4657-8518-2554662b90a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235789954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.235789954 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2350054741 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 42659563498 ps |
| CPU time | 641.05 seconds |
| Started | Aug 09 07:57:46 PM PDT 24 |
| Finished | Aug 09 08:08:27 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-3f6258ea-017d-4412-8b71-af39dc5aa32d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350054741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.2350054741 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1373556597 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 377683430 ps |
| CPU time | 15.36 seconds |
| Started | Aug 09 07:57:38 PM PDT 24 |
| Finished | Aug 09 07:57:54 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-bf982c60-852e-4fb6-ac01-d374bebd4003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373556597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .1373556597 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.2174488934 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 54194940 ps |
| CPU time | 6.93 seconds |
| Started | Aug 09 07:57:47 PM PDT 24 |
| Finished | Aug 09 07:57:54 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-f61daa62-c58a-4437-bdbc-1f50f3ba8e42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174488934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2174488934 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.1603589630 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 600906668 ps |
| CPU time | 23.34 seconds |
| Started | Aug 09 07:57:50 PM PDT 24 |
| Finished | Aug 09 07:58:14 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-5bb8423a-e89a-4b64-aac2-7038939a581f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603589630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.1603589630 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.56905223 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 103060041313 ps |
| CPU time | 1100.88 seconds |
| Started | Aug 09 07:57:40 PM PDT 24 |
| Finished | Aug 09 08:16:01 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-68f70b4f-f7e5-4a49-92c4-faf1e720673a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56905223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.56905223 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.1136299500 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 61595375282 ps |
| CPU time | 1053.13 seconds |
| Started | Aug 09 07:57:45 PM PDT 24 |
| Finished | Aug 09 08:15:19 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-a83a72d8-1c08-459f-9c02-39e4c91fb912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136299500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1136299500 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.3427266076 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 247746818 ps |
| CPU time | 21.87 seconds |
| Started | Aug 09 07:57:50 PM PDT 24 |
| Finished | Aug 09 07:58:12 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-04b46808-fc51-4791-9ae6-0a12ebf2c2a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427266076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.3427266076 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.100309729 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 344750061 ps |
| CPU time | 25.28 seconds |
| Started | Aug 09 07:57:39 PM PDT 24 |
| Finished | Aug 09 07:58:04 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-8daea2b2-159b-4c69-855e-a39ede0833b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100309729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.100309729 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.2435443645 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 211177999 ps |
| CPU time | 8.64 seconds |
| Started | Aug 09 07:57:41 PM PDT 24 |
| Finished | Aug 09 07:57:49 PM PDT 24 |
| Peak memory | 574812 kb |
| Host | smart-2a197b01-e10d-418d-aad4-d7ac88386aa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435443645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2435443645 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1583548036 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 6685639133 ps |
| CPU time | 68.12 seconds |
| Started | Aug 09 07:57:40 PM PDT 24 |
| Finished | Aug 09 07:58:48 PM PDT 24 |
| Peak memory | 574900 kb |
| Host | smart-15f1fbce-800c-4f85-9327-bf32fb4e6b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583548036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1583548036 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.929234361 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 4669803183 ps |
| CPU time | 78.58 seconds |
| Started | Aug 09 07:57:39 PM PDT 24 |
| Finished | Aug 09 07:58:58 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-cbbb267a-a3a9-4235-8e20-0c1e7f2deef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929234361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.929234361 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3698189383 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 47551928 ps |
| CPU time | 5.91 seconds |
| Started | Aug 09 07:57:36 PM PDT 24 |
| Finished | Aug 09 07:57:42 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-026ae825-ffbd-4cf7-965c-8bde5c00e285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698189383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .3698189383 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.1226681071 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 3735009883 ps |
| CPU time | 270.71 seconds |
| Started | Aug 09 07:57:41 PM PDT 24 |
| Finished | Aug 09 08:02:12 PM PDT 24 |
| Peak memory | 577120 kb |
| Host | smart-e893e933-ce90-4f13-90f5-0a60c5870f9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226681071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1226681071 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.3326744202 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 9821027961 ps |
| CPU time | 309.47 seconds |
| Started | Aug 09 07:57:44 PM PDT 24 |
| Finished | Aug 09 08:02:53 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-c40a95d8-8715-49e4-96be-d2ffa3d9a254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326744202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3326744202 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2481825157 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 92373415 ps |
| CPU time | 19.86 seconds |
| Started | Aug 09 07:57:40 PM PDT 24 |
| Finished | Aug 09 07:58:00 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-e32c3253-7165-4ef0-9fbd-1b0e05291a0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481825157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.2481825157 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.3418401075 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 7509750713 ps |
| CPU time | 430.46 seconds |
| Started | Aug 09 07:57:46 PM PDT 24 |
| Finished | Aug 09 08:04:56 PM PDT 24 |
| Peak memory | 577124 kb |
| Host | smart-327221b5-557e-461c-983f-8144c62d6367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418401075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.3418401075 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.3790347003 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 1122846949 ps |
| CPU time | 44.98 seconds |
| Started | Aug 09 07:57:40 PM PDT 24 |
| Finished | Aug 09 07:58:25 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-a3d1fc9e-4cb2-4554-ad9f-794bff5eff25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790347003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3790347003 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.1931684890 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 3261008254 ps |
| CPU time | 192.41 seconds |
| Started | Aug 09 08:00:07 PM PDT 24 |
| Finished | Aug 09 08:03:19 PM PDT 24 |
| Peak memory | 598824 kb |
| Host | smart-ad4c2a6e-a7e1-4051-872a-3659cc40e9a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931684890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.1931684890 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.131436733 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 1924744263 ps |
| CPU time | 79.25 seconds |
| Started | Aug 09 08:00:08 PM PDT 24 |
| Finished | Aug 09 08:01:28 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-46f2f749-cf97-4928-b0c1-9a70e6e6a872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131436733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device. 131436733 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2103916706 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 69761101587 ps |
| CPU time | 1307.04 seconds |
| Started | Aug 09 08:00:09 PM PDT 24 |
| Finished | Aug 09 08:21:57 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-2cdc1d21-f315-436c-9caa-c475388a1be3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103916706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.2103916706 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.103824625 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 187480439 ps |
| CPU time | 21.09 seconds |
| Started | Aug 09 08:00:11 PM PDT 24 |
| Finished | Aug 09 08:00:32 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-4015d76c-d43c-4e5d-ac3e-c122999e952f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103824625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr .103824625 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.4207136200 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 282852115 ps |
| CPU time | 22.51 seconds |
| Started | Aug 09 08:00:09 PM PDT 24 |
| Finished | Aug 09 08:00:31 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-3fd73266-3531-49e9-b82e-60865a4d82c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207136200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.4207136200 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.3897036998 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 108441672 ps |
| CPU time | 7.58 seconds |
| Started | Aug 09 08:00:04 PM PDT 24 |
| Finished | Aug 09 08:00:13 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-9155846e-65c2-4b78-97f2-7aa297dd2754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897036998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.3897036998 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.968844516 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 85103959008 ps |
| CPU time | 828.02 seconds |
| Started | Aug 09 08:00:12 PM PDT 24 |
| Finished | Aug 09 08:14:00 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-187cddff-9122-4a7b-8a93-54b7009bbba0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968844516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.968844516 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.1816770859 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 58484980330 ps |
| CPU time | 988.34 seconds |
| Started | Aug 09 08:00:10 PM PDT 24 |
| Finished | Aug 09 08:16:38 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-521b6327-9344-47b1-95e2-5fb220d039a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816770859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1816770859 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1290537221 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 152145323 ps |
| CPU time | 15.28 seconds |
| Started | Aug 09 08:00:09 PM PDT 24 |
| Finished | Aug 09 08:00:24 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-4cc8f87a-9c85-4b29-9bdd-087009ef4fc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290537221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.1290537221 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.672041322 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 480946870 ps |
| CPU time | 34.47 seconds |
| Started | Aug 09 08:00:09 PM PDT 24 |
| Finished | Aug 09 08:00:44 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-6f39a7a5-21a7-4682-bc5a-6844dc7844fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672041322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.672041322 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.2044386602 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 185577164 ps |
| CPU time | 8.87 seconds |
| Started | Aug 09 08:00:04 PM PDT 24 |
| Finished | Aug 09 08:00:15 PM PDT 24 |
| Peak memory | 574864 kb |
| Host | smart-2f41453e-49ae-4671-8921-afcc46472e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044386602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2044386602 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.2381623382 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 5124534785 ps |
| CPU time | 54.35 seconds |
| Started | Aug 09 08:00:04 PM PDT 24 |
| Finished | Aug 09 08:01:00 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-ca987508-1608-408f-bf28-0ee565cfe43f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381623382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2381623382 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2469226983 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 3764888407 ps |
| CPU time | 66.57 seconds |
| Started | Aug 09 08:00:05 PM PDT 24 |
| Finished | Aug 09 08:01:12 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-8f9e6bf3-9cac-4c54-945c-18584dd58103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469226983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2469226983 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2248792095 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 44686535 ps |
| CPU time | 6.31 seconds |
| Started | Aug 09 08:00:03 PM PDT 24 |
| Finished | Aug 09 08:00:12 PM PDT 24 |
| Peak memory | 574776 kb |
| Host | smart-8a01a5e0-9aab-49bf-b943-02c5ac73197c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248792095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.2248792095 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.3185623450 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 14119325713 ps |
| CPU time | 509.71 seconds |
| Started | Aug 09 08:00:12 PM PDT 24 |
| Finished | Aug 09 08:08:42 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-1ebd57d2-cf33-4fd5-9981-29b6e888ae6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185623450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3185623450 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.3238335735 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 12233407912 ps |
| CPU time | 412.06 seconds |
| Started | Aug 09 08:00:13 PM PDT 24 |
| Finished | Aug 09 08:07:05 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-5cee6a8c-c993-4183-8798-91038532bca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238335735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3238335735 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.4208225186 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 471078890 ps |
| CPU time | 92.33 seconds |
| Started | Aug 09 08:00:11 PM PDT 24 |
| Finished | Aug 09 08:01:44 PM PDT 24 |
| Peak memory | 577048 kb |
| Host | smart-59a9f094-f439-441e-ad63-f969730d98af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208225186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.4208225186 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1653573243 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 102320124 ps |
| CPU time | 38.87 seconds |
| Started | Aug 09 08:00:13 PM PDT 24 |
| Finished | Aug 09 08:00:52 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-bfbc666d-d3bf-4670-a2c8-1e873574413c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653573243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.1653573243 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.1484212656 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 380062700 ps |
| CPU time | 20.15 seconds |
| Started | Aug 09 08:00:09 PM PDT 24 |
| Finished | Aug 09 08:00:30 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-b67002b4-9c45-4563-8624-0ae86924c1e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484212656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1484212656 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.1512120012 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 156832426 ps |
| CPU time | 20.72 seconds |
| Started | Aug 09 08:00:18 PM PDT 24 |
| Finished | Aug 09 08:00:38 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-b8d8d9f5-a1a5-4194-952c-1098ebcabdc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512120012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .1512120012 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.736959317 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 53464486934 ps |
| CPU time | 900.63 seconds |
| Started | Aug 09 08:00:17 PM PDT 24 |
| Finished | Aug 09 08:15:19 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-b3790568-d535-497b-84c9-78b314da84a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736959317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_d evice_slow_rsp.736959317 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.4117959732 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 38035247 ps |
| CPU time | 6.75 seconds |
| Started | Aug 09 08:00:22 PM PDT 24 |
| Finished | Aug 09 08:00:29 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-6dc6c1b2-6941-448b-b97d-bfc6e3ae3919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117959732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.4117959732 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.924226379 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 953805268 ps |
| CPU time | 28.09 seconds |
| Started | Aug 09 08:00:20 PM PDT 24 |
| Finished | Aug 09 08:00:48 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-e5ab48a7-3d50-48e0-8ac3-7755ca970e59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924226379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.924226379 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.2609678497 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 868612662 ps |
| CPU time | 29.68 seconds |
| Started | Aug 09 08:00:17 PM PDT 24 |
| Finished | Aug 09 08:00:47 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-e8a35162-f4ed-4d43-a78f-7436fae460ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609678497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.2609678497 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.2463232944 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 106259269887 ps |
| CPU time | 1081.64 seconds |
| Started | Aug 09 08:00:20 PM PDT 24 |
| Finished | Aug 09 08:18:22 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-12a2b450-daed-45c5-aaf9-476d596e1b80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463232944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2463232944 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.4287116514 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 46040116417 ps |
| CPU time | 733.9 seconds |
| Started | Aug 09 08:00:18 PM PDT 24 |
| Finished | Aug 09 08:12:32 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-e1452c3c-e0c6-490a-8b51-2b3188e5d324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287116514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.4287116514 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.221649292 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 66116420 ps |
| CPU time | 8.47 seconds |
| Started | Aug 09 08:00:17 PM PDT 24 |
| Finished | Aug 09 08:00:25 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-68a1c440-5cd6-46f2-98fd-0be2af135a9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221649292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_dela ys.221649292 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.376080663 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 124793240 ps |
| CPU time | 10.77 seconds |
| Started | Aug 09 08:00:23 PM PDT 24 |
| Finished | Aug 09 08:00:33 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-82e3930b-e05c-4b1a-add3-737e86fd10db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376080663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.376080663 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.1343220106 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 165898262 ps |
| CPU time | 7.78 seconds |
| Started | Aug 09 08:00:12 PM PDT 24 |
| Finished | Aug 09 08:00:19 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-c7f7f689-8f91-4111-87b6-1a9b8b9ac7e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343220106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1343220106 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.68409347 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 8050335881 ps |
| CPU time | 80.24 seconds |
| Started | Aug 09 08:00:17 PM PDT 24 |
| Finished | Aug 09 08:01:37 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-1f398ae7-bb72-4774-a60d-ac018e56b15c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68409347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.68409347 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1438706020 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 6830079380 ps |
| CPU time | 111.81 seconds |
| Started | Aug 09 08:00:18 PM PDT 24 |
| Finished | Aug 09 08:02:10 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-e7b01d59-3d52-40e9-a58b-5096a8c788bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438706020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1438706020 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2228440169 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 55049311 ps |
| CPU time | 6.5 seconds |
| Started | Aug 09 08:00:22 PM PDT 24 |
| Finished | Aug 09 08:00:29 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-5a4191c6-6a83-4834-8384-a36e096d55fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228440169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.2228440169 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.1493269010 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 6658233302 ps |
| CPU time | 232.36 seconds |
| Started | Aug 09 08:00:19 PM PDT 24 |
| Finished | Aug 09 08:04:12 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-e2c3e432-1eb7-49d0-a0c4-dd8975e92f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493269010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1493269010 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2791713533 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 8046877962 ps |
| CPU time | 316.38 seconds |
| Started | Aug 09 08:00:17 PM PDT 24 |
| Finished | Aug 09 08:05:33 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-51ca1e25-b5f9-462e-b401-679d190995b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791713533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2791713533 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1657244611 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 2830850699 ps |
| CPU time | 248.41 seconds |
| Started | Aug 09 08:00:17 PM PDT 24 |
| Finished | Aug 09 08:04:26 PM PDT 24 |
| Peak memory | 577088 kb |
| Host | smart-6084af81-03c5-41e3-a1c1-b3a28cebdc3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657244611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.1657244611 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.48539941 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 72999738 ps |
| CPU time | 16.3 seconds |
| Started | Aug 09 08:00:18 PM PDT 24 |
| Finished | Aug 09 08:00:34 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-5040137d-8e83-4404-b3b7-44e9032f4b39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48539941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_ with_reset_error.48539941 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3899348281 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 763864083 ps |
| CPU time | 30.71 seconds |
| Started | Aug 09 08:00:19 PM PDT 24 |
| Finished | Aug 09 08:00:50 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-abfce98a-7d07-40fa-bbd5-44a9c08f4479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899348281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3899348281 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.2894450606 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 2021208384 ps |
| CPU time | 72.15 seconds |
| Started | Aug 09 08:00:21 PM PDT 24 |
| Finished | Aug 09 08:01:33 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-0ec5fb4f-7382-403c-bb6c-bb88a5c18943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894450606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .2894450606 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2888424617 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 12502358543 ps |
| CPU time | 208.49 seconds |
| Started | Aug 09 08:00:27 PM PDT 24 |
| Finished | Aug 09 08:03:56 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-ccfeb0c2-8e56-4459-bdeb-9c546a0b2631 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888424617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.2888424617 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.558670795 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 198588135 ps |
| CPU time | 20.92 seconds |
| Started | Aug 09 08:00:21 PM PDT 24 |
| Finished | Aug 09 08:00:42 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-5571da2c-7496-42ff-8769-3b69dfe195c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558670795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr .558670795 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.2503193238 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 1175877862 ps |
| CPU time | 40.12 seconds |
| Started | Aug 09 08:00:28 PM PDT 24 |
| Finished | Aug 09 08:01:08 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-1adff241-c419-46e3-98ad-46d2e140bac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503193238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2503193238 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.3455046911 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2497851338 ps |
| CPU time | 98.66 seconds |
| Started | Aug 09 08:00:22 PM PDT 24 |
| Finished | Aug 09 08:02:00 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-359ca122-190e-493a-9272-8de45c219a0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455046911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.3455046911 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2849201291 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 45046666074 ps |
| CPU time | 513.78 seconds |
| Started | Aug 09 08:00:22 PM PDT 24 |
| Finished | Aug 09 08:08:56 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-2bac190c-6c31-4434-8386-def89f65fe30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849201291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2849201291 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.154858234 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 41422349163 ps |
| CPU time | 711.84 seconds |
| Started | Aug 09 08:00:23 PM PDT 24 |
| Finished | Aug 09 08:12:15 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-8483187c-f90f-4388-a84a-34d1ab88393d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154858234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.154858234 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.1928762527 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 167043862 ps |
| CPU time | 16.99 seconds |
| Started | Aug 09 08:00:24 PM PDT 24 |
| Finished | Aug 09 08:00:41 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-1ca02760-5796-4d96-a086-67efae20548d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928762527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.1928762527 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.512427001 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 331903998 ps |
| CPU time | 20.63 seconds |
| Started | Aug 09 08:00:23 PM PDT 24 |
| Finished | Aug 09 08:00:44 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-60cc2217-c1c1-4524-bcdf-b6cc2f76cc62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512427001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.512427001 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.2819955158 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 180745524 ps |
| CPU time | 8.53 seconds |
| Started | Aug 09 08:00:24 PM PDT 24 |
| Finished | Aug 09 08:00:32 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-a58747a5-91dd-4b9b-aa56-3fa8fa165b66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819955158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2819955158 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.1522058088 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 6497419534 ps |
| CPU time | 71.6 seconds |
| Started | Aug 09 08:00:23 PM PDT 24 |
| Finished | Aug 09 08:01:34 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-a6d610d7-3da5-4b29-a8e8-dff487f5b9bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522058088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1522058088 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.1225683657 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 4743802030 ps |
| CPU time | 84.09 seconds |
| Started | Aug 09 08:00:22 PM PDT 24 |
| Finished | Aug 09 08:01:46 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-ebac1103-b09a-4b82-a32d-1836e581a1bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225683657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1225683657 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.3633084516 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 48736832 ps |
| CPU time | 6.55 seconds |
| Started | Aug 09 08:00:23 PM PDT 24 |
| Finished | Aug 09 08:00:30 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-4d70805f-6d04-4d19-8ac8-782e85845fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633084516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.3633084516 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.649098899 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 3472323637 ps |
| CPU time | 279.4 seconds |
| Started | Aug 09 08:00:22 PM PDT 24 |
| Finished | Aug 09 08:05:02 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-8dfac103-135d-4833-a998-6cde96a864cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649098899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.649098899 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3061384612 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 11113948756 ps |
| CPU time | 382.81 seconds |
| Started | Aug 09 08:00:31 PM PDT 24 |
| Finished | Aug 09 08:06:54 PM PDT 24 |
| Peak memory | 577152 kb |
| Host | smart-344024b7-abae-4d76-a607-a3984324160c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061384612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3061384612 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1221716152 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1405465921 ps |
| CPU time | 260.91 seconds |
| Started | Aug 09 08:00:31 PM PDT 24 |
| Finished | Aug 09 08:04:52 PM PDT 24 |
| Peak memory | 577012 kb |
| Host | smart-76b40cf8-20a1-4d45-9871-ed69640ef882 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221716152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.1221716152 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1697197963 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 30986312 ps |
| CPU time | 27.86 seconds |
| Started | Aug 09 08:00:31 PM PDT 24 |
| Finished | Aug 09 08:00:59 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-34d38e25-db68-468d-bb7a-e436e5e5f97b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697197963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.1697197963 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.615407076 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 62785802 ps |
| CPU time | 8.96 seconds |
| Started | Aug 09 08:00:28 PM PDT 24 |
| Finished | Aug 09 08:00:37 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-dfa5b374-dc22-4070-b47c-a56c76390243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615407076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.615407076 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.1220190636 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 3838916724 ps |
| CPU time | 277.4 seconds |
| Started | Aug 09 08:00:31 PM PDT 24 |
| Finished | Aug 09 08:05:08 PM PDT 24 |
| Peak memory | 599028 kb |
| Host | smart-bca5b802-9201-458d-a13f-ac6ed5341f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220190636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1220190636 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.2601532755 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 1252242610 ps |
| CPU time | 90.97 seconds |
| Started | Aug 09 08:00:29 PM PDT 24 |
| Finished | Aug 09 08:02:01 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-b0e2288e-a8c7-4c5e-943c-3025a6b22e35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601532755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .2601532755 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2382512773 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 58146958626 ps |
| CPU time | 955.58 seconds |
| Started | Aug 09 08:00:40 PM PDT 24 |
| Finished | Aug 09 08:16:36 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-2bcb1725-933b-48e9-bfba-94e63e7af95c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382512773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.2382512773 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2163938140 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 274675136 ps |
| CPU time | 14.09 seconds |
| Started | Aug 09 08:00:47 PM PDT 24 |
| Finished | Aug 09 08:01:02 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-ae06da80-c2cd-4170-9431-e7bf990ec42c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163938140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.2163938140 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.3943638695 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 110962464 ps |
| CPU time | 6.7 seconds |
| Started | Aug 09 08:00:46 PM PDT 24 |
| Finished | Aug 09 08:00:53 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-f1bf191d-e9d1-4cbb-8458-665f75d0ee51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943638695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3943638695 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.3943864511 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 527607077 ps |
| CPU time | 47.67 seconds |
| Started | Aug 09 08:00:29 PM PDT 24 |
| Finished | Aug 09 08:01:17 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-1352a176-48b3-4b2b-a7d1-328f4ffe9416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943864511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.3943864511 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.984967748 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 23258959020 ps |
| CPU time | 238.6 seconds |
| Started | Aug 09 08:00:35 PM PDT 24 |
| Finished | Aug 09 08:04:34 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-6fc470ab-0e5c-4632-b7c4-75cc9e322125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984967748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.984967748 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.376050165 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 54183753926 ps |
| CPU time | 911.13 seconds |
| Started | Aug 09 08:00:30 PM PDT 24 |
| Finished | Aug 09 08:15:41 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-613f6b3d-c4b0-4638-b86c-9cbdef6032e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376050165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.376050165 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.1651121261 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 452010908 ps |
| CPU time | 39.49 seconds |
| Started | Aug 09 08:00:30 PM PDT 24 |
| Finished | Aug 09 08:01:10 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-b69f4867-737c-4401-933f-92a15e16f4dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651121261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.1651121261 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.2058589922 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 1414843975 ps |
| CPU time | 43.25 seconds |
| Started | Aug 09 08:00:40 PM PDT 24 |
| Finished | Aug 09 08:01:23 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-2e75eeca-f101-48a0-b0b6-26bb3e3720f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058589922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2058589922 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.332904621 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 223147209 ps |
| CPU time | 10.18 seconds |
| Started | Aug 09 08:00:30 PM PDT 24 |
| Finished | Aug 09 08:00:40 PM PDT 24 |
| Peak memory | 574788 kb |
| Host | smart-e4d44c0a-d377-48a3-b10a-8da88e6fd723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332904621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.332904621 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2520712779 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 8969549618 ps |
| CPU time | 88.41 seconds |
| Started | Aug 09 08:00:31 PM PDT 24 |
| Finished | Aug 09 08:01:59 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-1a032d3f-23f7-4275-8177-805923583b84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520712779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2520712779 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.536627726 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 4450367013 ps |
| CPU time | 73.18 seconds |
| Started | Aug 09 08:00:35 PM PDT 24 |
| Finished | Aug 09 08:01:49 PM PDT 24 |
| Peak memory | 574856 kb |
| Host | smart-ad83ac55-fd06-4504-8bee-a334e8573573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536627726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.536627726 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.2345133235 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 35894992 ps |
| CPU time | 5.77 seconds |
| Started | Aug 09 08:00:30 PM PDT 24 |
| Finished | Aug 09 08:00:36 PM PDT 24 |
| Peak memory | 574804 kb |
| Host | smart-d9cb8a4d-316a-4986-829f-e26fd6a07fc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345133235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.2345133235 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.335068593 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 7978738663 ps |
| CPU time | 281.38 seconds |
| Started | Aug 09 08:00:44 PM PDT 24 |
| Finished | Aug 09 08:05:25 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-507462f5-2779-4d62-abd1-4f9d43f6549f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335068593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.335068593 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2486022163 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 4338191060 ps |
| CPU time | 170.66 seconds |
| Started | Aug 09 08:00:52 PM PDT 24 |
| Finished | Aug 09 08:03:42 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-de5c7b41-b18d-4b13-9f5a-6cd397762144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486022163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2486022163 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2928030513 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 721123978 ps |
| CPU time | 304.13 seconds |
| Started | Aug 09 08:00:48 PM PDT 24 |
| Finished | Aug 09 08:05:53 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-9549ac1c-333c-44bd-a323-65998287b7d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928030513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.2928030513 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.1287927780 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 427238848 ps |
| CPU time | 20.78 seconds |
| Started | Aug 09 08:00:40 PM PDT 24 |
| Finished | Aug 09 08:01:01 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-e8d11464-a7c9-4b21-8aa4-5770be4a9719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287927780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1287927780 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.2163455100 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 4744053590 ps |
| CPU time | 308.06 seconds |
| Started | Aug 09 08:00:48 PM PDT 24 |
| Finished | Aug 09 08:05:56 PM PDT 24 |
| Peak memory | 604012 kb |
| Host | smart-136a9deb-dd2c-4f12-9e31-59ce9caa3ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163455100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.2163455100 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.3824980002 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 1628113327 ps |
| CPU time | 58.94 seconds |
| Started | Aug 09 08:00:48 PM PDT 24 |
| Finished | Aug 09 08:01:47 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-bdf02744-e640-4a7c-823e-9a95569d3f7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824980002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .3824980002 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3524450076 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 57879017412 ps |
| CPU time | 956.74 seconds |
| Started | Aug 09 08:00:46 PM PDT 24 |
| Finished | Aug 09 08:16:43 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-5733b814-c98a-4c45-a928-4a1394a1184c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524450076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.3524450076 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1232490501 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 190418157 ps |
| CPU time | 23.64 seconds |
| Started | Aug 09 08:00:45 PM PDT 24 |
| Finished | Aug 09 08:01:09 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-70761126-4884-49f7-b4e3-249e9c5c5496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232490501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.1232490501 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.3029968051 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 2217217933 ps |
| CPU time | 78.72 seconds |
| Started | Aug 09 08:00:49 PM PDT 24 |
| Finished | Aug 09 08:02:08 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-82b85252-823a-45bc-a09f-340f13eb68f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029968051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3029968051 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.517916404 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 466333434 ps |
| CPU time | 45.22 seconds |
| Started | Aug 09 08:00:46 PM PDT 24 |
| Finished | Aug 09 08:01:31 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-c7006b1c-e815-44f5-a335-ec280a639174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517916404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.517916404 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1211351976 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 52155305234 ps |
| CPU time | 566.37 seconds |
| Started | Aug 09 08:00:37 PM PDT 24 |
| Finished | Aug 09 08:10:04 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-1b8cabd2-ceac-479a-ad3b-a5d0064e5bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211351976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1211351976 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.3000841388 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 54961695507 ps |
| CPU time | 902.72 seconds |
| Started | Aug 09 08:00:48 PM PDT 24 |
| Finished | Aug 09 08:15:51 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-a19011cb-8011-4d61-b151-4b2f4d825a5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000841388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3000841388 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.1074596575 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 563259983 ps |
| CPU time | 49.46 seconds |
| Started | Aug 09 08:00:49 PM PDT 24 |
| Finished | Aug 09 08:01:39 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-0b60ad0d-d944-4231-ba2a-84a4f919c270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074596575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.1074596575 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.3825813737 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 789110512 ps |
| CPU time | 25.53 seconds |
| Started | Aug 09 08:00:45 PM PDT 24 |
| Finished | Aug 09 08:01:11 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-7c843bc5-18bb-44da-bc37-5dad7740f5cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825813737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3825813737 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.2694012197 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 141683383 ps |
| CPU time | 7.91 seconds |
| Started | Aug 09 08:00:42 PM PDT 24 |
| Finished | Aug 09 08:00:50 PM PDT 24 |
| Peak memory | 574844 kb |
| Host | smart-44f3c9a3-0269-40cf-b8a0-c450a44f862b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694012197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2694012197 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.2599198897 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 7910750256 ps |
| CPU time | 80.94 seconds |
| Started | Aug 09 08:00:47 PM PDT 24 |
| Finished | Aug 09 08:02:08 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-fd206caf-5494-420d-8815-8affad80fdb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599198897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2599198897 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1456630099 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 4733484680 ps |
| CPU time | 80.94 seconds |
| Started | Aug 09 08:00:39 PM PDT 24 |
| Finished | Aug 09 08:02:00 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-44b6b10c-a5d9-4ff0-bef6-2f805c761e64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456630099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1456630099 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3696812371 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 48966474 ps |
| CPU time | 6.89 seconds |
| Started | Aug 09 08:00:46 PM PDT 24 |
| Finished | Aug 09 08:00:53 PM PDT 24 |
| Peak memory | 574852 kb |
| Host | smart-124e273c-7f71-4bd7-98d7-199407627541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696812371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.3696812371 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.2871975119 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 14842353849 ps |
| CPU time | 554.2 seconds |
| Started | Aug 09 08:00:50 PM PDT 24 |
| Finished | Aug 09 08:10:04 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-0b4c6e8d-a639-4b8a-8dbc-74c9a2923279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871975119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2871975119 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.3488732347 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 9827823917 ps |
| CPU time | 348.06 seconds |
| Started | Aug 09 08:00:50 PM PDT 24 |
| Finished | Aug 09 08:06:39 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-7359f87d-838c-4b4a-a897-07ccdf48a5e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488732347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3488732347 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1484596810 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 3214779292 ps |
| CPU time | 214.06 seconds |
| Started | Aug 09 08:00:50 PM PDT 24 |
| Finished | Aug 09 08:04:25 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-468725a3-66a1-44d2-8f62-08db487a1135 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484596810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.1484596810 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.1871078592 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 1002066254 ps |
| CPU time | 41.54 seconds |
| Started | Aug 09 08:00:47 PM PDT 24 |
| Finished | Aug 09 08:01:29 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-670be0e0-1816-4c77-b894-9f717a7a5a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871078592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1871078592 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.3407076601 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3931199534 ps |
| CPU time | 305.41 seconds |
| Started | Aug 09 08:00:56 PM PDT 24 |
| Finished | Aug 09 08:06:01 PM PDT 24 |
| Peak memory | 598856 kb |
| Host | smart-0abc6514-8add-4f73-98aa-3245c809ca38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407076601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.3407076601 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.1987679883 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 114901423 ps |
| CPU time | 12.67 seconds |
| Started | Aug 09 08:00:55 PM PDT 24 |
| Finished | Aug 09 08:01:08 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-4870b69e-ff7b-4f98-95ec-47653a3927f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987679883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .1987679883 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.359281115 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 50319533227 ps |
| CPU time | 885.03 seconds |
| Started | Aug 09 08:00:58 PM PDT 24 |
| Finished | Aug 09 08:15:44 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-634c1d3c-b4a4-4ac8-8199-8dceed37243c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359281115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_d evice_slow_rsp.359281115 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2134822618 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 450016217 ps |
| CPU time | 20.01 seconds |
| Started | Aug 09 08:01:01 PM PDT 24 |
| Finished | Aug 09 08:01:21 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-a7b39f1e-cdfa-4d15-9ba8-3b5b1b4b73d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134822618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.2134822618 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.1835403537 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 1920332042 ps |
| CPU time | 61.86 seconds |
| Started | Aug 09 08:00:59 PM PDT 24 |
| Finished | Aug 09 08:02:01 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-2d7f2fe1-662f-4edc-a6d5-369e54747f38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835403537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1835403537 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.315072332 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 785349601 ps |
| CPU time | 25.91 seconds |
| Started | Aug 09 08:00:51 PM PDT 24 |
| Finished | Aug 09 08:01:17 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-826ff166-4c0d-473b-9d63-1f6e46e07c24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315072332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.315072332 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1880884916 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 60707109380 ps |
| CPU time | 653.79 seconds |
| Started | Aug 09 08:00:53 PM PDT 24 |
| Finished | Aug 09 08:11:47 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-89a1c330-99b0-4e53-b0d5-2fdb28987e30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880884916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1880884916 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.1132733349 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 19691415275 ps |
| CPU time | 341.12 seconds |
| Started | Aug 09 08:00:51 PM PDT 24 |
| Finished | Aug 09 08:06:32 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-bd4e15cc-a3e6-4325-8f8e-136cff5cb35d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132733349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1132733349 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.295271131 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 324661150 ps |
| CPU time | 29.48 seconds |
| Started | Aug 09 08:00:52 PM PDT 24 |
| Finished | Aug 09 08:01:21 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-3364c775-f5a9-4d98-ade5-c988642732d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295271131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_dela ys.295271131 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.3116020523 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 2499700034 ps |
| CPU time | 76.85 seconds |
| Started | Aug 09 08:00:59 PM PDT 24 |
| Finished | Aug 09 08:02:15 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-b71ac201-30d2-4829-baea-0bfe17e1d6ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116020523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3116020523 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.1605559780 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 202327115 ps |
| CPU time | 8.93 seconds |
| Started | Aug 09 08:00:54 PM PDT 24 |
| Finished | Aug 09 08:01:03 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-10d3f192-e535-4384-be84-4858809f035d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605559780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1605559780 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.653247431 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 7595569627 ps |
| CPU time | 79.41 seconds |
| Started | Aug 09 08:00:52 PM PDT 24 |
| Finished | Aug 09 08:02:12 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-f6222320-407f-4d33-8884-d25d52c1e6e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653247431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.653247431 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2738224020 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 3864983145 ps |
| CPU time | 62.9 seconds |
| Started | Aug 09 08:00:53 PM PDT 24 |
| Finished | Aug 09 08:01:56 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-d1ad8c20-7e21-4ed8-bcba-bbd87f4b6093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738224020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2738224020 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.4080743358 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 46978762 ps |
| CPU time | 7.01 seconds |
| Started | Aug 09 08:00:51 PM PDT 24 |
| Finished | Aug 09 08:00:58 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-fffbc7b0-2507-491a-a352-143431e77747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080743358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.4080743358 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.4287216156 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 7805281446 ps |
| CPU time | 301.81 seconds |
| Started | Aug 09 08:01:04 PM PDT 24 |
| Finished | Aug 09 08:06:06 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-c06b4957-4194-4908-826c-481d6311c2e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287216156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.4287216156 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.2170312217 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 19404244994 ps |
| CPU time | 656.84 seconds |
| Started | Aug 09 08:01:01 PM PDT 24 |
| Finished | Aug 09 08:11:58 PM PDT 24 |
| Peak memory | 577156 kb |
| Host | smart-f04c68c4-72c3-43ab-ad18-b8e23144560d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170312217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2170312217 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.928145286 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 322955906 ps |
| CPU time | 74.98 seconds |
| Started | Aug 09 08:00:59 PM PDT 24 |
| Finished | Aug 09 08:02:14 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-553108e5-13db-42ef-a0a7-11d1984618f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928145286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_ with_rand_reset.928145286 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1997379011 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 67167214 ps |
| CPU time | 8.45 seconds |
| Started | Aug 09 08:01:03 PM PDT 24 |
| Finished | Aug 09 08:01:11 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-d9288d67-e1ca-4d89-bb0e-1dc909c8b678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997379011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.1997379011 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.2561787111 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 1194504100 ps |
| CPU time | 47.21 seconds |
| Started | Aug 09 08:00:56 PM PDT 24 |
| Finished | Aug 09 08:01:43 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-4250e981-7516-4143-ae32-2638bc99b036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561787111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2561787111 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.1438155549 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4501658640 ps |
| CPU time | 331.55 seconds |
| Started | Aug 09 08:00:56 PM PDT 24 |
| Finished | Aug 09 08:06:27 PM PDT 24 |
| Peak memory | 598840 kb |
| Host | smart-e460d7dc-4918-4da0-8052-22da5f4c61a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438155549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.1438155549 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.2079631530 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 1422153126 ps |
| CPU time | 59.15 seconds |
| Started | Aug 09 08:01:09 PM PDT 24 |
| Finished | Aug 09 08:02:09 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-78e99870-25be-4851-9ef6-939016ce87e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079631530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .2079631530 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.393128730 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 96963199947 ps |
| CPU time | 1623.03 seconds |
| Started | Aug 09 08:01:04 PM PDT 24 |
| Finished | Aug 09 08:28:08 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-f52cd6c5-287a-46fd-abde-986d0c781253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393128730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_d evice_slow_rsp.393128730 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.86247389 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 170953219 ps |
| CPU time | 19.1 seconds |
| Started | Aug 09 08:01:08 PM PDT 24 |
| Finished | Aug 09 08:01:27 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-6e813b74-2cd1-4291-9bc7-cbe35b20a269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86247389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.86247389 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.2444943155 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 439843603 ps |
| CPU time | 35.18 seconds |
| Started | Aug 09 08:01:07 PM PDT 24 |
| Finished | Aug 09 08:01:42 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-ca6632cb-ed92-42b0-bb02-ecbfeed78d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444943155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2444943155 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.112007884 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 222591545 ps |
| CPU time | 19.11 seconds |
| Started | Aug 09 08:01:06 PM PDT 24 |
| Finished | Aug 09 08:01:26 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-919f5189-14fa-4871-b501-f6d1ee7b64e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112007884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.112007884 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.3844610167 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 21192381137 ps |
| CPU time | 217.63 seconds |
| Started | Aug 09 08:01:05 PM PDT 24 |
| Finished | Aug 09 08:04:43 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-52fe798a-1424-4b69-ad5c-34be7b7ff3e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844610167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3844610167 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.824420674 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 21419119421 ps |
| CPU time | 340.69 seconds |
| Started | Aug 09 08:01:06 PM PDT 24 |
| Finished | Aug 09 08:06:47 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-64bc3ee6-3886-4384-96e1-a22a629f7638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824420674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.824420674 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.4287853358 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 579923020 ps |
| CPU time | 52.79 seconds |
| Started | Aug 09 08:01:06 PM PDT 24 |
| Finished | Aug 09 08:01:59 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-d83395cc-c576-4c5d-a71e-43459beddc22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287853358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.4287853358 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.138333049 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 185694852 ps |
| CPU time | 16.42 seconds |
| Started | Aug 09 08:01:05 PM PDT 24 |
| Finished | Aug 09 08:01:22 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-b5d36802-557c-4422-91bd-979bd2f5e795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138333049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.138333049 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.3635153211 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 159237167 ps |
| CPU time | 7.84 seconds |
| Started | Aug 09 08:00:59 PM PDT 24 |
| Finished | Aug 09 08:01:07 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-eca88435-8900-4f6c-9f50-a355ad5741e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635153211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3635153211 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.1106680574 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 10661085617 ps |
| CPU time | 104.8 seconds |
| Started | Aug 09 08:00:57 PM PDT 24 |
| Finished | Aug 09 08:02:42 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-bab16bd1-fa83-4259-bb32-9fe0332e96a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106680574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1106680574 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1496907981 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 4276104663 ps |
| CPU time | 68.95 seconds |
| Started | Aug 09 08:00:58 PM PDT 24 |
| Finished | Aug 09 08:02:07 PM PDT 24 |
| Peak memory | 574900 kb |
| Host | smart-60225a42-a931-4269-9a06-56b10e68ae31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496907981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1496907981 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3593025990 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 49759920 ps |
| CPU time | 6.58 seconds |
| Started | Aug 09 08:01:00 PM PDT 24 |
| Finished | Aug 09 08:01:07 PM PDT 24 |
| Peak memory | 574776 kb |
| Host | smart-70ba9689-a8b2-45eb-8bbe-228fc26453e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593025990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.3593025990 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.3607694763 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 5468732389 ps |
| CPU time | 199.68 seconds |
| Started | Aug 09 08:01:05 PM PDT 24 |
| Finished | Aug 09 08:04:25 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-b8fa2e10-1ba9-4a81-81fd-c3378189a91c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607694763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3607694763 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.1499350678 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 10406701281 ps |
| CPU time | 350.22 seconds |
| Started | Aug 09 08:01:09 PM PDT 24 |
| Finished | Aug 09 08:06:59 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-7ece83e1-f236-441f-9c21-4a7a4648e072 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499350678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1499350678 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2888677793 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 2300774804 ps |
| CPU time | 390.1 seconds |
| Started | Aug 09 08:01:05 PM PDT 24 |
| Finished | Aug 09 08:07:35 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-520fdf9d-2f5a-4b00-a98a-d0c592443a43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888677793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.2888677793 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.453118324 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2009967293 ps |
| CPU time | 244.71 seconds |
| Started | Aug 09 08:01:08 PM PDT 24 |
| Finished | Aug 09 08:05:12 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-efbc9dad-f41c-4db3-9532-abfb42d6434e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453118324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_reset_error.453118324 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.2568012934 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 83219456 ps |
| CPU time | 7.36 seconds |
| Started | Aug 09 08:01:05 PM PDT 24 |
| Finished | Aug 09 08:01:13 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-3a841d8f-d634-48bc-80d4-8f4f51840b75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568012934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2568012934 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.2928403336 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2566513826 ps |
| CPU time | 125.57 seconds |
| Started | Aug 09 08:01:04 PM PDT 24 |
| Finished | Aug 09 08:03:10 PM PDT 24 |
| Peak memory | 604012 kb |
| Host | smart-b4bf4a7d-4074-4cf5-8651-2d1114174b74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928403336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.2928403336 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.1523026279 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 2167364309 ps |
| CPU time | 92.08 seconds |
| Started | Aug 09 08:01:12 PM PDT 24 |
| Finished | Aug 09 08:02:44 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-8abdd00b-557f-4e6d-aa9e-1bdd1f732511 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523026279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .1523026279 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.621005813 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 60283102324 ps |
| CPU time | 958.86 seconds |
| Started | Aug 09 08:01:12 PM PDT 24 |
| Finished | Aug 09 08:17:11 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-2441eae4-f0da-4e32-ad2a-4eeefe592ee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621005813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_d evice_slow_rsp.621005813 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2818603373 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 222823970 ps |
| CPU time | 20.67 seconds |
| Started | Aug 09 08:01:11 PM PDT 24 |
| Finished | Aug 09 08:01:32 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-72fd6cb2-2c4a-4e11-822b-98e69b9e8501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818603373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.2818603373 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.3016686948 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 501429797 ps |
| CPU time | 17.8 seconds |
| Started | Aug 09 08:01:16 PM PDT 24 |
| Finished | Aug 09 08:01:34 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-692de0a7-310e-42f2-80c3-a33cf9ae721e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016686948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3016686948 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.43979287 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 1481204888 ps |
| CPU time | 47.33 seconds |
| Started | Aug 09 08:01:05 PM PDT 24 |
| Finished | Aug 09 08:01:53 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-1b1d9aa8-b58d-4c46-9220-ae92252bf1e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43979287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.43979287 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.2249251041 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 7394590952 ps |
| CPU time | 125.17 seconds |
| Started | Aug 09 08:01:13 PM PDT 24 |
| Finished | Aug 09 08:03:18 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-3f48977c-7950-49b7-bc00-9315257f1d25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249251041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2249251041 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.563958810 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 562329664 ps |
| CPU time | 51.88 seconds |
| Started | Aug 09 08:01:12 PM PDT 24 |
| Finished | Aug 09 08:02:04 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-cc638433-f181-4e8b-867f-7bb607a1e1da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563958810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_dela ys.563958810 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.652847263 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 72713793 ps |
| CPU time | 7.47 seconds |
| Started | Aug 09 08:01:12 PM PDT 24 |
| Finished | Aug 09 08:01:20 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-7f80999f-c57b-4b02-b812-9c36b5ddba44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652847263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.652847263 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.2777882943 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 46932525 ps |
| CPU time | 6.48 seconds |
| Started | Aug 09 08:01:06 PM PDT 24 |
| Finished | Aug 09 08:01:13 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-9ae715d5-89b7-4a5a-bdb7-489dcc53d760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777882943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2777882943 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.3788695773 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 3990275969 ps |
| CPU time | 40.94 seconds |
| Started | Aug 09 08:01:07 PM PDT 24 |
| Finished | Aug 09 08:01:48 PM PDT 24 |
| Peak memory | 574848 kb |
| Host | smart-21775481-95ce-4015-8060-4c178923eda0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788695773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3788695773 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.468253202 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 5183051460 ps |
| CPU time | 89.4 seconds |
| Started | Aug 09 08:01:04 PM PDT 24 |
| Finished | Aug 09 08:02:34 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-a8c818e6-d257-4ee4-806c-4a9bb7b9516a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468253202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.468253202 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2101886598 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 51267499 ps |
| CPU time | 6.81 seconds |
| Started | Aug 09 08:01:05 PM PDT 24 |
| Finished | Aug 09 08:01:12 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-2a6efcf9-f976-4e36-9951-c0ecbaa8c8ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101886598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.2101886598 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.2598341352 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 6039279985 ps |
| CPU time | 217.03 seconds |
| Started | Aug 09 08:01:09 PM PDT 24 |
| Finished | Aug 09 08:04:47 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-cfb3553c-2933-4fad-b7fe-123442f4d0db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598341352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2598341352 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.196898814 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 17453137981 ps |
| CPU time | 691.59 seconds |
| Started | Aug 09 08:01:12 PM PDT 24 |
| Finished | Aug 09 08:12:44 PM PDT 24 |
| Peak memory | 577188 kb |
| Host | smart-b50fd9bb-da8a-4edc-8a3c-65c7fcae014a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196898814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.196898814 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1690640817 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 3004026219 ps |
| CPU time | 267.53 seconds |
| Started | Aug 09 08:01:13 PM PDT 24 |
| Finished | Aug 09 08:05:41 PM PDT 24 |
| Peak memory | 577172 kb |
| Host | smart-fbd6a864-40e6-485f-a2c0-522f8ede9ddc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690640817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.1690640817 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.2933306699 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 7834032810 ps |
| CPU time | 459.32 seconds |
| Started | Aug 09 08:01:12 PM PDT 24 |
| Finished | Aug 09 08:08:51 PM PDT 24 |
| Peak memory | 577108 kb |
| Host | smart-f6066776-c5b7-45b5-a01c-ea3059fa05e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933306699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.2933306699 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.48239604 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 1064219511 ps |
| CPU time | 44.11 seconds |
| Started | Aug 09 08:01:11 PM PDT 24 |
| Finished | Aug 09 08:01:55 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-5d231777-a769-4844-b59c-81050604875e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48239604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.48239604 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.3541327153 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3926144560 ps |
| CPU time | 255.76 seconds |
| Started | Aug 09 08:01:12 PM PDT 24 |
| Finished | Aug 09 08:05:28 PM PDT 24 |
| Peak memory | 598912 kb |
| Host | smart-47c131e3-e5f3-4482-a1f2-7d807554b868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541327153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.3541327153 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.794085667 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 225850558 ps |
| CPU time | 20.33 seconds |
| Started | Aug 09 08:01:21 PM PDT 24 |
| Finished | Aug 09 08:01:41 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-e119abc2-a720-4202-b9a9-df6dcd71c871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794085667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device. 794085667 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3841471547 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 109297597858 ps |
| CPU time | 1993.61 seconds |
| Started | Aug 09 08:01:22 PM PDT 24 |
| Finished | Aug 09 08:34:35 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-a596fb42-4875-4f56-b349-764c81357f7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841471547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.3841471547 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2298791442 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 142743312 ps |
| CPU time | 16.5 seconds |
| Started | Aug 09 08:01:23 PM PDT 24 |
| Finished | Aug 09 08:01:39 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-fad0fa7a-2250-4365-9a0e-807db0515ab2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298791442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.2298791442 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.289320389 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 582312017 ps |
| CPU time | 23.59 seconds |
| Started | Aug 09 08:01:20 PM PDT 24 |
| Finished | Aug 09 08:01:44 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-83c53ca3-8b33-4697-adb6-51ed329aab24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289320389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.289320389 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.3429709427 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 556694079 ps |
| CPU time | 21.81 seconds |
| Started | Aug 09 08:01:18 PM PDT 24 |
| Finished | Aug 09 08:01:40 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-8724321d-8138-45df-b7d7-12d3798c4d88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429709427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.3429709427 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.2640219654 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 90976825352 ps |
| CPU time | 923.07 seconds |
| Started | Aug 09 08:01:19 PM PDT 24 |
| Finished | Aug 09 08:16:43 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-c82bc156-13a6-4360-bcac-8b6cfffd005b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640219654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2640219654 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.2060026532 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 57753527663 ps |
| CPU time | 926.68 seconds |
| Started | Aug 09 08:01:19 PM PDT 24 |
| Finished | Aug 09 08:16:46 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-11bf75bc-75ae-490f-a145-29a33ad9cc8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060026532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2060026532 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.835297945 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 175918147 ps |
| CPU time | 15.03 seconds |
| Started | Aug 09 08:01:18 PM PDT 24 |
| Finished | Aug 09 08:01:33 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-2462fa02-9ff3-4f16-a29e-dfa31a455e90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835297945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_dela ys.835297945 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.3715309227 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 429771176 ps |
| CPU time | 29.84 seconds |
| Started | Aug 09 08:01:19 PM PDT 24 |
| Finished | Aug 09 08:01:49 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-6068e9f5-5d6e-417b-85e3-c9a4e1d3114a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715309227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3715309227 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.2831419619 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 46641518 ps |
| CPU time | 6.37 seconds |
| Started | Aug 09 08:01:12 PM PDT 24 |
| Finished | Aug 09 08:01:18 PM PDT 24 |
| Peak memory | 574776 kb |
| Host | smart-00d589e3-6f6a-4431-bf63-c131121ea50c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831419619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2831419619 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.699514073 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 8323517922 ps |
| CPU time | 82.08 seconds |
| Started | Aug 09 08:01:15 PM PDT 24 |
| Finished | Aug 09 08:02:37 PM PDT 24 |
| Peak memory | 574940 kb |
| Host | smart-95b8f99c-0a0a-44c5-b717-bf2b9b2b731f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699514073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.699514073 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.1592661202 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 4050225379 ps |
| CPU time | 70.07 seconds |
| Started | Aug 09 08:01:19 PM PDT 24 |
| Finished | Aug 09 08:02:29 PM PDT 24 |
| Peak memory | 574924 kb |
| Host | smart-b532b95a-80a7-413a-90e3-3a38ed18e63d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592661202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1592661202 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2205941501 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 40652665 ps |
| CPU time | 5.99 seconds |
| Started | Aug 09 08:01:12 PM PDT 24 |
| Finished | Aug 09 08:01:18 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-f9d28059-57af-4523-aec8-ff2d9a9d9911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205941501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.2205941501 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.3582970978 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 7563926302 ps |
| CPU time | 269.9 seconds |
| Started | Aug 09 08:01:21 PM PDT 24 |
| Finished | Aug 09 08:05:50 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-93716e1c-4b8c-477d-b99f-cb13047525c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582970978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3582970978 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1232537737 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 558520510 ps |
| CPU time | 348.15 seconds |
| Started | Aug 09 08:01:19 PM PDT 24 |
| Finished | Aug 09 08:07:08 PM PDT 24 |
| Peak memory | 577096 kb |
| Host | smart-5acde0a9-4689-4975-a4b6-a78e4696d126 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232537737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.1232537737 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.553789953 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 3712985882 ps |
| CPU time | 341.16 seconds |
| Started | Aug 09 08:01:26 PM PDT 24 |
| Finished | Aug 09 08:07:08 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-cadb5de9-7649-4f6a-8f09-4871b14cc5ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553789953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_reset_error.553789953 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.783631931 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 937769043 ps |
| CPU time | 39.15 seconds |
| Started | Aug 09 08:01:23 PM PDT 24 |
| Finished | Aug 09 08:02:02 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-79fcac5b-e617-4a1b-ae5b-45adf8890399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783631931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.783631931 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.974060719 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 2787244849 ps |
| CPU time | 95.49 seconds |
| Started | Aug 09 08:01:24 PM PDT 24 |
| Finished | Aug 09 08:03:00 PM PDT 24 |
| Peak memory | 604208 kb |
| Host | smart-e96abd26-a841-47ff-adcb-6700fc9c2ef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974060719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.974060719 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.1493876543 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 1480041011 ps |
| CPU time | 60.83 seconds |
| Started | Aug 09 08:01:33 PM PDT 24 |
| Finished | Aug 09 08:02:33 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-33b603d6-1d84-42dc-aa31-304fcad1d4ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493876543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .1493876543 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1174897855 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 87609657891 ps |
| CPU time | 1518.99 seconds |
| Started | Aug 09 08:01:32 PM PDT 24 |
| Finished | Aug 09 08:26:51 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-a538fad2-236f-4043-a7ab-c20a3c616073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174897855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.1174897855 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.1155405285 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 150278424 ps |
| CPU time | 20.06 seconds |
| Started | Aug 09 08:01:28 PM PDT 24 |
| Finished | Aug 09 08:01:48 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-d3285adb-7568-4171-a7ad-6b519f0cd727 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155405285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.1155405285 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.3808624354 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 1452368434 ps |
| CPU time | 55.57 seconds |
| Started | Aug 09 08:01:30 PM PDT 24 |
| Finished | Aug 09 08:02:25 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-7f61e611-0715-4a22-b578-f8f0bbd2564e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808624354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3808624354 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.1911275080 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 409010964 ps |
| CPU time | 39.37 seconds |
| Started | Aug 09 08:01:31 PM PDT 24 |
| Finished | Aug 09 08:02:10 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-c4c8ce84-c7c8-4b25-8d8e-299a5d705445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911275080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.1911275080 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.3017632292 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 5872119323 ps |
| CPU time | 61.11 seconds |
| Started | Aug 09 08:01:30 PM PDT 24 |
| Finished | Aug 09 08:02:31 PM PDT 24 |
| Peak memory | 574844 kb |
| Host | smart-1087a5a9-10fb-4614-b22d-095a375e2a0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017632292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3017632292 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.2828808796 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 18001339555 ps |
| CPU time | 303.99 seconds |
| Started | Aug 09 08:01:30 PM PDT 24 |
| Finished | Aug 09 08:06:34 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-0239018b-96ec-460e-ac98-d9b7e9f1bead |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828808796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2828808796 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.2126688891 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 400838744 ps |
| CPU time | 36.33 seconds |
| Started | Aug 09 08:01:30 PM PDT 24 |
| Finished | Aug 09 08:02:06 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-b8b1e10a-cdf5-41b4-8f96-2b9a324adf27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126688891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.2126688891 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.3560216425 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 2576458135 ps |
| CPU time | 67.58 seconds |
| Started | Aug 09 08:01:31 PM PDT 24 |
| Finished | Aug 09 08:02:38 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-a3942315-b24b-4759-82b1-7131505a9b31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560216425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3560216425 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.2906118077 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 234681881 ps |
| CPU time | 8.67 seconds |
| Started | Aug 09 08:01:25 PM PDT 24 |
| Finished | Aug 09 08:01:34 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-c39e410b-450f-4417-bc25-43bf5d0a9805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906118077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2906118077 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.4108640771 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 9494116998 ps |
| CPU time | 97.33 seconds |
| Started | Aug 09 08:01:31 PM PDT 24 |
| Finished | Aug 09 08:03:08 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-8f069cc2-25be-4d3c-b359-6d6f97a5e92f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108640771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.4108640771 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.4085726514 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 4512980742 ps |
| CPU time | 76.96 seconds |
| Started | Aug 09 08:01:31 PM PDT 24 |
| Finished | Aug 09 08:02:48 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-c01ff98c-c60d-4a8d-95f0-83170ac694dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085726514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4085726514 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3432539458 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 42543270 ps |
| CPU time | 5.98 seconds |
| Started | Aug 09 08:01:25 PM PDT 24 |
| Finished | Aug 09 08:01:31 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-73cbef31-f687-4f82-9ba3-189492131cc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432539458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.3432539458 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.3779317980 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 4736795930 ps |
| CPU time | 182.86 seconds |
| Started | Aug 09 08:01:30 PM PDT 24 |
| Finished | Aug 09 08:04:33 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-4d83eb01-8310-4ec3-b6bb-d34d5001a6fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779317980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3779317980 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.3264936883 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 2959242101 ps |
| CPU time | 217.14 seconds |
| Started | Aug 09 08:01:37 PM PDT 24 |
| Finished | Aug 09 08:05:14 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-3429b4b6-46a8-4157-bda5-4cb91e0f388c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264936883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3264936883 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.777744547 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 232812643 ps |
| CPU time | 50.33 seconds |
| Started | Aug 09 08:01:37 PM PDT 24 |
| Finished | Aug 09 08:02:27 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-156ba7d8-753c-4a50-a634-685d3e848176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777744547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_ with_rand_reset.777744547 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3448013495 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 9099202676 ps |
| CPU time | 498.1 seconds |
| Started | Aug 09 08:01:38 PM PDT 24 |
| Finished | Aug 09 08:09:56 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-623ab036-300b-42d3-922c-8b54c8890ca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448013495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.3448013495 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.3786921703 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 1303654426 ps |
| CPU time | 60.32 seconds |
| Started | Aug 09 08:01:33 PM PDT 24 |
| Finished | Aug 09 08:02:33 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-01156b03-43ed-495c-9361-1ac050ce0bd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786921703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3786921703 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.3058986880 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 31866324920 ps |
| CPU time | 5427.63 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 09:28:20 PM PDT 24 |
| Peak memory | 594192 kb |
| Host | smart-62838dcd-f445-4b08-baed-d21eb183ac9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058986880 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.3058986880 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.1719356219 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 61473656899 ps |
| CPU time | 6519.09 seconds |
| Started | Aug 09 07:57:47 PM PDT 24 |
| Finished | Aug 09 09:46:27 PM PDT 24 |
| Peak memory | 593032 kb |
| Host | smart-fc301156-9792-4d37-b944-1cd377160f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719356219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.1719356219 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3851147848 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 8098215500 ps |
| CPU time | 395.68 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 08:04:28 PM PDT 24 |
| Peak memory | 662096 kb |
| Host | smart-12f06e99-b746-4b63-95c4-505cbeb09b89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851147848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.3851147848 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2766886476 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 8883683296 ps |
| CPU time | 905.42 seconds |
| Started | Aug 09 07:57:53 PM PDT 24 |
| Finished | Aug 09 08:12:59 PM PDT 24 |
| Peak memory | 653272 kb |
| Host | smart-35fa7704-d728-498a-91b7-0866ae97bc30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766886476 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.2766886476 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.480769815 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4301428330 ps |
| CPU time | 302.62 seconds |
| Started | Aug 09 07:57:47 PM PDT 24 |
| Finished | Aug 09 08:02:50 PM PDT 24 |
| Peak memory | 597480 kb |
| Host | smart-e0c91221-fcb3-44b6-8614-3bd7c87699b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480769815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.480769815 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.3424175373 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 16402312771 ps |
| CPU time | 1870.4 seconds |
| Started | Aug 09 07:57:46 PM PDT 24 |
| Finished | Aug 09 08:28:56 PM PDT 24 |
| Peak memory | 593552 kb |
| Host | smart-d1bba4a4-ccb7-49a4-aab1-dd963446c460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424175373 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.3424175373 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.3535198190 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 3121047102 ps |
| CPU time | 70.89 seconds |
| Started | Aug 09 07:57:38 PM PDT 24 |
| Finished | Aug 09 07:58:49 PM PDT 24 |
| Peak memory | 602740 kb |
| Host | smart-78a4d175-9a0b-4f0b-aae7-09b1bb427beb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535198190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.3535198190 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.4136818110 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 1325062249 ps |
| CPU time | 42.69 seconds |
| Started | Aug 09 07:57:49 PM PDT 24 |
| Finished | Aug 09 07:58:32 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-8e5b0fee-3f90-4619-a23a-f681cdb3f9fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136818110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 4136818110 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.445315607 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 110117745551 ps |
| CPU time | 1935.28 seconds |
| Started | Aug 09 07:57:51 PM PDT 24 |
| Finished | Aug 09 08:30:07 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-3678d1b3-951a-4a42-bdc6-a1630d7f8c0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445315607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_de vice_slow_rsp.445315607 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3946153295 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 278590350 ps |
| CPU time | 26.83 seconds |
| Started | Aug 09 07:57:49 PM PDT 24 |
| Finished | Aug 09 07:58:16 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-800a7684-fa0b-4973-bbaf-b958c23cadb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946153295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .3946153295 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.264300290 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 687876163 ps |
| CPU time | 23.53 seconds |
| Started | Aug 09 07:57:49 PM PDT 24 |
| Finished | Aug 09 07:58:13 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-64872513-4d23-413d-8741-6b940ccf4dcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264300290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.264300290 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.1590539991 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 1059624800 ps |
| CPU time | 35.34 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 07:58:27 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-21087304-a515-4f74-b96c-baad0b13c5c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590539991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.1590539991 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.1914097354 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 15611371177 ps |
| CPU time | 171.18 seconds |
| Started | Aug 09 07:57:47 PM PDT 24 |
| Finished | Aug 09 08:00:39 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-97082f8b-ad0e-424f-ace6-53509645b180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914097354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1914097354 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1081858026 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 34073643114 ps |
| CPU time | 535.34 seconds |
| Started | Aug 09 07:57:51 PM PDT 24 |
| Finished | Aug 09 08:06:47 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-b538220b-a233-44ca-8c19-89f7e2cbfc30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081858026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1081858026 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.2977946154 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 499548705 ps |
| CPU time | 37.12 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 07:58:29 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-b6cb813e-b7c5-46c8-848f-c807e240d810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977946154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.2977946154 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.726830666 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 285576010 ps |
| CPU time | 10.65 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 07:58:03 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-119ea235-e7bb-4105-bf2d-bd4504b198fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726830666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.726830666 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.3133269948 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 237089895 ps |
| CPU time | 9.47 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 07:58:02 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-59a55b49-dbf0-4afa-919e-513033246261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133269948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3133269948 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.1336651026 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 8972498000 ps |
| CPU time | 93.63 seconds |
| Started | Aug 09 07:57:47 PM PDT 24 |
| Finished | Aug 09 07:59:20 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-9ae3f54b-c79d-490f-af51-e368111c4ddf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336651026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1336651026 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2410780184 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 5036661796 ps |
| CPU time | 83.87 seconds |
| Started | Aug 09 07:57:42 PM PDT 24 |
| Finished | Aug 09 07:59:05 PM PDT 24 |
| Peak memory | 574820 kb |
| Host | smart-a1145479-2bdf-4c35-bd03-9081073f2f0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410780184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2410780184 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2023607920 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 42628751 ps |
| CPU time | 5.77 seconds |
| Started | Aug 09 07:57:47 PM PDT 24 |
| Finished | Aug 09 07:57:53 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-cadf565f-cbef-4164-aa7f-6197aca0c0e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023607920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .2023607920 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.1327495970 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 11196238461 ps |
| CPU time | 385.01 seconds |
| Started | Aug 09 07:57:45 PM PDT 24 |
| Finished | Aug 09 08:04:10 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-6231dfab-3192-4981-8259-bec5b84dd02c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327495970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1327495970 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2687819470 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 5525381526 ps |
| CPU time | 181.49 seconds |
| Started | Aug 09 07:57:50 PM PDT 24 |
| Finished | Aug 09 08:00:52 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-69511c4b-9e93-4d8e-a76e-1fe14a0ecfc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687819470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2687819470 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.195113103 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 412900148 ps |
| CPU time | 148.09 seconds |
| Started | Aug 09 07:57:49 PM PDT 24 |
| Finished | Aug 09 08:00:17 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-3949735e-1eea-4c8f-9b56-675ef6e812fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195113103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_w ith_rand_reset.195113103 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2957808192 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 52367764 ps |
| CPU time | 35.72 seconds |
| Started | Aug 09 07:57:47 PM PDT 24 |
| Finished | Aug 09 07:58:23 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-7f7875f6-53c4-46a8-9e4c-d54a971b0a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957808192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.2957808192 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.3669860436 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 126484361 ps |
| CPU time | 14.41 seconds |
| Started | Aug 09 07:57:50 PM PDT 24 |
| Finished | Aug 09 07:58:04 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-a778a359-46f9-4567-b3dc-c7d342761381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669860436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3669860436 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.3223579839 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 2887808610 ps |
| CPU time | 117.34 seconds |
| Started | Aug 09 08:01:43 PM PDT 24 |
| Finished | Aug 09 08:03:41 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-5f6e857b-b2be-4a94-bfea-b53ccb7d1268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223579839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .3223579839 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3914410109 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 90416740165 ps |
| CPU time | 1701.51 seconds |
| Started | Aug 09 08:01:37 PM PDT 24 |
| Finished | Aug 09 08:29:59 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-ad4f0234-113c-4fbe-96c1-7af385f16546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914410109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.3914410109 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.64388957 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 57236939 ps |
| CPU time | 9.38 seconds |
| Started | Aug 09 08:01:40 PM PDT 24 |
| Finished | Aug 09 08:01:50 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-a61167a4-5c0c-481a-9f21-1f3060bc6a7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64388957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.64388957 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.2734695116 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 255368315 ps |
| CPU time | 22.52 seconds |
| Started | Aug 09 08:01:43 PM PDT 24 |
| Finished | Aug 09 08:02:06 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-57338960-9147-4478-b166-39d19f9c79bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734695116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2734695116 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.1385873522 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 1821581288 ps |
| CPU time | 64.54 seconds |
| Started | Aug 09 08:01:38 PM PDT 24 |
| Finished | Aug 09 08:02:43 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-c6427cf1-130c-44bf-9afc-8915806cdec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385873522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.1385873522 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.1795612003 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 73617989279 ps |
| CPU time | 780.31 seconds |
| Started | Aug 09 08:01:42 PM PDT 24 |
| Finished | Aug 09 08:14:42 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-1a6b190d-b1af-45ef-ba20-7ea48c2c7287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795612003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1795612003 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.161741332 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 31935659402 ps |
| CPU time | 530.83 seconds |
| Started | Aug 09 08:01:40 PM PDT 24 |
| Finished | Aug 09 08:10:31 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-9fdcc120-f587-4b38-9fe8-ce944c8f8a1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161741332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.161741332 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2106327270 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 244346154 ps |
| CPU time | 25.56 seconds |
| Started | Aug 09 08:01:39 PM PDT 24 |
| Finished | Aug 09 08:02:04 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-dd3f7db9-f0c9-4fc5-b5b8-2b4111b5cec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106327270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.2106327270 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.1688432554 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 436081899 ps |
| CPU time | 30.56 seconds |
| Started | Aug 09 08:01:37 PM PDT 24 |
| Finished | Aug 09 08:02:08 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-0538eadc-35a3-4c92-898c-73ca25f5abf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688432554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1688432554 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.913715532 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 45828550 ps |
| CPU time | 6.79 seconds |
| Started | Aug 09 08:01:36 PM PDT 24 |
| Finished | Aug 09 08:01:43 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-5e046af9-f4c8-4129-af26-7d2b21b06fa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913715532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.913715532 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1315368346 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 7723980652 ps |
| CPU time | 77.63 seconds |
| Started | Aug 09 08:01:38 PM PDT 24 |
| Finished | Aug 09 08:02:55 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-8533da6f-ef9a-40dd-bba4-8bd1348a8945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315368346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1315368346 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.426961871 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 5190809290 ps |
| CPU time | 89.46 seconds |
| Started | Aug 09 08:01:41 PM PDT 24 |
| Finished | Aug 09 08:03:11 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-9df967d2-3bbb-4570-84aa-e89963cf8335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426961871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.426961871 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1615123876 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 49870962 ps |
| CPU time | 6.8 seconds |
| Started | Aug 09 08:01:43 PM PDT 24 |
| Finished | Aug 09 08:01:50 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-16a522b9-0f20-4906-85e6-476c888b0368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615123876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.1615123876 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.1355283151 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 1246894868 ps |
| CPU time | 104.14 seconds |
| Started | Aug 09 08:01:37 PM PDT 24 |
| Finished | Aug 09 08:03:21 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-bfbc66d8-5a8a-48bc-9741-94d370f2e8d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355283151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1355283151 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.3129662177 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 2065645544 ps |
| CPU time | 135.36 seconds |
| Started | Aug 09 08:01:43 PM PDT 24 |
| Finished | Aug 09 08:03:59 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-bfb86115-8a11-48e3-b2ae-d748a2f3cc27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129662177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3129662177 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2388703233 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 72724010 ps |
| CPU time | 34.36 seconds |
| Started | Aug 09 08:01:43 PM PDT 24 |
| Finished | Aug 09 08:02:17 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-b2d5dc86-da5d-4fcc-b349-6ec6ab697fd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388703233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.2388703233 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2386207998 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 729019497 ps |
| CPU time | 182.43 seconds |
| Started | Aug 09 08:01:43 PM PDT 24 |
| Finished | Aug 09 08:04:45 PM PDT 24 |
| Peak memory | 577052 kb |
| Host | smart-62550dab-6d85-48ec-87fd-783aaba5608f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386207998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.2386207998 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.2593327818 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 271390752 ps |
| CPU time | 14.52 seconds |
| Started | Aug 09 08:01:37 PM PDT 24 |
| Finished | Aug 09 08:01:52 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-dd035b5e-d6bb-4f5a-9b5c-36f4104b3c05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593327818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2593327818 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.127228599 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1788250049 ps |
| CPU time | 69.37 seconds |
| Started | Aug 09 08:01:48 PM PDT 24 |
| Finished | Aug 09 08:02:58 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-b347504a-766a-4136-bc3b-8d3d96231f4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127228599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device. 127228599 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3185537836 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 373429779 ps |
| CPU time | 17.56 seconds |
| Started | Aug 09 08:01:52 PM PDT 24 |
| Finished | Aug 09 08:02:09 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-321ba26b-8d62-49fa-99ff-d34b9e65885f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185537836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.3185537836 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.3664324389 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 614685344 ps |
| CPU time | 52.51 seconds |
| Started | Aug 09 08:01:50 PM PDT 24 |
| Finished | Aug 09 08:02:43 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-9b044b37-ef44-4178-a41d-154713eab807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664324389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3664324389 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.2665580382 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 1246263220 ps |
| CPU time | 42.42 seconds |
| Started | Aug 09 08:01:54 PM PDT 24 |
| Finished | Aug 09 08:02:36 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-2bbb14ef-700b-43a0-aae2-02316f1367d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665580382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.2665580382 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.4120740075 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 83750019383 ps |
| CPU time | 843.67 seconds |
| Started | Aug 09 08:01:44 PM PDT 24 |
| Finished | Aug 09 08:15:48 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-425fcf65-6256-4dd9-9dca-ec06cd647dac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120740075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.4120740075 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.1422537694 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 60799958100 ps |
| CPU time | 1138.28 seconds |
| Started | Aug 09 08:01:45 PM PDT 24 |
| Finished | Aug 09 08:20:43 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-ac2e8d1a-9b29-4ea3-a420-46ee163c692a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422537694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1422537694 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.134344034 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 64052753 ps |
| CPU time | 7.94 seconds |
| Started | Aug 09 08:01:53 PM PDT 24 |
| Finished | Aug 09 08:02:01 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-4fe47c13-14bd-46e9-a55c-a759442db01d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134344034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_dela ys.134344034 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.1972837339 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 710655007 ps |
| CPU time | 20.69 seconds |
| Started | Aug 09 08:01:42 PM PDT 24 |
| Finished | Aug 09 08:02:03 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-54f2bc92-5ca5-45b8-9ce7-81ba723578a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972837339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1972837339 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.819372562 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 178017172 ps |
| CPU time | 8.48 seconds |
| Started | Aug 09 08:01:43 PM PDT 24 |
| Finished | Aug 09 08:01:52 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-c26c1e78-f621-46bf-b35e-31023be949ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819372562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.819372562 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.3018076089 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 9187507410 ps |
| CPU time | 94.54 seconds |
| Started | Aug 09 08:01:44 PM PDT 24 |
| Finished | Aug 09 08:03:18 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-eff840dd-f2f4-4a06-bb7b-e1d31ba83404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018076089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3018076089 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2670250668 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 4654075905 ps |
| CPU time | 79.18 seconds |
| Started | Aug 09 08:01:48 PM PDT 24 |
| Finished | Aug 09 08:03:08 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-e7d50108-da75-4930-8a3d-ab3c1b66df11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670250668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2670250668 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3904837961 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 45550277 ps |
| CPU time | 5.74 seconds |
| Started | Aug 09 08:01:54 PM PDT 24 |
| Finished | Aug 09 08:01:59 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-fb429f98-bd62-409e-8dc7-4418a8e99b98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904837961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.3904837961 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.918825643 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 4315552982 ps |
| CPU time | 140.94 seconds |
| Started | Aug 09 08:02:00 PM PDT 24 |
| Finished | Aug 09 08:04:21 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-417f080e-8989-4d33-98d3-71ae8950f1d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918825643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.918825643 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.3369297280 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 15298053841 ps |
| CPU time | 556.94 seconds |
| Started | Aug 09 08:01:57 PM PDT 24 |
| Finished | Aug 09 08:11:14 PM PDT 24 |
| Peak memory | 577100 kb |
| Host | smart-ac8d788f-9da3-4c98-bf13-51592c024ce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369297280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3369297280 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2682756065 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 7461569 ps |
| CPU time | 3.76 seconds |
| Started | Aug 09 08:02:00 PM PDT 24 |
| Finished | Aug 09 08:02:04 PM PDT 24 |
| Peak memory | 565844 kb |
| Host | smart-d13c75ec-ce97-40fe-a957-8e17fe458799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682756065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.2682756065 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.50646872 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 312298785 ps |
| CPU time | 16.23 seconds |
| Started | Aug 09 08:01:52 PM PDT 24 |
| Finished | Aug 09 08:02:08 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-4b7e1320-bfb5-4c80-b65a-2d45bce978d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50646872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.50646872 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.172811075 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 1274322477 ps |
| CPU time | 43.68 seconds |
| Started | Aug 09 08:01:58 PM PDT 24 |
| Finished | Aug 09 08:02:41 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-3e30c17f-e88f-41e7-9cc7-60a693a5bbf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172811075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device. 172811075 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.284069038 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 74077063383 ps |
| CPU time | 1288.48 seconds |
| Started | Aug 09 08:01:57 PM PDT 24 |
| Finished | Aug 09 08:23:25 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-eb30edf7-972b-4834-b50a-78b301a73c27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284069038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_d evice_slow_rsp.284069038 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.2839201628 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 384398068 ps |
| CPU time | 15.59 seconds |
| Started | Aug 09 08:01:56 PM PDT 24 |
| Finished | Aug 09 08:02:12 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-eec4b7c7-015e-40b6-ab3f-4427e6d008cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839201628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.2839201628 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.3841588708 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 321151085 ps |
| CPU time | 12.6 seconds |
| Started | Aug 09 08:01:56 PM PDT 24 |
| Finished | Aug 09 08:02:09 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-8c96fff5-a42a-46b0-88a4-7737dfbb9474 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841588708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3841588708 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.1590111253 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 286395939 ps |
| CPU time | 24.56 seconds |
| Started | Aug 09 08:02:00 PM PDT 24 |
| Finished | Aug 09 08:02:24 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-a458453e-ee85-48c5-98eb-df435fa28910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590111253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.1590111253 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.2240758057 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 72177140410 ps |
| CPU time | 717.74 seconds |
| Started | Aug 09 08:01:56 PM PDT 24 |
| Finished | Aug 09 08:13:54 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-05b85f7c-209f-4d25-b4d0-6d2af0112d01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240758057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2240758057 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.190182316 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 37145853942 ps |
| CPU time | 592.12 seconds |
| Started | Aug 09 08:01:59 PM PDT 24 |
| Finished | Aug 09 08:11:52 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-69333c9d-550f-491a-bdcb-614190b818cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190182316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.190182316 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.3028849195 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 365017277 ps |
| CPU time | 30.94 seconds |
| Started | Aug 09 08:01:55 PM PDT 24 |
| Finished | Aug 09 08:02:26 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-44e78636-d685-4136-b096-ea276f683f1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028849195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.3028849195 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.4255037940 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 246237059 ps |
| CPU time | 20.25 seconds |
| Started | Aug 09 08:01:59 PM PDT 24 |
| Finished | Aug 09 08:02:20 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-0eafe11d-012d-44c3-afc6-e4d375e4218f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255037940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.4255037940 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.2916857891 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 48210474 ps |
| CPU time | 5.98 seconds |
| Started | Aug 09 08:01:59 PM PDT 24 |
| Finished | Aug 09 08:02:05 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-f82c5cbf-33ba-4b6c-bfbd-8ac32f18522d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916857891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2916857891 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.3014490473 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 10865300895 ps |
| CPU time | 114.47 seconds |
| Started | Aug 09 08:01:58 PM PDT 24 |
| Finished | Aug 09 08:03:52 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-f513d12e-e4e4-4671-b0e0-30ca22f27c99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014490473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3014490473 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2200380612 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 5593377609 ps |
| CPU time | 102.07 seconds |
| Started | Aug 09 08:01:57 PM PDT 24 |
| Finished | Aug 09 08:03:39 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-a84fb1d1-65c1-41aa-98e7-8d0845a72218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200380612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2200380612 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1973640563 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 44694031 ps |
| CPU time | 6.09 seconds |
| Started | Aug 09 08:01:58 PM PDT 24 |
| Finished | Aug 09 08:02:04 PM PDT 24 |
| Peak memory | 574824 kb |
| Host | smart-6cb423ae-e3fa-4616-97f9-30d0e06bb1d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973640563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.1973640563 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.166299468 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 3286005419 ps |
| CPU time | 234.17 seconds |
| Started | Aug 09 08:02:03 PM PDT 24 |
| Finished | Aug 09 08:05:57 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-fc562e0f-0f2c-42fa-ada5-42dd25def7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166299468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.166299468 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.1700088058 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 8740875061 ps |
| CPU time | 315.42 seconds |
| Started | Aug 09 08:02:04 PM PDT 24 |
| Finished | Aug 09 08:07:19 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-546485f2-29ab-40e7-9c83-f532f54f334d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700088058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1700088058 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3335198140 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 19386539706 ps |
| CPU time | 1008.18 seconds |
| Started | Aug 09 08:02:03 PM PDT 24 |
| Finished | Aug 09 08:18:51 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-872f902b-6bab-49dc-95d8-a2816bf9a22c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335198140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.3335198140 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1135753 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 8419466714 ps |
| CPU time | 387.83 seconds |
| Started | Aug 09 08:02:05 PM PDT 24 |
| Finished | Aug 09 08:08:33 PM PDT 24 |
| Peak memory | 577176 kb |
| Host | smart-f4338165-8a32-4b23-9d62-e941dcf05ef5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_w ith_reset_error.1135753 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.3443038579 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 104534701 ps |
| CPU time | 16.2 seconds |
| Started | Aug 09 08:01:58 PM PDT 24 |
| Finished | Aug 09 08:02:14 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-3ae71572-c43b-4f77-925b-e141dce470c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443038579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3443038579 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.3251052336 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 2750599909 ps |
| CPU time | 125.18 seconds |
| Started | Aug 09 08:02:11 PM PDT 24 |
| Finished | Aug 09 08:04:16 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-ccdb548b-175c-47da-ab5c-4b979437bd5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251052336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .3251052336 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.642993228 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 60642737781 ps |
| CPU time | 1104.11 seconds |
| Started | Aug 09 08:02:14 PM PDT 24 |
| Finished | Aug 09 08:20:38 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-a892a96c-d44c-4dc2-8571-6da409ae69bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642993228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_d evice_slow_rsp.642993228 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.4168714824 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 224230884 ps |
| CPU time | 25.55 seconds |
| Started | Aug 09 08:02:11 PM PDT 24 |
| Finished | Aug 09 08:02:36 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-c712d11d-b199-43ce-816a-d531031ff66d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168714824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.4168714824 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.3939622230 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 862884214 ps |
| CPU time | 33.83 seconds |
| Started | Aug 09 08:02:11 PM PDT 24 |
| Finished | Aug 09 08:02:45 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-a126e3f4-8b5e-4d9f-81c7-64853b90d77c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939622230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3939622230 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.3438958101 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 261747984 ps |
| CPU time | 13.31 seconds |
| Started | Aug 09 08:02:03 PM PDT 24 |
| Finished | Aug 09 08:02:17 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-eec7d9ea-e2b2-4ccb-a4d9-1d4db0b7cc75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438958101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.3438958101 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.2160050203 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 114584625671 ps |
| CPU time | 1196.31 seconds |
| Started | Aug 09 08:02:14 PM PDT 24 |
| Finished | Aug 09 08:22:10 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-125e60c4-fa5c-4598-a331-fc71a60146f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160050203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2160050203 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.3385174173 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 39637662733 ps |
| CPU time | 675.4 seconds |
| Started | Aug 09 08:02:10 PM PDT 24 |
| Finished | Aug 09 08:13:25 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-ebe5b3b9-4273-4f13-bdd7-422d861f7389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385174173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3385174173 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.673888898 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 91776282 ps |
| CPU time | 9.64 seconds |
| Started | Aug 09 08:02:04 PM PDT 24 |
| Finished | Aug 09 08:02:14 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-1eca81a0-78f1-4ce7-9fc8-860134b12eb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673888898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_dela ys.673888898 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.3338127525 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 950519559 ps |
| CPU time | 26.76 seconds |
| Started | Aug 09 08:02:10 PM PDT 24 |
| Finished | Aug 09 08:02:37 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-1e031123-8cd3-4490-9009-a9b76603a7a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338127525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3338127525 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.1666558004 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 54855866 ps |
| CPU time | 6.55 seconds |
| Started | Aug 09 08:02:04 PM PDT 24 |
| Finished | Aug 09 08:02:10 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-a4771432-a094-4170-b02c-4ff0663e3a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666558004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1666558004 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.2069500557 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 8519195766 ps |
| CPU time | 91.6 seconds |
| Started | Aug 09 08:02:05 PM PDT 24 |
| Finished | Aug 09 08:03:36 PM PDT 24 |
| Peak memory | 574920 kb |
| Host | smart-54f835c8-6cea-4e6a-824d-5489d43713ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069500557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2069500557 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1250954929 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 2994110439 ps |
| CPU time | 48.24 seconds |
| Started | Aug 09 08:02:03 PM PDT 24 |
| Finished | Aug 09 08:02:51 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-a1a8ebcb-6898-4270-a9f4-6adb5f03560a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250954929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1250954929 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2629396180 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 49555522 ps |
| CPU time | 6.85 seconds |
| Started | Aug 09 08:02:03 PM PDT 24 |
| Finished | Aug 09 08:02:10 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-dce1867d-8dab-4673-b678-fd209e5b2cdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629396180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.2629396180 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.2608219126 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 1243327031 ps |
| CPU time | 42.16 seconds |
| Started | Aug 09 08:02:10 PM PDT 24 |
| Finished | Aug 09 08:02:52 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-c73596b4-9506-4334-a1a8-fcb83066553d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608219126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2608219126 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3947010792 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 926064065 ps |
| CPU time | 76.57 seconds |
| Started | Aug 09 08:02:15 PM PDT 24 |
| Finished | Aug 09 08:03:32 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-06fa65ee-3bd4-4f50-b58f-ca5f33115a13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947010792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3947010792 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.208126885 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 887192138 ps |
| CPU time | 337.69 seconds |
| Started | Aug 09 08:02:17 PM PDT 24 |
| Finished | Aug 09 08:07:54 PM PDT 24 |
| Peak memory | 577088 kb |
| Host | smart-2f076931-4399-48c2-b585-7f5b83494bfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208126885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_ with_rand_reset.208126885 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1972149733 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 7349064572 ps |
| CPU time | 330.6 seconds |
| Started | Aug 09 08:02:17 PM PDT 24 |
| Finished | Aug 09 08:07:48 PM PDT 24 |
| Peak memory | 577100 kb |
| Host | smart-3f4c3830-8465-4f0a-9680-80f250f86cf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972149733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.1972149733 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.2038502983 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 247260914 ps |
| CPU time | 11.39 seconds |
| Started | Aug 09 08:02:12 PM PDT 24 |
| Finished | Aug 09 08:02:23 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-c2d10fdc-b122-466a-80b3-d14b281d5748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038502983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2038502983 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.4285436432 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 988984097 ps |
| CPU time | 78.1 seconds |
| Started | Aug 09 08:02:17 PM PDT 24 |
| Finished | Aug 09 08:03:36 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-c3949091-52b6-4e1e-95e8-c13befdfef93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285436432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .4285436432 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.114599935 |
| Short name | T2933 |
| Test name | |
| Test status | |
| Simulation time | 34127922345 ps |
| CPU time | 587.02 seconds |
| Started | Aug 09 08:02:17 PM PDT 24 |
| Finished | Aug 09 08:12:04 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-480f18df-54a8-40dd-90ad-a848eb084c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114599935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_d evice_slow_rsp.114599935 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3055562609 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 477353069 ps |
| CPU time | 22.11 seconds |
| Started | Aug 09 08:02:27 PM PDT 24 |
| Finished | Aug 09 08:02:50 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-7141c921-e01b-4647-92a7-7b425dcc8cb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055562609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.3055562609 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.2505749623 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 266806869 ps |
| CPU time | 22.33 seconds |
| Started | Aug 09 08:02:24 PM PDT 24 |
| Finished | Aug 09 08:02:47 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-3451dfc9-2df3-4d66-8803-a49d2f40c1f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505749623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2505749623 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.1481606383 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 196258282 ps |
| CPU time | 19.33 seconds |
| Started | Aug 09 08:02:21 PM PDT 24 |
| Finished | Aug 09 08:02:40 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-21dd981e-2a44-4019-9851-4ed41451cb56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481606383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.1481606383 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.1565270908 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 52185126919 ps |
| CPU time | 527.51 seconds |
| Started | Aug 09 08:02:16 PM PDT 24 |
| Finished | Aug 09 08:11:03 PM PDT 24 |
| Peak memory | 576964 kb |
| Host | smart-9676f6ce-0726-4cc0-a762-8bb7d8486ea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565270908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1565270908 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.83614253 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 38365809716 ps |
| CPU time | 692.19 seconds |
| Started | Aug 09 08:02:19 PM PDT 24 |
| Finished | Aug 09 08:13:51 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-427ce1c0-2291-4c2e-9cb2-b41036bcf8f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83614253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.83614253 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2310652343 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 93478765 ps |
| CPU time | 10.41 seconds |
| Started | Aug 09 08:02:20 PM PDT 24 |
| Finished | Aug 09 08:02:30 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-1febe5d8-ff67-42ee-a523-3ac58a27cff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310652343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.2310652343 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.3270090761 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 633390179 ps |
| CPU time | 20.12 seconds |
| Started | Aug 09 08:02:19 PM PDT 24 |
| Finished | Aug 09 08:02:39 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-88661fee-b0a0-488d-b3a4-f34734e0030a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270090761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3270090761 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.317431758 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 150498549 ps |
| CPU time | 7.89 seconds |
| Started | Aug 09 08:02:17 PM PDT 24 |
| Finished | Aug 09 08:02:25 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-b7608982-ff18-412f-8f9f-2093a6838d81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317431758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.317431758 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.3335252505 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 8295146666 ps |
| CPU time | 83.99 seconds |
| Started | Aug 09 08:02:18 PM PDT 24 |
| Finished | Aug 09 08:03:42 PM PDT 24 |
| Peak memory | 574912 kb |
| Host | smart-a14a7eb8-732f-4eb5-b430-d0e936c70568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335252505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3335252505 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3259086359 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 6030303567 ps |
| CPU time | 100.75 seconds |
| Started | Aug 09 08:02:16 PM PDT 24 |
| Finished | Aug 09 08:03:57 PM PDT 24 |
| Peak memory | 574852 kb |
| Host | smart-f04d60a2-1251-4473-bb29-19d1c265ff26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259086359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3259086359 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.2863881981 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 44233146 ps |
| CPU time | 5.95 seconds |
| Started | Aug 09 08:02:20 PM PDT 24 |
| Finished | Aug 09 08:02:26 PM PDT 24 |
| Peak memory | 574904 kb |
| Host | smart-d26bde8a-1461-4d42-a730-333fc5fcaacb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863881981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.2863881981 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.492510353 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 729108316 ps |
| CPU time | 62.27 seconds |
| Started | Aug 09 08:02:26 PM PDT 24 |
| Finished | Aug 09 08:03:28 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-1deb5cc3-6ef2-4199-9cf4-d9493b5188b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492510353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.492510353 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1604558224 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 2245684465 ps |
| CPU time | 78.46 seconds |
| Started | Aug 09 08:02:24 PM PDT 24 |
| Finished | Aug 09 08:03:42 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-7767abee-5713-42a2-9f96-1df3256ebd43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604558224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1604558224 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.4154963361 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2329935393 ps |
| CPU time | 232.94 seconds |
| Started | Aug 09 08:02:30 PM PDT 24 |
| Finished | Aug 09 08:06:23 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-749ac7eb-eb9b-425c-853d-a061be7e1e03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154963361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.4154963361 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.980361717 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 185625048 ps |
| CPU time | 86.47 seconds |
| Started | Aug 09 08:02:28 PM PDT 24 |
| Finished | Aug 09 08:03:54 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-b723a6e7-df7a-47ea-afa1-8569b690244e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980361717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_reset_error.980361717 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.2691238655 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 115263250 ps |
| CPU time | 14.26 seconds |
| Started | Aug 09 08:02:23 PM PDT 24 |
| Finished | Aug 09 08:02:37 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-2b82691f-8e44-4a5f-84b9-bf734f8688e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691238655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2691238655 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.1814099649 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 2650546863 ps |
| CPU time | 106.14 seconds |
| Started | Aug 09 08:02:33 PM PDT 24 |
| Finished | Aug 09 08:04:19 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-bcbcec2e-6531-4023-a76e-a5b4c9d69108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814099649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .1814099649 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2051976623 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 2439961598 ps |
| CPU time | 42.2 seconds |
| Started | Aug 09 08:02:33 PM PDT 24 |
| Finished | Aug 09 08:03:16 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-4fb186ea-abca-42e4-9163-00d0de9d3ac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051976623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.2051976623 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.4061223356 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 1010608233 ps |
| CPU time | 36.35 seconds |
| Started | Aug 09 08:02:33 PM PDT 24 |
| Finished | Aug 09 08:03:10 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-f45cdb9e-f8a1-4b10-8a43-f257f344b6a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061223356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.4061223356 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.2760878849 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 336658281 ps |
| CPU time | 26.54 seconds |
| Started | Aug 09 08:02:32 PM PDT 24 |
| Finished | Aug 09 08:02:58 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-8db57d92-2807-4413-871f-f93b0f0258b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760878849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2760878849 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.4032086329 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 216752248 ps |
| CPU time | 11.36 seconds |
| Started | Aug 09 08:02:30 PM PDT 24 |
| Finished | Aug 09 08:02:41 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-359f2d4b-e395-4da8-aeca-83bf80d82feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032086329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.4032086329 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.2157631644 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 79274485904 ps |
| CPU time | 870.2 seconds |
| Started | Aug 09 08:02:30 PM PDT 24 |
| Finished | Aug 09 08:17:00 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-4120473b-8712-493a-83bf-5b6ccfa53cb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157631644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2157631644 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.4177107822 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 18845325613 ps |
| CPU time | 301.16 seconds |
| Started | Aug 09 08:02:26 PM PDT 24 |
| Finished | Aug 09 08:07:28 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-cdc5a0fa-2456-4f1d-80d9-01bcad72337b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177107822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.4177107822 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2890785379 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 570609388 ps |
| CPU time | 44.9 seconds |
| Started | Aug 09 08:02:24 PM PDT 24 |
| Finished | Aug 09 08:03:09 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-e3fa77f0-bcb1-42bc-b906-e273c066514e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890785379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.2890785379 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.3945943754 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 334919814 ps |
| CPU time | 13.31 seconds |
| Started | Aug 09 08:02:31 PM PDT 24 |
| Finished | Aug 09 08:02:44 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-e4e8b0b8-dbd6-42be-a8bd-4bf98f92273e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945943754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3945943754 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.3773341591 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 160639391 ps |
| CPU time | 7.54 seconds |
| Started | Aug 09 08:02:25 PM PDT 24 |
| Finished | Aug 09 08:02:33 PM PDT 24 |
| Peak memory | 574856 kb |
| Host | smart-829bf450-f612-4f97-808d-beb2ccf2369f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773341591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3773341591 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.14150747 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 8905739806 ps |
| CPU time | 89.63 seconds |
| Started | Aug 09 08:02:23 PM PDT 24 |
| Finished | Aug 09 08:03:53 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-c104acbe-6c60-498a-9448-a9829ebc7aa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14150747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.14150747 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.3034976463 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 4933784233 ps |
| CPU time | 80.73 seconds |
| Started | Aug 09 08:02:26 PM PDT 24 |
| Finished | Aug 09 08:03:47 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-129dbd69-58dc-401c-8a24-8ae2db1710b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034976463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3034976463 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3223937610 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 45260565 ps |
| CPU time | 6.72 seconds |
| Started | Aug 09 08:02:25 PM PDT 24 |
| Finished | Aug 09 08:02:32 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-f75227f8-a62b-4d69-b5b3-4d3d54efdf5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223937610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.3223937610 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.1133670860 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 3026043232 ps |
| CPU time | 218.5 seconds |
| Started | Aug 09 08:02:33 PM PDT 24 |
| Finished | Aug 09 08:06:12 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-f1fcdcb9-334f-480e-a465-eaf08362feae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133670860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1133670860 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3428216737 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 2059331139 ps |
| CPU time | 71.37 seconds |
| Started | Aug 09 08:02:34 PM PDT 24 |
| Finished | Aug 09 08:03:46 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-7929b890-7555-4de4-8f5b-de69d4530514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428216737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3428216737 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3683741792 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 248541387 ps |
| CPU time | 39.03 seconds |
| Started | Aug 09 08:02:33 PM PDT 24 |
| Finished | Aug 09 08:03:12 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-cf88790a-8abb-4d44-a10a-bc47058a261b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683741792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.3683741792 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.278876034 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 1959483477 ps |
| CPU time | 310.88 seconds |
| Started | Aug 09 08:02:37 PM PDT 24 |
| Finished | Aug 09 08:07:48 PM PDT 24 |
| Peak memory | 577108 kb |
| Host | smart-9de6406c-f97d-455c-9d24-24046e394307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278876034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_reset_error.278876034 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.3952431908 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 795073086 ps |
| CPU time | 30.45 seconds |
| Started | Aug 09 08:02:32 PM PDT 24 |
| Finished | Aug 09 08:03:02 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-7aa32588-1102-4727-a8eb-6d12056057da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952431908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3952431908 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.4263175334 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 2761188322 ps |
| CPU time | 131.82 seconds |
| Started | Aug 09 08:02:37 PM PDT 24 |
| Finished | Aug 09 08:04:49 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-1be3b299-a251-4019-aa1c-1d4af0686ab6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263175334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .4263175334 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2983173289 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 17587812505 ps |
| CPU time | 301.97 seconds |
| Started | Aug 09 08:02:39 PM PDT 24 |
| Finished | Aug 09 08:07:41 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-b70b33da-4bfe-4988-ae3c-fe6b899a7835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983173289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.2983173289 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.973465132 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 833251359 ps |
| CPU time | 35.08 seconds |
| Started | Aug 09 08:02:38 PM PDT 24 |
| Finished | Aug 09 08:03:13 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-29f431a4-3202-4ce6-b19b-cf4d3ad0127a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973465132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr .973465132 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.3698051927 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 2059811547 ps |
| CPU time | 67.82 seconds |
| Started | Aug 09 08:02:37 PM PDT 24 |
| Finished | Aug 09 08:03:45 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-0ac289df-3f4a-4116-b865-2dc6536ab11c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698051927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3698051927 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.3555358170 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 526997035 ps |
| CPU time | 48.46 seconds |
| Started | Aug 09 08:02:40 PM PDT 24 |
| Finished | Aug 09 08:03:29 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-8874b7b3-827d-46cb-ae76-d712f0c5377c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555358170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.3555358170 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.3673298270 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 11294473074 ps |
| CPU time | 113.12 seconds |
| Started | Aug 09 08:02:37 PM PDT 24 |
| Finished | Aug 09 08:04:31 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-0af5e811-2af3-444b-84ee-7d3a49c86dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673298270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3673298270 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3088916932 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 62010930728 ps |
| CPU time | 1105.93 seconds |
| Started | Aug 09 08:02:39 PM PDT 24 |
| Finished | Aug 09 08:21:05 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-de13f41c-a87b-4795-a1f6-433837677b67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088916932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3088916932 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.364464593 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 337384862 ps |
| CPU time | 30.48 seconds |
| Started | Aug 09 08:02:37 PM PDT 24 |
| Finished | Aug 09 08:03:07 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-be2fb421-6dfb-4523-ad0d-b5268aad325c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364464593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_dela ys.364464593 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.2616374552 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 2598431422 ps |
| CPU time | 81.44 seconds |
| Started | Aug 09 08:02:38 PM PDT 24 |
| Finished | Aug 09 08:04:00 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-9282e9c2-885a-4402-b6bb-890c181588c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616374552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2616374552 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.70350126 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 189582295 ps |
| CPU time | 8.1 seconds |
| Started | Aug 09 08:02:38 PM PDT 24 |
| Finished | Aug 09 08:02:46 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-3cbd8bfb-7ebf-43cc-82c4-461ddc0c318d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70350126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.70350126 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.4170556584 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 6159758873 ps |
| CPU time | 62.54 seconds |
| Started | Aug 09 08:02:40 PM PDT 24 |
| Finished | Aug 09 08:03:42 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-5391d161-3bf7-4a8f-a339-57bf73a517cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170556584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.4170556584 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.4127803951 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 6634842839 ps |
| CPU time | 110.36 seconds |
| Started | Aug 09 08:02:38 PM PDT 24 |
| Finished | Aug 09 08:04:29 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-4a24bbfa-2493-43e3-b6db-e15d482c99e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127803951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.4127803951 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.2702958161 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 46425658 ps |
| CPU time | 6.13 seconds |
| Started | Aug 09 08:02:37 PM PDT 24 |
| Finished | Aug 09 08:02:44 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-c323b446-decc-45be-9a60-04a3507868bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702958161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.2702958161 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.801763989 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 211756273 ps |
| CPU time | 10.6 seconds |
| Started | Aug 09 08:02:52 PM PDT 24 |
| Finished | Aug 09 08:03:03 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-06af8121-4503-442b-a659-15c03e5d6f32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801763989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.801763989 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.3681560015 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 2963646455 ps |
| CPU time | 186.5 seconds |
| Started | Aug 09 08:02:48 PM PDT 24 |
| Finished | Aug 09 08:05:55 PM PDT 24 |
| Peak memory | 577112 kb |
| Host | smart-ce08d552-16a8-42b6-9ac0-701e7d30840e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681560015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3681560015 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.4073734725 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 5512597933 ps |
| CPU time | 433.78 seconds |
| Started | Aug 09 08:02:49 PM PDT 24 |
| Finished | Aug 09 08:10:03 PM PDT 24 |
| Peak memory | 577136 kb |
| Host | smart-e7e3381b-58b7-43b2-a1b2-4034c55786f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073734725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.4073734725 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.582003925 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 2081801218 ps |
| CPU time | 178.1 seconds |
| Started | Aug 09 08:02:47 PM PDT 24 |
| Finished | Aug 09 08:05:45 PM PDT 24 |
| Peak memory | 577068 kb |
| Host | smart-c10da9c4-18fe-4153-8c91-a3afdb75f97e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582003925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_reset_error.582003925 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.2717486928 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 259387347 ps |
| CPU time | 28.39 seconds |
| Started | Aug 09 08:02:38 PM PDT 24 |
| Finished | Aug 09 08:03:07 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-6c1ec755-6e0c-4d13-9ff1-7546d6247998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717486928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2717486928 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.1227835316 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 1931676813 ps |
| CPU time | 73.9 seconds |
| Started | Aug 09 08:02:59 PM PDT 24 |
| Finished | Aug 09 08:04:13 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-a36cb658-9395-425b-bf96-aeb65a0d9d99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227835316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .1227835316 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.584201821 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 92293468099 ps |
| CPU time | 1763.81 seconds |
| Started | Aug 09 08:02:58 PM PDT 24 |
| Finished | Aug 09 08:32:23 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-c8ba19b6-64bf-42b6-b6b2-fed33084fa77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584201821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_d evice_slow_rsp.584201821 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.81816373 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 582861911 ps |
| CPU time | 22.93 seconds |
| Started | Aug 09 08:02:56 PM PDT 24 |
| Finished | Aug 09 08:03:19 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-67cea2bc-8b70-426b-9a0e-b51ff3b8fc94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81816373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.81816373 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.370253598 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 93604445 ps |
| CPU time | 9.85 seconds |
| Started | Aug 09 08:03:05 PM PDT 24 |
| Finished | Aug 09 08:03:15 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-51ef8a90-a77c-47f0-b397-997a47e8d8c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370253598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.370253598 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.16572442 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 620859258 ps |
| CPU time | 52.9 seconds |
| Started | Aug 09 08:02:49 PM PDT 24 |
| Finished | Aug 09 08:03:42 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-341fa554-965f-4128-b07a-ab39ef0fbd59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16572442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.16572442 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.2372190726 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 56166001734 ps |
| CPU time | 556.21 seconds |
| Started | Aug 09 08:02:50 PM PDT 24 |
| Finished | Aug 09 08:12:06 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-389b0218-1b93-40d3-87d1-55d750a28ec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372190726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2372190726 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.384931102 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 43154578376 ps |
| CPU time | 713.39 seconds |
| Started | Aug 09 08:02:50 PM PDT 24 |
| Finished | Aug 09 08:14:44 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-d9647f65-dd1b-473e-b433-6410055955b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384931102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.384931102 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.3261616334 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 287468810 ps |
| CPU time | 27.92 seconds |
| Started | Aug 09 08:02:49 PM PDT 24 |
| Finished | Aug 09 08:03:17 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-61322028-98d3-4ac9-abf5-8f30cb32bc6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261616334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.3261616334 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.3957417022 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 1396317696 ps |
| CPU time | 38.13 seconds |
| Started | Aug 09 08:02:57 PM PDT 24 |
| Finished | Aug 09 08:03:35 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-aafc6e1d-b149-4539-b0cd-b5170d3fb233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957417022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3957417022 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2971884434 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 236113500 ps |
| CPU time | 9.49 seconds |
| Started | Aug 09 08:02:49 PM PDT 24 |
| Finished | Aug 09 08:02:59 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-0b34b391-8978-460d-8815-05ced5023cb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971884434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2971884434 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1362031140 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 6661228513 ps |
| CPU time | 70.09 seconds |
| Started | Aug 09 08:02:47 PM PDT 24 |
| Finished | Aug 09 08:03:57 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-e0a5c7a6-9eec-4283-9cc9-e69c676f1c61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362031140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1362031140 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1075470658 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 5103852380 ps |
| CPU time | 83.18 seconds |
| Started | Aug 09 08:02:52 PM PDT 24 |
| Finished | Aug 09 08:04:15 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-5cbc7172-de54-45d0-a095-0c1e0c2c9eb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075470658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1075470658 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.392696840 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 53977501 ps |
| CPU time | 6.45 seconds |
| Started | Aug 09 08:02:48 PM PDT 24 |
| Finished | Aug 09 08:02:54 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-0954cc7e-83d6-4a10-8ee5-342513cecc8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392696840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays .392696840 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.2574909184 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 4484034863 ps |
| CPU time | 177.44 seconds |
| Started | Aug 09 08:02:58 PM PDT 24 |
| Finished | Aug 09 08:05:56 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-a79eaec4-0ef1-43da-bad8-2daad7158819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574909184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2574909184 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.184935991 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 5167494487 ps |
| CPU time | 185.41 seconds |
| Started | Aug 09 08:03:05 PM PDT 24 |
| Finished | Aug 09 08:06:11 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-99d6835a-32f3-4a3a-b700-4fde81b5e958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184935991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.184935991 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3930047224 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 219843589 ps |
| CPU time | 65.05 seconds |
| Started | Aug 09 08:02:56 PM PDT 24 |
| Finished | Aug 09 08:04:01 PM PDT 24 |
| Peak memory | 576908 kb |
| Host | smart-af47ab84-717c-4c80-bd3e-2261f4d0a4e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930047224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.3930047224 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3125283534 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 11080154019 ps |
| CPU time | 507.56 seconds |
| Started | Aug 09 08:02:58 PM PDT 24 |
| Finished | Aug 09 08:11:25 PM PDT 24 |
| Peak memory | 577116 kb |
| Host | smart-53528587-6e49-4fe2-97e3-d59dc077d783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125283534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.3125283534 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1383567121 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 189598309 ps |
| CPU time | 24.05 seconds |
| Started | Aug 09 08:02:57 PM PDT 24 |
| Finished | Aug 09 08:03:22 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-b2bf1cb2-3b0e-4249-9154-57d8819ae62c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383567121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1383567121 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.198719563 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 376601350 ps |
| CPU time | 32.73 seconds |
| Started | Aug 09 08:02:57 PM PDT 24 |
| Finished | Aug 09 08:03:30 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-034151df-c5d9-48e8-b86f-75a093ea207c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198719563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device. 198719563 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.1547896519 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 44044153946 ps |
| CPU time | 776.96 seconds |
| Started | Aug 09 08:03:06 PM PDT 24 |
| Finished | Aug 09 08:16:03 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-76d1d0c8-592f-4fc9-a3db-c8435dfa4ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547896519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.1547896519 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1538416231 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 231177722 ps |
| CPU time | 28.13 seconds |
| Started | Aug 09 08:03:01 PM PDT 24 |
| Finished | Aug 09 08:03:30 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-812ea67b-8a5f-469a-802f-eed9316da5c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538416231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.1538416231 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.3215160753 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 810776223 ps |
| CPU time | 28.39 seconds |
| Started | Aug 09 08:03:03 PM PDT 24 |
| Finished | Aug 09 08:03:32 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-60df31fd-f4c4-41db-b6e7-48993fac1da6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215160753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3215160753 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.1043317288 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 579670471 ps |
| CPU time | 50.74 seconds |
| Started | Aug 09 08:03:02 PM PDT 24 |
| Finished | Aug 09 08:03:53 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-79833692-b504-49be-9f1d-33c791cc731e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043317288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.1043317288 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.269605717 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 113820361115 ps |
| CPU time | 1098.92 seconds |
| Started | Aug 09 08:03:06 PM PDT 24 |
| Finished | Aug 09 08:21:25 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-e0bb7548-c296-40e1-a069-cce66d36e95c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269605717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.269605717 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.2009157480 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 15323929596 ps |
| CPU time | 263.64 seconds |
| Started | Aug 09 08:02:56 PM PDT 24 |
| Finished | Aug 09 08:07:20 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-e454fe95-ff0c-481e-99dc-8ba07b9e2ca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009157480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2009157480 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.1449088967 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 463702840 ps |
| CPU time | 42.04 seconds |
| Started | Aug 09 08:02:58 PM PDT 24 |
| Finished | Aug 09 08:03:40 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-ee603b07-852f-420d-b345-ae3a284e6938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449088967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.1449088967 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.2751381164 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 116942597 ps |
| CPU time | 12.09 seconds |
| Started | Aug 09 08:02:57 PM PDT 24 |
| Finished | Aug 09 08:03:09 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-b0385fc5-faa5-4235-a141-e2556ec5889d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751381164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2751381164 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.2665166075 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 230091782 ps |
| CPU time | 10.11 seconds |
| Started | Aug 09 08:02:56 PM PDT 24 |
| Finished | Aug 09 08:03:06 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-61c902cf-0223-4ca1-a491-50315a12c195 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665166075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2665166075 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2943727607 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 7055298347 ps |
| CPU time | 77.73 seconds |
| Started | Aug 09 08:03:02 PM PDT 24 |
| Finished | Aug 09 08:04:20 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-272f1cb8-bb1e-4c65-b375-1d3bfeec6b24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943727607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2943727607 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3521944875 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 5544702527 ps |
| CPU time | 92.41 seconds |
| Started | Aug 09 08:02:57 PM PDT 24 |
| Finished | Aug 09 08:04:29 PM PDT 24 |
| Peak memory | 574944 kb |
| Host | smart-ce31ec7d-6177-49cc-a2df-a0453d4e410c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521944875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3521944875 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.3893029432 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 46214576 ps |
| CPU time | 6.41 seconds |
| Started | Aug 09 08:02:58 PM PDT 24 |
| Finished | Aug 09 08:03:05 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-7602fca1-8c90-4f9c-b18a-54e8fe1cfe18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893029432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.3893029432 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.1618054762 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2004036994 ps |
| CPU time | 171.49 seconds |
| Started | Aug 09 08:03:04 PM PDT 24 |
| Finished | Aug 09 08:05:55 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-cf7f2bb6-5033-441f-b21c-3d3501613484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618054762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1618054762 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3582556123 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 2605316634 ps |
| CPU time | 178.28 seconds |
| Started | Aug 09 08:03:04 PM PDT 24 |
| Finished | Aug 09 08:06:02 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-5395b401-cdaa-46fd-8107-89e768fd85a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582556123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3582556123 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.3588868157 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 332369333 ps |
| CPU time | 68.43 seconds |
| Started | Aug 09 08:03:04 PM PDT 24 |
| Finished | Aug 09 08:04:12 PM PDT 24 |
| Peak memory | 577056 kb |
| Host | smart-28447ce8-6aeb-4c0d-b7d3-7c3d2497a812 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588868157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.3588868157 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.1615611261 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 665523227 ps |
| CPU time | 180.55 seconds |
| Started | Aug 09 08:03:01 PM PDT 24 |
| Finished | Aug 09 08:06:02 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-3c253122-c062-4c4b-88d1-39bd0b68658a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615611261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.1615611261 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.3113384711 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 463211944 ps |
| CPU time | 22.26 seconds |
| Started | Aug 09 08:03:03 PM PDT 24 |
| Finished | Aug 09 08:03:25 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-ed5b89f2-2362-4fe8-b403-5685094b99cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113384711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3113384711 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.931141752 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 2882468798 ps |
| CPU time | 109.91 seconds |
| Started | Aug 09 08:03:12 PM PDT 24 |
| Finished | Aug 09 08:05:02 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-9c6b2506-c266-4220-a2b2-08d02996afbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931141752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device. 931141752 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.663409198 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 137733864906 ps |
| CPU time | 2605.56 seconds |
| Started | Aug 09 08:03:09 PM PDT 24 |
| Finished | Aug 09 08:46:35 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-aca7f00a-52a2-4ea6-b875-59ccb6062770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663409198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_d evice_slow_rsp.663409198 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3899315644 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 880937426 ps |
| CPU time | 35.99 seconds |
| Started | Aug 09 08:03:14 PM PDT 24 |
| Finished | Aug 09 08:03:50 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-865a58a3-2ee8-44e2-8903-4d1aa8514a8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899315644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.3899315644 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.2301358585 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 536247017 ps |
| CPU time | 40.44 seconds |
| Started | Aug 09 08:03:13 PM PDT 24 |
| Finished | Aug 09 08:03:53 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-2d1938d8-0f75-4124-a804-1c365387b659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301358585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2301358585 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.2239767840 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 131088079 ps |
| CPU time | 13.02 seconds |
| Started | Aug 09 08:03:03 PM PDT 24 |
| Finished | Aug 09 08:03:16 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-ab1467f3-8b96-4dfd-82a5-72fb09ab03ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239767840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2239767840 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.4189929793 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 19402470804 ps |
| CPU time | 206.9 seconds |
| Started | Aug 09 08:03:13 PM PDT 24 |
| Finished | Aug 09 08:06:40 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-c328f247-c473-433b-b5e3-b7e270fd53ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189929793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.4189929793 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.244395637 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 46613775417 ps |
| CPU time | 865.62 seconds |
| Started | Aug 09 08:03:10 PM PDT 24 |
| Finished | Aug 09 08:17:36 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-a8e302e6-317b-4473-be8a-995f00fe9437 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244395637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.244395637 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.2975172107 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 408292845 ps |
| CPU time | 39.25 seconds |
| Started | Aug 09 08:03:01 PM PDT 24 |
| Finished | Aug 09 08:03:40 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-026fef7a-1788-4ac8-a5b5-4ed524596cf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975172107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.2975172107 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.501758634 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 221632653 ps |
| CPU time | 10.34 seconds |
| Started | Aug 09 08:03:09 PM PDT 24 |
| Finished | Aug 09 08:03:19 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-fb3ded38-2820-4c6d-8924-cc0f19819661 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501758634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.501758634 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.2269610269 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 216358905 ps |
| CPU time | 9.62 seconds |
| Started | Aug 09 08:03:03 PM PDT 24 |
| Finished | Aug 09 08:03:12 PM PDT 24 |
| Peak memory | 575032 kb |
| Host | smart-2e75d35f-7eb2-49c2-a30c-0c8d84b5bd53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269610269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2269610269 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.193383631 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 7514116850 ps |
| CPU time | 77.36 seconds |
| Started | Aug 09 08:03:02 PM PDT 24 |
| Finished | Aug 09 08:04:19 PM PDT 24 |
| Peak memory | 574900 kb |
| Host | smart-b9b98058-58a0-4adf-85df-0d671758384f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193383631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.193383631 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.269077687 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 5110353347 ps |
| CPU time | 91.25 seconds |
| Started | Aug 09 08:03:02 PM PDT 24 |
| Finished | Aug 09 08:04:34 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-1202d3fa-b72b-4925-9937-be7db3d01212 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269077687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.269077687 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.157317767 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 38324296 ps |
| CPU time | 6.23 seconds |
| Started | Aug 09 08:03:01 PM PDT 24 |
| Finished | Aug 09 08:03:07 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-a1c538ee-7b22-4733-b8b1-97ef036e860c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157317767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays .157317767 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.3134352970 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 5086235953 ps |
| CPU time | 184.6 seconds |
| Started | Aug 09 08:03:12 PM PDT 24 |
| Finished | Aug 09 08:06:16 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-d758702c-7437-44a7-94d5-6745ef27fee5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134352970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3134352970 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.118088050 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 18978313120 ps |
| CPU time | 750.6 seconds |
| Started | Aug 09 08:03:09 PM PDT 24 |
| Finished | Aug 09 08:15:41 PM PDT 24 |
| Peak memory | 577180 kb |
| Host | smart-b224a380-e896-4c85-a2a2-f39ebeb07ae7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118088050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.118088050 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.4096467582 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 78586147 ps |
| CPU time | 32.19 seconds |
| Started | Aug 09 08:03:08 PM PDT 24 |
| Finished | Aug 09 08:03:41 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-58c5786d-6564-49e4-bd04-1f2cb5d72fe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096467582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.4096467582 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.759640359 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 381753693 ps |
| CPU time | 147.65 seconds |
| Started | Aug 09 08:03:18 PM PDT 24 |
| Finished | Aug 09 08:05:46 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-98e89315-3bb1-4afb-9316-13898d0d488b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759640359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_reset_error.759640359 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.2144683821 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 1172126173 ps |
| CPU time | 43.99 seconds |
| Started | Aug 09 08:03:09 PM PDT 24 |
| Finished | Aug 09 08:03:53 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-6b4af6fd-5d4c-43d2-a2cb-571f54e0762b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144683821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2144683821 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.2660646446 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 71039457794 ps |
| CPU time | 10542.4 seconds |
| Started | Aug 09 07:57:51 PM PDT 24 |
| Finished | Aug 09 10:53:35 PM PDT 24 |
| Peak memory | 639316 kb |
| Host | smart-b927a427-f566-43e9-acdb-c2f7b404a8c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660646446 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.2660646446 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.2335635766 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 61877811788 ps |
| CPU time | 6644 seconds |
| Started | Aug 09 07:57:53 PM PDT 24 |
| Finished | Aug 09 09:48:37 PM PDT 24 |
| Peak memory | 593092 kb |
| Host | smart-e3401021-876f-4649-b53e-45e788fd81f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335635766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.2335635766 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.3556502715 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 8176945877 ps |
| CPU time | 542.36 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 08:06:54 PM PDT 24 |
| Peak memory | 638868 kb |
| Host | smart-bbe11056-276c-4449-b42a-2a8450a1c37e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556502715 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.3556502715 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.3661194056 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4830501692 ps |
| CPU time | 346.1 seconds |
| Started | Aug 09 07:57:48 PM PDT 24 |
| Finished | Aug 09 08:03:34 PM PDT 24 |
| Peak memory | 597076 kb |
| Host | smart-79401d34-02d8-4a0d-b69c-0d3863b6d09d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661194056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.3661194056 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.2772682159 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 3245990317 ps |
| CPU time | 158.4 seconds |
| Started | Aug 09 07:57:48 PM PDT 24 |
| Finished | Aug 09 08:00:26 PM PDT 24 |
| Peak memory | 598932 kb |
| Host | smart-4cdb8d26-40e2-4dcd-aa5b-ac240cbd1720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772682159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2772682159 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.2668934042 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 1974472206 ps |
| CPU time | 74.73 seconds |
| Started | Aug 09 07:57:54 PM PDT 24 |
| Finished | Aug 09 07:59:09 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-9e3c41ad-ef20-4b4c-b302-37e4388df347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668934042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 2668934042 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.539572883 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 87850054951 ps |
| CPU time | 1418.12 seconds |
| Started | Aug 09 07:57:54 PM PDT 24 |
| Finished | Aug 09 08:21:33 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-5246124e-5fd5-40a9-8c5d-d0a6229f2233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539572883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_de vice_slow_rsp.539572883 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.4565970 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 712462861 ps |
| CPU time | 25.94 seconds |
| Started | Aug 09 07:57:48 PM PDT 24 |
| Finished | Aug 09 07:58:14 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-3d798f26-3021-4ca9-b698-078e3fab918c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4565970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.4565970 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.1805210393 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 1211658479 ps |
| CPU time | 42.28 seconds |
| Started | Aug 09 07:57:54 PM PDT 24 |
| Finished | Aug 09 07:58:36 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-a94dd800-d745-43e6-aa1d-c5a4cb7cf824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805210393 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1805210393 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.4206125982 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 428751341 ps |
| CPU time | 16.67 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 07:58:09 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-fc9745b4-cece-4b44-a178-4ae199dbdb6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206125982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.4206125982 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.3379162466 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 12520080571 ps |
| CPU time | 123.5 seconds |
| Started | Aug 09 07:57:50 PM PDT 24 |
| Finished | Aug 09 07:59:53 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-1f8b5317-b1c0-4dcf-847b-c5d9690b9f81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379162466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3379162466 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1677825066 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 38708854431 ps |
| CPU time | 595.85 seconds |
| Started | Aug 09 07:57:51 PM PDT 24 |
| Finished | Aug 09 08:07:47 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-f3dffa41-f70c-43fb-b089-f03e016f517f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677825066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1677825066 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3742351804 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 113754638 ps |
| CPU time | 13.09 seconds |
| Started | Aug 09 07:57:49 PM PDT 24 |
| Finished | Aug 09 07:58:02 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-b29d2a70-a989-4047-ab41-338acac8d4ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742351804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.3742351804 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.3394005732 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 545134275 ps |
| CPU time | 37.91 seconds |
| Started | Aug 09 07:57:46 PM PDT 24 |
| Finished | Aug 09 07:58:24 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-a981e433-982d-4ec1-8a3e-8f83cff10dae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394005732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3394005732 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.4004082218 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 53370317 ps |
| CPU time | 6.23 seconds |
| Started | Aug 09 07:57:51 PM PDT 24 |
| Finished | Aug 09 07:57:57 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-8e823406-6445-446f-9f81-c904b6f90944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004082218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4004082218 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2612690002 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 7227433918 ps |
| CPU time | 73.97 seconds |
| Started | Aug 09 07:57:49 PM PDT 24 |
| Finished | Aug 09 07:59:03 PM PDT 24 |
| Peak memory | 574912 kb |
| Host | smart-1c96e714-5f7d-4f06-b064-0248adf93825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612690002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2612690002 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1248348729 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 6009138748 ps |
| CPU time | 100.48 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 07:59:32 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-b1ceb474-3841-48fe-925d-bc5985cdb265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248348729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1248348729 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2597808641 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 43400283 ps |
| CPU time | 5.69 seconds |
| Started | Aug 09 07:57:50 PM PDT 24 |
| Finished | Aug 09 07:57:56 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-7636c244-4d4b-44b1-8f22-90427167fea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597808641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .2597808641 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.1847402994 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 5915986 ps |
| CPU time | 3.74 seconds |
| Started | Aug 09 07:57:53 PM PDT 24 |
| Finished | Aug 09 07:57:57 PM PDT 24 |
| Peak memory | 566492 kb |
| Host | smart-18ca1954-78c0-42c7-b8ad-b36c2e3b8e4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847402994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1847402994 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.945762873 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 10946400094 ps |
| CPU time | 326.05 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 08:03:18 PM PDT 24 |
| Peak memory | 577092 kb |
| Host | smart-ba3d9e2b-578e-401e-b7fe-b8d285e3dfe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945762873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.945762873 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.320939059 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 341054111 ps |
| CPU time | 128.68 seconds |
| Started | Aug 09 07:57:50 PM PDT 24 |
| Finished | Aug 09 07:59:59 PM PDT 24 |
| Peak memory | 577084 kb |
| Host | smart-ce13db1b-d3f3-4128-9904-235120c09fca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320939059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_w ith_rand_reset.320939059 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1678374592 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 4439079088 ps |
| CPU time | 278.91 seconds |
| Started | Aug 09 07:57:53 PM PDT 24 |
| Finished | Aug 09 08:02:32 PM PDT 24 |
| Peak memory | 577180 kb |
| Host | smart-61ab9bf4-cc3b-480d-a5d7-d5f381093d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678374592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.1678374592 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3872527722 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 458054003 ps |
| CPU time | 21.28 seconds |
| Started | Aug 09 07:57:48 PM PDT 24 |
| Finished | Aug 09 07:58:10 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-6859b20c-5f6c-48c2-a510-24c6bfd768c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872527722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3872527722 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.469592687 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 2396195123 ps |
| CPU time | 95.26 seconds |
| Started | Aug 09 08:03:16 PM PDT 24 |
| Finished | Aug 09 08:04:51 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-8300b9bb-f26b-48da-b547-7e7b81193869 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469592687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device. 469592687 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.168528492 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 97521536728 ps |
| CPU time | 1796.96 seconds |
| Started | Aug 09 08:03:19 PM PDT 24 |
| Finished | Aug 09 08:33:16 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-e72e0d5d-778a-412c-8af4-751df28284a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168528492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_d evice_slow_rsp.168528492 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.548977761 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 144411660 ps |
| CPU time | 16.95 seconds |
| Started | Aug 09 08:03:19 PM PDT 24 |
| Finished | Aug 09 08:03:36 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-9783c215-3e4c-45e4-9f8b-993f7355c75b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548977761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr .548977761 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.1586361448 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 1151081702 ps |
| CPU time | 35.04 seconds |
| Started | Aug 09 08:03:15 PM PDT 24 |
| Finished | Aug 09 08:03:50 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-be730671-96a1-43e7-9824-8558a8b281c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586361448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1586361448 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.691173622 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 1576160938 ps |
| CPU time | 54.77 seconds |
| Started | Aug 09 08:03:17 PM PDT 24 |
| Finished | Aug 09 08:04:11 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-e0f3d7a5-3ed9-47f4-bb84-00574f8af1ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691173622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.691173622 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.2269131755 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 51081157280 ps |
| CPU time | 517.91 seconds |
| Started | Aug 09 08:03:15 PM PDT 24 |
| Finished | Aug 09 08:11:53 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-f62d8d86-2646-40b6-8a9c-a9c70c5b71c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269131755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2269131755 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.980537443 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 3172663820 ps |
| CPU time | 50.91 seconds |
| Started | Aug 09 08:03:17 PM PDT 24 |
| Finished | Aug 09 08:04:08 PM PDT 24 |
| Peak memory | 574860 kb |
| Host | smart-863ef509-bd76-423a-b421-4899f19ae4db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980537443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.980537443 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1295242085 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 121903966 ps |
| CPU time | 12.73 seconds |
| Started | Aug 09 08:03:15 PM PDT 24 |
| Finished | Aug 09 08:03:28 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-09ed8cae-915f-4698-ba3a-c8391aeea8a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295242085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1295242085 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.187017753 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 1912193017 ps |
| CPU time | 50.38 seconds |
| Started | Aug 09 08:03:15 PM PDT 24 |
| Finished | Aug 09 08:04:05 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-115917e4-d9dd-45f2-887c-167bdc74c3c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187017753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.187017753 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3386080076 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 179323092 ps |
| CPU time | 8.64 seconds |
| Started | Aug 09 08:03:18 PM PDT 24 |
| Finished | Aug 09 08:03:27 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-65d3b7de-5fa6-4d44-9bce-b4012a70f232 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386080076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3386080076 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.3659250781 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 10068027243 ps |
| CPU time | 101.55 seconds |
| Started | Aug 09 08:03:15 PM PDT 24 |
| Finished | Aug 09 08:04:56 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-a54588b9-cc2b-47c6-afc7-f205d00343d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659250781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3659250781 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1510985654 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 5716973051 ps |
| CPU time | 98.08 seconds |
| Started | Aug 09 08:03:16 PM PDT 24 |
| Finished | Aug 09 08:04:54 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-201e2f8a-3a60-4a16-88d8-346c74edebb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510985654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1510985654 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.1203010002 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 41223823 ps |
| CPU time | 5.87 seconds |
| Started | Aug 09 08:03:18 PM PDT 24 |
| Finished | Aug 09 08:03:24 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-b5dc313e-5f47-4593-94a3-9efb45668f8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203010002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.1203010002 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.3122926980 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 2232086728 ps |
| CPU time | 184.09 seconds |
| Started | Aug 09 08:03:17 PM PDT 24 |
| Finished | Aug 09 08:06:21 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-cb1d1cd2-5160-4a2d-b8ca-d61ef1b6331c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122926980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3122926980 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1057843255 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 8992565200 ps |
| CPU time | 336.09 seconds |
| Started | Aug 09 08:03:17 PM PDT 24 |
| Finished | Aug 09 08:08:53 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-4bd49087-2e40-4b22-9c61-9b8b2c0630d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057843255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1057843255 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2110884294 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 56061943 ps |
| CPU time | 24.16 seconds |
| Started | Aug 09 08:03:18 PM PDT 24 |
| Finished | Aug 09 08:03:42 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-64acb4d8-854a-45c5-9533-9cbe00e3710a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110884294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.2110884294 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3226018471 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 5175395727 ps |
| CPU time | 600.79 seconds |
| Started | Aug 09 08:03:22 PM PDT 24 |
| Finished | Aug 09 08:13:23 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-27ac310c-dd44-445c-8878-facd4853fa2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226018471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.3226018471 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3277661680 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 193918934 ps |
| CPU time | 11.26 seconds |
| Started | Aug 09 08:03:16 PM PDT 24 |
| Finished | Aug 09 08:03:27 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-abb7fc82-2c25-4995-a8d0-f6e7a9a86b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277661680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3277661680 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.1162017900 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 1838184388 ps |
| CPU time | 74.45 seconds |
| Started | Aug 09 08:03:31 PM PDT 24 |
| Finished | Aug 09 08:04:45 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-64d6d217-a221-423b-8bbc-59bd5a845003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162017900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .1162017900 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1875630338 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 53757808472 ps |
| CPU time | 863.41 seconds |
| Started | Aug 09 08:03:31 PM PDT 24 |
| Finished | Aug 09 08:17:55 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-9d7ca62c-f4a0-4383-a4ad-09057e906476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875630338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.1875630338 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.829915047 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 442138447 ps |
| CPU time | 20.2 seconds |
| Started | Aug 09 08:03:29 PM PDT 24 |
| Finished | Aug 09 08:03:49 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-54c6ed3c-b98d-42c1-b849-710b802d4b05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829915047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr .829915047 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.3131714550 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 102086825 ps |
| CPU time | 11.31 seconds |
| Started | Aug 09 08:03:33 PM PDT 24 |
| Finished | Aug 09 08:03:44 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-85782249-3edb-4749-96e5-252cc12461fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131714550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3131714550 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.1449055344 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 428037192 ps |
| CPU time | 38.34 seconds |
| Started | Aug 09 08:03:26 PM PDT 24 |
| Finished | Aug 09 08:04:04 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-210497a5-8bb3-4496-824d-02965f46affa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449055344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.1449055344 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.4230396846 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 109620591209 ps |
| CPU time | 1222.65 seconds |
| Started | Aug 09 08:03:30 PM PDT 24 |
| Finished | Aug 09 08:23:53 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-ff41963a-ce0d-4935-8cf1-7f6d1a045231 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230396846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.4230396846 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.2584304251 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 7291707807 ps |
| CPU time | 114.23 seconds |
| Started | Aug 09 08:03:33 PM PDT 24 |
| Finished | Aug 09 08:05:27 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-e6d17bb5-d81e-4b5a-b8d6-f141bc25adba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584304251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2584304251 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2856723606 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 403614924 ps |
| CPU time | 38.38 seconds |
| Started | Aug 09 08:03:23 PM PDT 24 |
| Finished | Aug 09 08:04:01 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-951929bb-9d3d-40d6-9d50-9fd1edead0bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856723606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.2856723606 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.1925377455 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 407793211 ps |
| CPU time | 29.93 seconds |
| Started | Aug 09 08:03:30 PM PDT 24 |
| Finished | Aug 09 08:04:00 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-d192a5b4-ff35-4518-992d-3cb332197e2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925377455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1925377455 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.3311734382 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 198097297 ps |
| CPU time | 9.28 seconds |
| Started | Aug 09 08:03:23 PM PDT 24 |
| Finished | Aug 09 08:03:33 PM PDT 24 |
| Peak memory | 574796 kb |
| Host | smart-e68e5f95-d0fa-4233-b5e5-4b764b7f6050 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311734382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3311734382 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.222373337 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 7959926171 ps |
| CPU time | 83.66 seconds |
| Started | Aug 09 08:03:23 PM PDT 24 |
| Finished | Aug 09 08:04:47 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-b5662dde-2ef9-41d5-be79-f1d7196fca4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222373337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.222373337 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.478360583 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 5212755934 ps |
| CPU time | 85.04 seconds |
| Started | Aug 09 08:03:24 PM PDT 24 |
| Finished | Aug 09 08:04:49 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-421ebeff-3c07-4dd9-94ba-dc155880190d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478360583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.478360583 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.4269029850 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 43643133 ps |
| CPU time | 5.75 seconds |
| Started | Aug 09 08:03:23 PM PDT 24 |
| Finished | Aug 09 08:03:29 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-5e060b46-fff9-4956-aa09-44ba95aa3d2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269029850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.4269029850 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.2413175521 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 6849402668 ps |
| CPU time | 241.28 seconds |
| Started | Aug 09 08:03:28 PM PDT 24 |
| Finished | Aug 09 08:07:29 PM PDT 24 |
| Peak memory | 577084 kb |
| Host | smart-0628d5b4-c799-4e26-96cf-45e0b68cf889 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413175521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2413175521 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.1652157090 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 11800033877 ps |
| CPU time | 408.79 seconds |
| Started | Aug 09 08:03:33 PM PDT 24 |
| Finished | Aug 09 08:10:22 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-dd07f0ff-70cb-4f82-9842-63a130486ca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652157090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1652157090 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1286132412 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 229233100 ps |
| CPU time | 58.59 seconds |
| Started | Aug 09 08:03:33 PM PDT 24 |
| Finished | Aug 09 08:04:31 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-277c2620-88b7-40a8-9e6d-8be6537f06c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286132412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.1286132412 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.924238902 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 157344529 ps |
| CPU time | 18.78 seconds |
| Started | Aug 09 08:03:32 PM PDT 24 |
| Finished | Aug 09 08:03:50 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-541ecd6b-d432-4d18-bfcd-08b06e469dca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924238902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.924238902 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1650787497 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 14131209246 ps |
| CPU time | 248.73 seconds |
| Started | Aug 09 08:03:36 PM PDT 24 |
| Finished | Aug 09 08:07:44 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-065e6642-8a75-46bf-9ead-e61cbf4363fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650787497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.1650787497 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.836018360 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 41605657 ps |
| CPU time | 6.46 seconds |
| Started | Aug 09 08:03:43 PM PDT 24 |
| Finished | Aug 09 08:03:50 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-1a6c54bf-01e8-40d3-90c3-8875cc9bea31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836018360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr .836018360 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.278296403 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 103867422 ps |
| CPU time | 10.67 seconds |
| Started | Aug 09 08:03:35 PM PDT 24 |
| Finished | Aug 09 08:03:46 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-1a0a8149-3c8c-4b32-8367-20e3ba0c467b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278296403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.278296403 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.685447113 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1388108042 ps |
| CPU time | 54.55 seconds |
| Started | Aug 09 08:03:36 PM PDT 24 |
| Finished | Aug 09 08:04:31 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-c88fe63d-4a3e-43a5-92dd-731f30febb4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685447113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.685447113 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.1607055855 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 19406687851 ps |
| CPU time | 206.14 seconds |
| Started | Aug 09 08:03:40 PM PDT 24 |
| Finished | Aug 09 08:07:06 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-4d3403d8-71e8-4c8c-91d7-edfed770303d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607055855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1607055855 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.4046244197 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 53957380923 ps |
| CPU time | 963.11 seconds |
| Started | Aug 09 08:03:36 PM PDT 24 |
| Finished | Aug 09 08:19:39 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-e260b3cc-581f-444b-9a3c-040112250908 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046244197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.4046244197 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.803259135 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 449852647 ps |
| CPU time | 41.28 seconds |
| Started | Aug 09 08:03:37 PM PDT 24 |
| Finished | Aug 09 08:04:18 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-2cbf5630-8ae1-4a37-b48e-fe53e1a4b6ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803259135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_dela ys.803259135 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.1141198733 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 2252155431 ps |
| CPU time | 68.96 seconds |
| Started | Aug 09 08:03:37 PM PDT 24 |
| Finished | Aug 09 08:04:46 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-c8dc1d90-220a-4200-9863-8ae723309be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141198733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1141198733 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.167780021 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 151667547 ps |
| CPU time | 7.53 seconds |
| Started | Aug 09 08:03:39 PM PDT 24 |
| Finished | Aug 09 08:03:46 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-e0019091-db1e-4c84-9d43-84a09071edab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167780021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.167780021 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.802523027 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 6574655341 ps |
| CPU time | 69.31 seconds |
| Started | Aug 09 08:03:36 PM PDT 24 |
| Finished | Aug 09 08:04:45 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-ae449657-6232-4324-afde-042919494fcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802523027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.802523027 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3013394950 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 5626543309 ps |
| CPU time | 100.75 seconds |
| Started | Aug 09 08:03:35 PM PDT 24 |
| Finished | Aug 09 08:05:16 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-1acad93d-0081-4ef0-a898-2500f38091dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013394950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3013394950 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1329510484 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 49248338 ps |
| CPU time | 6.2 seconds |
| Started | Aug 09 08:03:35 PM PDT 24 |
| Finished | Aug 09 08:03:41 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-81295f01-0e1f-4931-933b-68e09f1465e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329510484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.1329510484 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.3425708692 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 8559630675 ps |
| CPU time | 260.06 seconds |
| Started | Aug 09 08:03:45 PM PDT 24 |
| Finished | Aug 09 08:08:05 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-19b806c0-b17c-4beb-90a9-6dcc6be64538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425708692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3425708692 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3547503960 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 2785217446 ps |
| CPU time | 86.06 seconds |
| Started | Aug 09 08:03:49 PM PDT 24 |
| Finished | Aug 09 08:05:16 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-380747fb-a3be-43f1-985c-8c93df10e18c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547503960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3547503960 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3297431606 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 4267184025 ps |
| CPU time | 509.98 seconds |
| Started | Aug 09 08:03:44 PM PDT 24 |
| Finished | Aug 09 08:12:14 PM PDT 24 |
| Peak memory | 577184 kb |
| Host | smart-a49a3d36-e402-4efa-932b-a4f1af9d90e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297431606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.3297431606 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.2696069526 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 6921281000 ps |
| CPU time | 319.34 seconds |
| Started | Aug 09 08:03:42 PM PDT 24 |
| Finished | Aug 09 08:09:01 PM PDT 24 |
| Peak memory | 577148 kb |
| Host | smart-5698b129-f324-4a13-944c-55fe9115292f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696069526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.2696069526 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.4048764429 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 198765598 ps |
| CPU time | 26.2 seconds |
| Started | Aug 09 08:03:46 PM PDT 24 |
| Finished | Aug 09 08:04:13 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-a644eec5-83d7-46e3-aaf9-8b2d2c722bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048764429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.4048764429 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.872703435 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 3108173351 ps |
| CPU time | 135.26 seconds |
| Started | Aug 09 08:03:43 PM PDT 24 |
| Finished | Aug 09 08:05:58 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-017350fb-3483-4807-90a4-28a7a05dfbf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872703435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device. 872703435 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2550264596 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 19297169404 ps |
| CPU time | 323.42 seconds |
| Started | Aug 09 08:03:44 PM PDT 24 |
| Finished | Aug 09 08:09:07 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-77826462-2bd6-4506-8469-7ec336a5f5d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550264596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.2550264596 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1047632630 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 41149646 ps |
| CPU time | 7.47 seconds |
| Started | Aug 09 08:03:50 PM PDT 24 |
| Finished | Aug 09 08:03:58 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-828a748b-01d1-4840-9f52-342734d8f225 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047632630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.1047632630 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.3179671607 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 2485533232 ps |
| CPU time | 70.33 seconds |
| Started | Aug 09 08:03:49 PM PDT 24 |
| Finished | Aug 09 08:05:00 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-75241f23-58f3-497c-aeb5-1315850e007b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179671607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3179671607 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.2709604355 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 73437534 ps |
| CPU time | 9.84 seconds |
| Started | Aug 09 08:03:45 PM PDT 24 |
| Finished | Aug 09 08:03:55 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-31ba7f5f-6718-4e9e-8ec5-ab80a34c59e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709604355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.2709604355 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.1129827375 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 73438669335 ps |
| CPU time | 733.63 seconds |
| Started | Aug 09 08:03:43 PM PDT 24 |
| Finished | Aug 09 08:15:57 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-90ab362e-9b98-4fd7-a6c3-5492f1174f0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129827375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1129827375 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.3084465272 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 46930919729 ps |
| CPU time | 850.57 seconds |
| Started | Aug 09 08:03:47 PM PDT 24 |
| Finished | Aug 09 08:17:58 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-7eaeb046-65e8-4d5c-a278-b18b8fef3579 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084465272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3084465272 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.2548787236 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 394234927 ps |
| CPU time | 36.63 seconds |
| Started | Aug 09 08:03:43 PM PDT 24 |
| Finished | Aug 09 08:04:19 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-de55dd39-cf09-47a1-b245-ce46264ba50b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548787236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.2548787236 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.405880621 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 423337771 ps |
| CPU time | 33.74 seconds |
| Started | Aug 09 08:03:50 PM PDT 24 |
| Finished | Aug 09 08:04:24 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-9fee6504-4899-4bb8-b7ca-8468fb696e9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405880621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.405880621 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.2778681369 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 146727511 ps |
| CPU time | 8.35 seconds |
| Started | Aug 09 08:03:43 PM PDT 24 |
| Finished | Aug 09 08:03:52 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-61d7fc1e-1ef0-4c05-ae15-0ed66197bfdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778681369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2778681369 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.418297069 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 8281290592 ps |
| CPU time | 90.19 seconds |
| Started | Aug 09 08:03:44 PM PDT 24 |
| Finished | Aug 09 08:05:14 PM PDT 24 |
| Peak memory | 574864 kb |
| Host | smart-842f0bf1-376f-42e5-85da-e5562bea0ea3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418297069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.418297069 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1574359164 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 5911642667 ps |
| CPU time | 96.53 seconds |
| Started | Aug 09 08:03:42 PM PDT 24 |
| Finished | Aug 09 08:05:18 PM PDT 24 |
| Peak memory | 574872 kb |
| Host | smart-e83a5b50-87d0-4fa8-b768-4f82cf96276e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574359164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1574359164 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3920377210 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 38850734 ps |
| CPU time | 6.49 seconds |
| Started | Aug 09 08:03:42 PM PDT 24 |
| Finished | Aug 09 08:03:49 PM PDT 24 |
| Peak memory | 574788 kb |
| Host | smart-eb2e5b85-6464-4a6e-8b5b-f52d478dbfba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920377210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.3920377210 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.1484258333 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 9557645939 ps |
| CPU time | 343.38 seconds |
| Started | Aug 09 08:03:50 PM PDT 24 |
| Finished | Aug 09 08:09:34 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-9bafd4c1-cfa9-4bdb-bb40-b28493137570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484258333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1484258333 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.578840910 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 11211717364 ps |
| CPU time | 405.83 seconds |
| Started | Aug 09 08:03:50 PM PDT 24 |
| Finished | Aug 09 08:10:36 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-d6865ee1-da83-4794-897c-98e43aca68fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578840910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.578840910 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.3186723839 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 211807897 ps |
| CPU time | 135.86 seconds |
| Started | Aug 09 08:03:50 PM PDT 24 |
| Finished | Aug 09 08:06:06 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-9a2060b2-586f-41de-99da-a89e365c0214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186723839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.3186723839 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.176783399 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 9617271078 ps |
| CPU time | 485.34 seconds |
| Started | Aug 09 08:03:51 PM PDT 24 |
| Finished | Aug 09 08:11:56 PM PDT 24 |
| Peak memory | 578152 kb |
| Host | smart-7c291d1e-cbd3-4d76-a299-c4ab400c7a4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176783399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_reset_error.176783399 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.681353817 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 271912508 ps |
| CPU time | 31.38 seconds |
| Started | Aug 09 08:03:57 PM PDT 24 |
| Finished | Aug 09 08:04:28 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-e79f29df-e405-43ad-83b3-b0591b16b4e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681353817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.681353817 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.790888510 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 2439602624 ps |
| CPU time | 102.1 seconds |
| Started | Aug 09 08:03:57 PM PDT 24 |
| Finished | Aug 09 08:05:39 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-a196165b-55bf-4ff5-a67c-2ce2fe2f51c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790888510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device. 790888510 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2379264436 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 15540391795 ps |
| CPU time | 259.04 seconds |
| Started | Aug 09 08:03:57 PM PDT 24 |
| Finished | Aug 09 08:08:16 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-ade78fd4-1ec9-428e-a964-e4b9400c963d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379264436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.2379264436 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1569017411 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 88170225 ps |
| CPU time | 11.84 seconds |
| Started | Aug 09 08:03:57 PM PDT 24 |
| Finished | Aug 09 08:04:09 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-8f79e9e8-5c2e-430a-a278-0cf796bf880d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569017411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.1569017411 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.51396643 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 55610904 ps |
| CPU time | 7.27 seconds |
| Started | Aug 09 08:03:56 PM PDT 24 |
| Finished | Aug 09 08:04:03 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-3473bceb-666d-41d6-a61c-b3a13cfe1171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51396643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.51396643 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.4117091720 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 736777366 ps |
| CPU time | 25.99 seconds |
| Started | Aug 09 08:03:56 PM PDT 24 |
| Finished | Aug 09 08:04:23 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-e1e3355f-a9ee-470f-aab9-5440373f830c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117091720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.4117091720 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.1763075821 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 6195351827 ps |
| CPU time | 60.2 seconds |
| Started | Aug 09 08:03:58 PM PDT 24 |
| Finished | Aug 09 08:04:58 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-4916d643-7cc0-4236-a4b7-0cddf2312ed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763075821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1763075821 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3039260696 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 34095181859 ps |
| CPU time | 556.75 seconds |
| Started | Aug 09 08:03:57 PM PDT 24 |
| Finished | Aug 09 08:13:13 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-cde503b2-dd9a-42d0-abb1-89ef95f2fc7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039260696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3039260696 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3971507796 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 252273502 ps |
| CPU time | 23.61 seconds |
| Started | Aug 09 08:03:50 PM PDT 24 |
| Finished | Aug 09 08:04:13 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-21aa76f3-bed1-4adf-925b-1b45ff4afc91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971507796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.3971507796 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.3554023027 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 1163833273 ps |
| CPU time | 29.29 seconds |
| Started | Aug 09 08:03:56 PM PDT 24 |
| Finished | Aug 09 08:04:25 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-73de2b4f-e374-4657-aac6-065f78d79ae7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554023027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3554023027 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3900855761 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 49740927 ps |
| CPU time | 6.33 seconds |
| Started | Aug 09 08:03:50 PM PDT 24 |
| Finished | Aug 09 08:03:57 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-9fe3e296-4ba9-49bd-a4a0-bb0264544565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900855761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3900855761 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.161196072 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 7820403604 ps |
| CPU time | 83.62 seconds |
| Started | Aug 09 08:03:56 PM PDT 24 |
| Finished | Aug 09 08:05:20 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-cf21940a-5611-432e-9d09-11537a6f110c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161196072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.161196072 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.1382551886 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 4497544216 ps |
| CPU time | 77.38 seconds |
| Started | Aug 09 08:03:51 PM PDT 24 |
| Finished | Aug 09 08:05:09 PM PDT 24 |
| Peak memory | 574936 kb |
| Host | smart-5f6498a2-a2eb-4836-9627-76e62e169c5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382551886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1382551886 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3186666946 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 54046199 ps |
| CPU time | 6.41 seconds |
| Started | Aug 09 08:03:53 PM PDT 24 |
| Finished | Aug 09 08:03:59 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-20ec63b2-da14-4564-a662-3055918107df |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186666946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.3186666946 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.1257128151 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 1786409005 ps |
| CPU time | 167.12 seconds |
| Started | Aug 09 08:03:57 PM PDT 24 |
| Finished | Aug 09 08:06:45 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-c3d09179-9f5d-48ea-8e7b-62da89d0a1a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257128151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1257128151 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2334571133 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 6546204 ps |
| CPU time | 3.86 seconds |
| Started | Aug 09 08:04:02 PM PDT 24 |
| Finished | Aug 09 08:04:06 PM PDT 24 |
| Peak memory | 565936 kb |
| Host | smart-11b7e04a-df00-4c07-b57b-96fd6803f713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334571133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2334571133 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1381663239 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 148578689 ps |
| CPU time | 56.33 seconds |
| Started | Aug 09 08:03:56 PM PDT 24 |
| Finished | Aug 09 08:04:52 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-710c3315-4037-4c4f-8fef-a62f6b805e47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381663239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.1381663239 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.355533622 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 85743044 ps |
| CPU time | 28 seconds |
| Started | Aug 09 08:03:55 PM PDT 24 |
| Finished | Aug 09 08:04:23 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-b703bb1d-49c4-4613-829d-d8809f59c26a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355533622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_reset_error.355533622 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.821987797 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 1172526063 ps |
| CPU time | 49.96 seconds |
| Started | Aug 09 08:03:57 PM PDT 24 |
| Finished | Aug 09 08:04:47 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-ece73790-186a-4ef7-8253-99395e867519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821987797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.821987797 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3150613760 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2208490512 ps |
| CPU time | 91.33 seconds |
| Started | Aug 09 08:04:04 PM PDT 24 |
| Finished | Aug 09 08:05:36 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-e873087e-311c-4718-84c7-2bc8231b8bc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150613760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3150613760 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.2941124234 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 14001778663 ps |
| CPU time | 228.11 seconds |
| Started | Aug 09 08:04:06 PM PDT 24 |
| Finished | Aug 09 08:07:54 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-a2d625ac-7af9-4a56-8d53-04dfada9eb33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941124234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.2941124234 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.4033912519 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 35958785 ps |
| CPU time | 6.39 seconds |
| Started | Aug 09 08:04:09 PM PDT 24 |
| Finished | Aug 09 08:04:15 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-9f8db582-2a35-4688-b5c6-3b0af81c7521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033912519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.4033912519 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.4077659475 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 107313692 ps |
| CPU time | 7.33 seconds |
| Started | Aug 09 08:04:05 PM PDT 24 |
| Finished | Aug 09 08:04:13 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-65966faa-926b-4329-a8f3-9e2b6e17bf73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077659475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.4077659475 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.3116617473 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2479989179 ps |
| CPU time | 80.17 seconds |
| Started | Aug 09 08:04:06 PM PDT 24 |
| Finished | Aug 09 08:05:26 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-10ecf692-564d-4a73-8d7a-1196bd228075 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116617473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.3116617473 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2409143384 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 7355019309 ps |
| CPU time | 81.8 seconds |
| Started | Aug 09 08:04:07 PM PDT 24 |
| Finished | Aug 09 08:05:29 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-d6b88204-ffc4-482d-89ce-6c02329f0928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409143384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2409143384 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.1723719918 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 11589493939 ps |
| CPU time | 202.81 seconds |
| Started | Aug 09 08:04:06 PM PDT 24 |
| Finished | Aug 09 08:07:29 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-97a77060-5dd5-4181-90b3-f8895cf8af1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723719918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1723719918 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.3119799833 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 171341827 ps |
| CPU time | 16.16 seconds |
| Started | Aug 09 08:04:07 PM PDT 24 |
| Finished | Aug 09 08:04:23 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-ca4f1971-6b55-4276-a456-40826e9df319 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119799833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.3119799833 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.3844692224 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 205531848 ps |
| CPU time | 18.91 seconds |
| Started | Aug 09 08:04:07 PM PDT 24 |
| Finished | Aug 09 08:04:26 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-92b6a549-0142-43c0-b9c2-978b27fd74ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844692224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3844692224 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.4210802367 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 49736284 ps |
| CPU time | 6.52 seconds |
| Started | Aug 09 08:03:57 PM PDT 24 |
| Finished | Aug 09 08:04:03 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-e30a0bba-c1f1-4810-ada0-0e3a9fe79a5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210802367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4210802367 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.4206856729 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 6598154483 ps |
| CPU time | 72.21 seconds |
| Started | Aug 09 08:04:08 PM PDT 24 |
| Finished | Aug 09 08:05:20 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-690a462f-289d-403b-8787-404741325532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206856729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.4206856729 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1435575845 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 7130271260 ps |
| CPU time | 118.11 seconds |
| Started | Aug 09 08:04:06 PM PDT 24 |
| Finished | Aug 09 08:06:04 PM PDT 24 |
| Peak memory | 574912 kb |
| Host | smart-00ec9afb-a756-488f-ac51-0cb2dbe3f6f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435575845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1435575845 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.433601163 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 53069858 ps |
| CPU time | 6.91 seconds |
| Started | Aug 09 08:04:04 PM PDT 24 |
| Finished | Aug 09 08:04:11 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-d7bed843-d475-4abc-b059-82b5f61901ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433601163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays .433601163 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.2516321920 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 199351545 ps |
| CPU time | 14.59 seconds |
| Started | Aug 09 08:04:16 PM PDT 24 |
| Finished | Aug 09 08:04:31 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-6f57a552-0ede-4629-987f-46acf8456345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516321920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2516321920 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.3390251856 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 8186499443 ps |
| CPU time | 241.14 seconds |
| Started | Aug 09 08:04:12 PM PDT 24 |
| Finished | Aug 09 08:08:14 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-ebaaef61-527a-4681-95b9-cd2c33c0857e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390251856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3390251856 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.341512182 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 13525346099 ps |
| CPU time | 701.61 seconds |
| Started | Aug 09 08:04:11 PM PDT 24 |
| Finished | Aug 09 08:15:53 PM PDT 24 |
| Peak memory | 577176 kb |
| Host | smart-7df244f3-758a-4071-b75e-12bd957d9171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341512182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_ with_rand_reset.341512182 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.348629859 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 2629967432 ps |
| CPU time | 179.37 seconds |
| Started | Aug 09 08:04:11 PM PDT 24 |
| Finished | Aug 09 08:07:11 PM PDT 24 |
| Peak memory | 577340 kb |
| Host | smart-606ed7d1-2ba7-448f-aeec-797d94a95345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348629859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_reset_error.348629859 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.3473587192 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 219665589 ps |
| CPU time | 24.38 seconds |
| Started | Aug 09 08:04:13 PM PDT 24 |
| Finished | Aug 09 08:04:38 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-549825d3-a0a8-405b-8d83-f97b3239d8b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473587192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3473587192 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.597354670 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 454815108 ps |
| CPU time | 29.98 seconds |
| Started | Aug 09 08:04:08 PM PDT 24 |
| Finished | Aug 09 08:04:38 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-6b850998-0317-49af-a9e6-c0df18bf6feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597354670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device. 597354670 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3200014132 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 115178443528 ps |
| CPU time | 2061.14 seconds |
| Started | Aug 09 08:04:16 PM PDT 24 |
| Finished | Aug 09 08:38:37 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-6f6cb8e2-6a8f-4c40-9099-302bf3ef97e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200014132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.3200014132 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2487328723 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 272362029 ps |
| CPU time | 27.56 seconds |
| Started | Aug 09 08:04:18 PM PDT 24 |
| Finished | Aug 09 08:04:46 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-b1da2342-9ab3-45af-a973-fcc960001e6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487328723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.2487328723 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.2071902014 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 520596743 ps |
| CPU time | 38.34 seconds |
| Started | Aug 09 08:04:11 PM PDT 24 |
| Finished | Aug 09 08:04:50 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-36c25572-521d-4968-87c3-2b099a6f522a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071902014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2071902014 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.4018942671 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 354843945 ps |
| CPU time | 14.7 seconds |
| Started | Aug 09 08:04:11 PM PDT 24 |
| Finished | Aug 09 08:04:26 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-2c5f2a29-a71d-4e8a-99db-21edadd83430 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018942671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.4018942671 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.2586949392 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 19685034881 ps |
| CPU time | 199.76 seconds |
| Started | Aug 09 08:04:11 PM PDT 24 |
| Finished | Aug 09 08:07:30 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-e2d62565-d4b5-469a-8160-90500e032ae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586949392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2586949392 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2359892216 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 10327628471 ps |
| CPU time | 177.44 seconds |
| Started | Aug 09 08:04:11 PM PDT 24 |
| Finished | Aug 09 08:07:08 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-0212c485-a0d0-4175-83f9-8b4ce1acd797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359892216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2359892216 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.422118669 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 300669942 ps |
| CPU time | 23.74 seconds |
| Started | Aug 09 08:04:11 PM PDT 24 |
| Finished | Aug 09 08:04:35 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-774353f1-f9a0-4783-9195-094fcec46fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422118669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_dela ys.422118669 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.1524347444 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2752480460 ps |
| CPU time | 82.11 seconds |
| Started | Aug 09 08:04:14 PM PDT 24 |
| Finished | Aug 09 08:05:36 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-87242a32-cc5e-4f78-9120-74deea192853 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524347444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1524347444 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.2820990050 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 45866804 ps |
| CPU time | 6.18 seconds |
| Started | Aug 09 08:04:16 PM PDT 24 |
| Finished | Aug 09 08:04:22 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-e1361570-c877-4430-9417-b2bea8d20086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820990050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2820990050 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1489574877 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 8840410546 ps |
| CPU time | 96.86 seconds |
| Started | Aug 09 08:04:10 PM PDT 24 |
| Finished | Aug 09 08:05:47 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-390b05c7-de93-4a61-ad2f-bbb5cc2fc6ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489574877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1489574877 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.48765924 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 5254920273 ps |
| CPU time | 85.72 seconds |
| Started | Aug 09 08:04:13 PM PDT 24 |
| Finished | Aug 09 08:05:39 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-48798eac-bffb-4b10-b3b1-b404762ff7b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48765924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.48765924 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.309985317 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 46291848 ps |
| CPU time | 6.46 seconds |
| Started | Aug 09 08:04:10 PM PDT 24 |
| Finished | Aug 09 08:04:16 PM PDT 24 |
| Peak memory | 574808 kb |
| Host | smart-52afe03c-159a-460d-9e31-cc7770e40197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309985317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays .309985317 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.2024973814 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 4894780362 ps |
| CPU time | 172.03 seconds |
| Started | Aug 09 08:04:21 PM PDT 24 |
| Finished | Aug 09 08:07:13 PM PDT 24 |
| Peak memory | 577224 kb |
| Host | smart-ccdcaa6e-a4e5-4088-891e-189fedc3a7ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024973814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2024973814 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.4216815647 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 3970782048 ps |
| CPU time | 313.07 seconds |
| Started | Aug 09 08:04:18 PM PDT 24 |
| Finished | Aug 09 08:09:32 PM PDT 24 |
| Peak memory | 577152 kb |
| Host | smart-c984aa66-c8e6-4c59-b0b7-efa63aede0c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216815647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.4216815647 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1690953634 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 763084896 ps |
| CPU time | 366.14 seconds |
| Started | Aug 09 08:04:20 PM PDT 24 |
| Finished | Aug 09 08:10:26 PM PDT 24 |
| Peak memory | 577280 kb |
| Host | smart-709ecf55-b41e-4c63-adba-6477c0ef0c89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690953634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.1690953634 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1780402498 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 847512554 ps |
| CPU time | 159.79 seconds |
| Started | Aug 09 08:04:16 PM PDT 24 |
| Finished | Aug 09 08:06:56 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-a0afec8d-c543-4ddd-916f-fb88af4d1a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780402498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.1780402498 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3323654480 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 336005018 ps |
| CPU time | 37.88 seconds |
| Started | Aug 09 08:04:11 PM PDT 24 |
| Finished | Aug 09 08:04:49 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-bab34f81-e82d-4235-ba42-215279b8cc36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323654480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3323654480 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.2713930072 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 1339384131 ps |
| CPU time | 46.63 seconds |
| Started | Aug 09 08:04:28 PM PDT 24 |
| Finished | Aug 09 08:05:15 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-de8bf008-7c51-415c-8ba9-3dd0ce6c1a60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713930072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .2713930072 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3154659275 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 12099363233 ps |
| CPU time | 207.44 seconds |
| Started | Aug 09 08:04:25 PM PDT 24 |
| Finished | Aug 09 08:07:53 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-796ecf67-f3df-459f-b604-45f639190053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154659275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.3154659275 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.455915029 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 49175897 ps |
| CPU time | 7.97 seconds |
| Started | Aug 09 08:04:25 PM PDT 24 |
| Finished | Aug 09 08:04:33 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-ea34ac44-ce45-40b0-9538-b85d2a6e1a14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455915029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr .455915029 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.1533544770 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 155549094 ps |
| CPU time | 7.41 seconds |
| Started | Aug 09 08:04:23 PM PDT 24 |
| Finished | Aug 09 08:04:31 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-047bcb73-c6cf-46f5-a8c4-8b2ce415d749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533544770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1533544770 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.143820393 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 136379187 ps |
| CPU time | 8.01 seconds |
| Started | Aug 09 08:04:19 PM PDT 24 |
| Finished | Aug 09 08:04:27 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-ae425b12-2fa4-4c66-a458-35cd8492d027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143820393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.143820393 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.1647539825 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 10423284561 ps |
| CPU time | 107.68 seconds |
| Started | Aug 09 08:04:23 PM PDT 24 |
| Finished | Aug 09 08:06:10 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-c8821dee-d87e-43e2-95b6-eb1cfc4c9c2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647539825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1647539825 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.3326059817 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 57923082733 ps |
| CPU time | 929.67 seconds |
| Started | Aug 09 08:04:23 PM PDT 24 |
| Finished | Aug 09 08:19:53 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-a7e8a2c1-a1c8-4f2c-8cdb-6ce21e59b871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326059817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3326059817 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.2448241322 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 218808723 ps |
| CPU time | 17.36 seconds |
| Started | Aug 09 08:04:23 PM PDT 24 |
| Finished | Aug 09 08:04:40 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-88506371-1909-41c0-b695-15c02c430484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448241322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.2448241322 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.303758551 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 1824464176 ps |
| CPU time | 46.23 seconds |
| Started | Aug 09 08:04:22 PM PDT 24 |
| Finished | Aug 09 08:05:09 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-6a0b68d4-a451-4eda-9657-4ca7c72ae920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303758551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.303758551 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.2639499950 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 227571525 ps |
| CPU time | 9.91 seconds |
| Started | Aug 09 08:04:18 PM PDT 24 |
| Finished | Aug 09 08:04:28 PM PDT 24 |
| Peak memory | 574828 kb |
| Host | smart-2dfc49c2-5031-4f4c-ae8b-8fe77468d0d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639499950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2639499950 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.863586638 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 6224210836 ps |
| CPU time | 62.79 seconds |
| Started | Aug 09 08:04:18 PM PDT 24 |
| Finished | Aug 09 08:05:21 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-5081c649-e6a4-494c-8097-1cb37e8cf3aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863586638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.863586638 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3971888830 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 4842860433 ps |
| CPU time | 73.55 seconds |
| Started | Aug 09 08:04:18 PM PDT 24 |
| Finished | Aug 09 08:05:32 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-c8e535ad-ac70-4bdf-81a8-42a90e86d022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971888830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3971888830 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1868060824 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 48572770 ps |
| CPU time | 5.86 seconds |
| Started | Aug 09 08:04:21 PM PDT 24 |
| Finished | Aug 09 08:04:27 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-1a818ede-0cbb-404f-978b-fa11f4124398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868060824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.1868060824 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.4181986153 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 1696864170 ps |
| CPU time | 114.2 seconds |
| Started | Aug 09 08:04:26 PM PDT 24 |
| Finished | Aug 09 08:06:21 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-e101b590-3ce0-4ef7-bcbf-411d222874ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181986153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.4181986153 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.4183441692 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 1160025792 ps |
| CPU time | 95.32 seconds |
| Started | Aug 09 08:04:26 PM PDT 24 |
| Finished | Aug 09 08:06:02 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-42b152c7-2245-4edf-a76a-897c21cd2c6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183441692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.4183441692 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2771123421 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 2455248383 ps |
| CPU time | 423.59 seconds |
| Started | Aug 09 08:04:28 PM PDT 24 |
| Finished | Aug 09 08:11:32 PM PDT 24 |
| Peak memory | 577096 kb |
| Host | smart-bb9a2607-7db8-45d3-90ed-175eb92b995a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771123421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.2771123421 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1242755027 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 5168731450 ps |
| CPU time | 447.26 seconds |
| Started | Aug 09 08:04:24 PM PDT 24 |
| Finished | Aug 09 08:11:51 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-c8c1d9c1-d57d-4fe8-bba7-1d5bdc64a7b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242755027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.1242755027 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.3422434423 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 152558607 ps |
| CPU time | 9.91 seconds |
| Started | Aug 09 08:04:25 PM PDT 24 |
| Finished | Aug 09 08:04:35 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-eb6ceb46-53e3-4641-be55-34aa2ce02762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422434423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3422434423 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.862972738 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 101819823 ps |
| CPU time | 8.94 seconds |
| Started | Aug 09 08:04:32 PM PDT 24 |
| Finished | Aug 09 08:04:41 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-8f452c72-35d0-461b-bb55-c03b7331044e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862972738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device. 862972738 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3511901399 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 19044105969 ps |
| CPU time | 313.57 seconds |
| Started | Aug 09 08:04:32 PM PDT 24 |
| Finished | Aug 09 08:09:45 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-abcbaa58-2d73-4573-8bcf-7ac5b9ed38f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511901399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.3511901399 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2029770786 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 265560832 ps |
| CPU time | 12.67 seconds |
| Started | Aug 09 08:04:31 PM PDT 24 |
| Finished | Aug 09 08:04:44 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-132fa831-52ce-48c2-89c7-9a320be2f86c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029770786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.2029770786 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.2691158087 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 2157085555 ps |
| CPU time | 72.4 seconds |
| Started | Aug 09 08:04:31 PM PDT 24 |
| Finished | Aug 09 08:05:44 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-ad09d0e1-f084-49c7-ad04-1e4fc54b9076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691158087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2691158087 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.2218312163 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 2098970996 ps |
| CPU time | 74.95 seconds |
| Started | Aug 09 08:04:31 PM PDT 24 |
| Finished | Aug 09 08:05:46 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-f83e6451-1abe-4f29-8eff-b7626e98e837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218312163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2218312163 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3106281733 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 56798434446 ps |
| CPU time | 607.4 seconds |
| Started | Aug 09 08:04:32 PM PDT 24 |
| Finished | Aug 09 08:14:39 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-44dde465-f35b-4aa9-ba8f-9440ab3afd07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106281733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3106281733 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.982970239 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 43148767072 ps |
| CPU time | 730.32 seconds |
| Started | Aug 09 08:04:32 PM PDT 24 |
| Finished | Aug 09 08:16:42 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-7555d225-21da-40d9-8608-f07e43d2d9f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982970239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.982970239 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.2354402941 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 514994125 ps |
| CPU time | 42.6 seconds |
| Started | Aug 09 08:04:33 PM PDT 24 |
| Finished | Aug 09 08:05:16 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-8c054227-533f-4031-be25-0f507edb1fd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354402941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.2354402941 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.3763030607 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 108351556 ps |
| CPU time | 9.91 seconds |
| Started | Aug 09 08:04:32 PM PDT 24 |
| Finished | Aug 09 08:04:42 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-0f674777-7595-412f-8eb5-40d5d6396242 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763030607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3763030607 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.1287229442 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 198133984 ps |
| CPU time | 9.28 seconds |
| Started | Aug 09 08:04:23 PM PDT 24 |
| Finished | Aug 09 08:04:33 PM PDT 24 |
| Peak memory | 574860 kb |
| Host | smart-688cfc0a-5304-4452-ac7f-9a4b6f6731e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287229442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1287229442 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.85740402 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 9257384382 ps |
| CPU time | 95.14 seconds |
| Started | Aug 09 08:04:33 PM PDT 24 |
| Finished | Aug 09 08:06:09 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-1dff0050-d7c6-46f8-9436-7a1f03b4512c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85740402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.85740402 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3259091766 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 5690097098 ps |
| CPU time | 96.85 seconds |
| Started | Aug 09 08:04:33 PM PDT 24 |
| Finished | Aug 09 08:06:09 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-0879b754-3840-40c1-bc3f-4844e39fb261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259091766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3259091766 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.4267492918 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 46468200 ps |
| CPU time | 6.83 seconds |
| Started | Aug 09 08:04:24 PM PDT 24 |
| Finished | Aug 09 08:04:31 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-5636fa9c-d8e5-492c-9cc5-9ed16e6abb1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267492918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.4267492918 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.519607108 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 1850166050 ps |
| CPU time | 72.22 seconds |
| Started | Aug 09 08:04:38 PM PDT 24 |
| Finished | Aug 09 08:05:50 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-68e24398-9e40-46f1-8de9-0c3e3213d8e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519607108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.519607108 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.3749310732 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 51632460 ps |
| CPU time | 6.17 seconds |
| Started | Aug 09 08:04:37 PM PDT 24 |
| Finished | Aug 09 08:04:43 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-8aa12134-e94c-467a-b10b-edca4db48ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749310732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3749310732 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1691053353 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 67888753 ps |
| CPU time | 12.82 seconds |
| Started | Aug 09 08:04:36 PM PDT 24 |
| Finished | Aug 09 08:04:49 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-1ec86c62-42c3-4a46-a216-f42069cb2628 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691053353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.1691053353 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1696151153 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 4979114215 ps |
| CPU time | 413.11 seconds |
| Started | Aug 09 08:04:39 PM PDT 24 |
| Finished | Aug 09 08:11:33 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-536ea0ef-f0e4-4929-ac13-fe696724701a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696151153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.1696151153 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.633714781 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 100997428 ps |
| CPU time | 7.67 seconds |
| Started | Aug 09 08:04:31 PM PDT 24 |
| Finished | Aug 09 08:04:38 PM PDT 24 |
| Peak memory | 574840 kb |
| Host | smart-9e994ecb-4cef-461f-9e41-6ccbc36841a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633714781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.633714781 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.1536208277 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 134306896 ps |
| CPU time | 20.22 seconds |
| Started | Aug 09 08:04:46 PM PDT 24 |
| Finished | Aug 09 08:05:06 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-54effd49-2e27-40dc-97e3-014816f7ca86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536208277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .1536208277 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2368379213 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 56327902209 ps |
| CPU time | 1014.1 seconds |
| Started | Aug 09 08:04:46 PM PDT 24 |
| Finished | Aug 09 08:21:40 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-c5f0f793-86b5-4965-91c2-bec4b84d79e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368379213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.2368379213 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.2595512372 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 151046580 ps |
| CPU time | 17.17 seconds |
| Started | Aug 09 08:04:43 PM PDT 24 |
| Finished | Aug 09 08:05:01 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-bfa1b027-750d-418b-a5a0-dba084fb7ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595512372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.2595512372 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.3966633575 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 2059511411 ps |
| CPU time | 65.27 seconds |
| Started | Aug 09 08:04:42 PM PDT 24 |
| Finished | Aug 09 08:05:48 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-1c72c59e-a8b8-4594-a6a5-0900cbc2ffe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966633575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3966633575 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.3238753723 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 459755953 ps |
| CPU time | 46.7 seconds |
| Started | Aug 09 08:04:39 PM PDT 24 |
| Finished | Aug 09 08:05:26 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-256d7333-6c96-4901-8916-a41f31fcab89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238753723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3238753723 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.479558971 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 9629106856 ps |
| CPU time | 92.92 seconds |
| Started | Aug 09 08:04:38 PM PDT 24 |
| Finished | Aug 09 08:06:11 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-f63ed193-07ad-4dda-b78a-68ab8cfeee69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479558971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.479558971 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2659038415 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 30148987897 ps |
| CPU time | 476.4 seconds |
| Started | Aug 09 08:04:36 PM PDT 24 |
| Finished | Aug 09 08:12:32 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-1d2c6f74-9fd8-43dc-aecb-2106a799119c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659038415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2659038415 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.1013564993 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 164668919 ps |
| CPU time | 17.38 seconds |
| Started | Aug 09 08:04:41 PM PDT 24 |
| Finished | Aug 09 08:04:58 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-92e5b8b5-ea25-473f-9284-06cf34479716 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013564993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.1013564993 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.2531209591 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 1010403751 ps |
| CPU time | 31 seconds |
| Started | Aug 09 08:04:45 PM PDT 24 |
| Finished | Aug 09 08:05:16 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-53a8f159-1b4d-433b-a5d2-ffce279a2fcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531209591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2531209591 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.2945878258 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 56100732 ps |
| CPU time | 6.28 seconds |
| Started | Aug 09 08:04:37 PM PDT 24 |
| Finished | Aug 09 08:04:43 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-4b480c81-1291-4140-8646-803fa3863727 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945878258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2945878258 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.3181598305 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 8018383806 ps |
| CPU time | 78.13 seconds |
| Started | Aug 09 08:04:39 PM PDT 24 |
| Finished | Aug 09 08:05:57 PM PDT 24 |
| Peak memory | 574920 kb |
| Host | smart-63f398c2-c6fc-4434-934a-cfab542adb64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181598305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3181598305 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1226355062 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 4542900639 ps |
| CPU time | 79.28 seconds |
| Started | Aug 09 08:04:37 PM PDT 24 |
| Finished | Aug 09 08:05:56 PM PDT 24 |
| Peak memory | 575056 kb |
| Host | smart-7a5fc633-7c59-4062-b2a8-0881529876af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226355062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1226355062 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.990845219 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 43874870 ps |
| CPU time | 5.9 seconds |
| Started | Aug 09 08:04:38 PM PDT 24 |
| Finished | Aug 09 08:04:44 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-90d3b26e-2686-42b5-ab30-49578853d7ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990845219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays .990845219 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.3393364773 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 22380929027 ps |
| CPU time | 893.03 seconds |
| Started | Aug 09 08:04:45 PM PDT 24 |
| Finished | Aug 09 08:19:39 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-0ce2dbfc-44f1-41b5-b54a-ada073c59153 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393364773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3393364773 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.4166450559 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 1365286983 ps |
| CPU time | 54.14 seconds |
| Started | Aug 09 08:04:44 PM PDT 24 |
| Finished | Aug 09 08:05:38 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-c7bffce5-35a1-4336-bbd2-2ce23eda9711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166450559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.4166450559 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.476839981 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 14899186097 ps |
| CPU time | 652.73 seconds |
| Started | Aug 09 08:04:46 PM PDT 24 |
| Finished | Aug 09 08:15:39 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-bb87a032-06a8-4f36-a82d-596c7e8f4de1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476839981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_ with_rand_reset.476839981 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2275469978 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4388403581 ps |
| CPU time | 548.61 seconds |
| Started | Aug 09 08:04:52 PM PDT 24 |
| Finished | Aug 09 08:14:01 PM PDT 24 |
| Peak memory | 583236 kb |
| Host | smart-508d1db6-ba46-467a-898d-9ea485052ad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275469978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.2275469978 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.3833359425 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 767642613 ps |
| CPU time | 33.77 seconds |
| Started | Aug 09 08:04:47 PM PDT 24 |
| Finished | Aug 09 08:05:20 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-44e66c1e-1f48-42de-a7e4-6063209edc05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833359425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3833359425 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.2165216406 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 6024474025 ps |
| CPU time | 542.29 seconds |
| Started | Aug 09 07:58:05 PM PDT 24 |
| Finished | Aug 09 08:07:07 PM PDT 24 |
| Peak memory | 598564 kb |
| Host | smart-a45167e4-6114-4b2f-84e0-8fdbae9be089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165216406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.2165216406 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2604128152 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 29798561267 ps |
| CPU time | 4318 seconds |
| Started | Aug 09 07:57:49 PM PDT 24 |
| Finished | Aug 09 09:09:47 PM PDT 24 |
| Peak memory | 593240 kb |
| Host | smart-b927d99c-8b86-4265-b2d2-80372589126f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604128152 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.2604128152 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.1750805736 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3305058238 ps |
| CPU time | 116.62 seconds |
| Started | Aug 09 07:57:48 PM PDT 24 |
| Finished | Aug 09 07:59:45 PM PDT 24 |
| Peak memory | 592728 kb |
| Host | smart-cba1b057-a571-4c56-b4e2-69187c21a005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750805736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.1750805736 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.3947261279 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 1563830531 ps |
| CPU time | 70.31 seconds |
| Started | Aug 09 07:57:50 PM PDT 24 |
| Finished | Aug 09 07:59:00 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-98db6e1f-9c60-4430-8b11-52ae15d3d9ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947261279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 3947261279 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3804678857 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 34716278339 ps |
| CPU time | 577.42 seconds |
| Started | Aug 09 07:57:51 PM PDT 24 |
| Finished | Aug 09 08:07:28 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-539b5077-2ad5-4aac-96be-cd33f0571e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804678857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.3804678857 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1179028188 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 478432476 ps |
| CPU time | 18.86 seconds |
| Started | Aug 09 07:57:54 PM PDT 24 |
| Finished | Aug 09 07:58:13 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-a5fc3dfe-e0fd-40ee-bd91-ad3c0d7478b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179028188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .1179028188 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.3495166690 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 598004386 ps |
| CPU time | 41.71 seconds |
| Started | Aug 09 07:57:49 PM PDT 24 |
| Finished | Aug 09 07:58:31 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-efde9ea4-1987-4491-ab8f-c1c42e3bb0c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495166690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3495166690 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.1612614607 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 779343172 ps |
| CPU time | 25.5 seconds |
| Started | Aug 09 07:57:50 PM PDT 24 |
| Finished | Aug 09 07:58:15 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-1b12d458-1db8-4c82-934c-93258cbda80c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612614607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.1612614607 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.2758615771 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 33158544009 ps |
| CPU time | 326.39 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 08:03:18 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-019f6e4c-54ab-4f28-bdc0-c840e64f6fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758615771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2758615771 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.2988494708 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 42905758463 ps |
| CPU time | 680.2 seconds |
| Started | Aug 09 07:57:51 PM PDT 24 |
| Finished | Aug 09 08:09:11 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-f92ce0dd-f844-4f98-a1a3-92376a4bca73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988494708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2988494708 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.3824284174 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 563155477 ps |
| CPU time | 46.21 seconds |
| Started | Aug 09 07:57:51 PM PDT 24 |
| Finished | Aug 09 07:58:37 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-78a10ee5-c637-4bbf-bd23-437233e0098e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824284174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.3824284174 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.3723110206 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 1548628537 ps |
| CPU time | 49.89 seconds |
| Started | Aug 09 07:57:53 PM PDT 24 |
| Finished | Aug 09 07:58:43 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-d51847f9-fc15-41c0-8a8c-76bef4ec9519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723110206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3723110206 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.2469909233 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 44732440 ps |
| CPU time | 6.05 seconds |
| Started | Aug 09 07:57:53 PM PDT 24 |
| Finished | Aug 09 07:57:59 PM PDT 24 |
| Peak memory | 574792 kb |
| Host | smart-89373b12-a5ff-4328-b462-0b666a9b8f6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469909233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2469909233 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.4036250034 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 8127321857 ps |
| CPU time | 83.01 seconds |
| Started | Aug 09 07:57:47 PM PDT 24 |
| Finished | Aug 09 07:59:10 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-c4f329d3-da53-4fec-920a-25a7e8b872e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036250034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4036250034 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.4114704329 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 6160651163 ps |
| CPU time | 95.32 seconds |
| Started | Aug 09 07:57:48 PM PDT 24 |
| Finished | Aug 09 07:59:23 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-88f6492f-7ae0-4028-8c73-8904dcc4b39f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114704329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.4114704329 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.1051378947 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 40711302 ps |
| CPU time | 5.77 seconds |
| Started | Aug 09 07:57:48 PM PDT 24 |
| Finished | Aug 09 07:57:53 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-25031d52-c795-4f3c-8560-0f3ce0b973b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051378947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .1051378947 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.3142310394 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 766058674 ps |
| CPU time | 56.27 seconds |
| Started | Aug 09 07:58:00 PM PDT 24 |
| Finished | Aug 09 07:58:56 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-b96d9509-31ac-4785-a424-aad2028e864f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142310394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3142310394 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.4070648503 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 15901284482 ps |
| CPU time | 542.96 seconds |
| Started | Aug 09 07:57:57 PM PDT 24 |
| Finished | Aug 09 08:07:00 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-423e5b9a-cd61-4b8a-95dd-41064c7b1398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070648503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4070648503 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1378277764 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 442222492 ps |
| CPU time | 135.52 seconds |
| Started | Aug 09 07:58:01 PM PDT 24 |
| Finished | Aug 09 08:00:16 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-6642c21f-9e11-44fe-8753-0fc32e075604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378277764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.1378277764 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.252622365 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 425167432 ps |
| CPU time | 21.2 seconds |
| Started | Aug 09 07:57:52 PM PDT 24 |
| Finished | Aug 09 07:58:14 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-c5a2fa38-fad1-4f9a-9b4e-48376be93b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252622365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.252622365 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.1249704230 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2279015473 ps |
| CPU time | 91.91 seconds |
| Started | Aug 09 08:04:52 PM PDT 24 |
| Finished | Aug 09 08:06:24 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-43304e30-bb68-41e4-aaa9-c34e24a38023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249704230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1249704230 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1559189289 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 14091413894 ps |
| CPU time | 232.11 seconds |
| Started | Aug 09 08:04:52 PM PDT 24 |
| Finished | Aug 09 08:08:44 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-51a5be7f-e818-4b90-b3b1-58f8e580d6af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559189289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.1559189289 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1814356837 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 216987327 ps |
| CPU time | 11.91 seconds |
| Started | Aug 09 08:04:58 PM PDT 24 |
| Finished | Aug 09 08:05:10 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-30639bdb-5423-40f4-9ef4-69974b6832d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814356837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.1814356837 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.2452224732 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 2198632022 ps |
| CPU time | 76.72 seconds |
| Started | Aug 09 08:04:50 PM PDT 24 |
| Finished | Aug 09 08:06:07 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-d5a65835-8148-487a-bf3f-082a20a77933 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452224732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.2452224732 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.3624968532 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 439513453 ps |
| CPU time | 36.64 seconds |
| Started | Aug 09 08:04:53 PM PDT 24 |
| Finished | Aug 09 08:05:30 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-262aedae-e4c4-42d9-8746-7eb29c822180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624968532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.3624968532 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.2178419239 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 39419764563 ps |
| CPU time | 371.26 seconds |
| Started | Aug 09 08:04:52 PM PDT 24 |
| Finished | Aug 09 08:11:03 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-041a42cf-3c8f-46f0-ba21-295be01ee3f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178419239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.2178419239 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.2577424004 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 53906752461 ps |
| CPU time | 908.82 seconds |
| Started | Aug 09 08:04:50 PM PDT 24 |
| Finished | Aug 09 08:19:59 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-40d45800-32ee-4330-b499-3a26623faf56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577424004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.2577424004 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1999554027 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 542819997 ps |
| CPU time | 45.31 seconds |
| Started | Aug 09 08:04:51 PM PDT 24 |
| Finished | Aug 09 08:05:36 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-6cd5536f-d9f3-4dd3-b23a-70a9998df383 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999554027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.1999554027 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.361702198 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 275396113 ps |
| CPU time | 20.15 seconds |
| Started | Aug 09 08:04:52 PM PDT 24 |
| Finished | Aug 09 08:05:13 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-817286fd-0e38-4527-913b-fa54d4842ef4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361702198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.361702198 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.3125589718 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 188959996 ps |
| CPU time | 8.75 seconds |
| Started | Aug 09 08:04:51 PM PDT 24 |
| Finished | Aug 09 08:05:00 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-ae7ede3f-5279-47ad-9118-c2675066308b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125589718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3125589718 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.3561391864 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 5639870153 ps |
| CPU time | 59.37 seconds |
| Started | Aug 09 08:04:52 PM PDT 24 |
| Finished | Aug 09 08:05:51 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-90e72b88-e256-41e9-97ce-bd3c4341b210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561391864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.3561391864 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.4164565605 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 3595476188 ps |
| CPU time | 57.67 seconds |
| Started | Aug 09 08:04:51 PM PDT 24 |
| Finished | Aug 09 08:05:49 PM PDT 24 |
| Peak memory | 574912 kb |
| Host | smart-37337c92-6d7d-407b-bda3-a26b1a5041d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164565605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.4164565605 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.4085356672 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 45976113 ps |
| CPU time | 6.27 seconds |
| Started | Aug 09 08:04:51 PM PDT 24 |
| Finished | Aug 09 08:04:57 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-cfe41752-f4b6-418a-a6b1-db888199632d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085356672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.4085356672 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.392729093 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 15379813361 ps |
| CPU time | 612.73 seconds |
| Started | Aug 09 08:04:59 PM PDT 24 |
| Finished | Aug 09 08:15:12 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-fb7b6e62-089d-4a44-aec1-0c192b18fa4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392729093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.392729093 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.2741115867 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 5132730328 ps |
| CPU time | 179.49 seconds |
| Started | Aug 09 08:04:57 PM PDT 24 |
| Finished | Aug 09 08:07:56 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-5c8b0741-5527-418e-9be5-513983aa7b23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741115867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.2741115867 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2076206296 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 4746986164 ps |
| CPU time | 566.72 seconds |
| Started | Aug 09 08:05:01 PM PDT 24 |
| Finished | Aug 09 08:14:28 PM PDT 24 |
| Peak memory | 577172 kb |
| Host | smart-915978e3-1a90-4843-aec4-a4d4d5e7b52f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076206296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.2076206296 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.4190218476 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 247486583 ps |
| CPU time | 42.73 seconds |
| Started | Aug 09 08:04:59 PM PDT 24 |
| Finished | Aug 09 08:05:42 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-357fa75b-20f0-409b-8d4b-c143ed8815f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190218476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.4190218476 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.1143933383 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 73382420 ps |
| CPU time | 12.3 seconds |
| Started | Aug 09 08:04:57 PM PDT 24 |
| Finished | Aug 09 08:05:09 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-aa9732ad-6829-49ee-ae2d-9714eb5c96e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143933383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1143933383 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.4081150008 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 2575481209 ps |
| CPU time | 106.85 seconds |
| Started | Aug 09 08:05:02 PM PDT 24 |
| Finished | Aug 09 08:06:48 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-8914d836-c991-4555-9324-106f1b2ece07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081150008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .4081150008 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.4081956501 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 9084593382 ps |
| CPU time | 156.33 seconds |
| Started | Aug 09 08:04:59 PM PDT 24 |
| Finished | Aug 09 08:07:36 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-544c9776-1d7f-4fd1-9fc9-2f9c0b1f2178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081956501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.4081956501 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.47249378 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 515248434 ps |
| CPU time | 21.58 seconds |
| Started | Aug 09 08:04:58 PM PDT 24 |
| Finished | Aug 09 08:05:20 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-47432933-d2a1-4e64-8567-91ccdf8f109c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47249378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr.47249378 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.2232853692 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 2320721392 ps |
| CPU time | 79.92 seconds |
| Started | Aug 09 08:04:58 PM PDT 24 |
| Finished | Aug 09 08:06:18 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-f41e0a0f-77f0-487e-bb18-a8e6ad434a57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232853692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.2232853692 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.3863432357 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 305782812 ps |
| CPU time | 26.33 seconds |
| Started | Aug 09 08:05:00 PM PDT 24 |
| Finished | Aug 09 08:05:26 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-fc3f9198-973a-4307-b9ba-5187b16cfa69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863432357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3863432357 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.293929457 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 98876957971 ps |
| CPU time | 1056.75 seconds |
| Started | Aug 09 08:04:59 PM PDT 24 |
| Finished | Aug 09 08:22:35 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-3dedc9dd-651b-4f80-a932-1e3f6d80c8d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293929457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.293929457 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2226717420 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 42071929791 ps |
| CPU time | 689.92 seconds |
| Started | Aug 09 08:05:00 PM PDT 24 |
| Finished | Aug 09 08:16:30 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-ea16cd05-9734-4d1f-b62c-53b17b1e5fac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226717420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2226717420 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.1814156299 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 474631853 ps |
| CPU time | 42.3 seconds |
| Started | Aug 09 08:04:58 PM PDT 24 |
| Finished | Aug 09 08:05:40 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-c1097695-bb93-42e9-9a1c-c0675d800622 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814156299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.1814156299 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.2463866919 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 272347411 ps |
| CPU time | 21.92 seconds |
| Started | Aug 09 08:05:01 PM PDT 24 |
| Finished | Aug 09 08:05:23 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-cba1ee67-7dcc-420a-a068-ce4dad088176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463866919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2463866919 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.3241940356 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 196657824 ps |
| CPU time | 8.75 seconds |
| Started | Aug 09 08:05:00 PM PDT 24 |
| Finished | Aug 09 08:05:08 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-b4547788-53ce-48dc-acd7-60ca273988ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241940356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.3241940356 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.922571525 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 6502090380 ps |
| CPU time | 69.98 seconds |
| Started | Aug 09 08:05:01 PM PDT 24 |
| Finished | Aug 09 08:06:11 PM PDT 24 |
| Peak memory | 574868 kb |
| Host | smart-1ef6523b-a951-4d1a-8efc-75b4408c16ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922571525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.922571525 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1661020012 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 5585201805 ps |
| CPU time | 90.57 seconds |
| Started | Aug 09 08:04:58 PM PDT 24 |
| Finished | Aug 09 08:06:29 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-e63c846c-c07f-47a2-a3c4-64bcb266359c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661020012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1661020012 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.4294055707 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 49809031 ps |
| CPU time | 6.03 seconds |
| Started | Aug 09 08:04:58 PM PDT 24 |
| Finished | Aug 09 08:05:04 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-697df6e0-fed1-42d6-8f93-b24d10f1e590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294055707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.4294055707 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.1307698686 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 5035923142 ps |
| CPU time | 202.94 seconds |
| Started | Aug 09 08:05:01 PM PDT 24 |
| Finished | Aug 09 08:08:24 PM PDT 24 |
| Peak memory | 577128 kb |
| Host | smart-ba675dc2-b912-4628-bd33-e6afb576f7d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307698686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1307698686 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.678070739 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 15895847241 ps |
| CPU time | 569.49 seconds |
| Started | Aug 09 08:05:05 PM PDT 24 |
| Finished | Aug 09 08:14:34 PM PDT 24 |
| Peak memory | 577156 kb |
| Host | smart-913ef36c-50c0-44ce-9806-764aa7846dae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678070739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.678070739 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1789175559 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 76299439 ps |
| CPU time | 47.89 seconds |
| Started | Aug 09 08:05:08 PM PDT 24 |
| Finished | Aug 09 08:05:56 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-632ffd26-b784-427e-8b3b-e0257356860f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789175559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.1789175559 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.3409507449 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 1085658996 ps |
| CPU time | 46.19 seconds |
| Started | Aug 09 08:04:57 PM PDT 24 |
| Finished | Aug 09 08:05:43 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-bc376109-a7bc-422c-8566-56459704b678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409507449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.3409507449 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.959648103 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 753162780 ps |
| CPU time | 75.18 seconds |
| Started | Aug 09 08:05:07 PM PDT 24 |
| Finished | Aug 09 08:06:22 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-5688c5eb-3e17-4928-9710-9cce57541b69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959648103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device. 959648103 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.1955479731 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 27743879186 ps |
| CPU time | 483.58 seconds |
| Started | Aug 09 08:05:10 PM PDT 24 |
| Finished | Aug 09 08:13:14 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-ffe6c055-5007-4f3b-bfbf-1de3c77a2593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955479731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.1955479731 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.3530390301 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 815350538 ps |
| CPU time | 31.2 seconds |
| Started | Aug 09 08:05:14 PM PDT 24 |
| Finished | Aug 09 08:05:45 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-8885a367-a6cc-4644-b890-16cc0e511937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530390301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.3530390301 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.2622491040 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 136643789 ps |
| CPU time | 7.6 seconds |
| Started | Aug 09 08:05:17 PM PDT 24 |
| Finished | Aug 09 08:05:25 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-42f2afa6-f63f-4bd6-b5f7-b3deb7bd074e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622491040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.2622491040 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.4264134820 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 211510865 ps |
| CPU time | 22.35 seconds |
| Started | Aug 09 08:05:11 PM PDT 24 |
| Finished | Aug 09 08:05:33 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-d4749cfa-a622-485c-9cda-862c09e25713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264134820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.4264134820 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.3285436128 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 100187899841 ps |
| CPU time | 1052.35 seconds |
| Started | Aug 09 08:05:07 PM PDT 24 |
| Finished | Aug 09 08:22:40 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-25288e47-9cb1-491e-8cef-2e080be67f4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285436128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.3285436128 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.1368129261 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 11437453336 ps |
| CPU time | 182.11 seconds |
| Started | Aug 09 08:05:06 PM PDT 24 |
| Finished | Aug 09 08:08:08 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-9eaf7be4-e4bd-46f4-9325-0c05688bcbd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368129261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.1368129261 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.4255918917 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 382052603 ps |
| CPU time | 35.39 seconds |
| Started | Aug 09 08:05:09 PM PDT 24 |
| Finished | Aug 09 08:05:45 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-dded244c-e7c1-4c91-b293-d5734ceeb692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255918917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.4255918917 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.349210103 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 1264967002 ps |
| CPU time | 37.51 seconds |
| Started | Aug 09 08:05:12 PM PDT 24 |
| Finished | Aug 09 08:05:49 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-d6c18b39-fd31-4f0e-8153-197c1e69e2cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349210103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.349210103 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.1207437848 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 42503829 ps |
| CPU time | 5.93 seconds |
| Started | Aug 09 08:05:09 PM PDT 24 |
| Finished | Aug 09 08:05:15 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-c14f6318-dac2-40e8-bf0d-3be832066c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207437848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.1207437848 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.1593300266 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 7920552982 ps |
| CPU time | 86.68 seconds |
| Started | Aug 09 08:05:06 PM PDT 24 |
| Finished | Aug 09 08:06:32 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-598fd3b1-c33c-43ce-b7b2-eace5d001d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593300266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.1593300266 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3529174741 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 4522328065 ps |
| CPU time | 77.67 seconds |
| Started | Aug 09 08:05:07 PM PDT 24 |
| Finished | Aug 09 08:06:24 PM PDT 24 |
| Peak memory | 574948 kb |
| Host | smart-09a2997c-f4ed-4cb7-8f4a-42477cc6d5bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529174741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.3529174741 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.119263232 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 44915849 ps |
| CPU time | 6.04 seconds |
| Started | Aug 09 08:05:05 PM PDT 24 |
| Finished | Aug 09 08:05:11 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-292fd611-3410-4e00-bc01-5a03eaee9013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119263232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays .119263232 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.3644952409 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 6255399091 ps |
| CPU time | 217.33 seconds |
| Started | Aug 09 08:05:19 PM PDT 24 |
| Finished | Aug 09 08:08:56 PM PDT 24 |
| Peak memory | 577168 kb |
| Host | smart-6eafef11-48ae-4c52-908d-36870a750bd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644952409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.3644952409 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.1256258932 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 7714442891 ps |
| CPU time | 292.18 seconds |
| Started | Aug 09 08:05:12 PM PDT 24 |
| Finished | Aug 09 08:10:04 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-6ec9562c-57bf-402c-b90c-eb6b7065e00f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256258932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.1256258932 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3763464296 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 4184872105 ps |
| CPU time | 189.39 seconds |
| Started | Aug 09 08:05:18 PM PDT 24 |
| Finished | Aug 09 08:08:27 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-251545af-9ac4-4550-82de-20355b620f75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763464296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.3763464296 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1533918974 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 2658474595 ps |
| CPU time | 119.63 seconds |
| Started | Aug 09 08:05:13 PM PDT 24 |
| Finished | Aug 09 08:07:12 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-0bfdfc74-c54d-4082-a6ec-6692e12ee4ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533918974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.1533918974 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.4097400268 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 200074731 ps |
| CPU time | 21.76 seconds |
| Started | Aug 09 08:05:12 PM PDT 24 |
| Finished | Aug 09 08:05:34 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-07de6edd-4d6b-4993-b140-08b10f15c6b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097400268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.4097400268 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.4185761742 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 1781178498 ps |
| CPU time | 66.9 seconds |
| Started | Aug 09 08:05:27 PM PDT 24 |
| Finished | Aug 09 08:06:34 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-23ebbfc1-6c20-4654-b452-eefb5377131f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185761742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .4185761742 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1480615326 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 535585774 ps |
| CPU time | 24.56 seconds |
| Started | Aug 09 08:05:19 PM PDT 24 |
| Finished | Aug 09 08:05:44 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-805a096f-0185-4748-ae25-d6c385108428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480615326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.1480615326 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.278757399 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 88735455 ps |
| CPU time | 9.38 seconds |
| Started | Aug 09 08:05:20 PM PDT 24 |
| Finished | Aug 09 08:05:29 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-37824fde-5226-4ea1-8833-6481d4eadbf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278757399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.278757399 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.2184906621 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 381318620 ps |
| CPU time | 29.11 seconds |
| Started | Aug 09 08:05:19 PM PDT 24 |
| Finished | Aug 09 08:05:48 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-d3b727b2-623f-4196-abea-02ae8a565487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184906621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.2184906621 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.503912080 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 59791822721 ps |
| CPU time | 680.61 seconds |
| Started | Aug 09 08:05:23 PM PDT 24 |
| Finished | Aug 09 08:16:44 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-1fe531eb-9b6d-4600-9126-0aeb504fcf30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503912080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.503912080 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.93081440 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 45100439077 ps |
| CPU time | 807.17 seconds |
| Started | Aug 09 08:05:18 PM PDT 24 |
| Finished | Aug 09 08:18:46 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-90eb4405-f42e-4e26-b240-49a139c07a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93081440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.93081440 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.563629416 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 496210467 ps |
| CPU time | 43.47 seconds |
| Started | Aug 09 08:05:19 PM PDT 24 |
| Finished | Aug 09 08:06:02 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-4cd8c9e2-a26d-4257-a4e3-2db59cfc5c91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563629416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_dela ys.563629416 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.4009847571 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 1091172197 ps |
| CPU time | 30.29 seconds |
| Started | Aug 09 08:05:26 PM PDT 24 |
| Finished | Aug 09 08:05:57 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-ae1b75cb-79af-4446-90c4-1b91e2adf1a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009847571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.4009847571 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.1744808765 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 45364935 ps |
| CPU time | 6.23 seconds |
| Started | Aug 09 08:05:13 PM PDT 24 |
| Finished | Aug 09 08:05:19 PM PDT 24 |
| Peak memory | 574792 kb |
| Host | smart-4bbce128-d6b6-4df2-a1af-ca53c98b8f0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744808765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1744808765 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.1180482827 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 9783657508 ps |
| CPU time | 99.56 seconds |
| Started | Aug 09 08:05:12 PM PDT 24 |
| Finished | Aug 09 08:06:52 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-f1caa9cc-b5b9-4325-bfab-4c341beb0e2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180482827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.1180482827 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1460496046 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 5092707160 ps |
| CPU time | 82.01 seconds |
| Started | Aug 09 08:05:17 PM PDT 24 |
| Finished | Aug 09 08:06:40 PM PDT 24 |
| Peak memory | 574892 kb |
| Host | smart-d9cdc7c9-7097-4e07-a048-920835d18cab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460496046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1460496046 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1281649116 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 47732440 ps |
| CPU time | 6.73 seconds |
| Started | Aug 09 08:05:12 PM PDT 24 |
| Finished | Aug 09 08:05:19 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-d070c6db-580c-4e37-9f32-5d882f920a7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281649116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.1281649116 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.2255018969 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 2089520810 ps |
| CPU time | 81.35 seconds |
| Started | Aug 09 08:05:24 PM PDT 24 |
| Finished | Aug 09 08:06:46 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-71b9b77e-31d9-4f70-8b00-cd13e07c6269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255018969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.2255018969 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.4112779240 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 582915767 ps |
| CPU time | 48.86 seconds |
| Started | Aug 09 08:05:20 PM PDT 24 |
| Finished | Aug 09 08:06:08 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-eef4b412-c213-4c0e-b9e6-76874b9b14fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112779240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.4112779240 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.4271380998 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 1727000283 ps |
| CPU time | 263.86 seconds |
| Started | Aug 09 08:05:23 PM PDT 24 |
| Finished | Aug 09 08:09:46 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-b620e9d5-ca2a-4180-b060-bc47bdfbace1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271380998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.4271380998 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2734327735 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 2237374061 ps |
| CPU time | 206.7 seconds |
| Started | Aug 09 08:05:19 PM PDT 24 |
| Finished | Aug 09 08:08:46 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-700a7a5e-49f5-41ba-ada3-aa14705ccec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734327735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.2734327735 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2363207400 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 127926798 ps |
| CPU time | 17.26 seconds |
| Started | Aug 09 08:05:20 PM PDT 24 |
| Finished | Aug 09 08:05:38 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-339b8df8-687b-4410-9e2f-18191342c3dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363207400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.2363207400 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.1817793923 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 1173892553 ps |
| CPU time | 48.45 seconds |
| Started | Aug 09 08:05:26 PM PDT 24 |
| Finished | Aug 09 08:06:14 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-14b777d1-91b9-41d4-9115-35f403e7cff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817793923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .1817793923 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2489854531 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 59799304618 ps |
| CPU time | 1062.23 seconds |
| Started | Aug 09 08:05:25 PM PDT 24 |
| Finished | Aug 09 08:23:08 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-1d9524a7-8f89-4108-b43c-8b20bf636180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489854531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.2489854531 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.85027684 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 529094819 ps |
| CPU time | 22.38 seconds |
| Started | Aug 09 08:05:27 PM PDT 24 |
| Finished | Aug 09 08:05:50 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-62754c59-72d2-4cf0-855a-a60c839f22e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85027684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr.85027684 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.995252675 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 162874983 ps |
| CPU time | 8.2 seconds |
| Started | Aug 09 08:05:25 PM PDT 24 |
| Finished | Aug 09 08:05:34 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-b4045639-1fd0-4894-95aa-11563b9f42fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995252675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.995252675 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.1067155515 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 63361430 ps |
| CPU time | 9.06 seconds |
| Started | Aug 09 08:05:25 PM PDT 24 |
| Finished | Aug 09 08:05:34 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-391ddf66-2367-45ef-a446-bd833d199f7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067155515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.1067155515 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.3341408351 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 69456328539 ps |
| CPU time | 748.59 seconds |
| Started | Aug 09 08:05:32 PM PDT 24 |
| Finished | Aug 09 08:18:01 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-c1dd76ff-1ace-4faa-9cd7-8f6626fff997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341408351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.3341408351 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.4254389051 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 15541248100 ps |
| CPU time | 246.96 seconds |
| Started | Aug 09 08:05:28 PM PDT 24 |
| Finished | Aug 09 08:09:35 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-dc097603-5f19-49b3-b11d-0416daf14938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254389051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.4254389051 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.2599312364 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 471194412 ps |
| CPU time | 37.74 seconds |
| Started | Aug 09 08:05:32 PM PDT 24 |
| Finished | Aug 09 08:06:10 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-48455065-4052-4cce-b565-b9d07c44a9be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599312364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.2599312364 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.3541045451 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 1721500095 ps |
| CPU time | 49.53 seconds |
| Started | Aug 09 08:05:28 PM PDT 24 |
| Finished | Aug 09 08:06:17 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-a56f2d39-708e-4c29-83a3-01d83e5fe3e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541045451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.3541045451 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.3189468722 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 194595763 ps |
| CPU time | 8.06 seconds |
| Started | Aug 09 08:05:28 PM PDT 24 |
| Finished | Aug 09 08:05:36 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-594a713d-4fa1-4343-a8a5-3710fccac162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189468722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.3189468722 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.3617770264 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 7813192145 ps |
| CPU time | 77.76 seconds |
| Started | Aug 09 08:05:23 PM PDT 24 |
| Finished | Aug 09 08:06:41 PM PDT 24 |
| Peak memory | 574904 kb |
| Host | smart-7b7f01ef-e8ab-473c-90cc-29e87ce7c6ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617770264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.3617770264 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.917009228 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 6185324821 ps |
| CPU time | 105.78 seconds |
| Started | Aug 09 08:05:27 PM PDT 24 |
| Finished | Aug 09 08:07:12 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-bd767fea-5652-4592-a2d6-f2b07e5da9f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917009228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.917009228 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1361360969 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 41699521 ps |
| CPU time | 5.92 seconds |
| Started | Aug 09 08:05:20 PM PDT 24 |
| Finished | Aug 09 08:05:26 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-516e8043-2d5b-428e-b4c2-df78fb2f5a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361360969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1361360969 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.3441354639 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 2737089358 ps |
| CPU time | 210.59 seconds |
| Started | Aug 09 08:05:25 PM PDT 24 |
| Finished | Aug 09 08:08:55 PM PDT 24 |
| Peak memory | 576432 kb |
| Host | smart-6b2d372f-8116-4622-9dd0-db242fcf5f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441354639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.3441354639 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.4183706034 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 7002751654 ps |
| CPU time | 224.82 seconds |
| Started | Aug 09 08:05:24 PM PDT 24 |
| Finished | Aug 09 08:09:09 PM PDT 24 |
| Peak memory | 576432 kb |
| Host | smart-4b13e901-91f3-4393-9b4a-b1d526ef7f2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183706034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.4183706034 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.4057903294 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 473395002 ps |
| CPU time | 199.94 seconds |
| Started | Aug 09 08:05:32 PM PDT 24 |
| Finished | Aug 09 08:08:52 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-697d853f-4d17-4174-a0ef-f28e75c8f822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057903294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.4057903294 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.798336390 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 3319515227 ps |
| CPU time | 485.33 seconds |
| Started | Aug 09 08:05:36 PM PDT 24 |
| Finished | Aug 09 08:13:41 PM PDT 24 |
| Peak memory | 578780 kb |
| Host | smart-b549ae8b-83f4-4bab-bdd1-a1b627a048a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798336390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_reset_error.798336390 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.4100375387 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 213922298 ps |
| CPU time | 12.31 seconds |
| Started | Aug 09 08:05:27 PM PDT 24 |
| Finished | Aug 09 08:05:39 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-acb7ae16-4922-4fc0-a830-9ed89e067aed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100375387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.4100375387 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.2713547449 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 2435601972 ps |
| CPU time | 100.28 seconds |
| Started | Aug 09 08:05:33 PM PDT 24 |
| Finished | Aug 09 08:07:14 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-58fea495-b545-47e2-b86f-635496c1436e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713547449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .2713547449 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.4251392082 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 45121709579 ps |
| CPU time | 718.03 seconds |
| Started | Aug 09 08:05:36 PM PDT 24 |
| Finished | Aug 09 08:17:34 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-c760463b-8188-461e-bf27-ba394136d88b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251392082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.4251392082 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.1748152984 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 531251306 ps |
| CPU time | 20.93 seconds |
| Started | Aug 09 08:05:32 PM PDT 24 |
| Finished | Aug 09 08:05:53 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-e4ca3ed0-8a09-457f-b2a4-c2d2c66e5a2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748152984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.1748152984 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.391150162 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 350193501 ps |
| CPU time | 27.38 seconds |
| Started | Aug 09 08:05:33 PM PDT 24 |
| Finished | Aug 09 08:06:01 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-379b558d-42f3-4ff1-94ba-c48bfaf6e882 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391150162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.391150162 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.1734226419 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 241525841 ps |
| CPU time | 23.1 seconds |
| Started | Aug 09 08:05:34 PM PDT 24 |
| Finished | Aug 09 08:05:57 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-fd7ad37b-da0b-411e-85bc-03a426f3e5c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734226419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.1734226419 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.3571858684 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 113156186201 ps |
| CPU time | 1274.13 seconds |
| Started | Aug 09 08:05:32 PM PDT 24 |
| Finished | Aug 09 08:26:46 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-474d8cf3-2292-4d6a-9bd4-9a0eba323692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571858684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.3571858684 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.1394038324 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 7544885728 ps |
| CPU time | 131.66 seconds |
| Started | Aug 09 08:05:32 PM PDT 24 |
| Finished | Aug 09 08:07:44 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-0ea19869-0b44-4108-953a-f11447593d2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394038324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.1394038324 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1101522329 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 265681422 ps |
| CPU time | 26.04 seconds |
| Started | Aug 09 08:05:32 PM PDT 24 |
| Finished | Aug 09 08:05:59 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-c88132d5-4f76-4c91-a0b5-8531e2cc86ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101522329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.1101522329 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.3941461247 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 2645152339 ps |
| CPU time | 82.61 seconds |
| Started | Aug 09 08:05:32 PM PDT 24 |
| Finished | Aug 09 08:06:55 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-aeef7d4f-6180-4be8-8980-52d89165d1d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941461247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.3941461247 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.2988691397 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 41433951 ps |
| CPU time | 5.81 seconds |
| Started | Aug 09 08:05:38 PM PDT 24 |
| Finished | Aug 09 08:05:44 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-b73705f1-768e-4bbc-baf2-4ff35fcaba88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988691397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.2988691397 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2288566937 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 9160326574 ps |
| CPU time | 98.43 seconds |
| Started | Aug 09 08:05:33 PM PDT 24 |
| Finished | Aug 09 08:07:11 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-a5684779-28da-4ffe-b152-c0c57169df6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288566937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.2288566937 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.79599179 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 5235265212 ps |
| CPU time | 94.62 seconds |
| Started | Aug 09 08:05:32 PM PDT 24 |
| Finished | Aug 09 08:07:07 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-425dd626-7317-4b4f-b841-9525f99dc3d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79599179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.79599179 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.436992258 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 53440418 ps |
| CPU time | 6.91 seconds |
| Started | Aug 09 08:05:38 PM PDT 24 |
| Finished | Aug 09 08:05:45 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-1161a634-4f79-41ac-9047-9e90ae171864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436992258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays .436992258 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.3026937123 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1539318573 ps |
| CPU time | 62.73 seconds |
| Started | Aug 09 08:05:33 PM PDT 24 |
| Finished | Aug 09 08:06:36 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-bf018a82-5558-4b3e-8116-e41f3a5f16ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026937123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3026937123 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.1948812289 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 662869247 ps |
| CPU time | 56.78 seconds |
| Started | Aug 09 08:05:33 PM PDT 24 |
| Finished | Aug 09 08:06:30 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-843b7299-e546-4ef7-b1e7-963d2d9b4b0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948812289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.1948812289 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.614950754 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 161420242 ps |
| CPU time | 59.87 seconds |
| Started | Aug 09 08:05:35 PM PDT 24 |
| Finished | Aug 09 08:06:35 PM PDT 24 |
| Peak memory | 577080 kb |
| Host | smart-dfadb519-b900-4841-8b10-e80c1bd0aa39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614950754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_ with_rand_reset.614950754 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3836938335 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 1171670831 ps |
| CPU time | 49.59 seconds |
| Started | Aug 09 08:05:35 PM PDT 24 |
| Finished | Aug 09 08:06:24 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-2c1821fa-0823-4a68-955e-5755b7e255c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836938335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3836938335 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.1848718172 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 376076602 ps |
| CPU time | 19.57 seconds |
| Started | Aug 09 08:05:38 PM PDT 24 |
| Finished | Aug 09 08:05:58 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-c62583b2-2166-40c9-9da4-ea0d76bf9910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848718172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .1848718172 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.993377040 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 67520866228 ps |
| CPU time | 1126.15 seconds |
| Started | Aug 09 08:05:45 PM PDT 24 |
| Finished | Aug 09 08:24:32 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-df4cb395-7ddb-4d0a-8259-0a2619ef4be3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993377040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_d evice_slow_rsp.993377040 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1426067331 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 1316591630 ps |
| CPU time | 50.92 seconds |
| Started | Aug 09 08:05:51 PM PDT 24 |
| Finished | Aug 09 08:06:42 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-137d1e05-b4cb-46b8-aa04-767ef18e5749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426067331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.1426067331 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.3119473950 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 1247598530 ps |
| CPU time | 39.07 seconds |
| Started | Aug 09 08:05:46 PM PDT 24 |
| Finished | Aug 09 08:06:25 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-0c70eeb8-1c67-4aa6-967a-2de22ec9f22e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119473950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.3119473950 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.2278787148 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 416754623 ps |
| CPU time | 37.89 seconds |
| Started | Aug 09 08:05:40 PM PDT 24 |
| Finished | Aug 09 08:06:18 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-fb02600f-2f11-411e-b5c3-21308ad2c109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278787148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2278787148 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1821645300 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 86244626466 ps |
| CPU time | 884.53 seconds |
| Started | Aug 09 08:05:45 PM PDT 24 |
| Finished | Aug 09 08:20:30 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-885d276b-ffb7-4ea3-a09b-815dd8959f55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821645300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1821645300 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.2525375806 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 49321213164 ps |
| CPU time | 928.57 seconds |
| Started | Aug 09 08:05:40 PM PDT 24 |
| Finished | Aug 09 08:21:09 PM PDT 24 |
| Peak memory | 576416 kb |
| Host | smart-abddf6af-4020-4c8a-af62-8587e25fcdad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525375806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.2525375806 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.2983979692 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 398147306 ps |
| CPU time | 37.31 seconds |
| Started | Aug 09 08:05:40 PM PDT 24 |
| Finished | Aug 09 08:06:17 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-2e11fa8b-e585-43e4-b8d2-779a835bfaf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983979692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.2983979692 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.824699537 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 1391790198 ps |
| CPU time | 40.59 seconds |
| Started | Aug 09 08:05:45 PM PDT 24 |
| Finished | Aug 09 08:06:26 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-403c87ba-643c-4cf7-9cab-e5062440a9c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824699537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.824699537 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.969069190 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 246943875 ps |
| CPU time | 10.3 seconds |
| Started | Aug 09 08:05:39 PM PDT 24 |
| Finished | Aug 09 08:05:50 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-41a40497-a36c-4615-986c-56149cbea9cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969069190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.969069190 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3016016257 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 10759106999 ps |
| CPU time | 117.5 seconds |
| Started | Aug 09 08:05:42 PM PDT 24 |
| Finished | Aug 09 08:07:39 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-3d499ca9-01a7-4d98-a05a-7ffa358495d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016016257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3016016257 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1311490058 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 5703812433 ps |
| CPU time | 92.82 seconds |
| Started | Aug 09 08:05:39 PM PDT 24 |
| Finished | Aug 09 08:07:12 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-abb0f06a-1250-40c9-bfad-548446d63bf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311490058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.1311490058 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3165277757 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 41212640 ps |
| CPU time | 5.87 seconds |
| Started | Aug 09 08:05:42 PM PDT 24 |
| Finished | Aug 09 08:05:48 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-59b9a13a-7275-4d5e-b5e6-87bf4327bfb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165277757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.3165277757 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.81497450 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2342993674 ps |
| CPU time | 201.67 seconds |
| Started | Aug 09 08:05:52 PM PDT 24 |
| Finished | Aug 09 08:09:14 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-8bd7759c-a2fe-43fc-8346-b40903993a24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81497450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.81497450 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.1258035739 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 1609879595 ps |
| CPU time | 114.75 seconds |
| Started | Aug 09 08:05:46 PM PDT 24 |
| Finished | Aug 09 08:07:41 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-8a841edb-8a21-4371-aa64-e8f239f9e9f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258035739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.1258035739 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2647550743 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2893931529 ps |
| CPU time | 394.6 seconds |
| Started | Aug 09 08:05:46 PM PDT 24 |
| Finished | Aug 09 08:12:21 PM PDT 24 |
| Peak memory | 577100 kb |
| Host | smart-69359fd5-78e0-4ae6-9cc2-41b819ace048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647550743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.2647550743 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2039608450 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 497141304 ps |
| CPU time | 201.53 seconds |
| Started | Aug 09 08:05:46 PM PDT 24 |
| Finished | Aug 09 08:09:08 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-866be40a-065d-40fa-b0f2-10f512fbd5c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039608450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.2039608450 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.767675349 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 711114800 ps |
| CPU time | 30.68 seconds |
| Started | Aug 09 08:05:44 PM PDT 24 |
| Finished | Aug 09 08:06:14 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-329b0cb3-802e-4413-abc7-5b8cdf01d0a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767675349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.767675349 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.3789698031 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 1910519180 ps |
| CPU time | 70.05 seconds |
| Started | Aug 09 08:05:51 PM PDT 24 |
| Finished | Aug 09 08:07:02 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-24494da5-31e4-498e-b373-26a682227060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789698031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .3789698031 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.251797210 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 2853421550 ps |
| CPU time | 49.91 seconds |
| Started | Aug 09 08:05:53 PM PDT 24 |
| Finished | Aug 09 08:06:43 PM PDT 24 |
| Peak memory | 574868 kb |
| Host | smart-78baa3f8-618d-41f3-ba91-952c97f8ecf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251797210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_d evice_slow_rsp.251797210 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.2641835029 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 417316590 ps |
| CPU time | 16.01 seconds |
| Started | Aug 09 08:05:54 PM PDT 24 |
| Finished | Aug 09 08:06:10 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-8625811d-9627-48f6-bb72-53a2b49b67db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641835029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.2641835029 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.3757915347 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 547548045 ps |
| CPU time | 20 seconds |
| Started | Aug 09 08:05:52 PM PDT 24 |
| Finished | Aug 09 08:06:12 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-cb8e54c6-37fa-4a15-a442-567a9940c884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757915347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.3757915347 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.994829188 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 515940759 ps |
| CPU time | 36.35 seconds |
| Started | Aug 09 08:05:44 PM PDT 24 |
| Finished | Aug 09 08:06:21 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-801e285e-e619-4c47-be5b-83b0e79285be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994829188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.994829188 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.2397643696 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 45012145578 ps |
| CPU time | 448.39 seconds |
| Started | Aug 09 08:05:45 PM PDT 24 |
| Finished | Aug 09 08:13:14 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-136bb900-b8f0-4315-b085-934bb1c366a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397643696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.2397643696 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.1466320908 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 17561437312 ps |
| CPU time | 293.7 seconds |
| Started | Aug 09 08:05:45 PM PDT 24 |
| Finished | Aug 09 08:10:39 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-ed6430c2-3cde-481c-947d-87b56051e550 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466320908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.1466320908 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.2372141570 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 462556342 ps |
| CPU time | 40.74 seconds |
| Started | Aug 09 08:05:47 PM PDT 24 |
| Finished | Aug 09 08:06:28 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-d80443c2-292d-4e35-b2df-8504858ecf40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372141570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.2372141570 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.1929470876 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 778275945 ps |
| CPU time | 23.31 seconds |
| Started | Aug 09 08:05:53 PM PDT 24 |
| Finished | Aug 09 08:06:16 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-1f4d05b9-2106-4c44-b9f3-daa22e77cc69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929470876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.1929470876 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.1600552335 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 270530916 ps |
| CPU time | 10 seconds |
| Started | Aug 09 08:05:45 PM PDT 24 |
| Finished | Aug 09 08:05:55 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-4abcf2a6-6a20-4253-a404-38923f36ac89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600552335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.1600552335 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.1736955446 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 9895820198 ps |
| CPU time | 100.83 seconds |
| Started | Aug 09 08:05:45 PM PDT 24 |
| Finished | Aug 09 08:07:26 PM PDT 24 |
| Peak memory | 574916 kb |
| Host | smart-b992ea8f-7b4a-4dfc-b69e-8b7767357156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736955446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.1736955446 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.4254020129 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 3401835203 ps |
| CPU time | 57.91 seconds |
| Started | Aug 09 08:05:47 PM PDT 24 |
| Finished | Aug 09 08:06:45 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-d88267c4-1b25-465c-ad16-2172399004fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254020129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.4254020129 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2884206264 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 37229576 ps |
| CPU time | 6.03 seconds |
| Started | Aug 09 08:05:47 PM PDT 24 |
| Finished | Aug 09 08:05:53 PM PDT 24 |
| Peak memory | 574820 kb |
| Host | smart-202e33be-aba1-4316-97e8-6b0ed7333b80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884206264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.2884206264 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.3612725555 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 3660684767 ps |
| CPU time | 288.88 seconds |
| Started | Aug 09 08:05:58 PM PDT 24 |
| Finished | Aug 09 08:10:47 PM PDT 24 |
| Peak memory | 577144 kb |
| Host | smart-2a2deeb2-9a01-44da-b64b-5e73ec85cee5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612725555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.3612725555 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2458654728 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 10285347482 ps |
| CPU time | 363.04 seconds |
| Started | Aug 09 08:05:52 PM PDT 24 |
| Finished | Aug 09 08:11:55 PM PDT 24 |
| Peak memory | 577132 kb |
| Host | smart-6a9d05d0-8a31-42bc-921b-a1bbdd90c55c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458654728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2458654728 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3855044453 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 108465575 ps |
| CPU time | 34.45 seconds |
| Started | Aug 09 08:05:54 PM PDT 24 |
| Finished | Aug 09 08:06:28 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-de417454-a5d7-41b0-91cd-f209633302d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855044453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.3855044453 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3139896077 |
| Short name | T2934 |
| Test name | |
| Test status | |
| Simulation time | 6573872952 ps |
| CPU time | 387.79 seconds |
| Started | Aug 09 08:05:54 PM PDT 24 |
| Finished | Aug 09 08:12:22 PM PDT 24 |
| Peak memory | 577148 kb |
| Host | smart-0410ac9f-c0ab-4d00-9c3d-e3ef16dbd3b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139896077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.3139896077 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.1959501573 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1073566450 ps |
| CPU time | 43.85 seconds |
| Started | Aug 09 08:05:58 PM PDT 24 |
| Finished | Aug 09 08:06:42 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-9944dcd1-b6f7-4b9a-9bc1-088e72960be4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959501573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.1959501573 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.3404263476 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 585565783 ps |
| CPU time | 27.33 seconds |
| Started | Aug 09 08:06:10 PM PDT 24 |
| Finished | Aug 09 08:06:38 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-9f0ae6d5-ea4b-4be9-8631-e3e21a5411b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404263476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .3404263476 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.941104718 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 91595345629 ps |
| CPU time | 1486.79 seconds |
| Started | Aug 09 08:06:00 PM PDT 24 |
| Finished | Aug 09 08:30:47 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-7db51337-1c40-4d85-9eaf-dadaab1f5aa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941104718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_d evice_slow_rsp.941104718 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.1691375776 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 1164265827 ps |
| CPU time | 41.09 seconds |
| Started | Aug 09 08:06:00 PM PDT 24 |
| Finished | Aug 09 08:06:41 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-6459c643-8caa-4a3c-9e52-dd2adf176087 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691375776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.1691375776 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.3147114351 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 597839925 ps |
| CPU time | 45.89 seconds |
| Started | Aug 09 08:06:01 PM PDT 24 |
| Finished | Aug 09 08:06:47 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-9804b80c-aaf0-4b8b-a210-5c74889a9c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147114351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.3147114351 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.3817445165 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 440862590 ps |
| CPU time | 36.57 seconds |
| Started | Aug 09 08:05:54 PM PDT 24 |
| Finished | Aug 09 08:06:31 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-43c3b8b8-6f4d-4124-bab6-97d9968adfba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817445165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.3817445165 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.3413359318 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 21539541234 ps |
| CPU time | 213.6 seconds |
| Started | Aug 09 08:05:52 PM PDT 24 |
| Finished | Aug 09 08:09:26 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-c50d6c31-d229-4568-b513-89000321f563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413359318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.3413359318 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.928089655 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 61483571282 ps |
| CPU time | 1013.81 seconds |
| Started | Aug 09 08:05:53 PM PDT 24 |
| Finished | Aug 09 08:22:47 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-8d2ec15e-f63b-4d4d-9a3d-17321090436e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928089655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.928089655 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.603279341 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 414630080 ps |
| CPU time | 34.2 seconds |
| Started | Aug 09 08:05:54 PM PDT 24 |
| Finished | Aug 09 08:06:28 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-eef45e39-3b07-40a9-b35a-81c0ac458c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603279341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_dela ys.603279341 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.2618160511 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 371190123 ps |
| CPU time | 27.22 seconds |
| Started | Aug 09 08:06:00 PM PDT 24 |
| Finished | Aug 09 08:06:27 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-e6ccb350-918b-4fee-b84a-05f178b23dd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618160511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.2618160511 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.197409273 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 47043438 ps |
| CPU time | 5.84 seconds |
| Started | Aug 09 08:05:53 PM PDT 24 |
| Finished | Aug 09 08:05:58 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-5c5df865-a395-497c-be75-80080e0e08d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197409273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.197409273 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2003061366 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 7787400149 ps |
| CPU time | 79.71 seconds |
| Started | Aug 09 08:05:53 PM PDT 24 |
| Finished | Aug 09 08:07:12 PM PDT 24 |
| Peak memory | 574860 kb |
| Host | smart-feb292c3-7d46-4766-b753-c8ee566f3fcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003061366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.2003061366 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.687422641 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 4989693450 ps |
| CPU time | 86.27 seconds |
| Started | Aug 09 08:05:54 PM PDT 24 |
| Finished | Aug 09 08:07:20 PM PDT 24 |
| Peak memory | 574888 kb |
| Host | smart-cd6c7b8d-89e7-4a88-b837-e18bb1c50881 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687422641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.687422641 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.528733899 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 55533010 ps |
| CPU time | 6.52 seconds |
| Started | Aug 09 08:05:54 PM PDT 24 |
| Finished | Aug 09 08:06:01 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-42651568-9259-4f0f-bbbe-b0a45afe5f0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528733899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays .528733899 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.3332744777 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 2276907909 ps |
| CPU time | 170.65 seconds |
| Started | Aug 09 08:06:00 PM PDT 24 |
| Finished | Aug 09 08:08:51 PM PDT 24 |
| Peak memory | 577064 kb |
| Host | smart-4170b5c9-3d87-4d78-be2c-d69460df9f86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332744777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.3332744777 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.431993274 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 347319992 ps |
| CPU time | 124.65 seconds |
| Started | Aug 09 08:06:13 PM PDT 24 |
| Finished | Aug 09 08:08:18 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-17e1df14-454a-4102-9c46-94b21218939c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431993274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_ with_rand_reset.431993274 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2407687466 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 793999101 ps |
| CPU time | 240.48 seconds |
| Started | Aug 09 08:06:00 PM PDT 24 |
| Finished | Aug 09 08:10:00 PM PDT 24 |
| Peak memory | 577028 kb |
| Host | smart-ad86c17a-a5c6-4305-8d6f-6bdeaeb0df25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407687466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.2407687466 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.1589433635 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 272744967 ps |
| CPU time | 30.21 seconds |
| Started | Aug 09 08:06:12 PM PDT 24 |
| Finished | Aug 09 08:06:43 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-d9047357-321d-4192-84d4-aeb0736a41df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589433635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.1589433635 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.990107754 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 1281202661 ps |
| CPU time | 50.05 seconds |
| Started | Aug 09 08:06:08 PM PDT 24 |
| Finished | Aug 09 08:06:58 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-f2d2919c-4712-45cd-a708-78b415462137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990107754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device. 990107754 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.456085281 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 86334499833 ps |
| CPU time | 1599.18 seconds |
| Started | Aug 09 08:06:20 PM PDT 24 |
| Finished | Aug 09 08:32:59 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-0e92b386-455a-4d6b-8cd7-39e46282e231 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456085281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_d evice_slow_rsp.456085281 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3026894887 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 803188464 ps |
| CPU time | 36.44 seconds |
| Started | Aug 09 08:06:14 PM PDT 24 |
| Finished | Aug 09 08:06:50 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-743ce6ad-b031-4d32-b5e9-10bf00659507 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026894887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.3026894887 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.1283849037 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 40990630 ps |
| CPU time | 6.47 seconds |
| Started | Aug 09 08:06:14 PM PDT 24 |
| Finished | Aug 09 08:06:21 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-2da13179-f79a-4faa-b0c2-e4ff324c5837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283849037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.1283849037 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.1560278819 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 72998272 ps |
| CPU time | 9.88 seconds |
| Started | Aug 09 08:06:06 PM PDT 24 |
| Finished | Aug 09 08:06:16 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-a04a205f-70d9-4458-a60b-52e5db5c23f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560278819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.1560278819 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.483622628 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 35314048109 ps |
| CPU time | 355.48 seconds |
| Started | Aug 09 08:06:06 PM PDT 24 |
| Finished | Aug 09 08:12:02 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-f66b065e-3d91-4ad4-9579-102b5696fdc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483622628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.483622628 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.38891475 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 10596076310 ps |
| CPU time | 172.52 seconds |
| Started | Aug 09 08:06:18 PM PDT 24 |
| Finished | Aug 09 08:09:11 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-f8658ce4-dac3-4910-a6d7-22fa43a3d811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38891475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.38891475 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.567807086 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 116306920 ps |
| CPU time | 12.33 seconds |
| Started | Aug 09 08:06:18 PM PDT 24 |
| Finished | Aug 09 08:06:31 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-51243fda-6576-4cc5-8e47-a56ae915ad8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567807086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_dela ys.567807086 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.3998032333 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 96720517 ps |
| CPU time | 9.06 seconds |
| Started | Aug 09 08:06:14 PM PDT 24 |
| Finished | Aug 09 08:06:23 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-ef69b1f6-bb2b-49d2-8bb3-ebcb9d5287f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998032333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3998032333 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.901987016 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 205343502 ps |
| CPU time | 8.53 seconds |
| Started | Aug 09 08:06:06 PM PDT 24 |
| Finished | Aug 09 08:06:14 PM PDT 24 |
| Peak memory | 574796 kb |
| Host | smart-d33c2a85-75dd-48f5-9e18-e1ff07bfc689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901987016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.901987016 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.1426999145 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 7554371656 ps |
| CPU time | 81.72 seconds |
| Started | Aug 09 08:06:07 PM PDT 24 |
| Finished | Aug 09 08:07:29 PM PDT 24 |
| Peak memory | 574928 kb |
| Host | smart-f207990b-f2ca-4e27-b15d-5aa2b35b9db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426999145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.1426999145 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3426048004 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 6198449427 ps |
| CPU time | 107.62 seconds |
| Started | Aug 09 08:06:18 PM PDT 24 |
| Finished | Aug 09 08:08:05 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-5ac83914-5a19-4578-b10d-d09f95985f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426048004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.3426048004 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2689048449 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 46940863 ps |
| CPU time | 6.28 seconds |
| Started | Aug 09 08:06:06 PM PDT 24 |
| Finished | Aug 09 08:06:12 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-95ee7c55-22aa-410b-b432-31f43bf8b0b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689048449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.2689048449 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.3908874797 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 1450419132 ps |
| CPU time | 154.54 seconds |
| Started | Aug 09 08:06:13 PM PDT 24 |
| Finished | Aug 09 08:08:48 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-c68a2df3-551f-4c4c-9d41-0a48a4e99347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908874797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.3908874797 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3057571835 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1531708907 ps |
| CPU time | 253.46 seconds |
| Started | Aug 09 08:06:14 PM PDT 24 |
| Finished | Aug 09 08:10:28 PM PDT 24 |
| Peak memory | 577000 kb |
| Host | smart-85499cf5-2570-4fe5-9827-7118c9d5a0eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057571835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.3057571835 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.4175376115 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 9785447320 ps |
| CPU time | 540.56 seconds |
| Started | Aug 09 08:06:14 PM PDT 24 |
| Finished | Aug 09 08:15:14 PM PDT 24 |
| Peak memory | 577128 kb |
| Host | smart-eba95927-8c88-40bb-aa6a-99d0975a2a38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175376115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.4175376115 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.475445342 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 224293568 ps |
| CPU time | 25.86 seconds |
| Started | Aug 09 08:06:14 PM PDT 24 |
| Finished | Aug 09 08:06:40 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-b7ccaa92-0549-4618-a605-13d74bca86a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475445342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.475445342 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2045458217 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 6035695592 ps |
| CPU time | 465.7 seconds |
| Started | Aug 09 07:57:59 PM PDT 24 |
| Finished | Aug 09 08:05:45 PM PDT 24 |
| Peak memory | 640960 kb |
| Host | smart-a3d8cf10-0119-4464-bae3-ce01d1cae919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045458217 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.2045458217 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.4062614088 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 4674747173 ps |
| CPU time | 379.32 seconds |
| Started | Aug 09 07:58:02 PM PDT 24 |
| Finished | Aug 09 08:04:21 PM PDT 24 |
| Peak memory | 598720 kb |
| Host | smart-c8c2caa9-9ac4-468a-a4fb-3ac641b0f1c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062614088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.4062614088 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.250604988 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 15446340060 ps |
| CPU time | 1794.98 seconds |
| Started | Aug 09 07:57:59 PM PDT 24 |
| Finished | Aug 09 08:27:54 PM PDT 24 |
| Peak memory | 593592 kb |
| Host | smart-dbf05415-34b2-44ca-8b5e-91fbc1bcbcc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250604988 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.chip_same_csr_outstanding.250604988 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.4250028394 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1021360511 ps |
| CPU time | 73.83 seconds |
| Started | Aug 09 07:57:58 PM PDT 24 |
| Finished | Aug 09 07:59:12 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-0ada9684-fa00-4673-9ac8-28f724f37268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250028394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 4250028394 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2550811234 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 25618744846 ps |
| CPU time | 463.25 seconds |
| Started | Aug 09 07:58:02 PM PDT 24 |
| Finished | Aug 09 08:05:46 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-edf17b23-55b1-431a-90be-3021765048d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550811234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.2550811234 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.1672885154 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 209786429 ps |
| CPU time | 10.47 seconds |
| Started | Aug 09 07:58:00 PM PDT 24 |
| Finished | Aug 09 07:58:11 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-513f43a7-6941-44de-b3ad-21536d932bf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672885154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .1672885154 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.2913085737 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 607525596 ps |
| CPU time | 25.01 seconds |
| Started | Aug 09 07:58:01 PM PDT 24 |
| Finished | Aug 09 07:58:26 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-588fe042-6cb4-48b0-9ba9-ef4bb7a7e69a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913085737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2913085737 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.2320298347 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 522489438 ps |
| CPU time | 47.65 seconds |
| Started | Aug 09 07:58:02 PM PDT 24 |
| Finished | Aug 09 07:58:50 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-9dafad2f-6846-4c2b-a985-c37640657336 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320298347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2320298347 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.3272794000 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 60355317255 ps |
| CPU time | 621.01 seconds |
| Started | Aug 09 07:57:59 PM PDT 24 |
| Finished | Aug 09 08:08:20 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-178d32f5-e664-4b8c-9aa4-e7c9d9feaaa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272794000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3272794000 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.609545029 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 10059419672 ps |
| CPU time | 175.45 seconds |
| Started | Aug 09 07:57:58 PM PDT 24 |
| Finished | Aug 09 08:00:54 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-69d9b440-e0c0-4f86-a919-c12baf46e2d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609545029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.609545029 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.2195141910 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 501480605 ps |
| CPU time | 39.31 seconds |
| Started | Aug 09 07:58:03 PM PDT 24 |
| Finished | Aug 09 07:58:42 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-ef1975b2-235f-4721-a90e-e97f9e0e53d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195141910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.2195141910 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.822577661 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 431127828 ps |
| CPU time | 32.58 seconds |
| Started | Aug 09 07:58:04 PM PDT 24 |
| Finished | Aug 09 07:58:37 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-bd121c8f-2333-465d-b2e3-79af6b69ca10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822577661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.822577661 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.309522032 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 37195911 ps |
| CPU time | 5.78 seconds |
| Started | Aug 09 07:57:58 PM PDT 24 |
| Finished | Aug 09 07:58:04 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-147ecfe1-4420-4d5c-b5f2-51d797e5ef6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309522032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.309522032 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.1513414813 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 7203957329 ps |
| CPU time | 77.94 seconds |
| Started | Aug 09 07:58:11 PM PDT 24 |
| Finished | Aug 09 07:59:29 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-9804f5b6-2597-415a-9699-e2e42d68736b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513414813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1513414813 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1218343358 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 5667622679 ps |
| CPU time | 91.09 seconds |
| Started | Aug 09 07:57:58 PM PDT 24 |
| Finished | Aug 09 07:59:30 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-21ecc3f4-6904-4daf-9b1b-963706b42d14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218343358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1218343358 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2861830986 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 55032979 ps |
| CPU time | 6.19 seconds |
| Started | Aug 09 07:57:58 PM PDT 24 |
| Finished | Aug 09 07:58:04 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-36ded7ab-af4b-4f97-a72c-500c3e5b4afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861830986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .2861830986 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.3129488780 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 7008895576 ps |
| CPU time | 260.14 seconds |
| Started | Aug 09 07:58:03 PM PDT 24 |
| Finished | Aug 09 08:02:24 PM PDT 24 |
| Peak memory | 577112 kb |
| Host | smart-382dfbff-1096-4690-856b-75bb3da5cb65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129488780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3129488780 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.2992456443 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 2927031285 ps |
| CPU time | 96.89 seconds |
| Started | Aug 09 07:57:59 PM PDT 24 |
| Finished | Aug 09 07:59:36 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-853ce708-221b-4979-950d-baa849f92f5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992456443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2992456443 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1763318302 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 388684959 ps |
| CPU time | 51.25 seconds |
| Started | Aug 09 07:58:00 PM PDT 24 |
| Finished | Aug 09 07:58:51 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-69b25ecc-00c5-4fe5-9b9e-08158968810b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763318302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.1763318302 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.219610811 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 308366151 ps |
| CPU time | 32.41 seconds |
| Started | Aug 09 07:58:03 PM PDT 24 |
| Finished | Aug 09 07:58:35 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-1436b2ce-964b-40e4-b96d-92d02abf2d39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219610811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.219610811 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.2747148827 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 2648805855 ps |
| CPU time | 88.88 seconds |
| Started | Aug 09 08:06:22 PM PDT 24 |
| Finished | Aug 09 08:07:51 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-d5944936-4dbd-497c-86aa-ee6f0ae56647 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747148827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .2747148827 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1957796831 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 57306961477 ps |
| CPU time | 1130.49 seconds |
| Started | Aug 09 08:06:24 PM PDT 24 |
| Finished | Aug 09 08:25:15 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-93c81eb9-8fd7-4c7e-8be4-70318d181e3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957796831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.1957796831 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.371689807 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 611517048 ps |
| CPU time | 24.21 seconds |
| Started | Aug 09 08:06:20 PM PDT 24 |
| Finished | Aug 09 08:06:44 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-5f71a760-df21-43ad-aa69-552b568680be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371689807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr .371689807 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.2418416360 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 200217198 ps |
| CPU time | 10.05 seconds |
| Started | Aug 09 08:06:20 PM PDT 24 |
| Finished | Aug 09 08:06:30 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-3b9104aa-b9b0-46d0-8dd2-0ddf6506545a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418416360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.2418416360 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.738986856 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 2623166999 ps |
| CPU time | 98 seconds |
| Started | Aug 09 08:06:14 PM PDT 24 |
| Finished | Aug 09 08:07:52 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-dd2b0382-4471-49e6-b7f8-07dfe9b46cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738986856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.738986856 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.37574807 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 34657266035 ps |
| CPU time | 326.92 seconds |
| Started | Aug 09 08:06:21 PM PDT 24 |
| Finished | Aug 09 08:11:48 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-3614c144-7679-4bce-8ba9-6341534fb082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37574807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.37574807 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.2286317317 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 45879405156 ps |
| CPU time | 822.12 seconds |
| Started | Aug 09 08:06:21 PM PDT 24 |
| Finished | Aug 09 08:20:04 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-7b09261a-5ab4-4f71-bb1e-0f6f14f5d4fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286317317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.2286317317 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.4162761383 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 538358662 ps |
| CPU time | 47.05 seconds |
| Started | Aug 09 08:06:21 PM PDT 24 |
| Finished | Aug 09 08:07:08 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-d255a836-1679-46df-9967-cbf3ded8083d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162761383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.4162761383 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.4193428895 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 2009039071 ps |
| CPU time | 60.08 seconds |
| Started | Aug 09 08:06:20 PM PDT 24 |
| Finished | Aug 09 08:07:20 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-edaaffbf-02e5-44b5-b266-a34b1613215f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193428895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.4193428895 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.1491587937 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 199183125 ps |
| CPU time | 9.79 seconds |
| Started | Aug 09 08:06:15 PM PDT 24 |
| Finished | Aug 09 08:06:25 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-976b4146-6832-4ec1-bd1e-7ede3248d7da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491587937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.1491587937 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1334740222 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 4123538061 ps |
| CPU time | 74.6 seconds |
| Started | Aug 09 08:06:14 PM PDT 24 |
| Finished | Aug 09 08:07:29 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-a920f40e-ebe0-460a-8b6f-429481fa95f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334740222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.1334740222 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2732955642 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 55084045 ps |
| CPU time | 6.62 seconds |
| Started | Aug 09 08:06:13 PM PDT 24 |
| Finished | Aug 09 08:06:20 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-b43ad420-3c95-468c-a748-809a2d0a0146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732955642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.2732955642 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.1589294347 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 8321114127 ps |
| CPU time | 304.35 seconds |
| Started | Aug 09 08:06:20 PM PDT 24 |
| Finished | Aug 09 08:11:25 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-1505d806-51dd-40aa-a0eb-afb914d65d10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589294347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.1589294347 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.1912579059 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 2097773119 ps |
| CPU time | 71.99 seconds |
| Started | Aug 09 08:06:29 PM PDT 24 |
| Finished | Aug 09 08:07:41 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-c6f73bdc-b96b-4ddb-b308-3b05c28e49da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912579059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.1912579059 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2747264176 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 2818900841 ps |
| CPU time | 218.07 seconds |
| Started | Aug 09 08:06:20 PM PDT 24 |
| Finished | Aug 09 08:09:58 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-e37cef77-7a23-43bb-bde5-2793c848a8b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747264176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.2747264176 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.507375054 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 289021973 ps |
| CPU time | 163.01 seconds |
| Started | Aug 09 08:06:27 PM PDT 24 |
| Finished | Aug 09 08:09:10 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-08f79d29-f88c-46c2-8494-3dd011729411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507375054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_reset_error.507375054 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.169980386 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 327623378 ps |
| CPU time | 16.48 seconds |
| Started | Aug 09 08:06:23 PM PDT 24 |
| Finished | Aug 09 08:06:39 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-2b2555ec-d55a-4fc2-8a2d-7b06fb778dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169980386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.169980386 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.944981876 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 1921780588 ps |
| CPU time | 67.98 seconds |
| Started | Aug 09 08:06:31 PM PDT 24 |
| Finished | Aug 09 08:07:39 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-50802d53-2daa-421e-a373-bb2625f6e5a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944981876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device. 944981876 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2542161270 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 74306812425 ps |
| CPU time | 1205.57 seconds |
| Started | Aug 09 08:06:37 PM PDT 24 |
| Finished | Aug 09 08:26:42 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-1357d347-5e31-40ba-a3db-bfa2cc0e4603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542161270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.2542161270 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2630931557 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 216945535 ps |
| CPU time | 24.26 seconds |
| Started | Aug 09 08:06:34 PM PDT 24 |
| Finished | Aug 09 08:06:58 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-10cf4e2a-3463-463a-8412-99f7c306c510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630931557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.2630931557 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.1914738379 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 568322441 ps |
| CPU time | 44.79 seconds |
| Started | Aug 09 08:06:31 PM PDT 24 |
| Finished | Aug 09 08:07:16 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-c21719be-758e-41ee-99a8-0575f4c5ad16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914738379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.1914738379 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.1702346512 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 929695177 ps |
| CPU time | 33.37 seconds |
| Started | Aug 09 08:06:31 PM PDT 24 |
| Finished | Aug 09 08:07:04 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-2b1394da-7893-4771-a20e-db8c07f3d1e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702346512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.1702346512 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.2318401638 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 61792705949 ps |
| CPU time | 621.83 seconds |
| Started | Aug 09 08:06:28 PM PDT 24 |
| Finished | Aug 09 08:16:50 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-2dc249a2-ddf1-4d0b-9db1-85fac0318a0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318401638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.2318401638 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.3780425934 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 42620102388 ps |
| CPU time | 727.81 seconds |
| Started | Aug 09 08:06:31 PM PDT 24 |
| Finished | Aug 09 08:18:39 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-2c700759-7f55-4725-9fed-d9c2d44a2d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780425934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.3780425934 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.568903973 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 499654103 ps |
| CPU time | 45.46 seconds |
| Started | Aug 09 08:06:31 PM PDT 24 |
| Finished | Aug 09 08:07:17 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-a1dcb534-4cd6-4676-b6a6-5979d14a857a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568903973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_dela ys.568903973 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.1576365313 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 1978335174 ps |
| CPU time | 63.21 seconds |
| Started | Aug 09 08:06:33 PM PDT 24 |
| Finished | Aug 09 08:07:36 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-7b879087-21cd-4d66-b48e-9caf7468cf4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576365313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.1576365313 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.1185843542 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 197523818 ps |
| CPU time | 9.14 seconds |
| Started | Aug 09 08:06:28 PM PDT 24 |
| Finished | Aug 09 08:06:37 PM PDT 24 |
| Peak memory | 574792 kb |
| Host | smart-5789a6d5-3db4-4424-bfa1-aff0894a0f59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185843542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.1185843542 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.1055907647 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 10266300442 ps |
| CPU time | 100 seconds |
| Started | Aug 09 08:06:30 PM PDT 24 |
| Finished | Aug 09 08:08:10 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-1906ad58-8903-4e8c-9c7c-046a90d2b6b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055907647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.1055907647 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3928687335 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 2997016602 ps |
| CPU time | 48.5 seconds |
| Started | Aug 09 08:06:31 PM PDT 24 |
| Finished | Aug 09 08:07:20 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-e3678f5d-fd62-4861-a967-d293fcba23f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928687335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.3928687335 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.4247711062 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 37583852 ps |
| CPU time | 5.79 seconds |
| Started | Aug 09 08:06:32 PM PDT 24 |
| Finished | Aug 09 08:06:37 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-7c4c8652-97d5-4151-9148-9bb195ab0772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247711062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.4247711062 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.127444187 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 9841258802 ps |
| CPU time | 414.74 seconds |
| Started | Aug 09 08:06:39 PM PDT 24 |
| Finished | Aug 09 08:13:34 PM PDT 24 |
| Peak memory | 577160 kb |
| Host | smart-3950ae10-bc4a-4508-bac9-827460114fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127444187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.127444187 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3023431778 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 14394121433 ps |
| CPU time | 450.98 seconds |
| Started | Aug 09 08:06:34 PM PDT 24 |
| Finished | Aug 09 08:14:05 PM PDT 24 |
| Peak memory | 577100 kb |
| Host | smart-501a362b-36cd-4835-bcde-340a95d851dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023431778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3023431778 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.4169502212 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 4340369597 ps |
| CPU time | 533.3 seconds |
| Started | Aug 09 08:06:42 PM PDT 24 |
| Finished | Aug 09 08:15:36 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-1197e183-553c-4cd3-9a7d-2e1492027b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169502212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.4169502212 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.237295762 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 6605526387 ps |
| CPU time | 427 seconds |
| Started | Aug 09 08:06:32 PM PDT 24 |
| Finished | Aug 09 08:13:40 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-881ef970-d7fb-428c-b569-fa02d6e440ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237295762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_reset_error.237295762 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.977859286 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 291387344 ps |
| CPU time | 33.94 seconds |
| Started | Aug 09 08:06:34 PM PDT 24 |
| Finished | Aug 09 08:07:08 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-cc2dce2c-e7fb-4a4c-aa47-e84cac311efa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977859286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.977859286 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.264686055 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 3469329831 ps |
| CPU time | 125.09 seconds |
| Started | Aug 09 08:06:46 PM PDT 24 |
| Finished | Aug 09 08:08:51 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-c4d258fc-f8f5-4f80-8a08-be2fb59ca9f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264686055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device. 264686055 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1668425749 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 79445440153 ps |
| CPU time | 1399.31 seconds |
| Started | Aug 09 08:06:40 PM PDT 24 |
| Finished | Aug 09 08:30:00 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-e2c73354-c18f-40ee-8e06-ac2a842ba241 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668425749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.1668425749 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.237547694 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 1144461647 ps |
| CPU time | 38.9 seconds |
| Started | Aug 09 08:06:43 PM PDT 24 |
| Finished | Aug 09 08:07:22 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-1e089f6a-7905-4dc6-8977-5da5c70dd81c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237547694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr .237547694 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.1165291932 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 1966433153 ps |
| CPU time | 61.28 seconds |
| Started | Aug 09 08:06:44 PM PDT 24 |
| Finished | Aug 09 08:07:45 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-319616d4-45c2-45bb-9dbe-83e5e74aa421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165291932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1165291932 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.3909420340 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 529688946 ps |
| CPU time | 44.9 seconds |
| Started | Aug 09 08:06:33 PM PDT 24 |
| Finished | Aug 09 08:07:18 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-34db577b-bde1-4f51-9002-4b131b321282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909420340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3909420340 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.2856055724 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 84011673770 ps |
| CPU time | 898.53 seconds |
| Started | Aug 09 08:06:35 PM PDT 24 |
| Finished | Aug 09 08:21:34 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-168593f8-a60d-4449-bde9-164439c2e6de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856055724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.2856055724 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.1691421624 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 26940908273 ps |
| CPU time | 450.25 seconds |
| Started | Aug 09 08:06:42 PM PDT 24 |
| Finished | Aug 09 08:14:13 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-bc3f2e5c-626a-4625-97a6-d66700dcb58b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691421624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.1691421624 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2907099555 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 273036669 ps |
| CPU time | 22.87 seconds |
| Started | Aug 09 08:06:34 PM PDT 24 |
| Finished | Aug 09 08:06:57 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-c700c64c-a94f-4c0b-8093-6d10e8e33111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907099555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.2907099555 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.3414531965 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 139375084 ps |
| CPU time | 12.33 seconds |
| Started | Aug 09 08:06:43 PM PDT 24 |
| Finished | Aug 09 08:06:56 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-4c460a92-c888-4f64-9baa-eca17e774902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414531965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.3414531965 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.3735331959 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 187242654 ps |
| CPU time | 8.55 seconds |
| Started | Aug 09 08:06:35 PM PDT 24 |
| Finished | Aug 09 08:06:43 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-cdabb8d3-47de-4cc6-a89b-9d7c482a7972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735331959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.3735331959 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.47015612 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 7573650059 ps |
| CPU time | 76.11 seconds |
| Started | Aug 09 08:06:42 PM PDT 24 |
| Finished | Aug 09 08:07:58 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-4d726b3e-7cb7-4672-ba2b-acc9991d1429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47015612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.47015612 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1614397148 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 5995642062 ps |
| CPU time | 107.57 seconds |
| Started | Aug 09 08:06:37 PM PDT 24 |
| Finished | Aug 09 08:08:25 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-9a5ea2e9-d7a6-4d7f-acc0-103b5d3393b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614397148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.1614397148 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2538521854 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 55835052 ps |
| CPU time | 6.88 seconds |
| Started | Aug 09 08:06:42 PM PDT 24 |
| Finished | Aug 09 08:06:49 PM PDT 24 |
| Peak memory | 574796 kb |
| Host | smart-ab79b35a-f233-4593-9931-91e605e1b87b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538521854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.2538521854 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.2949812450 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 15767976191 ps |
| CPU time | 541.42 seconds |
| Started | Aug 09 08:06:44 PM PDT 24 |
| Finished | Aug 09 08:15:45 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-29995837-455d-49d3-a387-411febf6993b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949812450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.2949812450 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.2144083053 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 146470145 ps |
| CPU time | 13.82 seconds |
| Started | Aug 09 08:06:42 PM PDT 24 |
| Finished | Aug 09 08:06:56 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-6d48b472-4d6a-4229-8748-4a6d26724698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144083053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.2144083053 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3281671144 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 1338941192 ps |
| CPU time | 229.38 seconds |
| Started | Aug 09 08:06:42 PM PDT 24 |
| Finished | Aug 09 08:10:31 PM PDT 24 |
| Peak memory | 577032 kb |
| Host | smart-5a1a736a-79c8-4f16-be20-f3e1331380f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281671144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.3281671144 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3623660576 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 6125234056 ps |
| CPU time | 368.53 seconds |
| Started | Aug 09 08:06:41 PM PDT 24 |
| Finished | Aug 09 08:12:50 PM PDT 24 |
| Peak memory | 577348 kb |
| Host | smart-13ddc497-e260-416b-a349-685dd6006cf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623660576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.3623660576 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.2069510225 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 225514458 ps |
| CPU time | 27.97 seconds |
| Started | Aug 09 08:06:43 PM PDT 24 |
| Finished | Aug 09 08:07:11 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-867052e7-137b-44e7-a9ac-8b319eb3cad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069510225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.2069510225 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.1272348450 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 1038673178 ps |
| CPU time | 75.12 seconds |
| Started | Aug 09 08:06:54 PM PDT 24 |
| Finished | Aug 09 08:08:09 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-b7f25128-3bf1-4255-9ecd-19dd71b9ac5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272348450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .1272348450 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.19480237 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 743451367 ps |
| CPU time | 28.63 seconds |
| Started | Aug 09 08:06:47 PM PDT 24 |
| Finished | Aug 09 08:07:16 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-4273fb30-f1dd-4c20-ad5c-41a49c4c444b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19480237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr.19480237 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.2130382423 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 357407747 ps |
| CPU time | 26.45 seconds |
| Started | Aug 09 08:06:47 PM PDT 24 |
| Finished | Aug 09 08:07:13 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-0f3ea947-b8b5-4737-a09e-35b8d4f4ce5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130382423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.2130382423 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.1881707124 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 292360462 ps |
| CPU time | 13.21 seconds |
| Started | Aug 09 08:06:43 PM PDT 24 |
| Finished | Aug 09 08:06:56 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-13b769f4-23be-4d88-b18f-de992854812e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881707124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.1881707124 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.4168185443 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 16896908673 ps |
| CPU time | 186.88 seconds |
| Started | Aug 09 08:06:56 PM PDT 24 |
| Finished | Aug 09 08:10:03 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-ff12e638-ddf6-41fd-afc5-27e19eb93f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168185443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.4168185443 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.3083398970 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 32442646350 ps |
| CPU time | 543.13 seconds |
| Started | Aug 09 08:06:55 PM PDT 24 |
| Finished | Aug 09 08:15:58 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-85668647-1aaf-46c9-b5a8-91dad2685ad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083398970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.3083398970 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.3942927535 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 224924512 ps |
| CPU time | 22.19 seconds |
| Started | Aug 09 08:06:46 PM PDT 24 |
| Finished | Aug 09 08:07:09 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-951ebee7-75d5-4488-8edb-c7f435fd56f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942927535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.3942927535 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.567791261 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 391418188 ps |
| CPU time | 14.58 seconds |
| Started | Aug 09 08:06:48 PM PDT 24 |
| Finished | Aug 09 08:07:02 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-45d764d1-fa58-44d0-8cdb-097f4c5ffa68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567791261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.567791261 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.22383881 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 204941647 ps |
| CPU time | 8.71 seconds |
| Started | Aug 09 08:06:41 PM PDT 24 |
| Finished | Aug 09 08:06:50 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-4419d17f-505e-4bf5-9768-feb5f5a4bdcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22383881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.22383881 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.4061214581 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 6589057509 ps |
| CPU time | 64.08 seconds |
| Started | Aug 09 08:06:43 PM PDT 24 |
| Finished | Aug 09 08:07:48 PM PDT 24 |
| Peak memory | 574892 kb |
| Host | smart-706cd96b-1e10-497e-8911-9bbec304cdfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061214581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.4061214581 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3214901166 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 3354033457 ps |
| CPU time | 57.3 seconds |
| Started | Aug 09 08:06:41 PM PDT 24 |
| Finished | Aug 09 08:07:38 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-b1c9a823-a659-42ef-ab6c-8a8d8c13530e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214901166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.3214901166 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.4124574657 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 48320260 ps |
| CPU time | 6.24 seconds |
| Started | Aug 09 08:06:45 PM PDT 24 |
| Finished | Aug 09 08:06:51 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-fafbb9fb-26cc-45b3-b91d-f3ee9f88a33e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124574657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.4124574657 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.4158372649 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 2342816884 ps |
| CPU time | 93.35 seconds |
| Started | Aug 09 08:06:56 PM PDT 24 |
| Finished | Aug 09 08:08:29 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-cbd58698-62b6-41f8-8c3c-5497003cdba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158372649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.4158372649 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.1235285704 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 1730813737 ps |
| CPU time | 66.02 seconds |
| Started | Aug 09 08:06:45 PM PDT 24 |
| Finished | Aug 09 08:07:51 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-d53f27bd-6f07-4664-8b8c-9e500003c6c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235285704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.1235285704 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3563605377 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2150577081 ps |
| CPU time | 317.61 seconds |
| Started | Aug 09 08:06:46 PM PDT 24 |
| Finished | Aug 09 08:12:03 PM PDT 24 |
| Peak memory | 577164 kb |
| Host | smart-e33eb974-f0e0-48a6-8ba8-23f807acb613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563605377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.3563605377 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2220680715 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2014551302 ps |
| CPU time | 277.12 seconds |
| Started | Aug 09 08:06:49 PM PDT 24 |
| Finished | Aug 09 08:11:26 PM PDT 24 |
| Peak memory | 577000 kb |
| Host | smart-e0682af1-4d5a-4edf-af87-a0be38f34fb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220680715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.2220680715 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.1224311444 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1295149602 ps |
| CPU time | 56.47 seconds |
| Started | Aug 09 08:06:47 PM PDT 24 |
| Finished | Aug 09 08:07:43 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-d0d776a6-33ee-4b8f-8c7c-f61828435255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224311444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.1224311444 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.3008604985 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 2576357313 ps |
| CPU time | 101.48 seconds |
| Started | Aug 09 08:06:54 PM PDT 24 |
| Finished | Aug 09 08:08:35 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-95cd3077-86a5-4875-ab9a-e30442ddab3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008604985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .3008604985 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1592569805 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 40243849235 ps |
| CPU time | 697.22 seconds |
| Started | Aug 09 08:06:55 PM PDT 24 |
| Finished | Aug 09 08:18:32 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-7dc4a72d-9d39-44e6-9c59-14978435bf5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592569805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.1592569805 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3506311152 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 1088985116 ps |
| CPU time | 44.78 seconds |
| Started | Aug 09 08:06:54 PM PDT 24 |
| Finished | Aug 09 08:07:38 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-702b2bbf-7736-41fa-971c-80f9045a624b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506311152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.3506311152 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.2103861033 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 2171448625 ps |
| CPU time | 67.92 seconds |
| Started | Aug 09 08:06:54 PM PDT 24 |
| Finished | Aug 09 08:08:02 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-b0ff4faf-92f0-49e3-bb07-e31f5bcd3266 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103861033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.2103861033 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.3697802228 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 170561492 ps |
| CPU time | 9.65 seconds |
| Started | Aug 09 08:06:55 PM PDT 24 |
| Finished | Aug 09 08:07:05 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-a2bc2e31-a863-4526-9430-2ff2b6325068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697802228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.3697802228 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.1678827111 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 43865811400 ps |
| CPU time | 507.15 seconds |
| Started | Aug 09 08:06:53 PM PDT 24 |
| Finished | Aug 09 08:15:21 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-8aca41f7-045c-43a1-ba94-a973f0535e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678827111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.1678827111 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1493599561 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 37774827621 ps |
| CPU time | 569.12 seconds |
| Started | Aug 09 08:06:57 PM PDT 24 |
| Finished | Aug 09 08:16:27 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-095138ab-539d-411d-ba4d-215c5cf71535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493599561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.1493599561 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.2280813321 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 609532608 ps |
| CPU time | 43.38 seconds |
| Started | Aug 09 08:06:56 PM PDT 24 |
| Finished | Aug 09 08:07:39 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-a8ca5d32-0522-4ab9-9730-af95b05eb742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280813321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.2280813321 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.4040049952 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 735427652 ps |
| CPU time | 24.99 seconds |
| Started | Aug 09 08:06:54 PM PDT 24 |
| Finished | Aug 09 08:07:19 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-5ea47e75-1c11-4932-8290-455bb7dcf5eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040049952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.4040049952 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.1747483655 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 203534963 ps |
| CPU time | 9.24 seconds |
| Started | Aug 09 08:06:47 PM PDT 24 |
| Finished | Aug 09 08:06:56 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-96dc9656-358a-4920-974a-bd8070e1c2a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747483655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.1747483655 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.2664179486 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 5952138784 ps |
| CPU time | 59.77 seconds |
| Started | Aug 09 08:06:56 PM PDT 24 |
| Finished | Aug 09 08:07:56 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-290c8ba7-0439-4e30-8761-a6b73074510d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664179486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.2664179486 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3801782963 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 5041012006 ps |
| CPU time | 81.91 seconds |
| Started | Aug 09 08:06:54 PM PDT 24 |
| Finished | Aug 09 08:08:16 PM PDT 24 |
| Peak memory | 574892 kb |
| Host | smart-ec41aa79-e891-4b03-bcf7-42f1693b0406 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801782963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.3801782963 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.396078814 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 46855092 ps |
| CPU time | 6.07 seconds |
| Started | Aug 09 08:06:55 PM PDT 24 |
| Finished | Aug 09 08:07:01 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-43c4b109-c3a7-4ae9-bd4a-822a9ea3d629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396078814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays .396078814 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.3957553025 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 3918515624 ps |
| CPU time | 338.04 seconds |
| Started | Aug 09 08:06:54 PM PDT 24 |
| Finished | Aug 09 08:12:32 PM PDT 24 |
| Peak memory | 577144 kb |
| Host | smart-e3145644-d444-43c5-a95d-36f37e2719f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957553025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.3957553025 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1972890108 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 903176887 ps |
| CPU time | 32.59 seconds |
| Started | Aug 09 08:06:54 PM PDT 24 |
| Finished | Aug 09 08:07:27 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-1c79cc4a-20e2-4b14-9b93-55e88c9c9dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972890108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1972890108 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.2616261184 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 65767071 ps |
| CPU time | 29.44 seconds |
| Started | Aug 09 08:06:52 PM PDT 24 |
| Finished | Aug 09 08:07:22 PM PDT 24 |
| Peak memory | 575020 kb |
| Host | smart-2ee9c8d1-1cdb-47a5-8bb4-c5fe0f3cbf4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616261184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.2616261184 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.256875051 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 101798890 ps |
| CPU time | 27.18 seconds |
| Started | Aug 09 08:06:56 PM PDT 24 |
| Finished | Aug 09 08:07:24 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-78554ff3-693f-44da-b2af-93d5b87a34f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256875051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_reset_error.256875051 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.113958686 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 551522847 ps |
| CPU time | 24.04 seconds |
| Started | Aug 09 08:06:57 PM PDT 24 |
| Finished | Aug 09 08:07:21 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-7099f6eb-fa64-42e5-8330-fb6cbe70e9a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113958686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.113958686 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.612706357 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 476123864 ps |
| CPU time | 27.05 seconds |
| Started | Aug 09 08:07:01 PM PDT 24 |
| Finished | Aug 09 08:07:28 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-12bfe8e3-519d-4e4e-9d54-d7387ec1dd6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612706357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device. 612706357 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.265115023 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 100376821970 ps |
| CPU time | 1895.59 seconds |
| Started | Aug 09 08:07:04 PM PDT 24 |
| Finished | Aug 09 08:38:40 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-9ed6039b-4038-435e-b82f-15615c5d4f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265115023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_d evice_slow_rsp.265115023 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.32164325 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 638798306 ps |
| CPU time | 29.11 seconds |
| Started | Aug 09 08:07:03 PM PDT 24 |
| Finished | Aug 09 08:07:33 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-13e2a326-fe44-41e7-b82c-cae59ae4a196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32164325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr.32164325 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.1936989675 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 602816977 ps |
| CPU time | 20.85 seconds |
| Started | Aug 09 08:07:00 PM PDT 24 |
| Finished | Aug 09 08:07:21 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-ef16c528-c66e-4423-8554-9546f0d89aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936989675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.1936989675 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.3234035888 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1858353511 ps |
| CPU time | 66.45 seconds |
| Started | Aug 09 08:07:02 PM PDT 24 |
| Finished | Aug 09 08:08:09 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-1037021f-1509-4d11-b102-cbb1b88af58d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234035888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.3234035888 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.1606491438 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 55270862819 ps |
| CPU time | 622.15 seconds |
| Started | Aug 09 08:07:01 PM PDT 24 |
| Finished | Aug 09 08:17:23 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-54b03a17-3b6b-48ba-9d6b-7cd6ac23e501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606491438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.1606491438 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.702752261 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 62775291343 ps |
| CPU time | 1235.26 seconds |
| Started | Aug 09 08:07:00 PM PDT 24 |
| Finished | Aug 09 08:27:36 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-e32a6567-930a-4d19-badd-9d11606b7bda |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702752261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.702752261 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3225466861 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 22143364 ps |
| CPU time | 5.34 seconds |
| Started | Aug 09 08:07:05 PM PDT 24 |
| Finished | Aug 09 08:07:10 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-22836730-8724-4a06-ab9e-3105360c9357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225466861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.3225466861 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.3229480706 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 649684758 ps |
| CPU time | 21.23 seconds |
| Started | Aug 09 08:07:01 PM PDT 24 |
| Finished | Aug 09 08:07:22 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-d4a94f61-2a72-40f5-b5b4-974f273bc6ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229480706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.3229480706 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.1154545457 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 190286459 ps |
| CPU time | 8.37 seconds |
| Started | Aug 09 08:06:55 PM PDT 24 |
| Finished | Aug 09 08:07:03 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-9680d1be-44a4-40ee-8f31-f1a9d6c9328c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154545457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.1154545457 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.639677647 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 6780479440 ps |
| CPU time | 71.3 seconds |
| Started | Aug 09 08:07:02 PM PDT 24 |
| Finished | Aug 09 08:08:13 PM PDT 24 |
| Peak memory | 575092 kb |
| Host | smart-b778f0ff-d4af-4d22-ba0b-ce591cb1fe5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639677647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.639677647 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3218514838 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 6155478804 ps |
| CPU time | 102.64 seconds |
| Started | Aug 09 08:07:03 PM PDT 24 |
| Finished | Aug 09 08:08:46 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-6659ec4f-a261-46ff-ad55-203ead3dfcb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218514838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.3218514838 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.843098889 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 50022380 ps |
| CPU time | 6.54 seconds |
| Started | Aug 09 08:07:01 PM PDT 24 |
| Finished | Aug 09 08:07:07 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-e99337b8-7288-429a-b4a8-8438af5effb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843098889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays .843098889 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.3713469483 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 15000313766 ps |
| CPU time | 501.99 seconds |
| Started | Aug 09 08:07:05 PM PDT 24 |
| Finished | Aug 09 08:15:27 PM PDT 24 |
| Peak memory | 577088 kb |
| Host | smart-1fb37e04-3149-431d-9e57-48589a149ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713469483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.3713469483 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.3193904196 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 6368112 ps |
| CPU time | 3.98 seconds |
| Started | Aug 09 08:06:59 PM PDT 24 |
| Finished | Aug 09 08:07:03 PM PDT 24 |
| Peak memory | 566416 kb |
| Host | smart-936483a1-9ad5-4b90-b330-068bb20a8a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193904196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.3193904196 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.707469695 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 237177826 ps |
| CPU time | 53.64 seconds |
| Started | Aug 09 08:07:03 PM PDT 24 |
| Finished | Aug 09 08:07:57 PM PDT 24 |
| Peak memory | 577048 kb |
| Host | smart-edc076b3-5267-497a-920d-88285a69c098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707469695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_ with_rand_reset.707469695 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.3675194274 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 6228609806 ps |
| CPU time | 587.84 seconds |
| Started | Aug 09 08:07:02 PM PDT 24 |
| Finished | Aug 09 08:16:50 PM PDT 24 |
| Peak memory | 582936 kb |
| Host | smart-8eecffaa-6cf5-4845-83a7-895b8e8ece5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675194274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.3675194274 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1617497756 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 62194192 ps |
| CPU time | 9.27 seconds |
| Started | Aug 09 08:07:02 PM PDT 24 |
| Finished | Aug 09 08:07:11 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-f0ee75f6-fb29-48ac-b782-ad6200a21b27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617497756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1617497756 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.3948420671 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 895214876 ps |
| CPU time | 36.52 seconds |
| Started | Aug 09 08:07:09 PM PDT 24 |
| Finished | Aug 09 08:07:46 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-ce17ec13-c558-49d2-bade-21a752ee7977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948420671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .3948420671 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.3684396198 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 91522522823 ps |
| CPU time | 1575.86 seconds |
| Started | Aug 09 08:07:09 PM PDT 24 |
| Finished | Aug 09 08:33:25 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-3457d9db-9047-4998-ba26-4d9a32566771 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684396198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.3684396198 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1424670682 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 1306984336 ps |
| CPU time | 48.51 seconds |
| Started | Aug 09 08:07:11 PM PDT 24 |
| Finished | Aug 09 08:07:59 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-af928cfb-d271-4ad5-a976-e4a3cb97d9f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424670682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.1424670682 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.801507240 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 2608912578 ps |
| CPU time | 83.3 seconds |
| Started | Aug 09 08:07:11 PM PDT 24 |
| Finished | Aug 09 08:08:35 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-306d9d71-5382-4e5f-9433-ae8d3ec950a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801507240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.801507240 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.1918471670 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 435197112 ps |
| CPU time | 38.4 seconds |
| Started | Aug 09 08:07:11 PM PDT 24 |
| Finished | Aug 09 08:07:50 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-b2f4cac3-2ee0-431f-aa02-82149c472fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918471670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1918471670 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2398842442 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 52368053776 ps |
| CPU time | 556.99 seconds |
| Started | Aug 09 08:07:12 PM PDT 24 |
| Finished | Aug 09 08:16:29 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-c370b9d3-2172-4bbc-a475-00312a2b950c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398842442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2398842442 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.91593105 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 35250637422 ps |
| CPU time | 619.11 seconds |
| Started | Aug 09 08:07:10 PM PDT 24 |
| Finished | Aug 09 08:17:29 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-93829169-374c-4c2d-9d2a-72bc537a2c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91593105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.91593105 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.2106531885 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 568360755 ps |
| CPU time | 51.09 seconds |
| Started | Aug 09 08:07:09 PM PDT 24 |
| Finished | Aug 09 08:08:01 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-c4b16294-cbbc-45e5-9928-a3247d8f1d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106531885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.2106531885 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.1078732308 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 241874706 ps |
| CPU time | 18.26 seconds |
| Started | Aug 09 08:07:10 PM PDT 24 |
| Finished | Aug 09 08:07:28 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-f37bfd0d-83a9-4d4e-b9ac-d9fc498ad479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078732308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.1078732308 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.1637710498 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 208363735 ps |
| CPU time | 9.46 seconds |
| Started | Aug 09 08:07:00 PM PDT 24 |
| Finished | Aug 09 08:07:10 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-d780f0d2-0803-4bad-9865-71e9a90f0b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637710498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1637710498 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.2892659119 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 7009889979 ps |
| CPU time | 72.51 seconds |
| Started | Aug 09 08:07:00 PM PDT 24 |
| Finished | Aug 09 08:08:13 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-3829d98e-9f38-4848-9d19-dd116b748e4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892659119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2892659119 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.517147864 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 6460636908 ps |
| CPU time | 112.45 seconds |
| Started | Aug 09 08:07:12 PM PDT 24 |
| Finished | Aug 09 08:09:04 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-0109ad4a-7b4a-41e0-9bb9-555e1469fa44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517147864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.517147864 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.947498772 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 46507057 ps |
| CPU time | 6.12 seconds |
| Started | Aug 09 08:07:04 PM PDT 24 |
| Finished | Aug 09 08:07:10 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-168a79dc-fcb3-4681-a7c7-9b04c6099f99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947498772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays .947498772 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.364658860 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 2765074615 ps |
| CPU time | 111.73 seconds |
| Started | Aug 09 08:07:10 PM PDT 24 |
| Finished | Aug 09 08:09:01 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-62585484-58ff-4255-92d4-d3f08c641708 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364658860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.364658860 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.2913035960 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 6609311444 ps |
| CPU time | 232.41 seconds |
| Started | Aug 09 08:07:19 PM PDT 24 |
| Finished | Aug 09 08:11:11 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-f64e7b45-e8fe-4817-8f37-76e840b76b87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913035960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.2913035960 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2378912570 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 191327531 ps |
| CPU time | 104.02 seconds |
| Started | Aug 09 08:07:21 PM PDT 24 |
| Finished | Aug 09 08:09:05 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-1eb3248a-f4ac-48bf-a8b2-eb29084dc50e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378912570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.2378912570 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.2715735939 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 14083286196 ps |
| CPU time | 614.48 seconds |
| Started | Aug 09 08:07:21 PM PDT 24 |
| Finished | Aug 09 08:17:36 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-9b0613fa-308a-42d9-81ee-d50fdf44ce3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715735939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.2715735939 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.2428745423 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1107209788 ps |
| CPU time | 48.36 seconds |
| Started | Aug 09 08:07:11 PM PDT 24 |
| Finished | Aug 09 08:08:00 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-04cd8760-b784-4014-a36a-5b633724f284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428745423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.2428745423 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.1090426493 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 14524266 ps |
| CPU time | 5.49 seconds |
| Started | Aug 09 08:07:19 PM PDT 24 |
| Finished | Aug 09 08:07:25 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-d37a2466-32af-43ab-98a5-08b53fe265b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090426493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .1090426493 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.1682009961 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 44425656848 ps |
| CPU time | 884.63 seconds |
| Started | Aug 09 08:07:20 PM PDT 24 |
| Finished | Aug 09 08:22:05 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-1d8e6d9f-b3f2-4171-85f6-c9e5686199f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682009961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.1682009961 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3247133400 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 211374167 ps |
| CPU time | 20.48 seconds |
| Started | Aug 09 08:07:20 PM PDT 24 |
| Finished | Aug 09 08:07:41 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-72ea0f82-b0ef-47eb-ab78-08be345887ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247133400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.3247133400 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.3743463271 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 42734626 ps |
| CPU time | 6.75 seconds |
| Started | Aug 09 08:07:22 PM PDT 24 |
| Finished | Aug 09 08:07:29 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-84fb2a20-facd-4fe0-9d14-1d1f3372c593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743463271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.3743463271 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.2024138585 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 1541957405 ps |
| CPU time | 49.59 seconds |
| Started | Aug 09 08:07:19 PM PDT 24 |
| Finished | Aug 09 08:08:09 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-267cf4c6-e8b4-4947-a2a2-9b64a5de9c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024138585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.2024138585 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.838777095 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 42021940871 ps |
| CPU time | 483.69 seconds |
| Started | Aug 09 08:07:19 PM PDT 24 |
| Finished | Aug 09 08:15:23 PM PDT 24 |
| Peak memory | 577068 kb |
| Host | smart-7f9a72fd-2ca2-454d-a779-8de9ee893a62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838777095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.838777095 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.52962536 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 3507361922 ps |
| CPU time | 57.42 seconds |
| Started | Aug 09 08:07:19 PM PDT 24 |
| Finished | Aug 09 08:08:17 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-4e3f6134-04ba-4dbb-a1db-b713c21412b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52962536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.52962536 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.2386003893 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 227718750 ps |
| CPU time | 20.08 seconds |
| Started | Aug 09 08:07:20 PM PDT 24 |
| Finished | Aug 09 08:07:40 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-e833a7cd-850a-469d-8b35-3ce59a481dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386003893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.2386003893 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.4067701462 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 328548564 ps |
| CPU time | 13.5 seconds |
| Started | Aug 09 08:07:18 PM PDT 24 |
| Finished | Aug 09 08:07:32 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-5b9aa909-aaf1-4ae2-abbf-8da5dd3f7e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067701462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.4067701462 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.2299214180 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 181569869 ps |
| CPU time | 8.58 seconds |
| Started | Aug 09 08:07:19 PM PDT 24 |
| Finished | Aug 09 08:07:28 PM PDT 24 |
| Peak memory | 574828 kb |
| Host | smart-9800bfda-1284-4a7a-b714-81843b2f1724 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299214180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.2299214180 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.3488630348 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 8021258025 ps |
| CPU time | 83.46 seconds |
| Started | Aug 09 08:07:20 PM PDT 24 |
| Finished | Aug 09 08:08:44 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-18070dcc-993f-484c-a4f9-110cb747cc84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488630348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.3488630348 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3922984499 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 5642233136 ps |
| CPU time | 97.31 seconds |
| Started | Aug 09 08:07:18 PM PDT 24 |
| Finished | Aug 09 08:08:55 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-0fbef275-b588-4679-b297-6f6a265fba56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922984499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.3922984499 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1874485802 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 43466955 ps |
| CPU time | 5.82 seconds |
| Started | Aug 09 08:07:19 PM PDT 24 |
| Finished | Aug 09 08:07:25 PM PDT 24 |
| Peak memory | 574840 kb |
| Host | smart-1de24747-3807-4f32-9c85-5fb3a0e5c4c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874485802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.1874485802 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.2381144704 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 6830330454 ps |
| CPU time | 256.64 seconds |
| Started | Aug 09 08:07:25 PM PDT 24 |
| Finished | Aug 09 08:11:42 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-092dce16-a4d0-4ae4-ac71-9eecc3755089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381144704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.2381144704 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2204728566 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 644105723 ps |
| CPU time | 267.58 seconds |
| Started | Aug 09 08:07:20 PM PDT 24 |
| Finished | Aug 09 08:11:48 PM PDT 24 |
| Peak memory | 577060 kb |
| Host | smart-042d9aa5-9d84-4b1a-af7f-bd03f1f62388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204728566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.2204728566 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2366681625 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 32757738 ps |
| CPU time | 25.87 seconds |
| Started | Aug 09 08:07:26 PM PDT 24 |
| Finished | Aug 09 08:07:52 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-6a7aafe0-335e-479d-9026-ea4ddb073d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366681625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.2366681625 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.3743856069 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 1365460262 ps |
| CPU time | 56.45 seconds |
| Started | Aug 09 08:07:22 PM PDT 24 |
| Finished | Aug 09 08:08:18 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-196327b9-b039-410c-b613-b95dc5a8c3a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743856069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.3743856069 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.1274902306 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 226213473 ps |
| CPU time | 20.5 seconds |
| Started | Aug 09 08:07:25 PM PDT 24 |
| Finished | Aug 09 08:07:46 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-2d19226f-5e98-4095-a49c-b6858973646b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274902306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .1274902306 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3708741772 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 68089499515 ps |
| CPU time | 1295.83 seconds |
| Started | Aug 09 08:07:26 PM PDT 24 |
| Finished | Aug 09 08:29:02 PM PDT 24 |
| Peak memory | 576392 kb |
| Host | smart-756c43a8-3ce8-425d-a94c-3a51163a3013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708741772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.3708741772 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2849836081 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 313400391 ps |
| CPU time | 30.51 seconds |
| Started | Aug 09 08:07:26 PM PDT 24 |
| Finished | Aug 09 08:07:56 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-64821a7b-8e44-4695-b30a-4e1a5d820eaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849836081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.2849836081 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.1145951296 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 534978281 ps |
| CPU time | 18.57 seconds |
| Started | Aug 09 08:07:27 PM PDT 24 |
| Finished | Aug 09 08:07:45 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-95a861cb-0a4d-4b90-92d3-d5efbce8f0a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145951296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.1145951296 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.1079140826 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 527670188 ps |
| CPU time | 43.77 seconds |
| Started | Aug 09 08:07:28 PM PDT 24 |
| Finished | Aug 09 08:08:12 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-1675d409-1fbe-4af9-a30f-54325b0be3f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079140826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.1079140826 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.1831782760 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 43256490438 ps |
| CPU time | 424.51 seconds |
| Started | Aug 09 08:07:27 PM PDT 24 |
| Finished | Aug 09 08:14:31 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-2d6dd416-d58a-4a7f-8149-3331ce3e4c89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831782760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.1831782760 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.110432238 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 45379979492 ps |
| CPU time | 819.16 seconds |
| Started | Aug 09 08:07:28 PM PDT 24 |
| Finished | Aug 09 08:21:07 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-ea9e439e-428a-4a4b-bd02-993a6cf888c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110432238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.110432238 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.1370272573 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 481304073 ps |
| CPU time | 41.56 seconds |
| Started | Aug 09 08:07:27 PM PDT 24 |
| Finished | Aug 09 08:08:08 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-83ed2952-584a-4489-8912-d4ab8442bb0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370272573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.1370272573 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.1540485330 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 297310008 ps |
| CPU time | 23.48 seconds |
| Started | Aug 09 08:07:26 PM PDT 24 |
| Finished | Aug 09 08:07:49 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-3110af49-621f-4205-9be5-b19608af97b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540485330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1540485330 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.1871249942 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 206282739 ps |
| CPU time | 9.44 seconds |
| Started | Aug 09 08:07:26 PM PDT 24 |
| Finished | Aug 09 08:07:36 PM PDT 24 |
| Peak memory | 574840 kb |
| Host | smart-d8e42b41-4d63-4d52-8e4c-4f49d5484d76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871249942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.1871249942 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.3321975955 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 8191979927 ps |
| CPU time | 79.08 seconds |
| Started | Aug 09 08:07:27 PM PDT 24 |
| Finished | Aug 09 08:08:46 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-7592420b-eb81-4012-9b2a-3e3060cf6be0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321975955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.3321975955 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.4210804179 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 6114287950 ps |
| CPU time | 91.78 seconds |
| Started | Aug 09 08:07:28 PM PDT 24 |
| Finished | Aug 09 08:09:00 PM PDT 24 |
| Peak memory | 574872 kb |
| Host | smart-ad1ade10-f10d-4f7a-9e6b-5e404bf984ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210804179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.4210804179 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2897887380 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 41061790 ps |
| CPU time | 6.28 seconds |
| Started | Aug 09 08:07:25 PM PDT 24 |
| Finished | Aug 09 08:07:32 PM PDT 24 |
| Peak memory | 574796 kb |
| Host | smart-4771bcb4-aa3f-45e2-bdc4-aee9217743f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897887380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.2897887380 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.1155127990 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 7985271925 ps |
| CPU time | 260.06 seconds |
| Started | Aug 09 08:07:31 PM PDT 24 |
| Finished | Aug 09 08:11:51 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-3c101be0-bd9d-4aa7-94a4-a1b84569bcb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155127990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.1155127990 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.1215138585 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 5305011557 ps |
| CPU time | 207.11 seconds |
| Started | Aug 09 08:07:34 PM PDT 24 |
| Finished | Aug 09 08:11:01 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-6c35a8b4-7185-4188-8419-9e881b50ea25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215138585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.1215138585 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3197929410 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 6120703663 ps |
| CPU time | 343.03 seconds |
| Started | Aug 09 08:07:31 PM PDT 24 |
| Finished | Aug 09 08:13:14 PM PDT 24 |
| Peak memory | 577128 kb |
| Host | smart-dfabc7b4-4fce-403b-8368-bb532a8e9278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197929410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.3197929410 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.93450031 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 107741186 ps |
| CPU time | 27.36 seconds |
| Started | Aug 09 08:07:35 PM PDT 24 |
| Finished | Aug 09 08:08:03 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-69ee8701-86ae-41b6-8155-3d18f8aa358c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93450031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_ with_reset_error.93450031 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.998584455 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 229647311 ps |
| CPU time | 12.06 seconds |
| Started | Aug 09 08:07:27 PM PDT 24 |
| Finished | Aug 09 08:07:39 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-889e1484-ed6a-40f3-aae7-ad2441e3f8f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998584455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.998584455 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.2802746293 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 196800469 ps |
| CPU time | 11.86 seconds |
| Started | Aug 09 08:07:33 PM PDT 24 |
| Finished | Aug 09 08:07:45 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-fac12389-ec01-4d5a-9907-a4d368032c0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802746293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .2802746293 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.1152701495 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 38958953154 ps |
| CPU time | 584.94 seconds |
| Started | Aug 09 08:07:38 PM PDT 24 |
| Finished | Aug 09 08:17:23 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-ae97102d-1049-4cca-bdc3-d8c8b0340b22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152701495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.1152701495 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.449855084 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 1266415974 ps |
| CPU time | 54.35 seconds |
| Started | Aug 09 08:07:36 PM PDT 24 |
| Finished | Aug 09 08:08:30 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-a0f17fcd-6af6-4af7-adea-7d160678c9ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449855084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr .449855084 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.3910200767 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 323499253 ps |
| CPU time | 12.98 seconds |
| Started | Aug 09 08:07:37 PM PDT 24 |
| Finished | Aug 09 08:07:50 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-402a11a5-3abf-47d3-980e-1de05528110a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910200767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.3910200767 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.1490550473 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 1176151856 ps |
| CPU time | 46.98 seconds |
| Started | Aug 09 08:07:34 PM PDT 24 |
| Finished | Aug 09 08:08:21 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-ce384f2f-6c5c-4345-8358-38a97834bfae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490550473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.1490550473 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2320785577 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 79213198224 ps |
| CPU time | 875.47 seconds |
| Started | Aug 09 08:07:34 PM PDT 24 |
| Finished | Aug 09 08:22:10 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-8a7a2008-d18e-49e3-8e0b-01585efe1fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320785577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.2320785577 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.2262649656 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 31687087419 ps |
| CPU time | 546.42 seconds |
| Started | Aug 09 08:07:34 PM PDT 24 |
| Finished | Aug 09 08:16:40 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-abcf41e0-8d61-4a29-8511-362749077038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262649656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.2262649656 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.327458207 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 190132344 ps |
| CPU time | 18.96 seconds |
| Started | Aug 09 08:07:35 PM PDT 24 |
| Finished | Aug 09 08:07:54 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-f440e271-b9aa-4b5b-9fe8-31c6b61e60b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327458207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_dela ys.327458207 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.2656541408 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 430680610 ps |
| CPU time | 31.2 seconds |
| Started | Aug 09 08:07:32 PM PDT 24 |
| Finished | Aug 09 08:08:04 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-79a22198-e838-4363-a858-b09d79d8cb64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656541408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.2656541408 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.2313639732 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 194416162 ps |
| CPU time | 8.53 seconds |
| Started | Aug 09 08:07:35 PM PDT 24 |
| Finished | Aug 09 08:07:44 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-46eb48d4-b59e-412b-b90e-5de0391815dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313639732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.2313639732 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1921048458 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 9880254345 ps |
| CPU time | 104.24 seconds |
| Started | Aug 09 08:07:37 PM PDT 24 |
| Finished | Aug 09 08:09:22 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-70b425cd-2472-47fb-8ed4-92604581b504 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921048458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1921048458 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1069405714 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 4362734802 ps |
| CPU time | 63.58 seconds |
| Started | Aug 09 08:07:38 PM PDT 24 |
| Finished | Aug 09 08:08:41 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-66ec6ea1-ea01-49a1-bcee-4c249eab48a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069405714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.1069405714 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2468318156 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 35061326 ps |
| CPU time | 5.5 seconds |
| Started | Aug 09 08:07:34 PM PDT 24 |
| Finished | Aug 09 08:07:40 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-8ef8396e-f846-4cf6-9466-7c897c2f85ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468318156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.2468318156 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.1626668485 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 3725467686 ps |
| CPU time | 291.72 seconds |
| Started | Aug 09 08:07:33 PM PDT 24 |
| Finished | Aug 09 08:12:25 PM PDT 24 |
| Peak memory | 577136 kb |
| Host | smart-b778cdd2-b978-45f4-9d4f-cb822d6a5cf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626668485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.1626668485 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.2984391123 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 4137262570 ps |
| CPU time | 137.96 seconds |
| Started | Aug 09 08:07:41 PM PDT 24 |
| Finished | Aug 09 08:09:59 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-86bb01f0-4a5d-452e-ac90-bf36fa05a435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984391123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.2984391123 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.801697101 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 3228073622 ps |
| CPU time | 402.81 seconds |
| Started | Aug 09 08:07:36 PM PDT 24 |
| Finished | Aug 09 08:14:19 PM PDT 24 |
| Peak memory | 577160 kb |
| Host | smart-62b4bea9-e058-4fcf-a3f3-3f839cefdb68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801697101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_ with_rand_reset.801697101 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3428578259 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 10235976515 ps |
| CPU time | 409.15 seconds |
| Started | Aug 09 08:07:42 PM PDT 24 |
| Finished | Aug 09 08:14:31 PM PDT 24 |
| Peak memory | 577104 kb |
| Host | smart-20d330d5-7cac-4060-8c4f-e25bfc925774 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428578259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.3428578259 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2486279225 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 117244414 ps |
| CPU time | 15.07 seconds |
| Started | Aug 09 08:07:34 PM PDT 24 |
| Finished | Aug 09 08:07:49 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-b3a172b9-ca35-41f9-92e2-b496930837ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486279225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.2486279225 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1756768175 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 7181511979 ps |
| CPU time | 437.53 seconds |
| Started | Aug 09 07:58:04 PM PDT 24 |
| Finished | Aug 09 08:05:21 PM PDT 24 |
| Peak memory | 639884 kb |
| Host | smart-a3797189-30dd-4e3a-83af-fd13fdacb8fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756768175 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.1756768175 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.3712056585 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 4272206512 ps |
| CPU time | 290.84 seconds |
| Started | Aug 09 07:58:03 PM PDT 24 |
| Finished | Aug 09 08:02:54 PM PDT 24 |
| Peak memory | 599256 kb |
| Host | smart-b714fa7f-d8a5-45c5-815c-04ea4d285d19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712056585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.3712056585 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.54168465 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 25774514481 ps |
| CPU time | 3431.33 seconds |
| Started | Aug 09 07:57:57 PM PDT 24 |
| Finished | Aug 09 08:55:09 PM PDT 24 |
| Peak memory | 593676 kb |
| Host | smart-f6b1859f-fb96-4034-8115-f5185bcde344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54168465 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.chip_same_csr_outstanding.54168465 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.1070839319 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3926614120 ps |
| CPU time | 182.94 seconds |
| Started | Aug 09 07:58:03 PM PDT 24 |
| Finished | Aug 09 08:01:06 PM PDT 24 |
| Peak memory | 604004 kb |
| Host | smart-c44e68aa-4fa2-46d1-b491-662cdf715fee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070839319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.1070839319 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.2262876988 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 904116200 ps |
| CPU time | 39.56 seconds |
| Started | Aug 09 07:58:03 PM PDT 24 |
| Finished | Aug 09 07:58:43 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-015861a4-b4ed-46c1-ab90-96b408e42723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262876988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 2262876988 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.791943804 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 33875458725 ps |
| CPU time | 576.79 seconds |
| Started | Aug 09 07:58:10 PM PDT 24 |
| Finished | Aug 09 08:07:47 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-dba42d76-7aeb-4340-ace8-251142c6dd65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791943804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_de vice_slow_rsp.791943804 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.797741417 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 1283581598 ps |
| CPU time | 44.42 seconds |
| Started | Aug 09 07:57:57 PM PDT 24 |
| Finished | Aug 09 07:58:42 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-b41fa073-34c1-4b82-8d56-b68ab4d66c31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797741417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr. 797741417 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.3560584714 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 2546256784 ps |
| CPU time | 94.6 seconds |
| Started | Aug 09 07:58:04 PM PDT 24 |
| Finished | Aug 09 07:59:39 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-3331592a-f9b3-4ab1-9f40-e140d42e8e3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560584714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3560584714 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.909506730 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 1736752460 ps |
| CPU time | 61.86 seconds |
| Started | Aug 09 07:57:57 PM PDT 24 |
| Finished | Aug 09 07:58:58 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-15242fa0-cc45-470c-a290-0b14f7cc312a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909506730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.909506730 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.2463848339 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 15886236315 ps |
| CPU time | 175.88 seconds |
| Started | Aug 09 07:58:04 PM PDT 24 |
| Finished | Aug 09 08:01:00 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-035e4892-ddd3-4443-aa63-1d05acdb8409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463848339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2463848339 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.277646037 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 20886079518 ps |
| CPU time | 351.4 seconds |
| Started | Aug 09 07:57:58 PM PDT 24 |
| Finished | Aug 09 08:03:49 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-bf38de99-f345-48db-b23d-5f19f867ed31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277646037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.277646037 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.276832275 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 512590842 ps |
| CPU time | 41.57 seconds |
| Started | Aug 09 07:57:59 PM PDT 24 |
| Finished | Aug 09 07:58:41 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-c972f71c-ea06-4347-acbe-ff9764e75279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276832275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delay s.276832275 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.1044816202 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 2570733090 ps |
| CPU time | 77.83 seconds |
| Started | Aug 09 07:58:03 PM PDT 24 |
| Finished | Aug 09 07:59:21 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-508e6527-c37d-45de-b209-b4951eb29d2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044816202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1044816202 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.3087863956 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 41817299 ps |
| CPU time | 5.82 seconds |
| Started | Aug 09 07:57:58 PM PDT 24 |
| Finished | Aug 09 07:58:04 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-391a9fec-e295-4d5a-8a96-47899dc06ed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087863956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3087863956 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2470191875 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 9711499092 ps |
| CPU time | 97.11 seconds |
| Started | Aug 09 07:57:57 PM PDT 24 |
| Finished | Aug 09 07:59:34 PM PDT 24 |
| Peak memory | 575096 kb |
| Host | smart-fc0741cc-4be9-4a7a-8547-8907964518ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470191875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2470191875 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.1197247202 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 6249667752 ps |
| CPU time | 107.77 seconds |
| Started | Aug 09 07:58:01 PM PDT 24 |
| Finished | Aug 09 07:59:49 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-f8c48740-6381-4fd3-a30c-e0ed43b3afb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197247202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1197247202 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.959418211 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 38421435 ps |
| CPU time | 5.63 seconds |
| Started | Aug 09 07:58:03 PM PDT 24 |
| Finished | Aug 09 07:58:08 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-9fc2def5-3114-4fdd-8b06-f6f2d2407882 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959418211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays. 959418211 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.1975111336 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 165148810 ps |
| CPU time | 14.81 seconds |
| Started | Aug 09 07:58:10 PM PDT 24 |
| Finished | Aug 09 07:58:25 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-b44be48a-b267-4c69-9819-c4ba64f46fe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975111336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1975111336 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2261883859 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 2880023395 ps |
| CPU time | 181.46 seconds |
| Started | Aug 09 07:57:55 PM PDT 24 |
| Finished | Aug 09 08:00:57 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-846ad82a-2ce5-4b45-b791-eb1f5d55dc94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261883859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2261883859 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2661214538 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 8382719528 ps |
| CPU time | 526.75 seconds |
| Started | Aug 09 07:57:58 PM PDT 24 |
| Finished | Aug 09 08:06:45 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-4297e3be-b68a-47ba-bd11-ce70b77d1cb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661214538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.2661214538 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2751923810 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 5008654863 ps |
| CPU time | 425.52 seconds |
| Started | Aug 09 07:58:02 PM PDT 24 |
| Finished | Aug 09 08:05:07 PM PDT 24 |
| Peak memory | 577192 kb |
| Host | smart-ac37f21c-a18c-4277-90c4-ec5810987925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751923810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.2751923810 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.2521706079 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 71199179 ps |
| CPU time | 9.14 seconds |
| Started | Aug 09 07:58:00 PM PDT 24 |
| Finished | Aug 09 07:58:09 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-5d583ce3-e6df-411b-8bb6-cbb83381fe54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521706079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2521706079 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2366343142 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 857413588 ps |
| CPU time | 39.92 seconds |
| Started | Aug 09 08:07:41 PM PDT 24 |
| Finished | Aug 09 08:08:21 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-dfc8bf37-5afe-45c3-8de5-18da16bf630e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366343142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .2366343142 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.100748652 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 822964471 ps |
| CPU time | 34.48 seconds |
| Started | Aug 09 08:07:58 PM PDT 24 |
| Finished | Aug 09 08:08:32 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-293cb926-a589-41bd-ade2-28f2d200acda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100748652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr .100748652 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.2811186155 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 2271266020 ps |
| CPU time | 71.35 seconds |
| Started | Aug 09 08:07:59 PM PDT 24 |
| Finished | Aug 09 08:09:10 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-653f4983-44b2-4d31-a098-5d9aeb913b33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811186155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2811186155 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.794337173 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 1355738351 ps |
| CPU time | 43.02 seconds |
| Started | Aug 09 08:07:43 PM PDT 24 |
| Finished | Aug 09 08:08:26 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-f7f59cd8-ced4-4d09-903a-ee4731512d81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794337173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.794337173 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1353237314 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 67709996288 ps |
| CPU time | 774.33 seconds |
| Started | Aug 09 08:07:44 PM PDT 24 |
| Finished | Aug 09 08:20:39 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-6b0d717f-e257-46f7-88ab-136e8f892c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353237314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.1353237314 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.3698754759 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 6748122141 ps |
| CPU time | 113.52 seconds |
| Started | Aug 09 08:07:45 PM PDT 24 |
| Finished | Aug 09 08:09:38 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-cfef4bdd-bec4-4218-975e-3176d02f3240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698754759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.3698754759 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.861969801 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 324071347 ps |
| CPU time | 30.51 seconds |
| Started | Aug 09 08:07:42 PM PDT 24 |
| Finished | Aug 09 08:08:13 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-4f838d9e-339d-4f02-8729-d420de8e3a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861969801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_dela ys.861969801 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.3958684297 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 558463075 ps |
| CPU time | 40.56 seconds |
| Started | Aug 09 08:07:50 PM PDT 24 |
| Finished | Aug 09 08:08:31 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-bc8cc300-9b36-470e-9957-1d0d696b33a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958684297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.3958684297 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.1988048612 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 205739271 ps |
| CPU time | 8.97 seconds |
| Started | Aug 09 08:07:43 PM PDT 24 |
| Finished | Aug 09 08:07:52 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-b2cf2a7e-3c1f-42c7-9e77-a31bfc2f7cbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988048612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.1988048612 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.816890818 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 6956541544 ps |
| CPU time | 77.42 seconds |
| Started | Aug 09 08:07:42 PM PDT 24 |
| Finished | Aug 09 08:09:00 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-af208243-f086-42f5-9af1-663432abf3d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816890818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.816890818 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3165157793 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 4709768163 ps |
| CPU time | 81.21 seconds |
| Started | Aug 09 08:07:41 PM PDT 24 |
| Finished | Aug 09 08:09:02 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-3925d0aa-dac9-4035-ba6e-d163cbc146ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165157793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.3165157793 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1273785575 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 43881198 ps |
| CPU time | 5.97 seconds |
| Started | Aug 09 08:07:44 PM PDT 24 |
| Finished | Aug 09 08:07:50 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-8e7f8d01-fefc-48df-afa5-d90ccc8833f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273785575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.1273785575 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.4014931656 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 6532815926 ps |
| CPU time | 223.26 seconds |
| Started | Aug 09 08:07:48 PM PDT 24 |
| Finished | Aug 09 08:11:32 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-f1080b50-4f53-4bd3-af9b-b5c097180bad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014931656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.4014931656 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2766455563 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 1348903282 ps |
| CPU time | 90.64 seconds |
| Started | Aug 09 08:07:59 PM PDT 24 |
| Finished | Aug 09 08:09:30 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-d602eec9-36b0-4062-a3fc-8a0626730999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766455563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2766455563 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1879728358 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 1198094118 ps |
| CPU time | 349.4 seconds |
| Started | Aug 09 08:07:49 PM PDT 24 |
| Finished | Aug 09 08:13:39 PM PDT 24 |
| Peak memory | 577060 kb |
| Host | smart-c0c4790d-c936-4631-acd6-9055ec7c63e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879728358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.1879728358 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2923143346 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 273246278 ps |
| CPU time | 105.93 seconds |
| Started | Aug 09 08:07:52 PM PDT 24 |
| Finished | Aug 09 08:09:38 PM PDT 24 |
| Peak memory | 577080 kb |
| Host | smart-093aa101-65f3-4c31-b52f-1e038bda4738 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923143346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.2923143346 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.4212792957 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 177823970 ps |
| CPU time | 19.79 seconds |
| Started | Aug 09 08:07:57 PM PDT 24 |
| Finished | Aug 09 08:08:17 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-1a42ff18-0a98-4da2-958c-9b42a82970f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212792957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.4212792957 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.275964106 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 923071930 ps |
| CPU time | 62.73 seconds |
| Started | Aug 09 08:07:57 PM PDT 24 |
| Finished | Aug 09 08:09:00 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-2095168b-d0dd-413d-a936-77582734b666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275964106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device. 275964106 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.1695175140 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 993089870 ps |
| CPU time | 36.43 seconds |
| Started | Aug 09 08:07:56 PM PDT 24 |
| Finished | Aug 09 08:08:32 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-c6099d49-11e1-4041-a04f-a8c790a7b5ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695175140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.1695175140 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.3539198014 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 89725263 ps |
| CPU time | 9.28 seconds |
| Started | Aug 09 08:07:52 PM PDT 24 |
| Finished | Aug 09 08:08:01 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-2d2482e6-a6b1-4b98-a6e5-df307a94f156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539198014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.3539198014 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.2250939893 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2404036349 ps |
| CPU time | 84.48 seconds |
| Started | Aug 09 08:07:49 PM PDT 24 |
| Finished | Aug 09 08:09:14 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-f19781ab-92ec-477e-b278-9b925f7c8a64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250939893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.2250939893 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.1807400276 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 44256769259 ps |
| CPU time | 498.8 seconds |
| Started | Aug 09 08:07:48 PM PDT 24 |
| Finished | Aug 09 08:16:07 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-8effb91d-d866-4e0a-b283-0f717fd340db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807400276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.1807400276 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.806513541 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 7689399033 ps |
| CPU time | 134.92 seconds |
| Started | Aug 09 08:07:48 PM PDT 24 |
| Finished | Aug 09 08:10:03 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-0827f13e-b365-495e-9d63-7d81f8388b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806513541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.806513541 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.1978919004 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 373587610 ps |
| CPU time | 30.11 seconds |
| Started | Aug 09 08:07:49 PM PDT 24 |
| Finished | Aug 09 08:08:19 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-75b4ca38-260c-4e1a-abe5-edede8223d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978919004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.1978919004 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.472432281 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 2660961323 ps |
| CPU time | 70.71 seconds |
| Started | Aug 09 08:07:51 PM PDT 24 |
| Finished | Aug 09 08:09:02 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-d9bb6fa9-e3cb-435b-80d3-d2ad6f5811dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472432281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.472432281 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.3660742274 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 46579702 ps |
| CPU time | 7.23 seconds |
| Started | Aug 09 08:07:52 PM PDT 24 |
| Finished | Aug 09 08:07:59 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-22809742-b399-4f5d-a0ff-b635c63566ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660742274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.3660742274 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.1615807638 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 6606043033 ps |
| CPU time | 65.02 seconds |
| Started | Aug 09 08:07:58 PM PDT 24 |
| Finished | Aug 09 08:09:03 PM PDT 24 |
| Peak memory | 574860 kb |
| Host | smart-19ffe381-4ea0-4fb2-a918-a13ebbb141fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615807638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.1615807638 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2190958831 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3795774785 ps |
| CPU time | 62.81 seconds |
| Started | Aug 09 08:07:51 PM PDT 24 |
| Finished | Aug 09 08:08:54 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-dd969bf7-d4ef-4581-9741-c9e410816068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190958831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2190958831 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1697314805 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 54158441 ps |
| CPU time | 7 seconds |
| Started | Aug 09 08:07:53 PM PDT 24 |
| Finished | Aug 09 08:08:00 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-1ab1daa3-df8b-493e-ba4b-e9b1e29c4a0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697314805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.1697314805 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.2482269 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 2908619272 ps |
| CPU time | 239.95 seconds |
| Started | Aug 09 08:07:54 PM PDT 24 |
| Finished | Aug 09 08:11:54 PM PDT 24 |
| Peak memory | 577056 kb |
| Host | smart-2cd5e478-6204-435e-9a69-ce0622bea792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.2482269 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3431048233 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 2167757026 ps |
| CPU time | 74.87 seconds |
| Started | Aug 09 08:07:56 PM PDT 24 |
| Finished | Aug 09 08:09:11 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-730ade38-7716-4c3b-8873-236227d9496f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431048233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.3431048233 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.4192429667 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 741260404 ps |
| CPU time | 221.4 seconds |
| Started | Aug 09 08:07:56 PM PDT 24 |
| Finished | Aug 09 08:11:38 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-aa6e3b1e-c0d5-4484-ac55-90dc4d639c80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192429667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.4192429667 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.1744702439 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 536704195 ps |
| CPU time | 22.42 seconds |
| Started | Aug 09 08:07:55 PM PDT 24 |
| Finished | Aug 09 08:08:18 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-f7e52f97-4999-4fa0-a521-63dba180b0df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744702439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.1744702439 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.2680798335 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 1192415984 ps |
| CPU time | 52.3 seconds |
| Started | Aug 09 08:08:01 PM PDT 24 |
| Finished | Aug 09 08:08:54 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-8d8358cb-5ee3-41a3-a6a1-d77d5f0915d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680798335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .2680798335 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1963450167 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 29680903225 ps |
| CPU time | 508.4 seconds |
| Started | Aug 09 08:08:02 PM PDT 24 |
| Finished | Aug 09 08:16:30 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-4410f01e-b83c-4ccb-a464-b02cadfe873f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963450167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.1963450167 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2212272620 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 628863529 ps |
| CPU time | 24.96 seconds |
| Started | Aug 09 08:08:03 PM PDT 24 |
| Finished | Aug 09 08:08:28 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-214b608f-7ef5-4121-85ad-4885ea07d315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212272620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.2212272620 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.615150452 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 394402610 ps |
| CPU time | 32.28 seconds |
| Started | Aug 09 08:08:02 PM PDT 24 |
| Finished | Aug 09 08:08:34 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-f34473f6-d195-4510-9a3a-e91423c3592d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615150452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.615150452 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.1143978439 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 1182706830 ps |
| CPU time | 38.21 seconds |
| Started | Aug 09 08:08:02 PM PDT 24 |
| Finished | Aug 09 08:08:40 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-820f0434-2f2a-4c92-ab0d-8af6337d6064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143978439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.1143978439 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.1456589323 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 88737001670 ps |
| CPU time | 939.14 seconds |
| Started | Aug 09 08:08:02 PM PDT 24 |
| Finished | Aug 09 08:23:41 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-b53cbdb1-adb8-4abb-b2a8-960fa52ff626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456589323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.1456589323 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.107459855 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 19272027754 ps |
| CPU time | 336.96 seconds |
| Started | Aug 09 08:08:01 PM PDT 24 |
| Finished | Aug 09 08:13:38 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-17e4d2b2-282b-43c7-957a-40976c001375 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107459855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.107459855 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.2901152689 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 132934416 ps |
| CPU time | 14.58 seconds |
| Started | Aug 09 08:08:01 PM PDT 24 |
| Finished | Aug 09 08:08:16 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-f41dd241-1a5b-48b8-8d5c-5aa3ed6c338b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901152689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.2901152689 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.3019750431 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 535360034 ps |
| CPU time | 33.55 seconds |
| Started | Aug 09 08:08:05 PM PDT 24 |
| Finished | Aug 09 08:08:38 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-a9ce0a1a-9aa9-4723-894e-b10acbce6dc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019750431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.3019750431 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.1582772294 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 213828249 ps |
| CPU time | 9.45 seconds |
| Started | Aug 09 08:07:55 PM PDT 24 |
| Finished | Aug 09 08:08:05 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-dec60766-bc45-436c-a647-41d3d89208a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582772294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1582772294 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.1918571941 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 8979461200 ps |
| CPU time | 90.01 seconds |
| Started | Aug 09 08:07:58 PM PDT 24 |
| Finished | Aug 09 08:09:28 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-7504b218-0373-4a89-acc1-9c9615d0fe33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918571941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.1918571941 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.673248320 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 5685878104 ps |
| CPU time | 90.2 seconds |
| Started | Aug 09 08:07:59 PM PDT 24 |
| Finished | Aug 09 08:09:29 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-42425c99-9a78-43f2-8f76-9a292736450b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673248320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.673248320 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2202669622 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 42876054 ps |
| CPU time | 6.33 seconds |
| Started | Aug 09 08:07:57 PM PDT 24 |
| Finished | Aug 09 08:08:03 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-0667515b-7d2f-4a3f-ab98-d5ee308a2d43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202669622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.2202669622 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.1958825365 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 13151339708 ps |
| CPU time | 476.32 seconds |
| Started | Aug 09 08:08:02 PM PDT 24 |
| Finished | Aug 09 08:15:58 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-a9577226-c2f2-4a9e-9c81-96e4838562c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958825365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.1958825365 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.381334383 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 2629143328 ps |
| CPU time | 84.71 seconds |
| Started | Aug 09 08:08:05 PM PDT 24 |
| Finished | Aug 09 08:09:30 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-81d1c496-3816-4df9-bf0d-55baf158406d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381334383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.381334383 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.3249465638 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 7456705616 ps |
| CPU time | 323.09 seconds |
| Started | Aug 09 08:08:02 PM PDT 24 |
| Finished | Aug 09 08:13:25 PM PDT 24 |
| Peak memory | 577132 kb |
| Host | smart-69a71e45-50d9-464c-ae6a-b6a3eaba69c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249465638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.3249465638 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.4201980224 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 680640149 ps |
| CPU time | 200.75 seconds |
| Started | Aug 09 08:08:01 PM PDT 24 |
| Finished | Aug 09 08:11:22 PM PDT 24 |
| Peak memory | 577104 kb |
| Host | smart-ecbba936-5e51-420f-bcdd-717f11d30c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201980224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.4201980224 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.3075865038 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 163744574 ps |
| CPU time | 21.72 seconds |
| Started | Aug 09 08:08:01 PM PDT 24 |
| Finished | Aug 09 08:08:23 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-cb0bd511-27ae-4b2f-a321-3eb5e7802d78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075865038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.3075865038 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2915856180 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 33416356934 ps |
| CPU time | 623.18 seconds |
| Started | Aug 09 08:08:05 PM PDT 24 |
| Finished | Aug 09 08:18:29 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-72454cad-9477-4182-ac68-8b64d0c611f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915856180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.2915856180 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2956785464 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 1255546170 ps |
| CPU time | 45.25 seconds |
| Started | Aug 09 08:08:18 PM PDT 24 |
| Finished | Aug 09 08:09:04 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-83c17c53-47c0-4fbc-a3ff-79e1a655f725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956785464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.2956785464 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.894769798 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 585015957 ps |
| CPU time | 54.51 seconds |
| Started | Aug 09 08:08:14 PM PDT 24 |
| Finished | Aug 09 08:09:09 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-71a03ef7-ea57-44b5-97c4-fa101ebb08e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894769798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.894769798 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.1045568737 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 768183899 ps |
| CPU time | 30.12 seconds |
| Started | Aug 09 08:08:07 PM PDT 24 |
| Finished | Aug 09 08:08:38 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-4212e833-3b8d-4be6-a759-29346593245c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045568737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1045568737 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.3062575316 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 50035727685 ps |
| CPU time | 560.59 seconds |
| Started | Aug 09 08:08:12 PM PDT 24 |
| Finished | Aug 09 08:17:32 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-c98f9a41-5ca4-4eaf-9d17-78c287e27f6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062575316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.3062575316 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.1322171913 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 42969363333 ps |
| CPU time | 794.33 seconds |
| Started | Aug 09 08:08:10 PM PDT 24 |
| Finished | Aug 09 08:21:24 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-14cb9d4a-4f83-4b08-b5ea-fbf436aa673b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322171913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.1322171913 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.3090219958 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 169239137 ps |
| CPU time | 19 seconds |
| Started | Aug 09 08:08:10 PM PDT 24 |
| Finished | Aug 09 08:08:29 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-4b940029-3fe7-48b6-a35e-02f363c410dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090219958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.3090219958 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.24013422 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 1968919767 ps |
| CPU time | 53.32 seconds |
| Started | Aug 09 08:08:10 PM PDT 24 |
| Finished | Aug 09 08:09:03 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-f2179198-16e6-4537-8d14-0e1837f6be00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24013422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.24013422 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.3210800509 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 152384445 ps |
| CPU time | 7.71 seconds |
| Started | Aug 09 08:08:03 PM PDT 24 |
| Finished | Aug 09 08:08:11 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-5b28784d-b0a1-4a60-86e1-13b4f4defa23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210800509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.3210800509 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.226774469 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 10152094359 ps |
| CPU time | 112.98 seconds |
| Started | Aug 09 08:08:07 PM PDT 24 |
| Finished | Aug 09 08:10:00 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-0343502b-3019-4b09-8d6a-4150ecd7a41d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226774469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.226774469 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.3447073152 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 4836181193 ps |
| CPU time | 85.71 seconds |
| Started | Aug 09 08:08:10 PM PDT 24 |
| Finished | Aug 09 08:09:36 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-d7a2eaa5-c969-4508-9ab5-8256d36ab3da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447073152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.3447073152 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.4196565880 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 44709128 ps |
| CPU time | 5.83 seconds |
| Started | Aug 09 08:08:07 PM PDT 24 |
| Finished | Aug 09 08:08:13 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-042f318a-c24f-46d5-920b-11ddaf01f6da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196565880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.4196565880 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.3427079232 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 4802030335 ps |
| CPU time | 165.21 seconds |
| Started | Aug 09 08:08:14 PM PDT 24 |
| Finished | Aug 09 08:11:00 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-782cde55-11bd-42ae-a196-2755ddf8fe28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427079232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.3427079232 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.325320983 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 148373853 ps |
| CPU time | 12 seconds |
| Started | Aug 09 08:08:15 PM PDT 24 |
| Finished | Aug 09 08:08:27 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-3195e933-47cf-4715-a21e-2a3476f67a99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325320983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.325320983 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.1592102214 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 3171831478 ps |
| CPU time | 178.7 seconds |
| Started | Aug 09 08:08:19 PM PDT 24 |
| Finished | Aug 09 08:11:18 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-75cca75a-7085-48ec-a232-c7fc7462d67b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592102214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.1592102214 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.4017693763 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 131258647 ps |
| CPU time | 36.6 seconds |
| Started | Aug 09 08:08:15 PM PDT 24 |
| Finished | Aug 09 08:08:52 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-9a8c5836-c817-4216-8bea-96997ac1de93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017693763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.4017693763 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.3456961921 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 222942511 ps |
| CPU time | 25.84 seconds |
| Started | Aug 09 08:08:13 PM PDT 24 |
| Finished | Aug 09 08:08:39 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-d0c8ca8d-93e0-4fa8-b234-06039d83ab46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456961921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.3456961921 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.392380312 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 757689544 ps |
| CPU time | 46.62 seconds |
| Started | Aug 09 08:08:18 PM PDT 24 |
| Finished | Aug 09 08:09:05 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-10589df1-1ee9-4e24-ab28-e8711b1a0f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392380312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device. 392380312 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.3565456545 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 45484606569 ps |
| CPU time | 837.03 seconds |
| Started | Aug 09 08:08:14 PM PDT 24 |
| Finished | Aug 09 08:22:11 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-dcad71ae-f3cf-4802-b4a3-2974a0687269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565456545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.3565456545 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.210814110 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 153946607 ps |
| CPU time | 9.01 seconds |
| Started | Aug 09 08:08:18 PM PDT 24 |
| Finished | Aug 09 08:08:27 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-eaa52d82-18ab-4505-8696-2f1650338fb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210814110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr .210814110 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.4119586805 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 198025401 ps |
| CPU time | 17.58 seconds |
| Started | Aug 09 08:08:21 PM PDT 24 |
| Finished | Aug 09 08:08:39 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-95967587-78e2-4b59-8fb1-ae3277ebec39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119586805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.4119586805 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.634123085 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2335624785 ps |
| CPU time | 87.06 seconds |
| Started | Aug 09 08:08:13 PM PDT 24 |
| Finished | Aug 09 08:09:40 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-c0c9b179-b126-4998-b546-b5a335a4564c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634123085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.634123085 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1185476891 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 18515583794 ps |
| CPU time | 203.29 seconds |
| Started | Aug 09 08:08:18 PM PDT 24 |
| Finished | Aug 09 08:11:42 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-e95bed79-1c27-44b5-b7b3-c5c6263401b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185476891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1185476891 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.3802565253 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 25364210435 ps |
| CPU time | 452.02 seconds |
| Started | Aug 09 08:08:18 PM PDT 24 |
| Finished | Aug 09 08:15:50 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-a5398dcc-3879-42a8-95bc-c21702a8a8ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802565253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.3802565253 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.3657278456 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 290750932 ps |
| CPU time | 28.12 seconds |
| Started | Aug 09 08:08:16 PM PDT 24 |
| Finished | Aug 09 08:08:44 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-f4d7ac66-03d1-4733-b103-216ddf82bea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657278456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.3657278456 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.74115202 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 885889885 ps |
| CPU time | 25.05 seconds |
| Started | Aug 09 08:08:12 PM PDT 24 |
| Finished | Aug 09 08:08:38 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-7fe00b3f-9ac5-4261-a28e-ac9fac2f8fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74115202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.74115202 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.2772436943 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 240278626 ps |
| CPU time | 10.39 seconds |
| Started | Aug 09 08:08:14 PM PDT 24 |
| Finished | Aug 09 08:08:25 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-300e6c2f-a791-4930-a8dd-5a448d1cc6c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772436943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.2772436943 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.3432839101 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 6504848234 ps |
| CPU time | 67.57 seconds |
| Started | Aug 09 08:08:13 PM PDT 24 |
| Finished | Aug 09 08:09:21 PM PDT 24 |
| Peak memory | 574844 kb |
| Host | smart-22c8fbf9-4272-4564-be4d-4c8bd6a84862 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432839101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.3432839101 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.412907927 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 5191697311 ps |
| CPU time | 90.49 seconds |
| Started | Aug 09 08:08:21 PM PDT 24 |
| Finished | Aug 09 08:09:52 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-a2bd3fb9-32b2-44db-bc25-de7838b02a7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412907927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.412907927 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.465875347 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 60714073 ps |
| CPU time | 7.01 seconds |
| Started | Aug 09 08:08:15 PM PDT 24 |
| Finished | Aug 09 08:08:22 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-fa26f8ae-3564-4095-b195-2f97c79fed7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465875347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays .465875347 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.2026592087 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 3462878171 ps |
| CPU time | 266.19 seconds |
| Started | Aug 09 08:08:22 PM PDT 24 |
| Finished | Aug 09 08:12:48 PM PDT 24 |
| Peak memory | 577004 kb |
| Host | smart-3d70f99e-b3d4-41cc-8152-78d754ac9832 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026592087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.2026592087 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1440294460 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 687633975 ps |
| CPU time | 219.62 seconds |
| Started | Aug 09 08:08:22 PM PDT 24 |
| Finished | Aug 09 08:12:02 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-c13b761b-23c2-4a20-8087-fca415ed0c13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440294460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.1440294460 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.2169077716 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 531261344 ps |
| CPU time | 109.44 seconds |
| Started | Aug 09 08:08:20 PM PDT 24 |
| Finished | Aug 09 08:10:10 PM PDT 24 |
| Peak memory | 577044 kb |
| Host | smart-15ed4d03-d323-454d-a507-7f941f1d6e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169077716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.2169077716 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.502370471 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 130155763 ps |
| CPU time | 7.62 seconds |
| Started | Aug 09 08:08:14 PM PDT 24 |
| Finished | Aug 09 08:08:22 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-a7f2dae6-2e90-4b57-bb9c-075b2e10e582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502370471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.502370471 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.2235122098 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 1245701073 ps |
| CPU time | 47.97 seconds |
| Started | Aug 09 08:08:28 PM PDT 24 |
| Finished | Aug 09 08:09:16 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-a47ec421-c26c-497b-b9f6-1f03681864ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235122098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .2235122098 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.4191068146 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 49942251026 ps |
| CPU time | 890.75 seconds |
| Started | Aug 09 08:08:31 PM PDT 24 |
| Finished | Aug 09 08:23:22 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-784323a9-bfca-4a9e-8ee3-b95de7b12378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191068146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.4191068146 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3786233677 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 88250494 ps |
| CPU time | 11.31 seconds |
| Started | Aug 09 08:08:27 PM PDT 24 |
| Finished | Aug 09 08:08:38 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-60fada2d-da6f-4980-a678-c23dad4eb49a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786233677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.3786233677 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.115516121 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 688772222 ps |
| CPU time | 25.99 seconds |
| Started | Aug 09 08:08:27 PM PDT 24 |
| Finished | Aug 09 08:08:53 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-775de4fc-00d0-476d-aa27-23507738e7b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115516121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.115516121 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.788963614 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 812314760 ps |
| CPU time | 28.76 seconds |
| Started | Aug 09 08:08:22 PM PDT 24 |
| Finished | Aug 09 08:08:51 PM PDT 24 |
| Peak memory | 576392 kb |
| Host | smart-3c689724-d9b4-4798-b5fb-26aed2febe6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788963614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.788963614 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.4288002844 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 13506341174 ps |
| CPU time | 144.14 seconds |
| Started | Aug 09 08:08:22 PM PDT 24 |
| Finished | Aug 09 08:10:46 PM PDT 24 |
| Peak memory | 577052 kb |
| Host | smart-95d500bb-bd29-4906-becd-74fc0db6dfab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288002844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.4288002844 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3919307779 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 61967781017 ps |
| CPU time | 1084.08 seconds |
| Started | Aug 09 08:08:31 PM PDT 24 |
| Finished | Aug 09 08:26:35 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-cc1db6be-5a5a-442d-87dc-014b85ac2de3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919307779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3919307779 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.3487987576 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 200251842 ps |
| CPU time | 19.38 seconds |
| Started | Aug 09 08:08:25 PM PDT 24 |
| Finished | Aug 09 08:08:45 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-d32681fc-0acb-4183-92a5-56091c71421a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487987576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.3487987576 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.3815601312 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 311783830 ps |
| CPU time | 27.2 seconds |
| Started | Aug 09 08:08:29 PM PDT 24 |
| Finished | Aug 09 08:08:56 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-00d7828c-8449-42f7-a4e1-7eab7d76f1c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815601312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3815601312 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.3902864543 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 43668825 ps |
| CPU time | 6.65 seconds |
| Started | Aug 09 08:08:21 PM PDT 24 |
| Finished | Aug 09 08:08:28 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-93cc43d7-dd35-43a1-8b54-93f77ed4b653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902864543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.3902864543 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.1637924039 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 10936578226 ps |
| CPU time | 113.68 seconds |
| Started | Aug 09 08:08:20 PM PDT 24 |
| Finished | Aug 09 08:10:14 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-0c82e1a0-796a-42bc-ae99-a92ee87a0460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637924039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.1637924039 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.4289261078 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 3795024776 ps |
| CPU time | 62.46 seconds |
| Started | Aug 09 08:08:26 PM PDT 24 |
| Finished | Aug 09 08:09:29 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-968cdb61-b9f8-4fa2-a0f5-8091d3d9677f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289261078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.4289261078 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2291485315 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 49570822 ps |
| CPU time | 6.8 seconds |
| Started | Aug 09 08:08:25 PM PDT 24 |
| Finished | Aug 09 08:08:32 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-6acf5da2-e557-4392-a63e-1336f1c9d8bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291485315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2291485315 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.998189138 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 8867869386 ps |
| CPU time | 282.18 seconds |
| Started | Aug 09 08:08:29 PM PDT 24 |
| Finished | Aug 09 08:13:12 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-0bc7cacd-8511-4030-a517-8954e31e9565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998189138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.998189138 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1314130169 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 1860496498 ps |
| CPU time | 120.78 seconds |
| Started | Aug 09 08:08:30 PM PDT 24 |
| Finished | Aug 09 08:10:31 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-487973fc-4369-4e6b-9a09-341df8fd0210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314130169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1314130169 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3475765096 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 10158499499 ps |
| CPU time | 579.22 seconds |
| Started | Aug 09 08:08:30 PM PDT 24 |
| Finished | Aug 09 08:18:09 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-c96c1f26-d121-45ab-b445-07e80a89f02a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475765096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.3475765096 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.487596145 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 1260382344 ps |
| CPU time | 47.12 seconds |
| Started | Aug 09 08:08:29 PM PDT 24 |
| Finished | Aug 09 08:09:16 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-d21ec847-5c57-4b33-80f5-4c64bfd8c873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487596145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.487596145 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.1742786883 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 701693328 ps |
| CPU time | 60.17 seconds |
| Started | Aug 09 08:08:33 PM PDT 24 |
| Finished | Aug 09 08:09:33 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-5bbbf7db-7331-49ec-bc2a-57ba012c80a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742786883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .1742786883 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3417296439 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 137268786638 ps |
| CPU time | 2561.78 seconds |
| Started | Aug 09 08:08:33 PM PDT 24 |
| Finished | Aug 09 08:51:16 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-9a30ad36-63ed-425b-8726-3b6c432678c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417296439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.3417296439 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2342300411 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 99472111 ps |
| CPU time | 11.06 seconds |
| Started | Aug 09 08:08:38 PM PDT 24 |
| Finished | Aug 09 08:08:49 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-f0eb4761-065f-4abe-924a-7c3a6bdb4787 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342300411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.2342300411 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.3532965442 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2087780106 ps |
| CPU time | 71.9 seconds |
| Started | Aug 09 08:08:37 PM PDT 24 |
| Finished | Aug 09 08:09:49 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-00c7d415-6ec8-40a0-9a43-25543b587e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532965442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3532965442 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.228094365 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 2691706528 ps |
| CPU time | 103.97 seconds |
| Started | Aug 09 08:08:34 PM PDT 24 |
| Finished | Aug 09 08:10:18 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-58137b85-7bbe-41d5-b0b7-4764a1aae7e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228094365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.228094365 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3311721357 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 102178928131 ps |
| CPU time | 1021.94 seconds |
| Started | Aug 09 08:08:37 PM PDT 24 |
| Finished | Aug 09 08:25:39 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-2460a962-eb5d-4f52-ab64-9bed22ad3a16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311721357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3311721357 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.2765603633 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 25372055735 ps |
| CPU time | 431.52 seconds |
| Started | Aug 09 08:08:37 PM PDT 24 |
| Finished | Aug 09 08:15:49 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-961d4cdf-460a-425c-98b3-181b05148f38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765603633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.2765603633 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.2803355285 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 84904276 ps |
| CPU time | 10.36 seconds |
| Started | Aug 09 08:08:35 PM PDT 24 |
| Finished | Aug 09 08:08:46 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-6d6a91f8-2432-4370-9f3a-39b2cd8dc754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803355285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.2803355285 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.4106150539 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 163275382 ps |
| CPU time | 14.08 seconds |
| Started | Aug 09 08:08:37 PM PDT 24 |
| Finished | Aug 09 08:08:51 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-274b96ff-af28-4890-84df-73753a7e0b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106150539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.4106150539 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.638988686 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 54489131 ps |
| CPU time | 6.46 seconds |
| Started | Aug 09 08:08:29 PM PDT 24 |
| Finished | Aug 09 08:08:36 PM PDT 24 |
| Peak memory | 574800 kb |
| Host | smart-9d9cd542-ca1b-4463-ae60-9486410ad968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638988686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.638988686 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.2585857250 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 6420616155 ps |
| CPU time | 70.96 seconds |
| Started | Aug 09 08:08:27 PM PDT 24 |
| Finished | Aug 09 08:09:38 PM PDT 24 |
| Peak memory | 574924 kb |
| Host | smart-46b8394c-9960-4e09-a22e-15ca15969cf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585857250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.2585857250 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3048309920 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 4064754350 ps |
| CPU time | 69.36 seconds |
| Started | Aug 09 08:08:37 PM PDT 24 |
| Finished | Aug 09 08:09:46 PM PDT 24 |
| Peak memory | 574920 kb |
| Host | smart-943ca8e0-57f3-499b-b660-db2920295e4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048309920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.3048309920 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.386054012 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 55837098 ps |
| CPU time | 6.57 seconds |
| Started | Aug 09 08:08:31 PM PDT 24 |
| Finished | Aug 09 08:08:38 PM PDT 24 |
| Peak memory | 574792 kb |
| Host | smart-3aafcd2f-95dc-48f8-82a7-cf19fc318546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386054012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays .386054012 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.2875123840 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 12906224330 ps |
| CPU time | 449.83 seconds |
| Started | Aug 09 08:08:35 PM PDT 24 |
| Finished | Aug 09 08:16:05 PM PDT 24 |
| Peak memory | 577092 kb |
| Host | smart-e2f3ab52-78a1-41f8-84e0-8f1ca3c39008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875123840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.2875123840 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.3816909258 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 3304940966 ps |
| CPU time | 111.75 seconds |
| Started | Aug 09 08:08:34 PM PDT 24 |
| Finished | Aug 09 08:10:25 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-723f5d7c-9b0d-4a76-b064-f60f49e2ffda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816909258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3816909258 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.1685897463 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 105537700 ps |
| CPU time | 29.9 seconds |
| Started | Aug 09 08:08:35 PM PDT 24 |
| Finished | Aug 09 08:09:04 PM PDT 24 |
| Peak memory | 575028 kb |
| Host | smart-cf5116b0-edb9-4b0f-875b-521160a47583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685897463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.1685897463 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3554851213 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 2066754646 ps |
| CPU time | 133.49 seconds |
| Started | Aug 09 08:08:33 PM PDT 24 |
| Finished | Aug 09 08:10:47 PM PDT 24 |
| Peak memory | 577092 kb |
| Host | smart-416ed285-15d4-458a-815a-d2b142294fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554851213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.3554851213 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.112598882 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 65233712 ps |
| CPU time | 10.25 seconds |
| Started | Aug 09 08:08:38 PM PDT 24 |
| Finished | Aug 09 08:08:49 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-ef1ee96d-1f3a-4523-9a70-1bb5325fb776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112598882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.112598882 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.3801777168 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 354008327 ps |
| CPU time | 24.49 seconds |
| Started | Aug 09 08:08:45 PM PDT 24 |
| Finished | Aug 09 08:09:09 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-d1ad31a9-134f-43f4-82db-c1f8547eebec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801777168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .3801777168 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3071242184 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 123763756477 ps |
| CPU time | 2367.29 seconds |
| Started | Aug 09 08:08:40 PM PDT 24 |
| Finished | Aug 09 08:48:08 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-cf020cb1-8d85-4c98-98d8-0bdc08de1ac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071242184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.3071242184 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.790604311 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 156677356 ps |
| CPU time | 18.12 seconds |
| Started | Aug 09 08:08:49 PM PDT 24 |
| Finished | Aug 09 08:09:07 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-31b8e42b-2266-41b3-b1f4-2d447a1764d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790604311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr .790604311 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.1911506171 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 2399771764 ps |
| CPU time | 86.66 seconds |
| Started | Aug 09 08:08:40 PM PDT 24 |
| Finished | Aug 09 08:10:06 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-45ef27f3-e432-41bb-94ee-ced89eab0056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911506171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.1911506171 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.3621645453 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 552615512 ps |
| CPU time | 42.57 seconds |
| Started | Aug 09 08:08:40 PM PDT 24 |
| Finished | Aug 09 08:09:22 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-6f2eea87-cc1e-42ab-a889-e8325d6bedf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621645453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3621645453 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.2071125836 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 86672759098 ps |
| CPU time | 1017.48 seconds |
| Started | Aug 09 08:08:42 PM PDT 24 |
| Finished | Aug 09 08:25:41 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-ee56e191-447b-474e-8ca8-e9a17d7b641b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071125836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.2071125836 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.3702002051 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 65734201565 ps |
| CPU time | 1209.69 seconds |
| Started | Aug 09 08:08:42 PM PDT 24 |
| Finished | Aug 09 08:28:52 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-39cd5af5-7b95-4806-b99d-8a2af7e4e47f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702002051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.3702002051 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3294229609 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 72602859 ps |
| CPU time | 9.58 seconds |
| Started | Aug 09 08:08:45 PM PDT 24 |
| Finished | Aug 09 08:08:54 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-0591234b-b0cf-440c-9667-5473b85cc296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294229609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.3294229609 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.1029926219 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2485448752 ps |
| CPU time | 75.2 seconds |
| Started | Aug 09 08:08:41 PM PDT 24 |
| Finished | Aug 09 08:09:56 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-95153706-612d-4dd5-820a-05ad66ed60d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029926219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.1029926219 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.3472958149 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 193184393 ps |
| CPU time | 8.69 seconds |
| Started | Aug 09 08:08:38 PM PDT 24 |
| Finished | Aug 09 08:08:47 PM PDT 24 |
| Peak memory | 574760 kb |
| Host | smart-d65fdd93-c9c1-453a-8df2-73dcbb0be3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472958149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3472958149 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.1332878977 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 7282705270 ps |
| CPU time | 73.84 seconds |
| Started | Aug 09 08:08:34 PM PDT 24 |
| Finished | Aug 09 08:09:48 PM PDT 24 |
| Peak memory | 574900 kb |
| Host | smart-d96e68f1-effa-42fa-a6b1-f6d14fef0b2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332878977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.1332878977 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.742448692 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 6083898317 ps |
| CPU time | 101.8 seconds |
| Started | Aug 09 08:08:41 PM PDT 24 |
| Finished | Aug 09 08:10:23 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-ba9f98a7-0a84-4a73-a854-701a4ac9bfc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742448692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.742448692 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.3215611362 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 49879915 ps |
| CPU time | 6.54 seconds |
| Started | Aug 09 08:08:34 PM PDT 24 |
| Finished | Aug 09 08:08:41 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-294ec5e2-ac45-4047-95e6-fc53cb534e7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215611362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.3215611362 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.2370937170 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 14753623638 ps |
| CPU time | 639.19 seconds |
| Started | Aug 09 08:08:47 PM PDT 24 |
| Finished | Aug 09 08:19:27 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-55845294-9725-4d55-8590-2f4086b4c651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370937170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.2370937170 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1940489139 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 192179720 ps |
| CPU time | 87.75 seconds |
| Started | Aug 09 08:08:48 PM PDT 24 |
| Finished | Aug 09 08:10:16 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-fae14dec-b2d2-4c36-add9-9ee71ef6bc13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940489139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.1940489139 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1022537057 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 2107036250 ps |
| CPU time | 356.77 seconds |
| Started | Aug 09 08:08:47 PM PDT 24 |
| Finished | Aug 09 08:14:44 PM PDT 24 |
| Peak memory | 577064 kb |
| Host | smart-edbb2c6d-4f26-44d6-aaa8-38e2d5e04183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022537057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.1022537057 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1289170811 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 1067297703 ps |
| CPU time | 41.77 seconds |
| Started | Aug 09 08:08:49 PM PDT 24 |
| Finished | Aug 09 08:09:31 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-7a9bbb31-a821-493c-ac9f-6f29b33a157a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289170811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1289170811 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.2146588644 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 2227105250 ps |
| CPU time | 103.47 seconds |
| Started | Aug 09 08:08:49 PM PDT 24 |
| Finished | Aug 09 08:10:33 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-a6bbdb19-0aa6-4ff6-b52b-a3d608e084a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146588644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .2146588644 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3389005814 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 68045393587 ps |
| CPU time | 1199.82 seconds |
| Started | Aug 09 08:08:49 PM PDT 24 |
| Finished | Aug 09 08:28:49 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-3fd3d391-e127-493c-a60a-80108b725bb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389005814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.3389005814 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3514824432 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 255773115 ps |
| CPU time | 26.38 seconds |
| Started | Aug 09 08:08:54 PM PDT 24 |
| Finished | Aug 09 08:09:20 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-63d4a15c-52bb-4af6-b6a8-8286a2595074 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514824432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.3514824432 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.829102844 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 1560195341 ps |
| CPU time | 51.56 seconds |
| Started | Aug 09 08:08:46 PM PDT 24 |
| Finished | Aug 09 08:09:37 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-5c8f9b2e-2be3-44e4-8c97-41c200aad934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829102844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.829102844 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.2487442735 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 398497798 ps |
| CPU time | 32.34 seconds |
| Started | Aug 09 08:08:49 PM PDT 24 |
| Finished | Aug 09 08:09:22 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-a22653ce-17aa-426f-beb6-b7c491a10a58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487442735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.2487442735 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.2012195592 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 69631075350 ps |
| CPU time | 796.13 seconds |
| Started | Aug 09 08:08:48 PM PDT 24 |
| Finished | Aug 09 08:22:04 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-3012a98b-83c9-4f5f-8e80-04693893eae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012195592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.2012195592 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.3445187367 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 64331896751 ps |
| CPU time | 1119.67 seconds |
| Started | Aug 09 08:08:48 PM PDT 24 |
| Finished | Aug 09 08:27:28 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-a501dc05-0803-4cb4-8c0e-dfe969af4c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445187367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.3445187367 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.3995129013 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 405874218 ps |
| CPU time | 35.72 seconds |
| Started | Aug 09 08:08:51 PM PDT 24 |
| Finished | Aug 09 08:09:27 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-759f074f-2007-4e90-a755-26a97361d36a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995129013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.3995129013 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.2035258623 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 1176541844 ps |
| CPU time | 34.07 seconds |
| Started | Aug 09 08:08:49 PM PDT 24 |
| Finished | Aug 09 08:09:24 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-a1ff6bf1-c5ef-487a-b878-1d4f9a9ac73c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035258623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.2035258623 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.650475670 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 46177751 ps |
| CPU time | 6.55 seconds |
| Started | Aug 09 08:08:46 PM PDT 24 |
| Finished | Aug 09 08:08:53 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-897d2384-2a54-42ab-9703-e8a54261b094 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650475670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.650475670 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2349883858 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 6452227633 ps |
| CPU time | 66.21 seconds |
| Started | Aug 09 08:08:47 PM PDT 24 |
| Finished | Aug 09 08:09:53 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-437f01d5-b031-464d-9f11-ae71550a6208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349883858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.2349883858 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.2342625850 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 4011856214 ps |
| CPU time | 70.33 seconds |
| Started | Aug 09 08:08:46 PM PDT 24 |
| Finished | Aug 09 08:09:57 PM PDT 24 |
| Peak memory | 574884 kb |
| Host | smart-043f3311-31d5-4d3c-bf0c-cfd46df86e82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342625850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.2342625850 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.3387039645 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 50649228 ps |
| CPU time | 6.44 seconds |
| Started | Aug 09 08:08:47 PM PDT 24 |
| Finished | Aug 09 08:08:54 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-803c979b-528c-4950-914e-f1acf8842f12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387039645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.3387039645 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.2037889152 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 4543280625 ps |
| CPU time | 188.44 seconds |
| Started | Aug 09 08:08:55 PM PDT 24 |
| Finished | Aug 09 08:12:04 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-32fcc00e-6e78-491c-b571-b528dec593d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037889152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2037889152 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.3320850057 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 3327007544 ps |
| CPU time | 122.29 seconds |
| Started | Aug 09 08:08:53 PM PDT 24 |
| Finished | Aug 09 08:10:55 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-89159798-5d9e-4a0e-88d6-2233d6693139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320850057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.3320850057 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3711355030 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 4275411742 ps |
| CPU time | 172.53 seconds |
| Started | Aug 09 08:08:57 PM PDT 24 |
| Finished | Aug 09 08:11:50 PM PDT 24 |
| Peak memory | 576908 kb |
| Host | smart-fbfe8815-7ec2-4081-8d40-55e557770a65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711355030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.3711355030 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.945474453 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 1980149518 ps |
| CPU time | 311.48 seconds |
| Started | Aug 09 08:08:57 PM PDT 24 |
| Finished | Aug 09 08:14:09 PM PDT 24 |
| Peak memory | 577104 kb |
| Host | smart-a2dccf82-a9b5-47b3-8f3e-9f695b4a6435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945474453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_reset_error.945474453 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.2788570024 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 260918503 ps |
| CPU time | 29.23 seconds |
| Started | Aug 09 08:08:47 PM PDT 24 |
| Finished | Aug 09 08:09:16 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-d4275677-4b15-4c4a-a34d-f4ed75d0a6eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788570024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.2788570024 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2509203092 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 3519035798 ps |
| CPU time | 138.52 seconds |
| Started | Aug 09 08:08:54 PM PDT 24 |
| Finished | Aug 09 08:11:12 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-9c05efd5-cc42-4ef4-99ee-2a8ebba0ad1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509203092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .2509203092 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2757461561 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 62454850576 ps |
| CPU time | 1128.73 seconds |
| Started | Aug 09 08:08:57 PM PDT 24 |
| Finished | Aug 09 08:27:46 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-02c38a66-5360-47b8-8acf-704291d79049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757461561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.2757461561 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.4027399300 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 1071477911 ps |
| CPU time | 40.05 seconds |
| Started | Aug 09 08:08:55 PM PDT 24 |
| Finished | Aug 09 08:09:35 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-da4d26f5-16f1-47be-b9de-dcc237bb1795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027399300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.4027399300 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.3293940723 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 1794343826 ps |
| CPU time | 62.92 seconds |
| Started | Aug 09 08:08:59 PM PDT 24 |
| Finished | Aug 09 08:10:02 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-ada705de-1d86-4367-860c-fea0d6d7b745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293940723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.3293940723 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.3059225518 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2337675395 ps |
| CPU time | 77.35 seconds |
| Started | Aug 09 08:08:55 PM PDT 24 |
| Finished | Aug 09 08:10:12 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-a5da184e-d8c3-49dc-a528-f0d278ce7242 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059225518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3059225518 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.838229413 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 83426371006 ps |
| CPU time | 1002.59 seconds |
| Started | Aug 09 08:08:53 PM PDT 24 |
| Finished | Aug 09 08:25:36 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-f9c8d5e3-37b2-49de-9e10-c148c01f14e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838229413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.838229413 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.1325364390 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 45431045118 ps |
| CPU time | 870.87 seconds |
| Started | Aug 09 08:08:54 PM PDT 24 |
| Finished | Aug 09 08:23:25 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-8fa3d212-90a5-4d31-be95-2998dfc7fd14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325364390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.1325364390 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.658545611 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 244170475 ps |
| CPU time | 23.22 seconds |
| Started | Aug 09 08:08:58 PM PDT 24 |
| Finished | Aug 09 08:09:21 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-fda25672-40b9-4c71-9baa-a9c7f2208b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658545611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_dela ys.658545611 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.2971294131 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 1808778431 ps |
| CPU time | 48.5 seconds |
| Started | Aug 09 08:08:58 PM PDT 24 |
| Finished | Aug 09 08:09:47 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-8322746c-6717-47de-bd57-922aa42ebd54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971294131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.2971294131 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.3979520027 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 198172858 ps |
| CPU time | 8.83 seconds |
| Started | Aug 09 08:08:54 PM PDT 24 |
| Finished | Aug 09 08:09:03 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-4d7b1ccc-a9a9-49cf-9c31-6e6636c57110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979520027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.3979520027 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3928359414 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 7961588564 ps |
| CPU time | 81.87 seconds |
| Started | Aug 09 08:08:53 PM PDT 24 |
| Finished | Aug 09 08:10:15 PM PDT 24 |
| Peak memory | 574932 kb |
| Host | smart-1cb72405-8a16-46f9-9230-653d184338fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928359414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.3928359414 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.179743102 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 6047939664 ps |
| CPU time | 102.03 seconds |
| Started | Aug 09 08:08:59 PM PDT 24 |
| Finished | Aug 09 08:10:41 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-0d00b4eb-c28e-4893-9f8b-ec02a2858709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179743102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.179743102 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2987645003 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 41820524 ps |
| CPU time | 5.78 seconds |
| Started | Aug 09 08:08:55 PM PDT 24 |
| Finished | Aug 09 08:09:01 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-4a02dbd6-311d-4f49-8093-b7ba8bcb58ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987645003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.2987645003 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.2005098337 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 3259549367 ps |
| CPU time | 227.13 seconds |
| Started | Aug 09 08:08:53 PM PDT 24 |
| Finished | Aug 09 08:12:40 PM PDT 24 |
| Peak memory | 577084 kb |
| Host | smart-9947c254-5539-4963-b168-4dc5307138f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005098337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2005098337 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.306525285 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 3432180688 ps |
| CPU time | 212.89 seconds |
| Started | Aug 09 08:09:02 PM PDT 24 |
| Finished | Aug 09 08:12:35 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-643e3ba3-757a-4945-bc98-d3e60f43c5e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306525285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.306525285 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.592306753 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 5833625517 ps |
| CPU time | 444.53 seconds |
| Started | Aug 09 08:09:01 PM PDT 24 |
| Finished | Aug 09 08:16:25 PM PDT 24 |
| Peak memory | 577160 kb |
| Host | smart-d4849d4b-e280-462b-937c-8f650003b531 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592306753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_ with_rand_reset.592306753 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.896313621 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 742637875 ps |
| CPU time | 305.33 seconds |
| Started | Aug 09 08:09:00 PM PDT 24 |
| Finished | Aug 09 08:14:06 PM PDT 24 |
| Peak memory | 577120 kb |
| Host | smart-21c8a20a-dfe5-4f4a-82c5-19558b553de5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896313621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_reset_error.896313621 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.2126930511 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 191979743 ps |
| CPU time | 23.71 seconds |
| Started | Aug 09 08:08:59 PM PDT 24 |
| Finished | Aug 09 08:09:23 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-cf58daea-87ff-4d84-82ef-91aa7d0174e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126930511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.2126930511 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.4079620836 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 6531432904 ps |
| CPU time | 459.89 seconds |
| Started | Aug 09 07:58:12 PM PDT 24 |
| Finished | Aug 09 08:05:52 PM PDT 24 |
| Peak memory | 637584 kb |
| Host | smart-ad13146a-e00e-4025-b0bd-3e6cf0ec5733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079620836 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.4079620836 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.3026742522 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 5723704040 ps |
| CPU time | 565.9 seconds |
| Started | Aug 09 07:58:04 PM PDT 24 |
| Finished | Aug 09 08:07:30 PM PDT 24 |
| Peak memory | 598700 kb |
| Host | smart-d6ba6d5f-5f60-4173-b6d6-ce5b171d017a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026742522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.3026742522 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.4012793221 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 29676294019 ps |
| CPU time | 3528.92 seconds |
| Started | Aug 09 07:57:58 PM PDT 24 |
| Finished | Aug 09 08:56:47 PM PDT 24 |
| Peak memory | 594016 kb |
| Host | smart-f40a23ca-3cb7-4f77-87b7-c46284f055ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012793221 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.4012793221 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.770255314 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 4033488740 ps |
| CPU time | 287.95 seconds |
| Started | Aug 09 07:58:05 PM PDT 24 |
| Finished | Aug 09 08:02:53 PM PDT 24 |
| Peak memory | 604000 kb |
| Host | smart-3315eb19-7832-44e1-b6c4-d7836e8955ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770255314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.770255314 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.3288873060 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 337955479 ps |
| CPU time | 24.82 seconds |
| Started | Aug 09 07:58:12 PM PDT 24 |
| Finished | Aug 09 07:58:37 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-57f8af19-c939-4c7d-9d20-c37f070b4832 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288873060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 3288873060 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3830577923 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 140907273 ps |
| CPU time | 16.27 seconds |
| Started | Aug 09 07:58:09 PM PDT 24 |
| Finished | Aug 09 07:58:26 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-42fe814f-4377-4953-87a0-72139b27d596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830577923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .3830577923 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.1883354295 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 345031094 ps |
| CPU time | 27.41 seconds |
| Started | Aug 09 07:58:26 PM PDT 24 |
| Finished | Aug 09 07:58:53 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-bd835d0a-4c35-428e-a825-ccecc7ce82ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883354295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1883354295 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.1122785499 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 1609650463 ps |
| CPU time | 61.72 seconds |
| Started | Aug 09 07:58:10 PM PDT 24 |
| Finished | Aug 09 07:59:11 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-2a8e444a-c2a1-4917-aab2-9adb0618c49e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122785499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.1122785499 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.411741530 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 59643887759 ps |
| CPU time | 644.59 seconds |
| Started | Aug 09 07:58:13 PM PDT 24 |
| Finished | Aug 09 08:08:58 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-ac76405b-ed95-4c9f-9de7-c59a0c5e0fd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411741530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.411741530 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.969655039 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 46762450701 ps |
| CPU time | 795.1 seconds |
| Started | Aug 09 07:58:12 PM PDT 24 |
| Finished | Aug 09 08:11:27 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-d472a7ef-6a38-425e-a0f9-927c8b4b4025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969655039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.969655039 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.2014493357 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 541982448 ps |
| CPU time | 42.42 seconds |
| Started | Aug 09 07:58:26 PM PDT 24 |
| Finished | Aug 09 07:59:09 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-efe473bf-2c83-4f46-b522-0f5ed49d3af4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014493357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.2014493357 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.2889831822 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 411711809 ps |
| CPU time | 27.57 seconds |
| Started | Aug 09 07:58:04 PM PDT 24 |
| Finished | Aug 09 07:58:32 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-f2575db2-4162-47d2-b801-c4f5bc2bc1c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889831822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2889831822 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.587305939 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 188016280 ps |
| CPU time | 7.74 seconds |
| Started | Aug 09 07:58:03 PM PDT 24 |
| Finished | Aug 09 07:58:10 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-83380384-aa16-41c7-8b7b-bc0df01e70b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587305939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.587305939 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.3472916019 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 8268434501 ps |
| CPU time | 79.26 seconds |
| Started | Aug 09 07:57:58 PM PDT 24 |
| Finished | Aug 09 07:59:17 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-ea4493c6-d588-419a-966a-04a2abc10e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472916019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3472916019 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.4165613469 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 4023242134 ps |
| CPU time | 60.92 seconds |
| Started | Aug 09 07:58:05 PM PDT 24 |
| Finished | Aug 09 07:59:06 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-5d637f14-fd98-4721-a640-bac9fe5f848f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165613469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.4165613469 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3472655923 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 51906584 ps |
| CPU time | 6.56 seconds |
| Started | Aug 09 07:57:57 PM PDT 24 |
| Finished | Aug 09 07:58:04 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-0e3ec505-b374-4639-b2b7-3ac7e864b573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472655923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .3472655923 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.386364249 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 5883321384 ps |
| CPU time | 200.43 seconds |
| Started | Aug 09 07:58:11 PM PDT 24 |
| Finished | Aug 09 08:01:32 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-33ef1b6c-b000-4117-96bf-dbb6afc6314c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386364249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.386364249 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.326951757 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 390221462 ps |
| CPU time | 131.74 seconds |
| Started | Aug 09 07:58:07 PM PDT 24 |
| Finished | Aug 09 08:00:19 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-a6fb4415-bc68-40db-b63a-be7eb3d07ae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326951757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_w ith_rand_reset.326951757 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1570295568 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 2507697888 ps |
| CPU time | 109.42 seconds |
| Started | Aug 09 07:58:11 PM PDT 24 |
| Finished | Aug 09 08:00:01 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-504042d1-5873-4093-82cb-fc8d8ade117c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570295568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.1570295568 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.90673378 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 348674293 ps |
| CPU time | 17.13 seconds |
| Started | Aug 09 07:58:07 PM PDT 24 |
| Finished | Aug 09 07:58:24 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-bc97d168-8770-433d-aecc-600ac095d4fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90673378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.90673378 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.1643503107 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 93374013 ps |
| CPU time | 9.07 seconds |
| Started | Aug 09 08:09:00 PM PDT 24 |
| Finished | Aug 09 08:09:10 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-a977bc7d-56bf-405c-9ad9-310ef3027fbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643503107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .1643503107 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3684931180 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 93626145732 ps |
| CPU time | 1661.31 seconds |
| Started | Aug 09 08:09:06 PM PDT 24 |
| Finished | Aug 09 08:36:47 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-7e36b705-d6ed-4c45-8933-4b5ae1e24e21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684931180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.3684931180 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.1145182597 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 257023763 ps |
| CPU time | 27.13 seconds |
| Started | Aug 09 08:09:07 PM PDT 24 |
| Finished | Aug 09 08:09:34 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-eb552541-6f04-459a-a33f-d0e99f493d75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145182597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.1145182597 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.3544313977 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 511118257 ps |
| CPU time | 38.3 seconds |
| Started | Aug 09 08:09:08 PM PDT 24 |
| Finished | Aug 09 08:09:46 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-8ffcee35-0bb4-43f2-b93b-e6cb36f2eef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544313977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.3544313977 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.1019603169 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 138678922 ps |
| CPU time | 7.9 seconds |
| Started | Aug 09 08:09:00 PM PDT 24 |
| Finished | Aug 09 08:09:08 PM PDT 24 |
| Peak memory | 574812 kb |
| Host | smart-48578428-1417-4e92-9742-08bf593ba058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019603169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.1019603169 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2529373247 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 82984080912 ps |
| CPU time | 888.33 seconds |
| Started | Aug 09 08:09:00 PM PDT 24 |
| Finished | Aug 09 08:23:49 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-f8e7fc57-877b-4f02-9ba6-6909924172d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529373247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2529373247 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2837795743 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 54857179766 ps |
| CPU time | 996.22 seconds |
| Started | Aug 09 08:09:01 PM PDT 24 |
| Finished | Aug 09 08:25:38 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-709746c7-58d3-4037-8c4d-6eca489eb7cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837795743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2837795743 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.2991714567 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 441818562 ps |
| CPU time | 35.07 seconds |
| Started | Aug 09 08:09:02 PM PDT 24 |
| Finished | Aug 09 08:09:37 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-c403f120-8a35-419b-972a-cd8021788e0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991714567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.2991714567 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.739729192 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 1519324854 ps |
| CPU time | 44.21 seconds |
| Started | Aug 09 08:09:08 PM PDT 24 |
| Finished | Aug 09 08:09:52 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-9e76c082-96c3-48ff-9a48-5a194abfb201 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739729192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.739729192 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.851761519 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 37616301 ps |
| CPU time | 5.77 seconds |
| Started | Aug 09 08:09:02 PM PDT 24 |
| Finished | Aug 09 08:09:08 PM PDT 24 |
| Peak memory | 574808 kb |
| Host | smart-2ee1d528-ca0b-4265-ad8b-0edc6836c4e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851761519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.851761519 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.403223542 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 6619731731 ps |
| CPU time | 67.19 seconds |
| Started | Aug 09 08:09:04 PM PDT 24 |
| Finished | Aug 09 08:10:12 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-59270e27-f37d-49e3-bc6f-23aa4bb283f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403223542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.403223542 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3877953423 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 5150121449 ps |
| CPU time | 86.82 seconds |
| Started | Aug 09 08:09:00 PM PDT 24 |
| Finished | Aug 09 08:10:27 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-8dda0d55-a32e-45c6-933a-ff97d01ad6af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877953423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.3877953423 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.991234710 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 48862522 ps |
| CPU time | 5.79 seconds |
| Started | Aug 09 08:09:03 PM PDT 24 |
| Finished | Aug 09 08:09:09 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-798d5a02-5fa3-49da-adc4-ec967a14ac2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991234710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays .991234710 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.2786164204 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 690124946 ps |
| CPU time | 24.98 seconds |
| Started | Aug 09 08:09:08 PM PDT 24 |
| Finished | Aug 09 08:09:33 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-012a228f-e6c5-418a-9905-2c0994d3c130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786164204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.2786164204 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2865453521 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 8587251810 ps |
| CPU time | 327.68 seconds |
| Started | Aug 09 08:09:07 PM PDT 24 |
| Finished | Aug 09 08:14:35 PM PDT 24 |
| Peak memory | 576432 kb |
| Host | smart-7ada38cb-eb36-4cbc-9de0-1bd832e8ec2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865453521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2865453521 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.109414462 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 761949366 ps |
| CPU time | 195.01 seconds |
| Started | Aug 09 08:09:08 PM PDT 24 |
| Finished | Aug 09 08:12:23 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-57e861d3-d63f-4e2a-9643-136e8f705364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109414462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_ with_rand_reset.109414462 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1322200682 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 4059298870 ps |
| CPU time | 220.57 seconds |
| Started | Aug 09 08:09:08 PM PDT 24 |
| Finished | Aug 09 08:12:49 PM PDT 24 |
| Peak memory | 577136 kb |
| Host | smart-5bf2251a-45a7-43ae-a430-f254f1002652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322200682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.1322200682 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.1415971242 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 627990780 ps |
| CPU time | 27.45 seconds |
| Started | Aug 09 08:09:09 PM PDT 24 |
| Finished | Aug 09 08:09:36 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-e82eb1ed-2dc7-490d-a951-d5f424cb1c3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415971242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.1415971242 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.313117877 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 687430338 ps |
| CPU time | 43.43 seconds |
| Started | Aug 09 08:09:14 PM PDT 24 |
| Finished | Aug 09 08:09:57 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-571ba4e5-f4fb-42f9-9443-b6faca2db7a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313117877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device. 313117877 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3414862604 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 62611168837 ps |
| CPU time | 1086.34 seconds |
| Started | Aug 09 08:09:14 PM PDT 24 |
| Finished | Aug 09 08:27:21 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-d13cc9c5-19e5-4bd4-9651-3344cd13d9d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414862604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.3414862604 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.918632335 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 312872112 ps |
| CPU time | 31.91 seconds |
| Started | Aug 09 08:09:31 PM PDT 24 |
| Finished | Aug 09 08:10:03 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-196a0be2-69b7-491d-ae5d-4cd7c16665d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918632335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr .918632335 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.946874661 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 1082287099 ps |
| CPU time | 34.85 seconds |
| Started | Aug 09 08:09:14 PM PDT 24 |
| Finished | Aug 09 08:09:49 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-468991bd-5cfc-4a8f-9510-a3c358c12b53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946874661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.946874661 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.1310917853 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 1721599287 ps |
| CPU time | 62.49 seconds |
| Started | Aug 09 08:09:13 PM PDT 24 |
| Finished | Aug 09 08:10:16 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-416c0fe8-9101-420e-92ec-4b9446504288 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310917853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.1310917853 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2655645995 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 91267116471 ps |
| CPU time | 945.74 seconds |
| Started | Aug 09 08:09:16 PM PDT 24 |
| Finished | Aug 09 08:25:02 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-acf61efa-feeb-4c5a-9985-4529b78b9d0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655645995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2655645995 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3668818224 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 29468874249 ps |
| CPU time | 478.23 seconds |
| Started | Aug 09 08:09:12 PM PDT 24 |
| Finished | Aug 09 08:17:10 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-3229e0f9-19a5-422d-91ac-5a8d4c215ed7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668818224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.3668818224 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.3451824622 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 405946436 ps |
| CPU time | 35.21 seconds |
| Started | Aug 09 08:09:15 PM PDT 24 |
| Finished | Aug 09 08:09:51 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-d96372d9-7598-489e-ba1e-8472fe4b5498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451824622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.3451824622 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.212268342 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 235647345 ps |
| CPU time | 10.12 seconds |
| Started | Aug 09 08:09:14 PM PDT 24 |
| Finished | Aug 09 08:09:24 PM PDT 24 |
| Peak memory | 574900 kb |
| Host | smart-693a9051-fe28-4e29-9333-2c82c312e4f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212268342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.212268342 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.1316868924 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 53443220 ps |
| CPU time | 7.12 seconds |
| Started | Aug 09 08:09:09 PM PDT 24 |
| Finished | Aug 09 08:09:16 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-10def620-a21e-4ea8-9e72-d042d73b0eee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316868924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.1316868924 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.3199001703 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 7429040230 ps |
| CPU time | 73.57 seconds |
| Started | Aug 09 08:09:07 PM PDT 24 |
| Finished | Aug 09 08:10:20 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-3431fc8d-c0f1-4286-875d-972b17c92ce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199001703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.3199001703 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1712546333 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 6696557249 ps |
| CPU time | 112.12 seconds |
| Started | Aug 09 08:09:08 PM PDT 24 |
| Finished | Aug 09 08:11:00 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-e161facd-1d24-478b-8708-fa56018844b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712546333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1712546333 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2884581951 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 54454035 ps |
| CPU time | 6.76 seconds |
| Started | Aug 09 08:09:06 PM PDT 24 |
| Finished | Aug 09 08:09:13 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-be9f8c33-823f-49f0-9833-8682058d13a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884581951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.2884581951 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.3969566637 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 21654497372 ps |
| CPU time | 782.62 seconds |
| Started | Aug 09 08:09:20 PM PDT 24 |
| Finished | Aug 09 08:22:23 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-95c028a5-7a90-423b-896f-28a690273a6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969566637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.3969566637 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.1664558362 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 9148496815 ps |
| CPU time | 303.51 seconds |
| Started | Aug 09 08:09:22 PM PDT 24 |
| Finished | Aug 09 08:14:26 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-d8284b93-a9d8-4809-9515-0d76f69f0fcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664558362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1664558362 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1455553975 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 4232987040 ps |
| CPU time | 388.55 seconds |
| Started | Aug 09 08:09:21 PM PDT 24 |
| Finished | Aug 09 08:15:50 PM PDT 24 |
| Peak memory | 577176 kb |
| Host | smart-6d35a61a-6449-4b71-a021-970091d65752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455553975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.1455553975 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.802280147 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 8817277887 ps |
| CPU time | 446.45 seconds |
| Started | Aug 09 08:09:20 PM PDT 24 |
| Finished | Aug 09 08:16:47 PM PDT 24 |
| Peak memory | 577140 kb |
| Host | smart-6d374d22-5b32-4d9f-ac0c-3469bbfc4046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802280147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_reset_error.802280147 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.2641771336 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 807421104 ps |
| CPU time | 33.2 seconds |
| Started | Aug 09 08:09:13 PM PDT 24 |
| Finished | Aug 09 08:09:46 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-8c5eb24b-aa13-402b-9c5d-f1bd5e128d7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641771336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.2641771336 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.1850590822 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 1749852468 ps |
| CPU time | 74.48 seconds |
| Started | Aug 09 08:09:19 PM PDT 24 |
| Finished | Aug 09 08:10:34 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-149ccdb0-2a86-4585-bf98-0d40b65c72d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850590822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .1850590822 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2518829569 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 38774339933 ps |
| CPU time | 721.11 seconds |
| Started | Aug 09 08:09:22 PM PDT 24 |
| Finished | Aug 09 08:21:24 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-55f789bd-2a5e-4f72-81ea-e31ad2c6d3dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518829569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.2518829569 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1379339428 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 52565369 ps |
| CPU time | 7.3 seconds |
| Started | Aug 09 08:09:28 PM PDT 24 |
| Finished | Aug 09 08:09:36 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-01e5538e-ba6f-49c9-8f5f-aa1fd993db77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379339428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.1379339428 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.1031724496 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 606652246 ps |
| CPU time | 51 seconds |
| Started | Aug 09 08:09:25 PM PDT 24 |
| Finished | Aug 09 08:10:16 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-81bbfaac-7bb3-4686-aa87-b82b768974a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031724496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.1031724496 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.822177281 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 2076041316 ps |
| CPU time | 73.67 seconds |
| Started | Aug 09 08:09:20 PM PDT 24 |
| Finished | Aug 09 08:10:34 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-a85e6624-c324-424d-8d70-40a591e25ff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822177281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.822177281 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3501123131 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 26581641095 ps |
| CPU time | 259.94 seconds |
| Started | Aug 09 08:09:20 PM PDT 24 |
| Finished | Aug 09 08:13:40 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-0c84fe66-107a-4bd9-aa3a-5a811fcd68e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501123131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.3501123131 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.544998024 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 43447052160 ps |
| CPU time | 793.67 seconds |
| Started | Aug 09 08:09:23 PM PDT 24 |
| Finished | Aug 09 08:22:37 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-9256ebc2-7190-49b4-80a9-1a6ef6b3df48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544998024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.544998024 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.2433349907 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 270022792 ps |
| CPU time | 23.21 seconds |
| Started | Aug 09 08:09:22 PM PDT 24 |
| Finished | Aug 09 08:09:45 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-12206f05-8c3f-4543-99c7-b435918414f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433349907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.2433349907 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.766467241 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 61946379 ps |
| CPU time | 7.23 seconds |
| Started | Aug 09 08:09:21 PM PDT 24 |
| Finished | Aug 09 08:09:28 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-6728aa66-9a2f-4bb2-af08-1d25ad1d5e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766467241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.766467241 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.3862343942 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 143474381 ps |
| CPU time | 7.29 seconds |
| Started | Aug 09 08:09:23 PM PDT 24 |
| Finished | Aug 09 08:09:30 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-4a0b9245-9337-4c66-aab8-29797a5c2e68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862343942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3862343942 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.2118321304 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 10806800837 ps |
| CPU time | 102.49 seconds |
| Started | Aug 09 08:09:22 PM PDT 24 |
| Finished | Aug 09 08:11:04 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-e5ee7e95-9441-4813-a8dd-e14c3c7b5142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118321304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.2118321304 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2915732779 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 3874423843 ps |
| CPU time | 68 seconds |
| Started | Aug 09 08:09:23 PM PDT 24 |
| Finished | Aug 09 08:10:31 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-fa065bea-f2e4-428c-b351-003a77007bcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915732779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.2915732779 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.618738305 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 50102176 ps |
| CPU time | 6.89 seconds |
| Started | Aug 09 08:09:20 PM PDT 24 |
| Finished | Aug 09 08:09:27 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-425bf5e8-ba3b-490c-bd37-f4cbba9013be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618738305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays .618738305 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.2053932054 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 2756627649 ps |
| CPU time | 203.82 seconds |
| Started | Aug 09 08:09:28 PM PDT 24 |
| Finished | Aug 09 08:12:51 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-bd002b16-c414-4d58-bbbc-c1ec88fd4a4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053932054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.2053932054 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.4074049448 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 4601213331 ps |
| CPU time | 430.15 seconds |
| Started | Aug 09 08:09:32 PM PDT 24 |
| Finished | Aug 09 08:16:42 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-103894a8-98b7-44cc-a40e-190f44eda52b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074049448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.4074049448 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.2919104230 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 150999866 ps |
| CPU time | 18.85 seconds |
| Started | Aug 09 08:09:27 PM PDT 24 |
| Finished | Aug 09 08:09:46 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-370c6e44-c70f-4552-abb9-d92d5c105c73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919104230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.2919104230 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.2352467909 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 2550461623 ps |
| CPU time | 102.11 seconds |
| Started | Aug 09 08:09:49 PM PDT 24 |
| Finished | Aug 09 08:11:31 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-76617519-7d7c-495d-bde7-f1905eefef48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352467909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .2352467909 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3628610017 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 36790683155 ps |
| CPU time | 656.86 seconds |
| Started | Aug 09 08:09:48 PM PDT 24 |
| Finished | Aug 09 08:20:46 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-1c8e0ff4-f7fc-4301-8ff5-b97bf7d728ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628610017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.3628610017 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2077868476 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 431707103 ps |
| CPU time | 18.44 seconds |
| Started | Aug 09 08:09:52 PM PDT 24 |
| Finished | Aug 09 08:10:10 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-e33405b9-474b-4d83-9c0c-16c70b12f5ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077868476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.2077868476 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.228939201 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 643949526 ps |
| CPU time | 23.32 seconds |
| Started | Aug 09 08:09:51 PM PDT 24 |
| Finished | Aug 09 08:10:15 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-d0365e56-fbcd-4046-acc9-a830a90672da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228939201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.228939201 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.2734556407 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 127037070 ps |
| CPU time | 13.04 seconds |
| Started | Aug 09 08:09:46 PM PDT 24 |
| Finished | Aug 09 08:09:59 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-4ba847f4-f2be-4eb8-b766-f6111cedc38f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734556407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.2734556407 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.914149429 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 39798413056 ps |
| CPU time | 407.78 seconds |
| Started | Aug 09 08:09:48 PM PDT 24 |
| Finished | Aug 09 08:16:36 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-8db3af2c-be7f-4b1c-a6bc-fdc5142645c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914149429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.914149429 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.648406351 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 5962715218 ps |
| CPU time | 94.91 seconds |
| Started | Aug 09 08:09:52 PM PDT 24 |
| Finished | Aug 09 08:11:27 PM PDT 24 |
| Peak memory | 574872 kb |
| Host | smart-8d6d539a-b68e-4580-9e4e-30fa47b2dff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648406351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.648406351 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.3147583534 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 163074436 ps |
| CPU time | 14.98 seconds |
| Started | Aug 09 08:09:47 PM PDT 24 |
| Finished | Aug 09 08:10:02 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-6ff19981-4f61-409c-95de-e4e98b5b7550 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147583534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.3147583534 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.1041802825 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 315245435 ps |
| CPU time | 12.13 seconds |
| Started | Aug 09 08:09:49 PM PDT 24 |
| Finished | Aug 09 08:10:01 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-7824a5ee-b45c-429d-a9f3-4c5263d76c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041802825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1041802825 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.1228477024 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 48333519 ps |
| CPU time | 6.35 seconds |
| Started | Aug 09 08:09:27 PM PDT 24 |
| Finished | Aug 09 08:09:33 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-8e0446dc-5e5e-4405-9796-b23ba8a0c546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228477024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.1228477024 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.3535897129 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 6688625063 ps |
| CPU time | 71.37 seconds |
| Started | Aug 09 08:09:28 PM PDT 24 |
| Finished | Aug 09 08:10:39 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-5ff3bca6-2de3-44fe-9909-d7e7c20aa4c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535897129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.3535897129 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3176402547 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 5307953588 ps |
| CPU time | 87.98 seconds |
| Started | Aug 09 08:09:25 PM PDT 24 |
| Finished | Aug 09 08:10:53 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-3cac6995-c35d-4b84-8cda-32743cc12722 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176402547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3176402547 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.21518289 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 44322628 ps |
| CPU time | 6.35 seconds |
| Started | Aug 09 08:09:32 PM PDT 24 |
| Finished | Aug 09 08:09:38 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-235c10cb-984f-4d62-92e5-34e09ba8171e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21518289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays.21518289 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.3959960522 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 2526339672 ps |
| CPU time | 215.02 seconds |
| Started | Aug 09 08:09:50 PM PDT 24 |
| Finished | Aug 09 08:13:25 PM PDT 24 |
| Peak memory | 577120 kb |
| Host | smart-74cce45a-2f78-4dd1-bd5c-71e6eb65f671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959960522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3959960522 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2222184921 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 1189316869 ps |
| CPU time | 33.15 seconds |
| Started | Aug 09 08:09:50 PM PDT 24 |
| Finished | Aug 09 08:10:24 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-1fc2dd31-0312-429a-85c6-7f0d021d55b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222184921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.2222184921 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1708475237 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2656414443 ps |
| CPU time | 339.07 seconds |
| Started | Aug 09 08:09:52 PM PDT 24 |
| Finished | Aug 09 08:15:31 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-e5c41931-4247-4f8b-a01d-ce992324765b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708475237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.1708475237 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.1295156346 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 741478538 ps |
| CPU time | 179.17 seconds |
| Started | Aug 09 08:09:48 PM PDT 24 |
| Finished | Aug 09 08:12:47 PM PDT 24 |
| Peak memory | 577092 kb |
| Host | smart-f51cede4-cf61-4995-b677-c1fb9ec9f613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295156346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.1295156346 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3839256834 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 688210887 ps |
| CPU time | 27.94 seconds |
| Started | Aug 09 08:09:46 PM PDT 24 |
| Finished | Aug 09 08:10:14 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-df1ce54e-78e0-42bc-ab50-6e1a10ef479a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839256834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3839256834 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.3660091827 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 650963014 ps |
| CPU time | 46 seconds |
| Started | Aug 09 08:09:49 PM PDT 24 |
| Finished | Aug 09 08:10:36 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-ce06ac3d-c974-4910-a82b-57fb1988c9b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660091827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .3660091827 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2561561240 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 121772766720 ps |
| CPU time | 2378.73 seconds |
| Started | Aug 09 08:09:47 PM PDT 24 |
| Finished | Aug 09 08:49:26 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-b37e73eb-1689-4699-bd7f-f6f2dc77ec08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561561240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.2561561240 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1273728570 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 532748663 ps |
| CPU time | 21.64 seconds |
| Started | Aug 09 08:09:52 PM PDT 24 |
| Finished | Aug 09 08:10:14 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-d8e0cdd9-89dd-4748-89d2-24b7a0e6c85c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273728570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.1273728570 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.1724967672 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 572901022 ps |
| CPU time | 46.95 seconds |
| Started | Aug 09 08:09:46 PM PDT 24 |
| Finished | Aug 09 08:10:33 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-45c64b47-ddf4-4827-b749-dbef0a8f7f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724967672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.1724967672 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.247574206 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1922202788 ps |
| CPU time | 69.77 seconds |
| Started | Aug 09 08:09:47 PM PDT 24 |
| Finished | Aug 09 08:10:57 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-5ae28973-9d6d-4a47-afbc-4f044ee90823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247574206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.247574206 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1429938694 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 82319307312 ps |
| CPU time | 822.37 seconds |
| Started | Aug 09 08:09:48 PM PDT 24 |
| Finished | Aug 09 08:23:31 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-720f52f6-f821-4f01-98c9-415692eccd12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429938694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1429938694 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.4235249126 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 40708932140 ps |
| CPU time | 702.24 seconds |
| Started | Aug 09 08:09:48 PM PDT 24 |
| Finished | Aug 09 08:21:31 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-9a72ae5d-3a43-424e-b419-ac54904eccbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235249126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.4235249126 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.2598301047 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 392228997 ps |
| CPU time | 31.03 seconds |
| Started | Aug 09 08:09:47 PM PDT 24 |
| Finished | Aug 09 08:10:18 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-585da12b-bf78-4cfd-9788-a4cfdeb182bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598301047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.2598301047 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.3045994780 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 363092889 ps |
| CPU time | 25.66 seconds |
| Started | Aug 09 08:09:48 PM PDT 24 |
| Finished | Aug 09 08:10:13 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-5af36b6c-8f00-4503-b7ab-24d2c1565ab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045994780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.3045994780 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.1876545148 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 203607548 ps |
| CPU time | 8.01 seconds |
| Started | Aug 09 08:09:48 PM PDT 24 |
| Finished | Aug 09 08:09:56 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-a2789a1d-9bdb-484e-97ee-bdf9ab794b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876545148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.1876545148 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.465108368 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 9845568622 ps |
| CPU time | 97.16 seconds |
| Started | Aug 09 08:09:46 PM PDT 24 |
| Finished | Aug 09 08:11:23 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-463d0d21-c33c-409c-ada8-403bfc32089c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465108368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.465108368 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3090755045 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 4666753799 ps |
| CPU time | 77.59 seconds |
| Started | Aug 09 08:09:47 PM PDT 24 |
| Finished | Aug 09 08:11:05 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-62c5d982-601d-46c9-b1f3-862be0ac99b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090755045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.3090755045 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3262866734 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 44955258 ps |
| CPU time | 6.25 seconds |
| Started | Aug 09 08:09:51 PM PDT 24 |
| Finished | Aug 09 08:09:57 PM PDT 24 |
| Peak memory | 574840 kb |
| Host | smart-ffc305bd-5378-475b-a77d-13539cfa2eb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262866734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.3262866734 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.2088406926 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 1246480030 ps |
| CPU time | 97.83 seconds |
| Started | Aug 09 08:09:48 PM PDT 24 |
| Finished | Aug 09 08:11:26 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-2d450271-26fe-41ad-a6b8-8d9e42f7b76b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088406926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2088406926 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1230672574 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 2403322641 ps |
| CPU time | 98.87 seconds |
| Started | Aug 09 08:10:02 PM PDT 24 |
| Finished | Aug 09 08:11:41 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-cd83dbc0-35b8-44e1-9de0-a295a7541e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230672574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.1230672574 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.388751567 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 2260158396 ps |
| CPU time | 171.75 seconds |
| Started | Aug 09 08:09:54 PM PDT 24 |
| Finished | Aug 09 08:12:46 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-adf45d0d-ec0c-4d5e-aae4-5ecdda10f455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388751567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_reset_error.388751567 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.2299721915 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 239295299 ps |
| CPU time | 13.25 seconds |
| Started | Aug 09 08:09:51 PM PDT 24 |
| Finished | Aug 09 08:10:04 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-0ff25a1a-6639-4515-b433-75c7c9baa00d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299721915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.2299721915 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.130960912 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 104667746406 ps |
| CPU time | 1807.76 seconds |
| Started | Aug 09 08:09:56 PM PDT 24 |
| Finished | Aug 09 08:40:04 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-7a02353c-853a-4584-bc42-0d791d106acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130960912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_d evice_slow_rsp.130960912 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.205654403 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 249031349 ps |
| CPU time | 27.34 seconds |
| Started | Aug 09 08:09:55 PM PDT 24 |
| Finished | Aug 09 08:10:22 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-e832ae73-1c65-4955-87e3-1238cbc1d856 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205654403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr .205654403 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.3750553694 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 1400404192 ps |
| CPU time | 47.51 seconds |
| Started | Aug 09 08:09:54 PM PDT 24 |
| Finished | Aug 09 08:10:42 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-b3f9c667-1958-4e6f-acb3-531da7e53209 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750553694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.3750553694 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.2752633985 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 448283187 ps |
| CPU time | 38.51 seconds |
| Started | Aug 09 08:09:53 PM PDT 24 |
| Finished | Aug 09 08:10:32 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-70aafc7e-e9a0-4221-a561-54023dd46514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752633985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.2752633985 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.923270408 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 82548630770 ps |
| CPU time | 858.34 seconds |
| Started | Aug 09 08:09:53 PM PDT 24 |
| Finished | Aug 09 08:24:11 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-098121de-bb4e-4f76-92f8-fb20f69cadc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923270408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.923270408 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.107601940 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 6000201921 ps |
| CPU time | 90.23 seconds |
| Started | Aug 09 08:09:55 PM PDT 24 |
| Finished | Aug 09 08:11:25 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-9391023b-5e41-4406-a51c-11d48f902c84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107601940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.107601940 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.3309970425 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 72106953 ps |
| CPU time | 8.76 seconds |
| Started | Aug 09 08:09:53 PM PDT 24 |
| Finished | Aug 09 08:10:02 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-8f45e23f-f11f-4bfb-b6b2-5f838da0fb7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309970425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.3309970425 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.1301011774 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2667688360 ps |
| CPU time | 76.63 seconds |
| Started | Aug 09 08:09:54 PM PDT 24 |
| Finished | Aug 09 08:11:11 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-fa814969-3eff-42b5-aa36-44cb55e85234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301011774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1301011774 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.2989556880 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 51607949 ps |
| CPU time | 5.87 seconds |
| Started | Aug 09 08:09:53 PM PDT 24 |
| Finished | Aug 09 08:09:59 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-2811544e-9e48-49c7-9dfd-208f70b39fc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989556880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.2989556880 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.3230072513 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 7626441653 ps |
| CPU time | 77.31 seconds |
| Started | Aug 09 08:09:56 PM PDT 24 |
| Finished | Aug 09 08:11:13 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-44688879-4a43-44c9-b0fa-9b55e508da87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230072513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.3230072513 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.917650531 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 4981723533 ps |
| CPU time | 92.64 seconds |
| Started | Aug 09 08:09:55 PM PDT 24 |
| Finished | Aug 09 08:11:27 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-ca244b1f-d0fc-4860-ab77-b71fbd5be576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917650531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.917650531 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.3171920604 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 39974160 ps |
| CPU time | 5.74 seconds |
| Started | Aug 09 08:10:00 PM PDT 24 |
| Finished | Aug 09 08:10:05 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-621c1bf3-405f-4560-b882-cfbfeb005427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171920604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.3171920604 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.2849820115 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 4311026106 ps |
| CPU time | 155.87 seconds |
| Started | Aug 09 08:09:54 PM PDT 24 |
| Finished | Aug 09 08:12:31 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-8d13d06f-216f-4aed-b92e-794148d9068e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849820115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.2849820115 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.4272609469 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 2726199537 ps |
| CPU time | 199.93 seconds |
| Started | Aug 09 08:09:59 PM PDT 24 |
| Finished | Aug 09 08:13:19 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-314ef844-1bbb-4534-8c74-5dc71defd43d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272609469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.4272609469 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.4033369649 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 3691356757 ps |
| CPU time | 269.33 seconds |
| Started | Aug 09 08:10:00 PM PDT 24 |
| Finished | Aug 09 08:14:29 PM PDT 24 |
| Peak memory | 577108 kb |
| Host | smart-cc885ced-1894-4e13-8075-5417a8eb7357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033369649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.4033369649 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3347638908 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 108819136 ps |
| CPU time | 13.9 seconds |
| Started | Aug 09 08:09:51 PM PDT 24 |
| Finished | Aug 09 08:10:05 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-8b8b191e-ec57-47bd-95f7-368fa1b9bbcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347638908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3347638908 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.4078730598 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 718286680 ps |
| CPU time | 73.18 seconds |
| Started | Aug 09 08:10:02 PM PDT 24 |
| Finished | Aug 09 08:11:15 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-e2f03c7a-b137-42d4-ab6b-900b49c8ffbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078730598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .4078730598 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1941957395 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 93024065189 ps |
| CPU time | 1720.8 seconds |
| Started | Aug 09 08:10:04 PM PDT 24 |
| Finished | Aug 09 08:38:46 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-e1ee028d-b2d0-42bf-91b4-92791649b0c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941957395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.1941957395 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3408651755 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 694344947 ps |
| CPU time | 27.24 seconds |
| Started | Aug 09 08:10:01 PM PDT 24 |
| Finished | Aug 09 08:10:28 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-fe100023-2feb-45e4-a041-88042e0f1dc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408651755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.3408651755 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.522959849 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 969568383 ps |
| CPU time | 37.13 seconds |
| Started | Aug 09 08:10:00 PM PDT 24 |
| Finished | Aug 09 08:10:38 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-bc9009f4-30db-4dc9-a8d1-6d06a181c284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522959849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.522959849 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.67846792 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 395068966 ps |
| CPU time | 30.81 seconds |
| Started | Aug 09 08:09:58 PM PDT 24 |
| Finished | Aug 09 08:10:29 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-bf19ab75-8160-4548-93b3-bf7424a749ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67846792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.67846792 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.486761799 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 40454291433 ps |
| CPU time | 424.41 seconds |
| Started | Aug 09 08:09:59 PM PDT 24 |
| Finished | Aug 09 08:17:03 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-379d1986-5a5a-4767-ade8-9b394bc84c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486761799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.486761799 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.1883345541 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 15840033909 ps |
| CPU time | 269.08 seconds |
| Started | Aug 09 08:10:00 PM PDT 24 |
| Finished | Aug 09 08:14:29 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-f7b46baa-a179-45a9-8fc2-6f626d52898a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883345541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.1883345541 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.3895256558 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 359131249 ps |
| CPU time | 30.52 seconds |
| Started | Aug 09 08:09:59 PM PDT 24 |
| Finished | Aug 09 08:10:29 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-3976d767-d86c-430d-9d6d-0f210e0a40c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895256558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.3895256558 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.2935678602 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 1793602772 ps |
| CPU time | 49.5 seconds |
| Started | Aug 09 08:10:05 PM PDT 24 |
| Finished | Aug 09 08:10:54 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-299be2c9-5aec-4379-a626-a29578742d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935678602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.2935678602 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.2831130232 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 198300907 ps |
| CPU time | 8.33 seconds |
| Started | Aug 09 08:10:00 PM PDT 24 |
| Finished | Aug 09 08:10:08 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-0f233029-9f35-4924-9747-f91e3113817e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831130232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.2831130232 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.379681419 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 7285458093 ps |
| CPU time | 75 seconds |
| Started | Aug 09 08:09:58 PM PDT 24 |
| Finished | Aug 09 08:11:13 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-548eacd8-be9b-4ee3-b6f5-b2a7abb101e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379681419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.379681419 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.122381174 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 5178931415 ps |
| CPU time | 90.64 seconds |
| Started | Aug 09 08:09:58 PM PDT 24 |
| Finished | Aug 09 08:11:29 PM PDT 24 |
| Peak memory | 574900 kb |
| Host | smart-0573fdab-b4b4-460a-9fcf-6bb89da38d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122381174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.122381174 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1287344416 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 50626467 ps |
| CPU time | 6.37 seconds |
| Started | Aug 09 08:09:59 PM PDT 24 |
| Finished | Aug 09 08:10:06 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-c335408a-260d-4782-8728-2a465ed42bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287344416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.1287344416 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.1695242904 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 7959817150 ps |
| CPU time | 294.47 seconds |
| Started | Aug 09 08:10:05 PM PDT 24 |
| Finished | Aug 09 08:15:00 PM PDT 24 |
| Peak memory | 577096 kb |
| Host | smart-d8e6af31-15a4-42ac-be20-c49b53ffb52d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695242904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.1695242904 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2362666745 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 9733369793 ps |
| CPU time | 315.52 seconds |
| Started | Aug 09 08:10:07 PM PDT 24 |
| Finished | Aug 09 08:15:23 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-c94cec59-5460-4a11-833e-e9c0e8625587 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362666745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.2362666745 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2099766434 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 2286675535 ps |
| CPU time | 228.37 seconds |
| Started | Aug 09 08:10:16 PM PDT 24 |
| Finished | Aug 09 08:14:04 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-88576f7a-ccbb-4045-a7e5-e67071589a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099766434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.2099766434 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3885827218 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 2758199078 ps |
| CPU time | 174.35 seconds |
| Started | Aug 09 08:10:06 PM PDT 24 |
| Finished | Aug 09 08:13:01 PM PDT 24 |
| Peak memory | 577148 kb |
| Host | smart-ef6bd9a4-d335-4b7f-8268-bb3cc90e13b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885827218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.3885827218 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.897512888 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 56665519 ps |
| CPU time | 9.56 seconds |
| Started | Aug 09 08:10:01 PM PDT 24 |
| Finished | Aug 09 08:10:11 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-ad37f031-2bbf-4431-a828-cc9b4555634b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897512888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.897512888 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.4103353952 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 1147615825 ps |
| CPU time | 78.33 seconds |
| Started | Aug 09 08:10:05 PM PDT 24 |
| Finished | Aug 09 08:11:24 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-13abf58e-f6c3-4ecf-8ace-00c6374cdd36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103353952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .4103353952 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2423932168 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 156022778756 ps |
| CPU time | 3017.14 seconds |
| Started | Aug 09 08:10:05 PM PDT 24 |
| Finished | Aug 09 09:00:22 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-2e8b70c7-c9ea-4d89-9f44-450cf9f90d17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423932168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.2423932168 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1316452700 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 155907597 ps |
| CPU time | 18.5 seconds |
| Started | Aug 09 08:10:13 PM PDT 24 |
| Finished | Aug 09 08:10:31 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-dfe6e4e5-b3f9-4bd7-a6ca-31786b6eec56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316452700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.1316452700 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.2965895650 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 176092242 ps |
| CPU time | 15.63 seconds |
| Started | Aug 09 08:10:14 PM PDT 24 |
| Finished | Aug 09 08:10:30 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-a36e7a42-cc6c-4180-815e-5853c4d89f9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965895650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.2965895650 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.3206252230 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 2554588403 ps |
| CPU time | 85.75 seconds |
| Started | Aug 09 08:10:04 PM PDT 24 |
| Finished | Aug 09 08:11:30 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-5ff18d27-87ba-4d63-8753-f3dceac635c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206252230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.3206252230 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.2565215663 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 17409659847 ps |
| CPU time | 178.17 seconds |
| Started | Aug 09 08:10:15 PM PDT 24 |
| Finished | Aug 09 08:13:13 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-7f63407c-2657-4fff-aaa1-1ee108beef09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565215663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.2565215663 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.3317773561 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 29257219474 ps |
| CPU time | 484.14 seconds |
| Started | Aug 09 08:10:06 PM PDT 24 |
| Finished | Aug 09 08:18:11 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-d5857232-8b68-44c0-b27d-6c43487b9617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317773561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.3317773561 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.270162982 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 99637080 ps |
| CPU time | 11.39 seconds |
| Started | Aug 09 08:10:16 PM PDT 24 |
| Finished | Aug 09 08:10:27 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-b95c29f3-cd1b-42b6-853c-24317cd9936b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270162982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_dela ys.270162982 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.1865482563 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 2611769733 ps |
| CPU time | 77.58 seconds |
| Started | Aug 09 08:10:04 PM PDT 24 |
| Finished | Aug 09 08:11:22 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-70768a21-bd75-4bdb-8e5b-4d44f282bc77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865482563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.1865482563 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.4286473853 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 48462353 ps |
| CPU time | 6.03 seconds |
| Started | Aug 09 08:10:05 PM PDT 24 |
| Finished | Aug 09 08:10:11 PM PDT 24 |
| Peak memory | 574820 kb |
| Host | smart-a3a2e318-c579-4d21-9dfb-25cdefff32d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286473853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.4286473853 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.2959189656 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 7249058519 ps |
| CPU time | 72.95 seconds |
| Started | Aug 09 08:10:04 PM PDT 24 |
| Finished | Aug 09 08:11:17 PM PDT 24 |
| Peak memory | 574872 kb |
| Host | smart-a6e84b16-8c79-43cd-bd06-e8bf818c9a0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959189656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.2959189656 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1987704047 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 4718644324 ps |
| CPU time | 80.58 seconds |
| Started | Aug 09 08:10:06 PM PDT 24 |
| Finished | Aug 09 08:11:27 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-a42b17b8-b43a-4ea0-be4d-6b441c448440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987704047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.1987704047 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2191220475 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 43974199 ps |
| CPU time | 5.91 seconds |
| Started | Aug 09 08:10:14 PM PDT 24 |
| Finished | Aug 09 08:10:20 PM PDT 24 |
| Peak memory | 574848 kb |
| Host | smart-4c3c6bfa-0c31-4365-a5fc-26bbe9443ab8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191220475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.2191220475 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.1552677496 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 1944453401 ps |
| CPU time | 153.28 seconds |
| Started | Aug 09 08:10:14 PM PDT 24 |
| Finished | Aug 09 08:12:47 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-fdd48220-d060-4090-92c5-1224cdec8adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552677496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.1552677496 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.1812608321 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 3104955330 ps |
| CPU time | 252.93 seconds |
| Started | Aug 09 08:10:17 PM PDT 24 |
| Finished | Aug 09 08:14:30 PM PDT 24 |
| Peak memory | 577076 kb |
| Host | smart-710db678-9349-46c6-9703-92e009f9592a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812608321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.1812608321 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3139529934 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 3920154988 ps |
| CPU time | 297.75 seconds |
| Started | Aug 09 08:10:11 PM PDT 24 |
| Finished | Aug 09 08:15:09 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-3122678a-3b85-44d3-a0e3-e1a83fca244e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139529934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.3139529934 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.4286232283 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 610491356 ps |
| CPU time | 168.7 seconds |
| Started | Aug 09 08:10:14 PM PDT 24 |
| Finished | Aug 09 08:13:03 PM PDT 24 |
| Peak memory | 577100 kb |
| Host | smart-bd82d5fe-9a26-4162-ad7e-bca9d27f68cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286232283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.4286232283 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.1820253299 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 207559750 ps |
| CPU time | 24.14 seconds |
| Started | Aug 09 08:10:14 PM PDT 24 |
| Finished | Aug 09 08:10:38 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-28b880b7-8ab0-46a3-921c-6535bab49b39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820253299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.1820253299 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2645870864 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 800456872 ps |
| CPU time | 58.89 seconds |
| Started | Aug 09 08:10:18 PM PDT 24 |
| Finished | Aug 09 08:11:17 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-f5ebbca9-1504-4587-b3a6-5467dd06d1cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645870864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2645870864 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.3557059711 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 314140242 ps |
| CPU time | 30.72 seconds |
| Started | Aug 09 08:10:21 PM PDT 24 |
| Finished | Aug 09 08:10:51 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-c3da849d-5081-46d6-a6fe-98f68e8424db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557059711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.3557059711 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.3340532295 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 81748404 ps |
| CPU time | 8.68 seconds |
| Started | Aug 09 08:10:21 PM PDT 24 |
| Finished | Aug 09 08:10:30 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-1b491e0b-0e74-4d05-83d0-c28e0552b44c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340532295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.3340532295 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.307455895 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 780205174 ps |
| CPU time | 27.41 seconds |
| Started | Aug 09 08:10:16 PM PDT 24 |
| Finished | Aug 09 08:10:43 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-6bfc1817-473f-4be7-b081-2e6958def845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307455895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.307455895 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.1663694269 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 34364458058 ps |
| CPU time | 354.39 seconds |
| Started | Aug 09 08:10:12 PM PDT 24 |
| Finished | Aug 09 08:16:07 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-c9419c41-2267-4239-8648-5f0f3a391982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663694269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.1663694269 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.2033397688 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 56147625164 ps |
| CPU time | 1119.59 seconds |
| Started | Aug 09 08:10:16 PM PDT 24 |
| Finished | Aug 09 08:28:56 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-cedb674d-9ff2-42b1-a16a-929c43a221c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033397688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.2033397688 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.4061523595 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 519344978 ps |
| CPU time | 46.33 seconds |
| Started | Aug 09 08:10:13 PM PDT 24 |
| Finished | Aug 09 08:10:59 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-4e85ed6f-3850-4a23-9ff7-ff904853d521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061523595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.4061523595 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.1690575602 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1551276539 ps |
| CPU time | 47.48 seconds |
| Started | Aug 09 08:10:15 PM PDT 24 |
| Finished | Aug 09 08:11:02 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-332e07c6-6cfb-4e94-97da-77ee39115a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690575602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.1690575602 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.2510327640 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 227463000 ps |
| CPU time | 9.57 seconds |
| Started | Aug 09 08:10:14 PM PDT 24 |
| Finished | Aug 09 08:10:23 PM PDT 24 |
| Peak memory | 574808 kb |
| Host | smart-f96dd78d-fc57-4941-b63a-ca50afc6909d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510327640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.2510327640 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1895477099 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 9198521397 ps |
| CPU time | 98.83 seconds |
| Started | Aug 09 08:10:14 PM PDT 24 |
| Finished | Aug 09 08:11:53 PM PDT 24 |
| Peak memory | 574936 kb |
| Host | smart-6ca16b8c-c015-4e0f-86d6-8f000f0b464c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895477099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1895477099 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3962744700 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3466021694 ps |
| CPU time | 58.96 seconds |
| Started | Aug 09 08:10:15 PM PDT 24 |
| Finished | Aug 09 08:11:14 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-cfdf1592-46af-42da-8c14-cbd76f06b5a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962744700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3962744700 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3219958744 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 45217589 ps |
| CPU time | 6.38 seconds |
| Started | Aug 09 08:10:14 PM PDT 24 |
| Finished | Aug 09 08:10:21 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-40df8901-fc14-465e-a6ce-9b75dc634bfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219958744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.3219958744 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.4265976031 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 1981041717 ps |
| CPU time | 81.13 seconds |
| Started | Aug 09 08:10:22 PM PDT 24 |
| Finished | Aug 09 08:11:43 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-7787458b-f5eb-4a08-8ccb-4a02167bc536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265976031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.4265976031 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.1083071046 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 8098256861 ps |
| CPU time | 279.36 seconds |
| Started | Aug 09 08:10:21 PM PDT 24 |
| Finished | Aug 09 08:15:01 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-46dd6996-e825-4dcb-8f4e-7f4f389d9336 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083071046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.1083071046 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.923017087 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 4189237481 ps |
| CPU time | 199.65 seconds |
| Started | Aug 09 08:10:21 PM PDT 24 |
| Finished | Aug 09 08:13:41 PM PDT 24 |
| Peak memory | 577328 kb |
| Host | smart-3ab7b22e-fb5f-4b25-b2ad-b942596c24f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923017087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_ with_rand_reset.923017087 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.565712834 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1951545231 ps |
| CPU time | 150.2 seconds |
| Started | Aug 09 08:10:20 PM PDT 24 |
| Finished | Aug 09 08:12:50 PM PDT 24 |
| Peak memory | 577124 kb |
| Host | smart-eac5e77f-3e73-47fa-8853-46a34e05ae4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565712834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_reset_error.565712834 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.845892621 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 563363309 ps |
| CPU time | 26.09 seconds |
| Started | Aug 09 08:10:13 PM PDT 24 |
| Finished | Aug 09 08:10:40 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-45ade579-a467-4ab7-89d5-856f2111150f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845892621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.845892621 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.2574938948 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 1219442368 ps |
| CPU time | 42.62 seconds |
| Started | Aug 09 08:10:30 PM PDT 24 |
| Finished | Aug 09 08:11:13 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-ba9a16b7-16c1-4b63-92da-b5061683bc50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574938948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .2574938948 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.4122505652 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 78497960382 ps |
| CPU time | 1393.36 seconds |
| Started | Aug 09 08:10:31 PM PDT 24 |
| Finished | Aug 09 08:33:44 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-36e8918c-7fc6-4255-8a31-9ced142e0720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122505652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.4122505652 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2915826665 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 1111367018 ps |
| CPU time | 42.63 seconds |
| Started | Aug 09 08:10:30 PM PDT 24 |
| Finished | Aug 09 08:11:13 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-4958d892-5c37-4541-986d-27899a9e82a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915826665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.2915826665 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.3830781811 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 2299709010 ps |
| CPU time | 74.88 seconds |
| Started | Aug 09 08:10:31 PM PDT 24 |
| Finished | Aug 09 08:11:46 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-c915472f-ec52-4d43-b906-11075271c672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830781811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.3830781811 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.739615613 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 388231966 ps |
| CPU time | 16.61 seconds |
| Started | Aug 09 08:10:19 PM PDT 24 |
| Finished | Aug 09 08:10:36 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-ad138a8d-6478-482b-901a-5783f4ac5a5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739615613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.739615613 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3982527573 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 39331058822 ps |
| CPU time | 442.54 seconds |
| Started | Aug 09 08:10:20 PM PDT 24 |
| Finished | Aug 09 08:17:43 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-ae6c1670-0ff9-4a49-bb5c-8332883aafe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982527573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3982527573 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.1473671939 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 48986080685 ps |
| CPU time | 880.92 seconds |
| Started | Aug 09 08:10:30 PM PDT 24 |
| Finished | Aug 09 08:25:11 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-a4f461f2-8eb2-475e-9f16-78408f22a58d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473671939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.1473671939 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.2797548911 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 411726955 ps |
| CPU time | 36.25 seconds |
| Started | Aug 09 08:10:21 PM PDT 24 |
| Finished | Aug 09 08:10:57 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-ca739f21-1c1e-4c02-afa9-5178e8440731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797548911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.2797548911 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.2166058301 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 346439568 ps |
| CPU time | 24.35 seconds |
| Started | Aug 09 08:10:30 PM PDT 24 |
| Finished | Aug 09 08:10:54 PM PDT 24 |
| Peak memory | 576180 kb |
| Host | smart-d181e99b-117a-4b65-b58c-df2ad0ef741d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166058301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2166058301 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.2581951133 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 173013578 ps |
| CPU time | 8.4 seconds |
| Started | Aug 09 08:10:20 PM PDT 24 |
| Finished | Aug 09 08:10:28 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-5931bfbc-8590-438b-805d-146b19d9629f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581951133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.2581951133 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.2745319559 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 8646081632 ps |
| CPU time | 97.37 seconds |
| Started | Aug 09 08:10:21 PM PDT 24 |
| Finished | Aug 09 08:11:59 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-807b0cb9-cb60-46c9-b90c-56d005c33a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745319559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.2745319559 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3540469866 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 5785319017 ps |
| CPU time | 95.73 seconds |
| Started | Aug 09 08:10:21 PM PDT 24 |
| Finished | Aug 09 08:11:57 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-183ea20d-0f70-4b26-8373-015d757766c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540469866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3540469866 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1293170005 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 38225174 ps |
| CPU time | 5.75 seconds |
| Started | Aug 09 08:10:20 PM PDT 24 |
| Finished | Aug 09 08:10:26 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-d95db916-5577-4053-b8f8-5583b1edbc9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293170005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.1293170005 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.1604214606 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 393578636 ps |
| CPU time | 16.42 seconds |
| Started | Aug 09 08:10:34 PM PDT 24 |
| Finished | Aug 09 08:10:51 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-bbbdce0b-81df-474b-b694-6aff62b06f0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604214606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.1604214606 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.1008733948 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 10485668717 ps |
| CPU time | 352.01 seconds |
| Started | Aug 09 08:10:30 PM PDT 24 |
| Finished | Aug 09 08:16:22 PM PDT 24 |
| Peak memory | 577136 kb |
| Host | smart-3fa79b48-d8e3-4855-b9d8-8611a9b24727 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008733948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.1008733948 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.130697045 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 150836401 ps |
| CPU time | 73.72 seconds |
| Started | Aug 09 08:10:30 PM PDT 24 |
| Finished | Aug 09 08:11:44 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-859d6c25-d575-46c0-8035-00301c8b6817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130697045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_ with_rand_reset.130697045 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.1005337476 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 2974155958 ps |
| CPU time | 212.6 seconds |
| Started | Aug 09 08:10:39 PM PDT 24 |
| Finished | Aug 09 08:14:11 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-001747d3-f7ff-4b31-b06e-2529c1ab6e5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005337476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.1005337476 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.2136674629 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 93817723 ps |
| CPU time | 12.82 seconds |
| Started | Aug 09 08:10:30 PM PDT 24 |
| Finished | Aug 09 08:10:43 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-62b04078-661a-4a3e-9b64-880d3aa41b02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136674629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.2136674629 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1934953193 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 6903475140 ps |
| CPU time | 389.78 seconds |
| Started | Aug 09 07:58:18 PM PDT 24 |
| Finished | Aug 09 08:04:48 PM PDT 24 |
| Peak memory | 641884 kb |
| Host | smart-93a2f3b7-fe79-4aa2-9b03-9c38ea54fff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934953193 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.1934953193 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.665384814 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 5689590840 ps |
| CPU time | 521.25 seconds |
| Started | Aug 09 07:58:07 PM PDT 24 |
| Finished | Aug 09 08:06:48 PM PDT 24 |
| Peak memory | 599052 kb |
| Host | smart-47c583a7-0ac6-41f2-9a1b-f3dfa851102f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665384814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.665384814 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.919946154 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 15457789271 ps |
| CPU time | 2253.19 seconds |
| Started | Aug 09 07:58:09 PM PDT 24 |
| Finished | Aug 09 08:35:43 PM PDT 24 |
| Peak memory | 593620 kb |
| Host | smart-77166fa5-0bfa-4cb1-8bf7-6d7c42db4554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919946154 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.chip_same_csr_outstanding.919946154 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.1908465907 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 114001249 ps |
| CPU time | 15.49 seconds |
| Started | Aug 09 07:58:05 PM PDT 24 |
| Finished | Aug 09 07:58:20 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-e032b510-7070-4bde-acb8-89b2e8ab2c4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908465907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 1908465907 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2588712947 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 81166097826 ps |
| CPU time | 1420.62 seconds |
| Started | Aug 09 07:58:05 PM PDT 24 |
| Finished | Aug 09 08:21:45 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-8f0bc9c4-cc4e-460e-a343-3853003325be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588712947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.2588712947 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.4106753078 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 708171599 ps |
| CPU time | 31.36 seconds |
| Started | Aug 09 07:58:06 PM PDT 24 |
| Finished | Aug 09 07:58:37 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-3b5a1054-2bdf-41f7-9e4a-d8a43017ba99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106753078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .4106753078 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.1309482918 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 1206855236 ps |
| CPU time | 40.13 seconds |
| Started | Aug 09 07:58:04 PM PDT 24 |
| Finished | Aug 09 07:58:45 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-c07c25e2-49f1-435b-ab06-23fdf6171c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309482918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1309482918 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.3975575303 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 2534317202 ps |
| CPU time | 86.81 seconds |
| Started | Aug 09 07:58:26 PM PDT 24 |
| Finished | Aug 09 07:59:53 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-ee12c277-55c0-4f44-82e3-dc10a8da0e0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975575303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.3975575303 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.2869722361 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 38963227348 ps |
| CPU time | 376.89 seconds |
| Started | Aug 09 07:58:04 PM PDT 24 |
| Finished | Aug 09 08:04:21 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-43847cc0-0537-46b7-b244-88c398a48720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869722361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2869722361 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1422166242 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 20675156043 ps |
| CPU time | 332.75 seconds |
| Started | Aug 09 07:58:26 PM PDT 24 |
| Finished | Aug 09 08:03:59 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-656cf46b-d16a-4c4a-8bd4-0339b44db7ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422166242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1422166242 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.3353602933 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 133240295 ps |
| CPU time | 13.93 seconds |
| Started | Aug 09 07:58:06 PM PDT 24 |
| Finished | Aug 09 07:58:20 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-94a3ac36-96d6-4a50-8b25-397966283851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353602933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.3353602933 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.1032973485 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 1435282075 ps |
| CPU time | 40.59 seconds |
| Started | Aug 09 07:58:05 PM PDT 24 |
| Finished | Aug 09 07:58:46 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-0e0c1cf4-880c-4e5f-8932-981be26e44c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032973485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1032973485 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.2251766638 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 48998779 ps |
| CPU time | 6.35 seconds |
| Started | Aug 09 07:58:14 PM PDT 24 |
| Finished | Aug 09 07:58:20 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-daf06e3d-a43b-4e5f-9959-ef65adf709e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251766638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2251766638 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.4202031976 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 7984790613 ps |
| CPU time | 86.51 seconds |
| Started | Aug 09 07:58:26 PM PDT 24 |
| Finished | Aug 09 07:59:53 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-312e7905-ecba-4e3d-95c2-b7077ac84ab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202031976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4202031976 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3101986697 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 6864000566 ps |
| CPU time | 120.21 seconds |
| Started | Aug 09 07:58:09 PM PDT 24 |
| Finished | Aug 09 08:00:09 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-4aefeb85-0db3-468d-9448-7d63d5588c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101986697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3101986697 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2367300393 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 45833957 ps |
| CPU time | 6.23 seconds |
| Started | Aug 09 07:58:07 PM PDT 24 |
| Finished | Aug 09 07:58:13 PM PDT 24 |
| Peak memory | 574820 kb |
| Host | smart-19bbc30c-7f03-43dd-956c-92e67b1fb7b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367300393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .2367300393 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.3345629875 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 1611751207 ps |
| CPU time | 62.06 seconds |
| Started | Aug 09 07:58:05 PM PDT 24 |
| Finished | Aug 09 07:59:07 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-0c067a1f-30c0-4a2e-a6f0-1065400046b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345629875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3345629875 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1362253134 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 12942239474 ps |
| CPU time | 484.63 seconds |
| Started | Aug 09 07:58:11 PM PDT 24 |
| Finished | Aug 09 08:06:15 PM PDT 24 |
| Peak memory | 577156 kb |
| Host | smart-5824b38b-38d8-4454-ab61-32791c6f5ed7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362253134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1362253134 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.4226838383 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 5684604205 ps |
| CPU time | 689.87 seconds |
| Started | Aug 09 07:58:09 PM PDT 24 |
| Finished | Aug 09 08:09:39 PM PDT 24 |
| Peak memory | 577096 kb |
| Host | smart-dc03b598-f0e2-4331-90f1-1e4b8cfd0d49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226838383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.4226838383 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2892891937 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 8670928643 ps |
| CPU time | 381.85 seconds |
| Started | Aug 09 07:58:13 PM PDT 24 |
| Finished | Aug 09 08:04:35 PM PDT 24 |
| Peak memory | 577176 kb |
| Host | smart-2aceb7ad-7549-4684-9e97-bf2795f8ae8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892891937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.2892891937 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3248265452 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 320599546 ps |
| CPU time | 30.09 seconds |
| Started | Aug 09 07:58:06 PM PDT 24 |
| Finished | Aug 09 07:58:36 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-3589b5a2-2a91-4b35-b710-f98414c99003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248265452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3248265452 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.641535224 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 217024393 ps |
| CPU time | 21.02 seconds |
| Started | Aug 09 08:10:37 PM PDT 24 |
| Finished | Aug 09 08:10:58 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-9fd8f6fb-0806-4315-b675-b8f785ccc4fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641535224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device. 641535224 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3608906644 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 108582155336 ps |
| CPU time | 2033.12 seconds |
| Started | Aug 09 08:10:37 PM PDT 24 |
| Finished | Aug 09 08:44:31 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-1a744035-45b2-420f-99f6-9e58f46de56e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608906644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.3608906644 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.4021410058 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 217111119 ps |
| CPU time | 23.41 seconds |
| Started | Aug 09 08:10:41 PM PDT 24 |
| Finished | Aug 09 08:11:05 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-7477dc68-a148-42e8-a4b5-0d8560e66813 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021410058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.4021410058 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.3136974329 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 2483440530 ps |
| CPU time | 80.55 seconds |
| Started | Aug 09 08:10:36 PM PDT 24 |
| Finished | Aug 09 08:11:57 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-d31145a5-a743-4cce-8e25-8a18c60143dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136974329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.3136974329 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.2446650999 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2246748719 ps |
| CPU time | 74.13 seconds |
| Started | Aug 09 08:10:37 PM PDT 24 |
| Finished | Aug 09 08:11:52 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-a941f77a-11a2-499d-8472-36e6e28bba7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446650999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.2446650999 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3514229489 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 12425412323 ps |
| CPU time | 125.18 seconds |
| Started | Aug 09 08:10:34 PM PDT 24 |
| Finished | Aug 09 08:12:40 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-6a837414-c4a7-4b6c-82c2-40e5683117fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514229489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.3514229489 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.2313782542 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 12842068996 ps |
| CPU time | 209.1 seconds |
| Started | Aug 09 08:10:34 PM PDT 24 |
| Finished | Aug 09 08:14:03 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-c2cc1936-3225-4a3c-a3d9-5e1b9ebb4455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313782542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.2313782542 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.3374579696 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 583947176 ps |
| CPU time | 45.32 seconds |
| Started | Aug 09 08:10:34 PM PDT 24 |
| Finished | Aug 09 08:11:20 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-9076ccf4-c4e5-40a4-90c7-a5c278d898e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374579696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.3374579696 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.1267795238 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1119456560 ps |
| CPU time | 34.02 seconds |
| Started | Aug 09 08:10:36 PM PDT 24 |
| Finished | Aug 09 08:11:10 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-c445082e-7fbf-4b7d-a2ce-81d7d12d8e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267795238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.1267795238 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.3222455914 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 53062321 ps |
| CPU time | 6.25 seconds |
| Started | Aug 09 08:10:36 PM PDT 24 |
| Finished | Aug 09 08:10:42 PM PDT 24 |
| Peak memory | 574844 kb |
| Host | smart-b6de9c39-879d-42a9-9c7f-bc25a6bd3179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222455914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.3222455914 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.2802432704 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 5708864305 ps |
| CPU time | 61.72 seconds |
| Started | Aug 09 08:10:37 PM PDT 24 |
| Finished | Aug 09 08:11:39 PM PDT 24 |
| Peak memory | 575076 kb |
| Host | smart-56093ee4-922a-491e-94c2-11fa369db517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802432704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.2802432704 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.344286950 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 4601312410 ps |
| CPU time | 76.41 seconds |
| Started | Aug 09 08:10:34 PM PDT 24 |
| Finished | Aug 09 08:11:51 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-f28f9d27-fe60-4233-b090-9b950172f518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344286950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.344286950 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2580993546 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 37050822 ps |
| CPU time | 5.87 seconds |
| Started | Aug 09 08:10:36 PM PDT 24 |
| Finished | Aug 09 08:10:42 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-c7bb23a5-4964-458f-8d58-8d59b3a8f106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580993546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.2580993546 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.178909905 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 15377269548 ps |
| CPU time | 617.63 seconds |
| Started | Aug 09 08:10:41 PM PDT 24 |
| Finished | Aug 09 08:20:59 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-9afaeb99-685a-479e-be9e-202c08232e3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178909905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.178909905 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.486895570 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 4790498593 ps |
| CPU time | 375.12 seconds |
| Started | Aug 09 08:10:44 PM PDT 24 |
| Finished | Aug 09 08:16:59 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-457334fc-d364-4dc3-8d75-0303123b5b3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486895570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.486895570 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.907978617 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 4301718065 ps |
| CPU time | 515.39 seconds |
| Started | Aug 09 08:10:41 PM PDT 24 |
| Finished | Aug 09 08:19:16 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-966ea45f-8913-4beb-b445-8d8dc9d73afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907978617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_ with_rand_reset.907978617 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.4091184454 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 7104738048 ps |
| CPU time | 295.29 seconds |
| Started | Aug 09 08:10:41 PM PDT 24 |
| Finished | Aug 09 08:15:36 PM PDT 24 |
| Peak memory | 577152 kb |
| Host | smart-cb068b05-1b29-42b6-a00f-dce09d46d0f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091184454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.4091184454 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.461776686 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 1057156360 ps |
| CPU time | 45.69 seconds |
| Started | Aug 09 08:10:40 PM PDT 24 |
| Finished | Aug 09 08:11:26 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-89795f58-372f-4dee-bd80-59f968c3b9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461776686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.461776686 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.2603915407 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 1147796832 ps |
| CPU time | 45.63 seconds |
| Started | Aug 09 08:10:41 PM PDT 24 |
| Finished | Aug 09 08:11:27 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-0583d878-91b1-4446-8eaf-8495fc346299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603915407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .2603915407 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3209040223 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 145618365329 ps |
| CPU time | 2598.79 seconds |
| Started | Aug 09 08:10:40 PM PDT 24 |
| Finished | Aug 09 08:53:59 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-209c93e6-6e98-4b2b-a74b-da7a786ceae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209040223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.3209040223 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2210718809 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 800213950 ps |
| CPU time | 33.34 seconds |
| Started | Aug 09 08:10:42 PM PDT 24 |
| Finished | Aug 09 08:11:16 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-d9a6011c-e405-4e9f-9146-b7a48923b206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210718809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.2210718809 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.2116232046 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 1012619202 ps |
| CPU time | 33.12 seconds |
| Started | Aug 09 08:10:44 PM PDT 24 |
| Finished | Aug 09 08:11:17 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-e6c62002-5f33-49c8-ada3-f85eca207b6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116232046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.2116232046 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.2738338213 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 1020544655 ps |
| CPU time | 34.48 seconds |
| Started | Aug 09 08:10:44 PM PDT 24 |
| Finished | Aug 09 08:11:18 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-3af7b119-914d-4634-a4bc-64f65fe94120 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738338213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.2738338213 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3131672314 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 23221908777 ps |
| CPU time | 245.76 seconds |
| Started | Aug 09 08:10:42 PM PDT 24 |
| Finished | Aug 09 08:14:47 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-69c18862-182a-4e8b-9972-b37edaf0ece7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131672314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.3131672314 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.2842769717 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 24152398752 ps |
| CPU time | 448.65 seconds |
| Started | Aug 09 08:10:44 PM PDT 24 |
| Finished | Aug 09 08:18:13 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-ad494888-c850-45ab-a7b2-c6554e45bc45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842769717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.2842769717 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.21870342 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 236988416 ps |
| CPU time | 21.91 seconds |
| Started | Aug 09 08:10:41 PM PDT 24 |
| Finished | Aug 09 08:11:03 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-9384431e-b1c4-48a4-b4d7-c4feb26021b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21870342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_delay s.21870342 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.3891528237 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 2021862736 ps |
| CPU time | 63.04 seconds |
| Started | Aug 09 08:10:43 PM PDT 24 |
| Finished | Aug 09 08:11:46 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-a778fd95-375b-4f7d-ad13-9724f60a035a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891528237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3891528237 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.3339335775 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 39839617 ps |
| CPU time | 5.95 seconds |
| Started | Aug 09 08:10:43 PM PDT 24 |
| Finished | Aug 09 08:10:49 PM PDT 24 |
| Peak memory | 574844 kb |
| Host | smart-d82c41c1-0909-46d1-a54c-d8466c44ed8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339335775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.3339335775 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.1589479514 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 8875822203 ps |
| CPU time | 86.86 seconds |
| Started | Aug 09 08:10:42 PM PDT 24 |
| Finished | Aug 09 08:12:09 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-a36e39e6-484f-4b91-b3e6-b4e0c82ea526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589479514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.1589479514 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.441644526 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 4570915377 ps |
| CPU time | 77.04 seconds |
| Started | Aug 09 08:10:41 PM PDT 24 |
| Finished | Aug 09 08:11:58 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-f5f5c307-3cd0-452a-9ec7-53e7380719c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441644526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.441644526 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.371438632 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 41724821 ps |
| CPU time | 5.63 seconds |
| Started | Aug 09 08:10:44 PM PDT 24 |
| Finished | Aug 09 08:10:50 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-7888f615-da10-4356-9545-b20a9a0ba6df |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371438632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays .371438632 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.4190724450 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 2904094479 ps |
| CPU time | 244.2 seconds |
| Started | Aug 09 08:10:47 PM PDT 24 |
| Finished | Aug 09 08:14:51 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-74dad3ae-2a56-4836-99b5-3a9d7a9220f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190724450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.4190724450 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.370136413 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 7680033738 ps |
| CPU time | 233.54 seconds |
| Started | Aug 09 08:10:52 PM PDT 24 |
| Finished | Aug 09 08:14:46 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-ef6806a8-9a53-45ea-8b0b-8b5dc0c7fc5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370136413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.370136413 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.21182487 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 391048430 ps |
| CPU time | 61.87 seconds |
| Started | Aug 09 08:10:47 PM PDT 24 |
| Finished | Aug 09 08:11:49 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-6af764e3-ffff-49e3-bf80-ab24adb2b29b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21182487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_w ith_rand_reset.21182487 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3966449012 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 164637818 ps |
| CPU time | 47.89 seconds |
| Started | Aug 09 08:10:52 PM PDT 24 |
| Finished | Aug 09 08:11:40 PM PDT 24 |
| Peak memory | 577048 kb |
| Host | smart-f00d55df-cb72-42fa-a479-dfa34d48ca20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966449012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.3966449012 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.436722271 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 79374535 ps |
| CPU time | 11.36 seconds |
| Started | Aug 09 08:10:41 PM PDT 24 |
| Finished | Aug 09 08:10:52 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-43ead51e-11b5-4162-a47a-11bee83e8233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436722271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.436722271 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.2134183084 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 338907849 ps |
| CPU time | 15.47 seconds |
| Started | Aug 09 08:10:52 PM PDT 24 |
| Finished | Aug 09 08:11:07 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-1a79da48-32b3-4166-b5f3-3c86cd498df8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134183084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .2134183084 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.3447954780 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 73615739850 ps |
| CPU time | 1460.53 seconds |
| Started | Aug 09 08:10:54 PM PDT 24 |
| Finished | Aug 09 08:35:14 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-a5f1fca4-a872-4ede-a2b1-502335f57df4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447954780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.3447954780 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.3474194673 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 806793553 ps |
| CPU time | 27.1 seconds |
| Started | Aug 09 08:10:57 PM PDT 24 |
| Finished | Aug 09 08:11:24 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-2fa4d6cc-c290-46d1-b7fd-aa94557ec314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474194673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.3474194673 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.2456403412 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 476730564 ps |
| CPU time | 37.17 seconds |
| Started | Aug 09 08:10:53 PM PDT 24 |
| Finished | Aug 09 08:11:31 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-b2383be7-fb1c-44d0-9317-3e1ac2781f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456403412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2456403412 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.1080349709 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 599165397 ps |
| CPU time | 48.57 seconds |
| Started | Aug 09 08:10:53 PM PDT 24 |
| Finished | Aug 09 08:11:42 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-1835ef3f-69a2-4a29-a1fc-91947d8e09c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080349709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.1080349709 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.1152965330 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 44537306904 ps |
| CPU time | 481.46 seconds |
| Started | Aug 09 08:10:54 PM PDT 24 |
| Finished | Aug 09 08:18:56 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-7fcd38ca-6f4e-4a88-877d-aa4f58642f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152965330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.1152965330 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.374879334 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 67085712600 ps |
| CPU time | 1202.63 seconds |
| Started | Aug 09 08:10:54 PM PDT 24 |
| Finished | Aug 09 08:30:57 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-6fb5f073-73ef-4850-9c33-38e403bad09d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374879334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.374879334 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.743329686 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 458522210 ps |
| CPU time | 34.62 seconds |
| Started | Aug 09 08:10:53 PM PDT 24 |
| Finished | Aug 09 08:11:28 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-ee07063a-3f9f-4226-ad02-3c3002ccc570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743329686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_dela ys.743329686 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.1915554637 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 618945976 ps |
| CPU time | 19.89 seconds |
| Started | Aug 09 08:10:53 PM PDT 24 |
| Finished | Aug 09 08:11:13 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-0d14b580-7a12-4a89-97e5-702a98958eb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915554637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.1915554637 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.282243349 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 170855713 ps |
| CPU time | 7.67 seconds |
| Started | Aug 09 08:10:47 PM PDT 24 |
| Finished | Aug 09 08:10:55 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-efb13c59-70e6-4c06-9a13-dcc13766265a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282243349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.282243349 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.1469772024 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 9035612403 ps |
| CPU time | 98.91 seconds |
| Started | Aug 09 08:10:54 PM PDT 24 |
| Finished | Aug 09 08:12:33 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-38aff333-d3f9-4a27-9988-b893fcd63e30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469772024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.1469772024 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.2707699181 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 5113492234 ps |
| CPU time | 84.2 seconds |
| Started | Aug 09 08:10:52 PM PDT 24 |
| Finished | Aug 09 08:12:16 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-748fbd03-e9c8-44d7-94e4-e618bb72227a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707699181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.2707699181 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.840321353 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 39514013 ps |
| CPU time | 5.48 seconds |
| Started | Aug 09 08:10:53 PM PDT 24 |
| Finished | Aug 09 08:10:59 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-b90ff6a4-1aac-4362-944e-1037d7cab804 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840321353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delays .840321353 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.1372252699 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 4327500911 ps |
| CPU time | 399.57 seconds |
| Started | Aug 09 08:10:58 PM PDT 24 |
| Finished | Aug 09 08:17:38 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-82d3eac7-9f57-434e-a811-a43df4ce8f40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372252699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.1372252699 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.1772157230 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 2635939112 ps |
| CPU time | 199.49 seconds |
| Started | Aug 09 08:10:57 PM PDT 24 |
| Finished | Aug 09 08:14:17 PM PDT 24 |
| Peak memory | 577096 kb |
| Host | smart-7f8d2302-e9e7-4bef-a64a-380d39d827de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772157230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.1772157230 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.299804461 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1658669212 ps |
| CPU time | 209.4 seconds |
| Started | Aug 09 08:10:59 PM PDT 24 |
| Finished | Aug 09 08:14:29 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-af8fd5dc-68a5-48ba-a2c0-df20e34dd365 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299804461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_reset_error.299804461 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.598979277 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 115871067 ps |
| CPU time | 16.62 seconds |
| Started | Aug 09 08:10:54 PM PDT 24 |
| Finished | Aug 09 08:11:11 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-606fde29-418e-4fd4-a8b6-b4d52469145f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598979277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.598979277 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.2402861619 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 2796706628 ps |
| CPU time | 95.37 seconds |
| Started | Aug 09 08:11:06 PM PDT 24 |
| Finished | Aug 09 08:12:41 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-e42fbdaa-84f3-431c-8ed7-f7ca7fa693ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402861619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .2402861619 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.157166033 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 61277614666 ps |
| CPU time | 1010.46 seconds |
| Started | Aug 09 08:11:03 PM PDT 24 |
| Finished | Aug 09 08:27:53 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-80bdf703-635c-4702-b2e8-5f75fa24b038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157166033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_d evice_slow_rsp.157166033 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3759201994 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 586668601 ps |
| CPU time | 25.99 seconds |
| Started | Aug 09 08:11:04 PM PDT 24 |
| Finished | Aug 09 08:11:31 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-08c30fcd-fc12-4df6-91c3-9cc41fd0c773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759201994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.3759201994 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.1929004896 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 355819141 ps |
| CPU time | 27.2 seconds |
| Started | Aug 09 08:11:05 PM PDT 24 |
| Finished | Aug 09 08:11:32 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-73d1e45a-1e35-4d88-af24-f54b4c41c2fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929004896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1929004896 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.2841951494 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 461367947 ps |
| CPU time | 36.65 seconds |
| Started | Aug 09 08:11:00 PM PDT 24 |
| Finished | Aug 09 08:11:37 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-50ba6ecc-3144-4395-beeb-dc9e65b3246a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841951494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.2841951494 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.3335399714 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 18858728111 ps |
| CPU time | 187.92 seconds |
| Started | Aug 09 08:11:03 PM PDT 24 |
| Finished | Aug 09 08:14:11 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-5608e2e4-d0d2-4abf-8232-9ebe23b282bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335399714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.3335399714 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.858782658 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 12894346150 ps |
| CPU time | 211.01 seconds |
| Started | Aug 09 08:11:04 PM PDT 24 |
| Finished | Aug 09 08:14:35 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-7bb0a563-6bea-4bea-850f-f05e5d26807f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858782658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.858782658 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.4213731248 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 238543146 ps |
| CPU time | 23.9 seconds |
| Started | Aug 09 08:11:05 PM PDT 24 |
| Finished | Aug 09 08:11:29 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-b0d51dd0-6eff-403b-81bf-f11e46c77b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213731248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.4213731248 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.1135383671 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 268531885 ps |
| CPU time | 20.25 seconds |
| Started | Aug 09 08:11:03 PM PDT 24 |
| Finished | Aug 09 08:11:24 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-11aba3e8-3123-45a0-96e5-0ca4fc6f3c40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135383671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.1135383671 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.1034683221 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 209843233 ps |
| CPU time | 8.71 seconds |
| Started | Aug 09 08:11:01 PM PDT 24 |
| Finished | Aug 09 08:11:10 PM PDT 24 |
| Peak memory | 574792 kb |
| Host | smart-69ae144c-9e98-4a3c-8f3d-2d2c26c3ccc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034683221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.1034683221 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.581829664 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 6971312718 ps |
| CPU time | 76.88 seconds |
| Started | Aug 09 08:10:58 PM PDT 24 |
| Finished | Aug 09 08:12:15 PM PDT 24 |
| Peak memory | 574908 kb |
| Host | smart-5bdd2f02-f069-4f4d-aec1-7cfd08f5007d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581829664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.581829664 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.2685028254 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 6095662879 ps |
| CPU time | 98.15 seconds |
| Started | Aug 09 08:11:01 PM PDT 24 |
| Finished | Aug 09 08:12:39 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-42f68f40-758d-489d-a688-1a2daf5238c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685028254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.2685028254 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.1770856790 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 48335100 ps |
| CPU time | 6.12 seconds |
| Started | Aug 09 08:10:59 PM PDT 24 |
| Finished | Aug 09 08:11:05 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-ec94c084-ccc0-49f0-b593-60b66892db5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770856790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.1770856790 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.1697348387 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 402204836 ps |
| CPU time | 28.53 seconds |
| Started | Aug 09 08:11:05 PM PDT 24 |
| Finished | Aug 09 08:11:34 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-b462a6c2-fb52-4df0-847b-ef72d498484b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697348387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.1697348387 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.2783616108 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 1730494364 ps |
| CPU time | 146.46 seconds |
| Started | Aug 09 08:11:11 PM PDT 24 |
| Finished | Aug 09 08:13:37 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-118e01a3-75ee-4bbc-8f39-1b5cbf48b03e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783616108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.2783616108 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.156434287 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 7715929108 ps |
| CPU time | 648.7 seconds |
| Started | Aug 09 08:11:04 PM PDT 24 |
| Finished | Aug 09 08:21:53 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-b1425a1b-cefa-4e63-b686-42559f1303fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156434287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_ with_rand_reset.156434287 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.4164600595 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 4765818119 ps |
| CPU time | 327.42 seconds |
| Started | Aug 09 08:11:04 PM PDT 24 |
| Finished | Aug 09 08:16:32 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-bbe58928-580e-4039-bfc1-972f9148f727 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164600595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.4164600595 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.741985661 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 374130986 ps |
| CPU time | 18.66 seconds |
| Started | Aug 09 08:11:04 PM PDT 24 |
| Finished | Aug 09 08:11:23 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-7fe41864-5572-4a2a-9def-4ab9367627d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741985661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.741985661 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.1263876871 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 206219583 ps |
| CPU time | 14.97 seconds |
| Started | Aug 09 08:11:11 PM PDT 24 |
| Finished | Aug 09 08:11:26 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-b5534faa-d259-4b35-a455-e64f7d8f7183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263876871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .1263876871 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.900968153 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 118084462876 ps |
| CPU time | 2135.05 seconds |
| Started | Aug 09 08:11:14 PM PDT 24 |
| Finished | Aug 09 08:46:50 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-0ab04508-5dc6-4bdd-8ec4-8100fda622a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900968153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_d evice_slow_rsp.900968153 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1049892932 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 1285352210 ps |
| CPU time | 51.66 seconds |
| Started | Aug 09 08:11:20 PM PDT 24 |
| Finished | Aug 09 08:12:12 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-bee9d40a-7a7a-4922-a981-939ca295824f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049892932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.1049892932 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.835784570 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 1257833021 ps |
| CPU time | 43.61 seconds |
| Started | Aug 09 08:11:11 PM PDT 24 |
| Finished | Aug 09 08:11:55 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-0ee79f6c-4807-44ed-8fff-ed681ec9a0c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835784570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.835784570 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.3748142494 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1880233966 ps |
| CPU time | 79.5 seconds |
| Started | Aug 09 08:11:12 PM PDT 24 |
| Finished | Aug 09 08:12:31 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-ff893d41-a16f-4baf-9fac-7a581ae6dacb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748142494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.3748142494 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.3083981906 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 51238063932 ps |
| CPU time | 554.67 seconds |
| Started | Aug 09 08:11:14 PM PDT 24 |
| Finished | Aug 09 08:20:28 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-a7b1dca9-5c68-4760-8fe4-04560154a047 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083981906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.3083981906 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.4095040374 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 3932601940 ps |
| CPU time | 64.48 seconds |
| Started | Aug 09 08:11:15 PM PDT 24 |
| Finished | Aug 09 08:12:19 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-7ccbbfb6-0a52-40bf-a7cf-6998d49c4b7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095040374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.4095040374 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.2209734977 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 321934000 ps |
| CPU time | 27.21 seconds |
| Started | Aug 09 08:11:11 PM PDT 24 |
| Finished | Aug 09 08:11:38 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-eafa7f8d-5c21-4b68-96d4-649bd8821a70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209734977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.2209734977 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.3028909221 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 1284400579 ps |
| CPU time | 34.39 seconds |
| Started | Aug 09 08:11:12 PM PDT 24 |
| Finished | Aug 09 08:11:46 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-f025cffe-bced-493a-adfd-2a6d5f662176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028909221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3028909221 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.930289119 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 41077547 ps |
| CPU time | 5.81 seconds |
| Started | Aug 09 08:11:16 PM PDT 24 |
| Finished | Aug 09 08:11:22 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-15cdc266-7033-4aba-ab78-401b3264c892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930289119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.930289119 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.400109430 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 7741495261 ps |
| CPU time | 79.31 seconds |
| Started | Aug 09 08:11:13 PM PDT 24 |
| Finished | Aug 09 08:12:32 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-8e45bc25-6363-49ca-ab51-ecc4a312d585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400109430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.400109430 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.467198662 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 4817371278 ps |
| CPU time | 79.68 seconds |
| Started | Aug 09 08:11:13 PM PDT 24 |
| Finished | Aug 09 08:12:33 PM PDT 24 |
| Peak memory | 574908 kb |
| Host | smart-e0518bd9-312b-4170-8a82-c8ec131ab98b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467198662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.467198662 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.1723658934 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 40016665 ps |
| CPU time | 5.58 seconds |
| Started | Aug 09 08:11:12 PM PDT 24 |
| Finished | Aug 09 08:11:18 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-a833b421-81de-48a8-8803-d52c0aa969c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723658934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.1723658934 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.2209766361 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 5280851808 ps |
| CPU time | 207.43 seconds |
| Started | Aug 09 08:11:14 PM PDT 24 |
| Finished | Aug 09 08:14:42 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-fd76114f-8208-4277-ab12-1cc6c9fbad6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209766361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.2209766361 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.567935083 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2593702588 ps |
| CPU time | 205.69 seconds |
| Started | Aug 09 08:11:15 PM PDT 24 |
| Finished | Aug 09 08:14:41 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-1f3b397a-1ee1-43f9-bedd-23fe9b471d11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567935083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.567935083 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.1919569288 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 4271833649 ps |
| CPU time | 557.1 seconds |
| Started | Aug 09 08:11:18 PM PDT 24 |
| Finished | Aug 09 08:20:35 PM PDT 24 |
| Peak memory | 577164 kb |
| Host | smart-ed578157-3917-444f-91ca-b35d541caa5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919569288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.1919569288 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3939821732 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 4502909578 ps |
| CPU time | 561.13 seconds |
| Started | Aug 09 08:11:16 PM PDT 24 |
| Finished | Aug 09 08:20:38 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-e4b6fa54-4f86-46bc-bbd2-dfba1dbba74a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939821732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.3939821732 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.3942950667 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 1217993566 ps |
| CPU time | 45.12 seconds |
| Started | Aug 09 08:11:10 PM PDT 24 |
| Finished | Aug 09 08:11:55 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-46975bb1-9874-4699-b9b4-2db487db8ac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942950667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.3942950667 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.2373804485 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 3164247480 ps |
| CPU time | 113.24 seconds |
| Started | Aug 09 08:11:23 PM PDT 24 |
| Finished | Aug 09 08:13:16 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-28912c45-9319-4dd8-a957-2de37c6278e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373804485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .2373804485 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1547645949 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 9587172460 ps |
| CPU time | 169.24 seconds |
| Started | Aug 09 08:11:23 PM PDT 24 |
| Finished | Aug 09 08:14:13 PM PDT 24 |
| Peak memory | 574904 kb |
| Host | smart-8d42ffeb-f1e4-4207-9084-6015b16f4c24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547645949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.1547645949 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.976498061 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 1173990192 ps |
| CPU time | 41.54 seconds |
| Started | Aug 09 08:11:21 PM PDT 24 |
| Finished | Aug 09 08:12:02 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-606211a2-b7b8-4174-9734-2bbb58af7c27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976498061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_addr .976498061 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.3315629696 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 1101857414 ps |
| CPU time | 37.53 seconds |
| Started | Aug 09 08:11:24 PM PDT 24 |
| Finished | Aug 09 08:12:02 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-194e9cf5-c6fb-41c2-9cc0-0e15dc8beb49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315629696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3315629696 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.1636185773 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 1382282210 ps |
| CPU time | 44.7 seconds |
| Started | Aug 09 08:11:20 PM PDT 24 |
| Finished | Aug 09 08:12:05 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-00e2958d-d60b-41fa-9ea7-204fc1358fb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636185773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.1636185773 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.2569241153 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 42650741453 ps |
| CPU time | 479.4 seconds |
| Started | Aug 09 08:11:23 PM PDT 24 |
| Finished | Aug 09 08:19:22 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-52ad27c3-f305-42fd-b3d0-f571f58763a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569241153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.2569241153 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.346471837 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 60324008352 ps |
| CPU time | 1080.94 seconds |
| Started | Aug 09 08:11:21 PM PDT 24 |
| Finished | Aug 09 08:29:22 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-2ca2b2b6-dff7-4e43-9488-c61978d62e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346471837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.346471837 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.1179436075 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 216532451 ps |
| CPU time | 21.79 seconds |
| Started | Aug 09 08:11:18 PM PDT 24 |
| Finished | Aug 09 08:11:40 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-5864c249-f388-4d65-895d-dcfec641a7e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179436075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.1179436075 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.1472961274 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 761154298 ps |
| CPU time | 23.66 seconds |
| Started | Aug 09 08:11:24 PM PDT 24 |
| Finished | Aug 09 08:11:47 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-eb1d1ecd-b0b4-4537-b701-d8984c60a105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472961274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.1472961274 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.789110109 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 207401344 ps |
| CPU time | 8.38 seconds |
| Started | Aug 09 08:11:17 PM PDT 24 |
| Finished | Aug 09 08:11:26 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-a4837f7e-59af-4640-9d3c-aef857a4c292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789110109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.789110109 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.3371931971 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 7613298514 ps |
| CPU time | 76.17 seconds |
| Started | Aug 09 08:11:17 PM PDT 24 |
| Finished | Aug 09 08:12:33 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-a3c542d4-0ac1-4312-877e-0488d60f750f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371931971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.3371931971 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.3219950827 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 5167031724 ps |
| CPU time | 82.1 seconds |
| Started | Aug 09 08:11:18 PM PDT 24 |
| Finished | Aug 09 08:12:40 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-5cd2dce8-e323-47cd-83e2-24166d24041d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219950827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.3219950827 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.598448216 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 36343567 ps |
| CPU time | 5.77 seconds |
| Started | Aug 09 08:11:18 PM PDT 24 |
| Finished | Aug 09 08:11:23 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-0dbf9fa2-aaad-4269-9af3-030dfdb11de7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598448216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays .598448216 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.2581811806 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 4323601614 ps |
| CPU time | 151.61 seconds |
| Started | Aug 09 08:11:21 PM PDT 24 |
| Finished | Aug 09 08:13:53 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-4ee14122-cd81-4114-8723-fea32a2efc07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581811806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.2581811806 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.3210254925 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 2224567273 ps |
| CPU time | 171.77 seconds |
| Started | Aug 09 08:11:29 PM PDT 24 |
| Finished | Aug 09 08:14:21 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-6fafb33b-78e1-4c4e-8af8-e54b3e8e8b6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210254925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.3210254925 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3829056587 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 695528767 ps |
| CPU time | 181.82 seconds |
| Started | Aug 09 08:11:22 PM PDT 24 |
| Finished | Aug 09 08:14:24 PM PDT 24 |
| Peak memory | 577092 kb |
| Host | smart-b8ac2092-adc6-4707-a868-88c985aabddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829056587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.3829056587 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1146538990 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 259448895 ps |
| CPU time | 56.2 seconds |
| Started | Aug 09 08:11:30 PM PDT 24 |
| Finished | Aug 09 08:12:26 PM PDT 24 |
| Peak memory | 577072 kb |
| Host | smart-7641a5c9-d71c-4d68-939f-991152cbbcf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146538990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.1146538990 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.1075129628 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 774306830 ps |
| CPU time | 33.62 seconds |
| Started | Aug 09 08:11:23 PM PDT 24 |
| Finished | Aug 09 08:11:57 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-f01c07f3-ecc4-4aca-8cc5-b9ed7936bb57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075129628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.1075129628 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.3463727486 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 958500621 ps |
| CPU time | 71.22 seconds |
| Started | Aug 09 08:11:30 PM PDT 24 |
| Finished | Aug 09 08:12:41 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-4a111771-3e54-4e17-8f78-310d33b9e02f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463727486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .3463727486 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1910687747 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 79510785110 ps |
| CPU time | 1491.81 seconds |
| Started | Aug 09 08:11:32 PM PDT 24 |
| Finished | Aug 09 08:36:24 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-add8c735-b8e0-4f17-94d6-246a10670f17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910687747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.1910687747 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3317572973 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 1334247914 ps |
| CPU time | 49.21 seconds |
| Started | Aug 09 08:11:40 PM PDT 24 |
| Finished | Aug 09 08:12:29 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-ab926d50-c65b-4888-b58e-2d55dbbb20e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317572973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.3317572973 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.3731565864 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 288246783 ps |
| CPU time | 25.6 seconds |
| Started | Aug 09 08:11:37 PM PDT 24 |
| Finished | Aug 09 08:12:03 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-b2851504-1074-4bfe-a3ae-f2bb84d68b74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731565864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.3731565864 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.1298508090 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 1398815830 ps |
| CPU time | 50.62 seconds |
| Started | Aug 09 08:11:29 PM PDT 24 |
| Finished | Aug 09 08:12:20 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-555041f8-cc96-44f6-892f-36c01972cac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298508090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1298508090 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.272660087 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 25600146882 ps |
| CPU time | 266.98 seconds |
| Started | Aug 09 08:11:33 PM PDT 24 |
| Finished | Aug 09 08:16:00 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-72253f7e-7ed9-47ef-bf3f-ae6b831468d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272660087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.272660087 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1956145193 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 30817959111 ps |
| CPU time | 513.67 seconds |
| Started | Aug 09 08:11:30 PM PDT 24 |
| Finished | Aug 09 08:20:04 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-1d5a70b4-ad0c-45e1-9b1a-17deeb6d9806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956145193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1956145193 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2397276805 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 143572158 ps |
| CPU time | 14.19 seconds |
| Started | Aug 09 08:11:28 PM PDT 24 |
| Finished | Aug 09 08:11:42 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-ccc33f2b-7f94-45e1-9dda-dccd1870a261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397276805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.2397276805 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.1133381369 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 209125714 ps |
| CPU time | 17.98 seconds |
| Started | Aug 09 08:11:38 PM PDT 24 |
| Finished | Aug 09 08:11:56 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-f48a0b22-711d-4ab9-892a-6e931127b387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133381369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.1133381369 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.2772786352 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 44044425 ps |
| CPU time | 6.11 seconds |
| Started | Aug 09 08:11:31 PM PDT 24 |
| Finished | Aug 09 08:11:37 PM PDT 24 |
| Peak memory | 574860 kb |
| Host | smart-ea8ab1eb-5a9e-4702-8a65-aae9bd1a0d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772786352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.2772786352 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.1140466701 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 7095763085 ps |
| CPU time | 74.98 seconds |
| Started | Aug 09 08:11:30 PM PDT 24 |
| Finished | Aug 09 08:12:45 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-eb0b7191-2793-4707-aa24-e035ec3b8277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140466701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.1140466701 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.490065432 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 5856305729 ps |
| CPU time | 101.41 seconds |
| Started | Aug 09 08:11:28 PM PDT 24 |
| Finished | Aug 09 08:13:10 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-fd5c6263-a5fa-45f7-a2d9-3b57f85ad368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490065432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.490065432 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3188982837 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 47265347 ps |
| CPU time | 6.43 seconds |
| Started | Aug 09 08:11:34 PM PDT 24 |
| Finished | Aug 09 08:11:40 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-6e0d642b-a00d-494d-8e47-2d1f41a7a784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188982837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.3188982837 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.3080684166 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 12457927341 ps |
| CPU time | 432.53 seconds |
| Started | Aug 09 08:11:35 PM PDT 24 |
| Finished | Aug 09 08:18:47 PM PDT 24 |
| Peak memory | 577132 kb |
| Host | smart-7a169e5b-424e-469f-a586-bc746a6dc719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080684166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.3080684166 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3291509623 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 8232274278 ps |
| CPU time | 295.92 seconds |
| Started | Aug 09 08:11:40 PM PDT 24 |
| Finished | Aug 09 08:16:37 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-6cc64864-9f9b-48e8-b942-96f27eea6ca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291509623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.3291509623 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.1992068048 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 491529966 ps |
| CPU time | 264.43 seconds |
| Started | Aug 09 08:11:36 PM PDT 24 |
| Finished | Aug 09 08:16:01 PM PDT 24 |
| Peak memory | 577092 kb |
| Host | smart-12b577ea-663f-4a49-99e1-71f4ce91dc2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992068048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.1992068048 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2906842368 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 1355783383 ps |
| CPU time | 106.67 seconds |
| Started | Aug 09 08:11:40 PM PDT 24 |
| Finished | Aug 09 08:13:27 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-26d3370b-49af-42ff-9476-b302bce3d1bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906842368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.2906842368 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2065686969 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 135120882 ps |
| CPU time | 18.2 seconds |
| Started | Aug 09 08:11:35 PM PDT 24 |
| Finished | Aug 09 08:11:53 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-68de6b77-3e2e-4e35-af28-35c4c71a6e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065686969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2065686969 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.2944153015 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 278494026 ps |
| CPU time | 11.64 seconds |
| Started | Aug 09 08:11:39 PM PDT 24 |
| Finished | Aug 09 08:11:51 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-6ff0d6b6-a51e-49d0-a252-9c0fbcece269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944153015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .2944153015 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.2894377623 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 95471097989 ps |
| CPU time | 1742.21 seconds |
| Started | Aug 09 08:11:41 PM PDT 24 |
| Finished | Aug 09 08:40:43 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-d6079799-8ff8-449f-b5a9-25a9198413a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894377623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.2894377623 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.228121975 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 196250931 ps |
| CPU time | 20.76 seconds |
| Started | Aug 09 08:11:40 PM PDT 24 |
| Finished | Aug 09 08:12:01 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-f22e33e5-bb68-423a-bded-51c3d68353ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228121975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_addr .228121975 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.2442483991 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 268122775 ps |
| CPU time | 11.75 seconds |
| Started | Aug 09 08:11:43 PM PDT 24 |
| Finished | Aug 09 08:11:55 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-8fb2ec42-5aa1-44be-88c5-a79a4d4deca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442483991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.2442483991 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.750698345 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 1228467664 ps |
| CPU time | 38.57 seconds |
| Started | Aug 09 08:11:33 PM PDT 24 |
| Finished | Aug 09 08:12:12 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-db5e9a18-2497-4e31-bf6f-77259d270a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750698345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.750698345 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1058235154 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 55440767486 ps |
| CPU time | 570.67 seconds |
| Started | Aug 09 08:11:34 PM PDT 24 |
| Finished | Aug 09 08:21:05 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-a5944484-b637-4c37-9091-b8ce0a02e49c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058235154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1058235154 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.3425983101 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 23346626221 ps |
| CPU time | 423.68 seconds |
| Started | Aug 09 08:11:35 PM PDT 24 |
| Finished | Aug 09 08:18:39 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-789da63b-f77f-4479-a920-4110606230c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425983101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.3425983101 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.4243725003 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 532728782 ps |
| CPU time | 46.44 seconds |
| Started | Aug 09 08:11:36 PM PDT 24 |
| Finished | Aug 09 08:12:23 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-b413974d-90a1-48ad-b754-aba4af15b6a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243725003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.4243725003 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.2488311597 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 308329110 ps |
| CPU time | 24 seconds |
| Started | Aug 09 08:11:41 PM PDT 24 |
| Finished | Aug 09 08:12:05 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-22d5ec63-b489-4338-a9c5-f8cd355f17b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488311597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.2488311597 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.157156096 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 41013084 ps |
| CPU time | 5.99 seconds |
| Started | Aug 09 08:11:34 PM PDT 24 |
| Finished | Aug 09 08:11:40 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-2ee4e794-f893-4ff3-9fc8-e1b5bf8cef1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157156096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.157156096 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.2111937830 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 8043348854 ps |
| CPU time | 82.99 seconds |
| Started | Aug 09 08:11:35 PM PDT 24 |
| Finished | Aug 09 08:12:58 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-3d9f069b-2723-45b0-aa3d-0d46f8f96b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111937830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.2111937830 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.3801750277 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 4119656303 ps |
| CPU time | 65.01 seconds |
| Started | Aug 09 08:11:35 PM PDT 24 |
| Finished | Aug 09 08:12:41 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-fe5fe369-93f9-461a-89e4-0db6e84d346a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801750277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.3801750277 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1863940942 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 40795878 ps |
| CPU time | 5.85 seconds |
| Started | Aug 09 08:11:33 PM PDT 24 |
| Finished | Aug 09 08:11:39 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-a123596d-0b59-40bf-af6b-8268f8fa8e84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863940942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.1863940942 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.2453865014 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 3548754768 ps |
| CPU time | 289.45 seconds |
| Started | Aug 09 08:11:42 PM PDT 24 |
| Finished | Aug 09 08:16:32 PM PDT 24 |
| Peak memory | 577140 kb |
| Host | smart-df0580f8-fc4a-4371-a9ee-754a86348fee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453865014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2453865014 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3530359875 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 1648132122 ps |
| CPU time | 61.61 seconds |
| Started | Aug 09 08:11:41 PM PDT 24 |
| Finished | Aug 09 08:12:43 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-9c2e8652-2a0a-4e9d-aab2-88d600b15daf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530359875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3530359875 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1029708581 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 663849465 ps |
| CPU time | 175.86 seconds |
| Started | Aug 09 08:11:41 PM PDT 24 |
| Finished | Aug 09 08:14:37 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-d33ee171-c38f-40df-a53b-f1d783b8ffea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029708581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.1029708581 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3113896100 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 337541682 ps |
| CPU time | 96.98 seconds |
| Started | Aug 09 08:11:40 PM PDT 24 |
| Finished | Aug 09 08:13:17 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-5cbcc435-b1a8-4da1-8fe9-06663213ad33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113896100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.3113896100 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.1060254670 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 236355951 ps |
| CPU time | 26.37 seconds |
| Started | Aug 09 08:11:40 PM PDT 24 |
| Finished | Aug 09 08:12:06 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-3e756772-159a-4df0-88dc-7e0c7daf8528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060254670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.1060254670 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.1943763048 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 835488485 ps |
| CPU time | 62.25 seconds |
| Started | Aug 09 08:11:46 PM PDT 24 |
| Finished | Aug 09 08:12:49 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-6964bd7a-5d35-45e2-a1a1-3da8d78ef4ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943763048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .1943763048 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2427794735 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 41143541039 ps |
| CPU time | 819.62 seconds |
| Started | Aug 09 08:11:48 PM PDT 24 |
| Finished | Aug 09 08:25:27 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-b1923c02-72cf-46ae-83ac-724ce53452e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427794735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.2427794735 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.641526342 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 197963370 ps |
| CPU time | 21.05 seconds |
| Started | Aug 09 08:11:54 PM PDT 24 |
| Finished | Aug 09 08:12:15 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-6f289f3b-3597-4434-bc17-7700a2b7cca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641526342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr .641526342 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.4017055077 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 1060302853 ps |
| CPU time | 39.78 seconds |
| Started | Aug 09 08:11:56 PM PDT 24 |
| Finished | Aug 09 08:12:36 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-7be17d97-21ef-48aa-94e5-39a592e5c4b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017055077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.4017055077 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.551413901 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 1611391563 ps |
| CPU time | 59.93 seconds |
| Started | Aug 09 08:11:46 PM PDT 24 |
| Finished | Aug 09 08:12:46 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-54b97a77-7d3e-4f24-b3b2-64ff13160e2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551413901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.551413901 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3289611867 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 53579000329 ps |
| CPU time | 641.28 seconds |
| Started | Aug 09 08:11:48 PM PDT 24 |
| Finished | Aug 09 08:22:29 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-4a2fa3bc-f720-437f-98d5-dec1f0a83ecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289611867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.3289611867 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.948522247 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 61571300893 ps |
| CPU time | 1098.84 seconds |
| Started | Aug 09 08:11:47 PM PDT 24 |
| Finished | Aug 09 08:30:06 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-32848d47-4178-43c7-81d3-c048d89224cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948522247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.948522247 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.2386602516 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 487137043 ps |
| CPU time | 36.75 seconds |
| Started | Aug 09 08:11:46 PM PDT 24 |
| Finished | Aug 09 08:12:23 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-83c9b41e-0180-4825-8d0e-d72c37623ccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386602516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.2386602516 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.2164544896 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 733100293 ps |
| CPU time | 22.45 seconds |
| Started | Aug 09 08:11:55 PM PDT 24 |
| Finished | Aug 09 08:12:18 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-be95abcd-7caf-46f7-9c64-b83c39d4827c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164544896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.2164544896 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.2353597744 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 129691539 ps |
| CPU time | 7.55 seconds |
| Started | Aug 09 08:11:41 PM PDT 24 |
| Finished | Aug 09 08:11:48 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-76fe42d0-7e80-489e-a5c8-a0041de035d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353597744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.2353597744 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3942937561 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 6614920273 ps |
| CPU time | 67.83 seconds |
| Started | Aug 09 08:11:45 PM PDT 24 |
| Finished | Aug 09 08:12:53 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-45e41732-c851-400e-bd49-25be2757310e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942937561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3942937561 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.2201924807 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 7300641386 ps |
| CPU time | 125.28 seconds |
| Started | Aug 09 08:11:47 PM PDT 24 |
| Finished | Aug 09 08:13:52 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-6cf40353-9dea-48b2-bdcc-5c0f112b5130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201924807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.2201924807 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.3625437556 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 43896194 ps |
| CPU time | 6.16 seconds |
| Started | Aug 09 08:11:47 PM PDT 24 |
| Finished | Aug 09 08:11:53 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-7e0faeaf-b17a-421d-bbc1-1da89012a93f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625437556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.3625437556 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.3136427717 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 3774611030 ps |
| CPU time | 303.3 seconds |
| Started | Aug 09 08:11:51 PM PDT 24 |
| Finished | Aug 09 08:16:54 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-937209d9-0203-42c7-9ee6-aefc871d29bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136427717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.3136427717 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.134446843 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 1976765860 ps |
| CPU time | 145.72 seconds |
| Started | Aug 09 08:11:56 PM PDT 24 |
| Finished | Aug 09 08:14:21 PM PDT 24 |
| Peak memory | 577024 kb |
| Host | smart-4a02aebd-2baf-4e08-98cc-830ecfed11bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134446843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.134446843 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.3141165856 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 788760106 ps |
| CPU time | 124.92 seconds |
| Started | Aug 09 08:11:55 PM PDT 24 |
| Finished | Aug 09 08:14:00 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-e9dbc742-f5bd-4969-b704-445193e3ea78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141165856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.3141165856 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1503817493 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 330351099 ps |
| CPU time | 16.06 seconds |
| Started | Aug 09 08:11:53 PM PDT 24 |
| Finished | Aug 09 08:12:09 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-6a672f9a-d308-4de4-8502-5269880628fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503817493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1503817493 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.2150764598 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 1216711751 ps |
| CPU time | 76.51 seconds |
| Started | Aug 09 08:12:00 PM PDT 24 |
| Finished | Aug 09 08:13:16 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-82f14f7f-a912-4e20-bd2b-5e0155f2e9df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150764598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .2150764598 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2683235172 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 47951879616 ps |
| CPU time | 871.71 seconds |
| Started | Aug 09 08:12:09 PM PDT 24 |
| Finished | Aug 09 08:26:41 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-4047d793-2bc4-482c-9419-eb83fd8d96bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683235172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.2683235172 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1018168011 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 202349540 ps |
| CPU time | 24.21 seconds |
| Started | Aug 09 08:12:08 PM PDT 24 |
| Finished | Aug 09 08:12:33 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-c8a7aec3-fee9-4088-ab51-b1491de200a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018168011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.1018168011 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.1719139334 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 120662920 ps |
| CPU time | 11.97 seconds |
| Started | Aug 09 08:12:07 PM PDT 24 |
| Finished | Aug 09 08:12:19 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-9d546bec-bbab-4148-94e3-b3a0ace16f4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719139334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.1719139334 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.2860721429 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 568803528 ps |
| CPU time | 54.35 seconds |
| Started | Aug 09 08:12:00 PM PDT 24 |
| Finished | Aug 09 08:12:54 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-2d0c8d74-d8af-43c8-87f9-bec897a98780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860721429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2860721429 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3671742497 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 58568996390 ps |
| CPU time | 632.17 seconds |
| Started | Aug 09 08:12:00 PM PDT 24 |
| Finished | Aug 09 08:22:33 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-0bc7adf5-b79b-4380-a721-c42242715d2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671742497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.3671742497 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.563076323 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 17004749110 ps |
| CPU time | 292.24 seconds |
| Started | Aug 09 08:12:00 PM PDT 24 |
| Finished | Aug 09 08:16:52 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-1f7d208c-09a6-4cbf-8f5f-802072062d68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563076323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.563076323 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.54107633 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 390136713 ps |
| CPU time | 36.67 seconds |
| Started | Aug 09 08:11:59 PM PDT 24 |
| Finished | Aug 09 08:12:36 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-0be3f3d0-afe1-48df-8ba5-5aa30c0e8f22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54107633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_delay s.54107633 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.4006267136 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 237391391 ps |
| CPU time | 9.08 seconds |
| Started | Aug 09 08:12:07 PM PDT 24 |
| Finished | Aug 09 08:12:16 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-974429ec-046d-4507-933b-c5539a1f42fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006267136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.4006267136 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.906208695 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 41540973 ps |
| CPU time | 5.62 seconds |
| Started | Aug 09 08:11:57 PM PDT 24 |
| Finished | Aug 09 08:12:03 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-a0bce74f-86b0-4d79-a3bc-44f9a4b38a78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906208695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.906208695 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.318209057 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 7701566761 ps |
| CPU time | 81.78 seconds |
| Started | Aug 09 08:11:59 PM PDT 24 |
| Finished | Aug 09 08:13:21 PM PDT 24 |
| Peak memory | 574892 kb |
| Host | smart-277aa54b-9320-433e-9b95-71b96ec96205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318209057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.318209057 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.4232899945 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 5956846507 ps |
| CPU time | 97.9 seconds |
| Started | Aug 09 08:11:59 PM PDT 24 |
| Finished | Aug 09 08:13:37 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-375766dd-1b3f-4348-b7da-38e6194c05a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232899945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.4232899945 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.818940067 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 46291609 ps |
| CPU time | 6.46 seconds |
| Started | Aug 09 08:12:00 PM PDT 24 |
| Finished | Aug 09 08:12:07 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-9118a3d8-a294-445e-affb-5d722eb2f9ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818940067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays .818940067 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.4083332469 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 3397898090 ps |
| CPU time | 124.26 seconds |
| Started | Aug 09 08:12:09 PM PDT 24 |
| Finished | Aug 09 08:14:13 PM PDT 24 |
| Peak memory | 576404 kb |
| Host | smart-a44f5f61-3cc1-4e84-97cf-74039b176ea2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083332469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.4083332469 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.4263519066 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 6938454728 ps |
| CPU time | 275.05 seconds |
| Started | Aug 09 08:12:07 PM PDT 24 |
| Finished | Aug 09 08:16:42 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-87ad9f1f-196a-4fc3-a144-7e61db82acba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263519066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.4263519066 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1190837308 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 1510194908 ps |
| CPU time | 162.3 seconds |
| Started | Aug 09 08:12:11 PM PDT 24 |
| Finished | Aug 09 08:14:53 PM PDT 24 |
| Peak memory | 577052 kb |
| Host | smart-3b38c34f-914d-4b59-a81d-83f6130a7fa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190837308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.1190837308 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.90960554 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 203480919 ps |
| CPU time | 58.32 seconds |
| Started | Aug 09 08:12:09 PM PDT 24 |
| Finished | Aug 09 08:13:07 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-29df442a-aea0-488d-ad1d-17c2915c74a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90960554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_ with_reset_error.90960554 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.2902197960 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 339036707 ps |
| CPU time | 16.05 seconds |
| Started | Aug 09 08:12:07 PM PDT 24 |
| Finished | Aug 09 08:12:23 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-0f9e5179-d2fa-46b6-8bb3-fc2d8af0417b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902197960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.2902197960 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.655981291 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 11153126360 ps |
| CPU time | 1006.47 seconds |
| Started | Aug 09 08:13:48 PM PDT 24 |
| Finished | Aug 09 08:30:35 PM PDT 24 |
| Peak memory | 607976 kb |
| Host | smart-2e100ca3-e298-4248-aa9a-d22cd42d5336 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655981291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_jtag_csr_rw.655981291 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.1739497620 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 13506491888 ps |
| CPU time | 1317.64 seconds |
| Started | Aug 09 08:13:43 PM PDT 24 |
| Finished | Aug 09 08:35:41 PM PDT 24 |
| Peak memory | 607708 kb |
| Host | smart-86f031cb-7cac-4091-a376-5774da7ad328 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739497620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.1 739497620 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.2265070066 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 3120044112 ps |
| CPU time | 310.01 seconds |
| Started | Aug 09 08:21:22 PM PDT 24 |
| Finished | Aug 09 08:26:33 PM PDT 24 |
| Peak memory | 608464 kb |
| Host | smart-94895472-aff4-46c5-bf0e-7574034cb859 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2265070066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.2265070066 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.266423578 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 2902118604 ps |
| CPU time | 281.3 seconds |
| Started | Aug 09 08:20:30 PM PDT 24 |
| Finished | Aug 09 08:25:12 PM PDT 24 |
| Peak memory | 609092 kb |
| Host | smart-edf2b280-ce04-44d1-8fc2-15542f7f2dd7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266423578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.266423578 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2495848178 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2975449148 ps |
| CPU time | 254.78 seconds |
| Started | Aug 09 08:25:03 PM PDT 24 |
| Finished | Aug 09 08:29:18 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-4cdfbc0b-557d-4262-9bd1-6da7a9d1e235 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495 848178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2495848178 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3449768016 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 2542379245 ps |
| CPU time | 285.68 seconds |
| Started | Aug 09 08:24:37 PM PDT 24 |
| Finished | Aug 09 08:29:25 PM PDT 24 |
| Peak memory | 608372 kb |
| Host | smart-df450fbd-ab92-40df-83f2-fe2e7e98f30b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449768016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3449768016 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.1275792303 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 2853549970 ps |
| CPU time | 327.81 seconds |
| Started | Aug 09 08:21:42 PM PDT 24 |
| Finished | Aug 09 08:27:10 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-677a0c9a-7afe-4b3e-9418-1b4062de5650 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275792303 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.1275792303 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.3256589685 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3069076550 ps |
| CPU time | 360.06 seconds |
| Started | Aug 09 08:22:51 PM PDT 24 |
| Finished | Aug 09 08:28:53 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-b0a43527-8b66-43ad-9c9f-8bcd100b84b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256589685 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.3256589685 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.3146088534 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2781305149 ps |
| CPU time | 274.16 seconds |
| Started | Aug 09 08:21:37 PM PDT 24 |
| Finished | Aug 09 08:26:11 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-4a9b1fb3-bccd-48b4-914a-de28552a2a5a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146088534 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.3146088534 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.337988125 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 2738566400 ps |
| CPU time | 281.92 seconds |
| Started | Aug 09 08:26:05 PM PDT 24 |
| Finished | Aug 09 08:30:47 PM PDT 24 |
| Peak memory | 609508 kb |
| Host | smart-a40df975-da34-4beb-a828-2fe22eb73475 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337988125 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.337988125 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1569076956 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3520000626 ps |
| CPU time | 336.8 seconds |
| Started | Aug 09 08:20:01 PM PDT 24 |
| Finished | Aug 09 08:25:38 PM PDT 24 |
| Peak memory | 609476 kb |
| Host | smart-614bf37f-52dc-4734-9d4e-3a6d8c3872ea |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1569076956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1569076956 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1250394993 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 6272188898 ps |
| CPU time | 559.74 seconds |
| Started | Aug 09 08:20:50 PM PDT 24 |
| Finished | Aug 09 08:30:11 PM PDT 24 |
| Peak memory | 619528 kb |
| Host | smart-4345fd17-1af4-42f1-995f-8c6b253d2020 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1250394993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.1250394993 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3617575183 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 7913757744 ps |
| CPU time | 1654.42 seconds |
| Started | Aug 09 08:20:26 PM PDT 24 |
| Finished | Aug 09 08:48:01 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-3bf20666-7734-4894-ae55-533f2601a7e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3617575183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.3617575183 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1515581480 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 7344395624 ps |
| CPU time | 1521.52 seconds |
| Started | Aug 09 08:22:49 PM PDT 24 |
| Finished | Aug 09 08:48:11 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-6f156cc2-95af-4c8e-a17c-272ca3ac21be |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515581480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.1515581480 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2241752162 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 10901513710 ps |
| CPU time | 1137.86 seconds |
| Started | Aug 09 08:20:32 PM PDT 24 |
| Finished | Aug 09 08:39:30 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-4604ee11-6383-499f-9aaa-60861af507c0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241752162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.2241752162 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3011900336 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 7579720440 ps |
| CPU time | 1567.32 seconds |
| Started | Aug 09 08:23:49 PM PDT 24 |
| Finished | Aug 09 08:49:57 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-71b11d97-d1d0-4423-9bb8-d7d5155232ef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3011900336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3011900336 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.945255578 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3162040040 ps |
| CPU time | 398.02 seconds |
| Started | Aug 09 08:21:39 PM PDT 24 |
| Finished | Aug 09 08:28:18 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-afeb3c80-fa55-4981-a578-324c00ac3498 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=945255578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.945255578 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2693102861 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 254819351052 ps |
| CPU time | 12814.5 seconds |
| Started | Aug 09 08:24:39 PM PDT 24 |
| Finished | Aug 09 11:58:15 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-9dc0573b-974a-4b24-8f08-9d20049e4f1e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693102861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2693102861 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.50799149 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 6477836552 ps |
| CPU time | 400.55 seconds |
| Started | Aug 09 08:20:28 PM PDT 24 |
| Finished | Aug 09 08:27:09 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-bd4d1f9a-565d-4705-8ed5-07577d1177d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=50799149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.50799149 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2952378011 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 2651612260 ps |
| CPU time | 286.38 seconds |
| Started | Aug 09 08:26:42 PM PDT 24 |
| Finished | Aug 09 08:31:28 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-23aefecd-12ef-443a-96ac-58b051e1fd00 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952378011 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.2952378011 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2010008404 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 8505826552 ps |
| CPU time | 852.4 seconds |
| Started | Aug 09 08:21:49 PM PDT 24 |
| Finished | Aug 09 08:36:01 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-4206a1ad-4063-45a2-9a71-c8f7ba07acc8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2010008404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2010008404 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.4096238914 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 5718120728 ps |
| CPU time | 703.39 seconds |
| Started | Aug 09 08:23:41 PM PDT 24 |
| Finished | Aug 09 08:35:25 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-1f208468-ee2a-43bc-b5fa-8a14dd35292e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4096238914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.4096238914 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.187621637 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 8099092200 ps |
| CPU time | 913.02 seconds |
| Started | Aug 09 08:24:50 PM PDT 24 |
| Finished | Aug 09 08:40:04 PM PDT 24 |
| Peak memory | 616840 kb |
| Host | smart-7f0e97bc-4f57-4fa4-b38a-c58b8821baf0 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187621637 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.187621637 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2353363304 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 5246267252 ps |
| CPU time | 509.87 seconds |
| Started | Aug 09 08:22:53 PM PDT 24 |
| Finished | Aug 09 08:31:23 PM PDT 24 |
| Peak memory | 620308 kb |
| Host | smart-d581bb13-5531-47e1-9713-44c694e10025 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2353363304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2353363304 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3107007118 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 4242204254 ps |
| CPU time | 645.86 seconds |
| Started | Aug 09 08:22:35 PM PDT 24 |
| Finished | Aug 09 08:33:21 PM PDT 24 |
| Peak memory | 611920 kb |
| Host | smart-24acc2f4-abac-488d-9153-4a75965fba84 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107007118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3107007118 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4117717317 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 4118017714 ps |
| CPU time | 590.43 seconds |
| Started | Aug 09 08:21:37 PM PDT 24 |
| Finished | Aug 09 08:31:27 PM PDT 24 |
| Peak memory | 611980 kb |
| Host | smart-766f3dd4-bf62-4ec2-8ca6-5a0e6d42dd17 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117717317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4117717317 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3931564998 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 4803604444 ps |
| CPU time | 615.94 seconds |
| Started | Aug 09 08:22:11 PM PDT 24 |
| Finished | Aug 09 08:32:27 PM PDT 24 |
| Peak memory | 612728 kb |
| Host | smart-2e4fcf6a-b832-4242-b539-2ea6492ec44e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931564998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3931564998 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1705699438 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 4417781110 ps |
| CPU time | 699.17 seconds |
| Started | Aug 09 08:24:25 PM PDT 24 |
| Finished | Aug 09 08:36:06 PM PDT 24 |
| Peak memory | 611924 kb |
| Host | smart-d0fc1d41-0649-4c8f-97d0-23e4fe24cdba |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705699438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1705699438 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.291980249 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 5007031134 ps |
| CPU time | 570.56 seconds |
| Started | Aug 09 08:21:01 PM PDT 24 |
| Finished | Aug 09 08:30:31 PM PDT 24 |
| Peak memory | 612812 kb |
| Host | smart-9855088a-65e6-48cf-a923-d0a078ca1124 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291980249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.291980249 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3864218059 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2848696143 ps |
| CPU time | 211.86 seconds |
| Started | Aug 09 08:22:57 PM PDT 24 |
| Finished | Aug 09 08:26:30 PM PDT 24 |
| Peak memory | 609108 kb |
| Host | smart-1e902f86-8b8a-4ff4-bf11-8d6b629ef045 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864218059 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.3864218059 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3994531397 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 3397140832 ps |
| CPU time | 415.28 seconds |
| Started | Aug 09 08:24:06 PM PDT 24 |
| Finished | Aug 09 08:31:01 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-6e87bb97-a8d3-48f9-a6a9-ad1f6a4a9a75 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994531397 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.3994531397 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.64670583 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 2551999137 ps |
| CPU time | 205.69 seconds |
| Started | Aug 09 08:24:04 PM PDT 24 |
| Finished | Aug 09 08:27:30 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-47835a9e-b39d-4eaf-8be6-8c08f02f97df |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64670583 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.64670583 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1920799123 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5465049350 ps |
| CPU time | 529.85 seconds |
| Started | Aug 09 08:21:28 PM PDT 24 |
| Finished | Aug 09 08:30:18 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-f723b4db-0520-4655-a85e-6c66b0727594 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920799123 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.1920799123 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1573683856 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 5871809216 ps |
| CPU time | 558 seconds |
| Started | Aug 09 08:20:41 PM PDT 24 |
| Finished | Aug 09 08:30:01 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-b87d1db6-6c5b-47e9-a4e6-1f60a8a0792c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573683856 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.1573683856 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1419090317 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 5984667380 ps |
| CPU time | 562.03 seconds |
| Started | Aug 09 08:22:58 PM PDT 24 |
| Finished | Aug 09 08:32:20 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-8f75a7a0-bd69-4867-9a7f-8b628d77b7f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419090317 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.1419090317 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.731015711 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4945788072 ps |
| CPU time | 385.72 seconds |
| Started | Aug 09 08:25:35 PM PDT 24 |
| Finished | Aug 09 08:32:01 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-e58a5faf-bfcb-470a-b2a3-1c5aa151fb5f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731015711 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.731015711 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1229017894 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 10191118570 ps |
| CPU time | 1248.7 seconds |
| Started | Aug 09 08:26:27 PM PDT 24 |
| Finished | Aug 09 08:47:16 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-68fb9bb5-2139-470e-b852-8a6c6cd80ed8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229017894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.1229017894 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2010063270 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 3616580178 ps |
| CPU time | 493.66 seconds |
| Started | Aug 09 08:22:24 PM PDT 24 |
| Finished | Aug 09 08:30:39 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-ccbe4c6e-c526-4d82-b006-e971dfbbe26a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010063270 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2010063270 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.207961204 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 4464678200 ps |
| CPU time | 531.13 seconds |
| Started | Aug 09 08:22:30 PM PDT 24 |
| Finished | Aug 09 08:31:21 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-20eabf55-d8c5-43e7-add7-4db8d75d551f |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207961204 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.207961204 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2457154079 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 2987736566 ps |
| CPU time | 278.46 seconds |
| Started | Aug 09 08:24:19 PM PDT 24 |
| Finished | Aug 09 08:28:57 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-3b09f814-4c13-4d83-bd06-6e4c9b946fb2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457154079 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.2457154079 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.566189585 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 71533932512 ps |
| CPU time | 13684.2 seconds |
| Started | Aug 09 08:25:52 PM PDT 24 |
| Finished | Aug 10 12:13:57 AM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-75084ffa-e35d-4276-bf74-205b408c1798 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=566189585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.566189585 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1209555227 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 27433772584 ps |
| CPU time | 6584.89 seconds |
| Started | Aug 09 08:22:09 PM PDT 24 |
| Finished | Aug 09 10:11:55 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-4f1bfd42-8626-4c7d-8b21-10f888459dcc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209555227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.1209555227 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.719788206 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 5099795804 ps |
| CPU time | 517.23 seconds |
| Started | Aug 09 08:23:33 PM PDT 24 |
| Finished | Aug 09 08:32:10 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-83884b18-d52f-46c0-962a-3f62155d41b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71978 8206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.719788206 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.4210237757 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 3040708660 ps |
| CPU time | 317.79 seconds |
| Started | Aug 09 08:21:04 PM PDT 24 |
| Finished | Aug 09 08:26:22 PM PDT 24 |
| Peak memory | 609432 kb |
| Host | smart-358b252c-724b-4594-8875-f2d4f2737641 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210237757 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.4210237757 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1533769160 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 8069993244 ps |
| CPU time | 965.35 seconds |
| Started | Aug 09 08:21:23 PM PDT 24 |
| Finished | Aug 09 08:37:29 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-b409b984-e1cd-4645-b5da-7b5b92720c88 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533769160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.1533769160 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.666129507 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 3079634380 ps |
| CPU time | 250.92 seconds |
| Started | Aug 09 08:24:00 PM PDT 24 |
| Finished | Aug 09 08:28:12 PM PDT 24 |
| Peak memory | 609092 kb |
| Host | smart-314cdcc4-406f-4a3f-a4ea-a3f4c39d48e5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666129507 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_csrng_smoketest.666129507 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1430348907 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4953452480 ps |
| CPU time | 848.64 seconds |
| Started | Aug 09 08:20:49 PM PDT 24 |
| Finished | Aug 09 08:34:58 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-7479e718-a191-4cf6-aad1-3a210262ddbc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1430348907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1430348907 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.2365706825 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5249514624 ps |
| CPU time | 1192.45 seconds |
| Started | Aug 09 08:21:05 PM PDT 24 |
| Finished | Aug 09 08:40:58 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-8c20360d-ecaf-4985-af0e-503a9cc30749 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365706825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.2365706825 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4224234561 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 7081560420 ps |
| CPU time | 1147.66 seconds |
| Started | Aug 09 08:24:15 PM PDT 24 |
| Finished | Aug 09 08:43:25 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-690f8433-b27e-4897-b358-b2a746dbbf58 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4224234561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.4224234561 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.3194876126 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 3463309288 ps |
| CPU time | 790.93 seconds |
| Started | Aug 09 08:22:25 PM PDT 24 |
| Finished | Aug 09 08:35:36 PM PDT 24 |
| Peak memory | 615380 kb |
| Host | smart-5adb16c9-78ff-4367-970d-e6d814553ad3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194876126 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.3194876126 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.35600810 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 6049325062 ps |
| CPU time | 1392.48 seconds |
| Started | Aug 09 08:22:40 PM PDT 24 |
| Finished | Aug 09 08:45:53 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-9c471d1d-d1e0-4cc9-8563-845fa1db7853 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35600810 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.35600810 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2079370890 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 2653815148 ps |
| CPU time | 263.02 seconds |
| Started | Aug 09 08:23:30 PM PDT 24 |
| Finished | Aug 09 08:27:53 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-04de87d3-b095-401f-8bb9-6322fb270b33 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20 79370890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2079370890 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2481933536 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 7557486212 ps |
| CPU time | 1547.57 seconds |
| Started | Aug 09 08:21:47 PM PDT 24 |
| Finished | Aug 09 08:47:34 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-30b7c37e-57c3-4d89-bbbd-6ee5266cb907 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2481933536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2481933536 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1726132206 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2437539136 ps |
| CPU time | 284.7 seconds |
| Started | Aug 09 08:28:22 PM PDT 24 |
| Finished | Aug 09 08:33:07 PM PDT 24 |
| Peak memory | 609504 kb |
| Host | smart-5bc22ba8-7718-4d03-92eb-726bf9a27054 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726132206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.1726132206 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3856678817 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3426726020 ps |
| CPU time | 586.96 seconds |
| Started | Aug 09 08:26:08 PM PDT 24 |
| Finished | Aug 09 08:35:56 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-45e078b2-510a-431a-809b-1e41f1e6a233 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3856678817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3856678817 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.227306600 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 3112127148 ps |
| CPU time | 300.04 seconds |
| Started | Aug 09 08:19:46 PM PDT 24 |
| Finished | Aug 09 08:24:46 PM PDT 24 |
| Peak memory | 608212 kb |
| Host | smart-765e8348-9f51-4c12-be5a-0c65884b15d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227306600 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.227306600 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.465147464 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2651209156 ps |
| CPU time | 172.12 seconds |
| Started | Aug 09 08:19:58 PM PDT 24 |
| Finished | Aug 09 08:22:51 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-1299eee0-3277-406a-ba92-55a136fe4ca8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465147464 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.465147464 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.2119787711 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2657251456 ps |
| CPU time | 225.89 seconds |
| Started | Aug 09 08:19:22 PM PDT 24 |
| Finished | Aug 09 08:23:09 PM PDT 24 |
| Peak memory | 609212 kb |
| Host | smart-371c20f5-e81c-41ae-a73c-5b1440983736 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119787711 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.2119787711 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.50785127 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2579488860 ps |
| CPU time | 116.84 seconds |
| Started | Aug 09 08:20:00 PM PDT 24 |
| Finished | Aug 09 08:21:57 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-de42bf66-54cd-45a2-a77a-e2dd9199d8a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50785127 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_example_rom.50785127 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2424982006 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 59829782738 ps |
| CPU time | 10892.7 seconds |
| Started | Aug 09 08:19:49 PM PDT 24 |
| Finished | Aug 09 11:21:23 PM PDT 24 |
| Peak memory | 624668 kb |
| Host | smart-017dfced-562b-4c75-ae0a-b678dd0d8fb1 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2424982006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.2424982006 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.3116744 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 4799923660 ps |
| CPU time | 714.36 seconds |
| Started | Aug 09 08:21:10 PM PDT 24 |
| Finished | Aug 09 08:33:05 PM PDT 24 |
| Peak memory | 611100 kb |
| Host | smart-81017d99-9b0a-4e6e-91dd-ff1894652d02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3116744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.3116744 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2667100460 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 5679259726 ps |
| CPU time | 1172.89 seconds |
| Started | Aug 09 08:26:23 PM PDT 24 |
| Finished | Aug 09 08:45:56 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-1df6e2ca-6d18-4330-957a-e93828cb244d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667100460 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.2667100460 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2923602648 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 6128576930 ps |
| CPU time | 1020.38 seconds |
| Started | Aug 09 08:19:49 PM PDT 24 |
| Finished | Aug 09 08:36:50 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-bd30c6dc-c834-4cb0-9161-518db52308f7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923602648 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.2923602648 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3918480509 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 6740090860 ps |
| CPU time | 1154.89 seconds |
| Started | Aug 09 08:21:54 PM PDT 24 |
| Finished | Aug 09 08:41:09 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-31df8b40-4c57-4547-b2f6-a1855c499ce8 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918480509 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3918480509 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1983031911 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 5720039752 ps |
| CPU time | 1320.51 seconds |
| Started | Aug 09 08:22:54 PM PDT 24 |
| Finished | Aug 09 08:44:55 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-477cd54d-a0ff-4c2f-a254-fcf81d412c9c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983031911 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.1983031911 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3867991488 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 2833110840 ps |
| CPU time | 414.77 seconds |
| Started | Aug 09 08:28:14 PM PDT 24 |
| Finished | Aug 09 08:35:09 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-419ab133-db6f-4d92-b268-f482e4851e18 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867991488 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.3867991488 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3090007401 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 3679490772 ps |
| CPU time | 365.45 seconds |
| Started | Aug 09 08:21:18 PM PDT 24 |
| Finished | Aug 09 08:27:24 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-c8631086-8f9f-4153-bd84-e85e74f300a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30 90007401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.3090007401 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1698605351 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 5916479180 ps |
| CPU time | 1200.13 seconds |
| Started | Aug 09 08:24:48 PM PDT 24 |
| Finished | Aug 09 08:44:48 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-aadf573f-1275-4764-bbd7-d3adf84464f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698605351 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.1698605351 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2740658998 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4640771205 ps |
| CPU time | 664 seconds |
| Started | Aug 09 08:21:53 PM PDT 24 |
| Finished | Aug 09 08:32:57 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-d304c3de-8235-46d2-ab57-024b927b8f86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2740658998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2740658998 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1592204783 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 3016700716 ps |
| CPU time | 336.07 seconds |
| Started | Aug 09 08:20:27 PM PDT 24 |
| Finished | Aug 09 08:26:04 PM PDT 24 |
| Peak memory | 608300 kb |
| Host | smart-fb09fd91-e9f8-49ca-b444-258f9c8cb9a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592204 783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.1592204783 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.741592645 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 25331406086 ps |
| CPU time | 2492.98 seconds |
| Started | Aug 09 08:20:22 PM PDT 24 |
| Finished | Aug 09 09:01:56 PM PDT 24 |
| Peak memory | 615260 kb |
| Host | smart-6a4fa991-0aba-4812-b026-63ef72add906 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741592645 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.741592645 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.738440064 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 23615399463 ps |
| CPU time | 2003.66 seconds |
| Started | Aug 09 08:21:30 PM PDT 24 |
| Finished | Aug 09 08:54:54 PM PDT 24 |
| Peak memory | 613060 kb |
| Host | smart-a52e63ac-1978-4814-ad70-4dad9a2537bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=738440064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.738440064 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3049175688 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 2479458856 ps |
| CPU time | 236.62 seconds |
| Started | Aug 09 08:26:59 PM PDT 24 |
| Finished | Aug 09 08:30:56 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-456e52ea-ce28-4398-a850-314d73762360 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3049175688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.3049175688 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.2863415262 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2657183805 ps |
| CPU time | 240.5 seconds |
| Started | Aug 09 08:25:58 PM PDT 24 |
| Finished | Aug 09 08:29:59 PM PDT 24 |
| Peak memory | 608812 kb |
| Host | smart-34f585ff-5726-4ad8-8b57-229bb373c6a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863415262 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2863415262 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3379671204 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 2553338384 ps |
| CPU time | 285.17 seconds |
| Started | Aug 09 08:20:59 PM PDT 24 |
| Finished | Aug 09 08:25:45 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-69e85a85-ada7-47ab-b298-dcf1fad08c1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379671204 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.3379671204 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3348633063 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 2821679849 ps |
| CPU time | 276.41 seconds |
| Started | Aug 09 08:24:40 PM PDT 24 |
| Finished | Aug 09 08:29:16 PM PDT 24 |
| Peak memory | 609540 kb |
| Host | smart-ef88baa9-922a-4846-bb93-d629accde980 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348633063 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.3348633063 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2743563666 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 2758809984 ps |
| CPU time | 258.82 seconds |
| Started | Aug 09 08:25:04 PM PDT 24 |
| Finished | Aug 09 08:29:23 PM PDT 24 |
| Peak memory | 608400 kb |
| Host | smart-1e67505d-116e-4d02-9f87-073c3a370019 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743563666 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.2743563666 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.4100555659 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 7830648400 ps |
| CPU time | 1823.79 seconds |
| Started | Aug 09 08:25:07 PM PDT 24 |
| Finished | Aug 09 08:55:31 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-4e96b3c6-dfef-422b-9ffe-ec4e460408d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100555659 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.4100555659 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.2036720880 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 3090355800 ps |
| CPU time | 409.81 seconds |
| Started | Aug 09 08:24:37 PM PDT 24 |
| Finished | Aug 09 08:31:28 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-d1d46fd1-da98-4246-bdba-badcbe4f8370 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036720880 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.2036720880 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.3813114862 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3853563534 ps |
| CPU time | 290.97 seconds |
| Started | Aug 09 08:25:25 PM PDT 24 |
| Finished | Aug 09 08:30:17 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-e6f8e754-592e-4af7-994e-1c8507a26d14 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813114862 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.3813114862 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2138550314 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4784699160 ps |
| CPU time | 675.82 seconds |
| Started | Aug 09 08:19:26 PM PDT 24 |
| Finished | Aug 09 08:30:43 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-51bcc43b-f3cf-414f-a1b9-4d2ac4e52b28 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138550314 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.2138550314 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2102644399 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4620593530 ps |
| CPU time | 722.64 seconds |
| Started | Aug 09 08:20:02 PM PDT 24 |
| Finished | Aug 09 08:32:06 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-9dabbae3-3f35-40f7-b384-ca9eb461efd2 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102644399 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.2102644399 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4041945709 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4591467120 ps |
| CPU time | 934.95 seconds |
| Started | Aug 09 08:21:13 PM PDT 24 |
| Finished | Aug 09 08:36:48 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-c503fb40-8f39-45dc-8d42-d545ad4b5dfa |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041945709 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.4041945709 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3078980511 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 65431600468 ps |
| CPU time | 11515.6 seconds |
| Started | Aug 09 08:20:50 PM PDT 24 |
| Finished | Aug 09 11:32:48 PM PDT 24 |
| Peak memory | 624592 kb |
| Host | smart-10a0f69b-0a9f-49f5-b091-6800c79640dd |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3078980511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3078980511 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.4094197797 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 9429591160 ps |
| CPU time | 1847.39 seconds |
| Started | Aug 09 08:20:22 PM PDT 24 |
| Finished | Aug 09 08:51:10 PM PDT 24 |
| Peak memory | 617740 kb |
| Host | smart-12780e29-bc51-433c-b37e-74561396c888 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094 197797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.4094197797 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1278887934 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 7329361788 ps |
| CPU time | 1158.62 seconds |
| Started | Aug 09 08:20:24 PM PDT 24 |
| Finished | Aug 09 08:39:43 PM PDT 24 |
| Peak memory | 617448 kb |
| Host | smart-3c4f094d-f4e5-4405-9ffe-d75f7f26b1d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1278887934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.1278887934 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2460272814 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 11200687320 ps |
| CPU time | 1785.99 seconds |
| Started | Aug 09 08:22:47 PM PDT 24 |
| Finished | Aug 09 08:52:35 PM PDT 24 |
| Peak memory | 617724 kb |
| Host | smart-c943c7d2-ebd6-4583-9188-5a868fa450fd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2460272814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2460272814 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2782599641 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 11638952688 ps |
| CPU time | 2725.21 seconds |
| Started | Aug 09 08:20:19 PM PDT 24 |
| Finished | Aug 09 09:05:44 PM PDT 24 |
| Peak memory | 616652 kb |
| Host | smart-1f15c664-947e-466f-a8aa-6f6ba182b0e6 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2782599641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.2782599641 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3937549169 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 7534011474 ps |
| CPU time | 1243.86 seconds |
| Started | Aug 09 08:24:50 PM PDT 24 |
| Finished | Aug 09 08:45:35 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-091b0c18-f6ef-4a9a-ac63-e9b9fc214fda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393754 9169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.3937549169 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3167653481 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 6434074200 ps |
| CPU time | 1374.37 seconds |
| Started | Aug 09 08:25:10 PM PDT 24 |
| Finished | Aug 09 08:48:05 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-36cb228e-54b7-4c6e-a2e2-5af8e2aaa4f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31676 53481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3167653481 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.1157086112 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2862825400 ps |
| CPU time | 274.99 seconds |
| Started | Aug 09 08:22:32 PM PDT 24 |
| Finished | Aug 09 08:27:07 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-6be87eb5-8c1a-4aca-8afc-c2fea352eb4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157086112 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.1157086112 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.430665484 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 3136413272 ps |
| CPU time | 271.84 seconds |
| Started | Aug 09 08:26:40 PM PDT 24 |
| Finished | Aug 09 08:31:12 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-d7a030d8-b6cf-4d80-97d1-c5e0513aac0d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430665484 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.430665484 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.3665154284 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2797952580 ps |
| CPU time | 240.77 seconds |
| Started | Aug 09 08:22:34 PM PDT 24 |
| Finished | Aug 09 08:26:34 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-10ce746f-54bf-4855-b820-a3eb9e724997 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665154284 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.3665154284 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3675092064 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 2484013648 ps |
| CPU time | 303.54 seconds |
| Started | Aug 09 08:21:58 PM PDT 24 |
| Finished | Aug 09 08:27:02 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-51ddf852-b72e-46b4-aeff-608d407378dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675092064 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3675092064 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3218168456 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 3111016912 ps |
| CPU time | 278.24 seconds |
| Started | Aug 09 08:23:20 PM PDT 24 |
| Finished | Aug 09 08:27:59 PM PDT 24 |
| Peak memory | 608268 kb |
| Host | smart-cb2185ae-1bee-45f4-9c22-2c0cafdac6e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218168456 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.3218168456 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1032096183 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 3591266713 ps |
| CPU time | 355.39 seconds |
| Started | Aug 09 08:22:59 PM PDT 24 |
| Finished | Aug 09 08:28:55 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-5a631d20-b776-4dcd-bc90-5af14dae6a1e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032096183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.1032096183 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2256399385 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2789760060 ps |
| CPU time | 251.28 seconds |
| Started | Aug 09 08:23:46 PM PDT 24 |
| Finished | Aug 09 08:27:58 PM PDT 24 |
| Peak memory | 608476 kb |
| Host | smart-8d5e16e2-6911-4c49-bcf6-533dd1ae5feb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22563993 85 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2256399385 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.51011417 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3285065556 ps |
| CPU time | 351.3 seconds |
| Started | Aug 09 08:24:49 PM PDT 24 |
| Finished | Aug 09 08:30:40 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-c8f13657-721e-4114-8201-2220e00caff4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51011417 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_smoketest.51011417 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1114471811 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 3464173824 ps |
| CPU time | 378.98 seconds |
| Started | Aug 09 08:25:52 PM PDT 24 |
| Finished | Aug 09 08:32:11 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-b4be75bb-3a79-410a-9c2c-3354fa073568 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114471811 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.1114471811 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1872680110 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3083964474 ps |
| CPU time | 174.81 seconds |
| Started | Aug 09 08:19:58 PM PDT 24 |
| Finished | Aug 09 08:22:53 PM PDT 24 |
| Peak memory | 619888 kb |
| Host | smart-45e82e84-8d5f-436c-9ec8-bcccbe001086 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872680110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.1872680110 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.88038084 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3689489557 ps |
| CPU time | 242.23 seconds |
| Started | Aug 09 08:21:27 PM PDT 24 |
| Finished | Aug 09 08:25:30 PM PDT 24 |
| Peak memory | 621140 kb |
| Host | smart-1ab92764-6710-46ef-bba8-aee3e9520954 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88038084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.88038084 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3229426096 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 3345581367 ps |
| CPU time | 175.94 seconds |
| Started | Aug 09 08:22:16 PM PDT 24 |
| Finished | Aug 09 08:25:13 PM PDT 24 |
| Peak memory | 619900 kb |
| Host | smart-365a13dd-6414-4eef-869d-02a6f644c06d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229426096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.3229426096 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2516611948 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 11011290359 ps |
| CPU time | 894.17 seconds |
| Started | Aug 09 08:21:19 PM PDT 24 |
| Finished | Aug 09 08:36:14 PM PDT 24 |
| Peak memory | 624356 kb |
| Host | smart-3a6e84bf-e6b1-4a82-8a5e-c24133d9bdcd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516611948 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.2516611948 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2302881715 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 2542378656 ps |
| CPU time | 123.43 seconds |
| Started | Aug 09 08:23:26 PM PDT 24 |
| Finished | Aug 09 08:25:31 PM PDT 24 |
| Peak memory | 617796 kb |
| Host | smart-d54cb789-fadd-413a-bf56-0658765566e1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2302881715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2302881715 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1770343905 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2424390064 ps |
| CPU time | 122.79 seconds |
| Started | Aug 09 08:21:59 PM PDT 24 |
| Finished | Aug 09 08:24:02 PM PDT 24 |
| Peak memory | 616844 kb |
| Host | smart-0f79b924-a5f5-44e9-ac86-677f66000ead |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770343905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1770343905 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1741937150 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 46828704836 ps |
| CPU time | 5705.49 seconds |
| Started | Aug 09 08:20:10 PM PDT 24 |
| Finished | Aug 09 09:55:17 PM PDT 24 |
| Peak memory | 620152 kb |
| Host | smart-2020e132-d6c8-43b3-9638-cbea36bcf286 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741937150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.1741937150 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3610232901 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 9271048793 ps |
| CPU time | 953.1 seconds |
| Started | Aug 09 08:26:47 PM PDT 24 |
| Finished | Aug 09 08:42:41 PM PDT 24 |
| Peak memory | 619948 kb |
| Host | smart-7398424b-7825-4b0e-8e83-f9e7d7287569 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610232901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3610232901 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.545136716 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 49649538040 ps |
| CPU time | 5920.31 seconds |
| Started | Aug 09 08:21:01 PM PDT 24 |
| Finished | Aug 09 09:59:42 PM PDT 24 |
| Peak memory | 620632 kb |
| Host | smart-aa5156a6-8900-4641-bdf6-338847e9b650 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545136716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_rma.545136716 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3007260164 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 21341794508 ps |
| CPU time | 1992.71 seconds |
| Started | Aug 09 08:20:18 PM PDT 24 |
| Finished | Aug 09 08:53:31 PM PDT 24 |
| Peak memory | 620784 kb |
| Host | smart-8c7f415e-a448-4f1b-8287-4542bea58955 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3007260164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.3007260164 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1947287038 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 17132222676 ps |
| CPU time | 3269.09 seconds |
| Started | Aug 09 08:25:05 PM PDT 24 |
| Finished | Aug 09 09:19:34 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-19571945-9632-40ac-b076-b3f8824eb9f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1947287038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.1947287038 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.681472425 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 19258103266 ps |
| CPU time | 4139.12 seconds |
| Started | Aug 09 08:23:17 PM PDT 24 |
| Finished | Aug 09 09:32:17 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-9172d64c-3a48-45dc-b9eb-9bb124a413fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=681472425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.681472425 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3708517430 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 25743883525 ps |
| CPU time | 4281.98 seconds |
| Started | Aug 09 08:26:17 PM PDT 24 |
| Finished | Aug 09 09:37:40 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-e25db82c-8a33-4577-83e3-277df4c5c31c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708517430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3708517430 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3078701553 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3220754068 ps |
| CPU time | 484.09 seconds |
| Started | Aug 09 08:20:23 PM PDT 24 |
| Finished | Aug 09 08:28:27 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-52784230-7834-4de9-b210-225b496bf3c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078701553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.3078701553 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.75260020 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 6282014270 ps |
| CPU time | 841.64 seconds |
| Started | Aug 09 08:25:11 PM PDT 24 |
| Finished | Aug 09 08:39:13 PM PDT 24 |
| Peak memory | 608900 kb |
| Host | smart-d6084477-dedf-4779-9443-652cb79c1984 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=75260020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.75260020 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.415932276 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 5186919992 ps |
| CPU time | 1148.38 seconds |
| Started | Aug 09 08:24:46 PM PDT 24 |
| Finished | Aug 09 08:43:55 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-1a3e5d9d-cb19-4558-abee-86952b2cb362 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415932276 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_smoketest.415932276 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2437200721 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 27443005520 ps |
| CPU time | 5311.58 seconds |
| Started | Aug 09 08:21:31 PM PDT 24 |
| Finished | Aug 09 09:50:03 PM PDT 24 |
| Peak memory | 608988 kb |
| Host | smart-45f0ff33-6661-4949-a6eb-bf651d17d890 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243720 0721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.2437200721 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2015752184 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2505409869 ps |
| CPU time | 286.1 seconds |
| Started | Aug 09 08:19:57 PM PDT 24 |
| Finished | Aug 09 08:24:44 PM PDT 24 |
| Peak memory | 608580 kb |
| Host | smart-6e1bee2d-8389-4cdb-9b97-824be4187328 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015752184 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.2015752184 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4206648453 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 6064501592 ps |
| CPU time | 613.25 seconds |
| Started | Aug 09 08:25:51 PM PDT 24 |
| Finished | Aug 09 08:36:05 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-8fc50237-f74f-4889-affa-34dc81ce13f9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4206648453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.4206648453 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.582232113 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 6730455120 ps |
| CPU time | 1493.56 seconds |
| Started | Aug 09 08:21:34 PM PDT 24 |
| Finished | Aug 09 08:46:28 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-1fcf5afc-cfcb-4238-85e7-882269ac6065 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=582232113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.582232113 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2949339181 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 7754656696 ps |
| CPU time | 964.96 seconds |
| Started | Aug 09 08:25:51 PM PDT 24 |
| Finished | Aug 09 08:41:58 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-417640a6-1dbd-4ba0-9add-9133b9d48908 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2949339181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.2949339181 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3588064392 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 6648752190 ps |
| CPU time | 1268.55 seconds |
| Started | Aug 09 08:20:46 PM PDT 24 |
| Finished | Aug 09 08:41:55 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-4ef1d9d2-9f11-4c3e-9251-567febf71799 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3588064392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3588064392 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2878017296 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4402566242 ps |
| CPU time | 748.6 seconds |
| Started | Aug 09 08:27:24 PM PDT 24 |
| Finished | Aug 09 08:39:54 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-ebb52dc5-0a86-4f26-bb7d-e9a0cd9b2d5e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2878017296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2878017296 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3421637392 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 3165219818 ps |
| CPU time | 198.54 seconds |
| Started | Aug 09 08:22:25 PM PDT 24 |
| Finished | Aug 09 08:25:44 PM PDT 24 |
| Peak memory | 608144 kb |
| Host | smart-8b4941de-5cae-41bb-8d44-eb5994201752 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421637392 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.3421637392 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.3075563835 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 4077772172 ps |
| CPU time | 661.6 seconds |
| Started | Aug 09 08:23:20 PM PDT 24 |
| Finished | Aug 09 08:34:22 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-e50d07bb-ee3b-4e92-a163-7c4be789e1b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075563835 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.3075563835 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.1072384437 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 11763942568 ps |
| CPU time | 660.24 seconds |
| Started | Aug 09 08:22:59 PM PDT 24 |
| Finished | Aug 09 08:34:00 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-3881572d-ef25-4160-bcd6-35f81d576d7f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072384437 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.1072384437 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_virus.2970885710 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 5802216952 ps |
| CPU time | 1589.38 seconds |
| Started | Aug 09 08:27:28 PM PDT 24 |
| Finished | Aug 09 08:53:57 PM PDT 24 |
| Peak memory | 624804 kb |
| Host | smart-12057a8a-f4ac-4076-9044-d6b58a1efb98 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2970885710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.2970885710 |
| Directory | /workspace/0.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2907692175 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 11144587217 ps |
| CPU time | 1412.18 seconds |
| Started | Aug 09 08:19:41 PM PDT 24 |
| Finished | Aug 09 08:43:14 PM PDT 24 |
| Peak memory | 611020 kb |
| Host | smart-ce36ade4-7f04-49af-8957-f41e58d0e811 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907 692175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2907692175 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.82215978 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 24369267333 ps |
| CPU time | 2194 seconds |
| Started | Aug 09 08:22:37 PM PDT 24 |
| Finished | Aug 09 08:59:12 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-9595eb00-7af8-4e6c-a9f4-4c844de730c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822 15978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.82215978 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1842792628 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 13527387171 ps |
| CPU time | 1119.33 seconds |
| Started | Aug 09 08:19:17 PM PDT 24 |
| Finished | Aug 09 08:37:57 PM PDT 24 |
| Peak memory | 611416 kb |
| Host | smart-e090ad5c-6281-4589-9b0c-10fafda73a0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1842792628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1842792628 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1626047685 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 23611627120 ps |
| CPU time | 1540.06 seconds |
| Started | Aug 09 08:27:06 PM PDT 24 |
| Finished | Aug 09 08:52:47 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-eea87d1d-24da-4b95-bfdd-1f5e42f85cfc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1626047685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1626047685 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.981707227 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 8724202500 ps |
| CPU time | 637.27 seconds |
| Started | Aug 09 08:23:19 PM PDT 24 |
| Finished | Aug 09 08:33:57 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-a7277983-8a03-4db4-aa19-18deca2e1efc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981707227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.981707227 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2633485838 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 6199701140 ps |
| CPU time | 601.33 seconds |
| Started | Aug 09 08:27:54 PM PDT 24 |
| Finished | Aug 09 08:37:57 PM PDT 24 |
| Peak memory | 617292 kb |
| Host | smart-ab28ea30-a7e7-485e-99b3-65a6e1f537e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2633485838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2633485838 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1379773224 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 7719407097 ps |
| CPU time | 569.61 seconds |
| Started | Aug 09 08:23:38 PM PDT 24 |
| Finished | Aug 09 08:33:08 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-293bbd98-a8b5-47a3-8cdb-35f8f2236f71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379773224 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.1379773224 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1684521374 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 4614695946 ps |
| CPU time | 514.51 seconds |
| Started | Aug 09 08:20:13 PM PDT 24 |
| Finished | Aug 09 08:28:48 PM PDT 24 |
| Peak memory | 616492 kb |
| Host | smart-cdf5e662-7b22-477f-b36d-164a790d0b89 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1684521374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.1684521374 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1291740414 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 10712171231 ps |
| CPU time | 1251.28 seconds |
| Started | Aug 09 08:28:10 PM PDT 24 |
| Finished | Aug 09 08:49:02 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-10fa11f4-225b-4b25-a09b-75fd213bfa38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291740414 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1291740414 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1994743480 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 6826406292 ps |
| CPU time | 437.77 seconds |
| Started | Aug 09 08:22:54 PM PDT 24 |
| Finished | Aug 09 08:30:12 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-e0189bdd-41cc-4d1b-be76-0182df79802f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994743480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1994743480 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1817325777 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 6811237860 ps |
| CPU time | 657.84 seconds |
| Started | Aug 09 08:22:01 PM PDT 24 |
| Finished | Aug 09 08:32:59 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-14640197-4691-4327-bc62-011b6ecf85a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817325777 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.1817325777 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1771297506 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 26647354548 ps |
| CPU time | 2469.36 seconds |
| Started | Aug 09 08:20:19 PM PDT 24 |
| Finished | Aug 09 09:01:29 PM PDT 24 |
| Peak memory | 611384 kb |
| Host | smart-30b43947-635f-43ac-9325-a5c8bf971add |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1771297506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1771297506 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2118722903 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 36852386226 ps |
| CPU time | 4352.88 seconds |
| Started | Aug 09 08:19:43 PM PDT 24 |
| Finished | Aug 09 09:32:17 PM PDT 24 |
| Peak memory | 611740 kb |
| Host | smart-7c288de8-fac5-46a9-b3ab-f7ad761a1cf8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118722903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2118722903 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1824505061 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 2927248720 ps |
| CPU time | 272.04 seconds |
| Started | Aug 09 08:27:50 PM PDT 24 |
| Finished | Aug 09 08:32:23 PM PDT 24 |
| Peak memory | 609576 kb |
| Host | smart-15c0d644-7613-4d90-97e4-accd535d518e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824505061 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.1824505061 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.654597615 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 6244654388 ps |
| CPU time | 490.57 seconds |
| Started | Aug 09 08:21:07 PM PDT 24 |
| Finished | Aug 09 08:29:18 PM PDT 24 |
| Peak memory | 616672 kb |
| Host | smart-087138d5-8290-4a7d-a621-30f65463bc69 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=654597615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.654597615 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1104414599 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5235679300 ps |
| CPU time | 337.73 seconds |
| Started | Aug 09 08:23:03 PM PDT 24 |
| Finished | Aug 09 08:28:41 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-fd3862f2-ea04-45cd-9192-a6ec996d4bf8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1104414599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1104414599 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2533575781 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 5426582636 ps |
| CPU time | 372.32 seconds |
| Started | Aug 09 08:22:52 PM PDT 24 |
| Finished | Aug 09 08:29:04 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-b65f8e29-7a76-4b48-b106-bf995bc024da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533575781 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.2533575781 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.123506462 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 5798961485 ps |
| CPU time | 1008.71 seconds |
| Started | Aug 09 08:20:43 PM PDT 24 |
| Finished | Aug 09 08:37:34 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-c20eb196-1cf2-4d1c-9031-e5f12a356609 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123506462 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.123506462 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1617088841 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 5183024616 ps |
| CPU time | 433.49 seconds |
| Started | Aug 09 08:20:26 PM PDT 24 |
| Finished | Aug 09 08:27:40 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-0530c86c-b483-46ce-a70f-104ee7e98343 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617088841 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1617088841 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2324568619 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 4703209042 ps |
| CPU time | 288.98 seconds |
| Started | Aug 09 08:24:47 PM PDT 24 |
| Finished | Aug 09 08:29:36 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-7bf224b6-b8ed-4637-92c6-245fac5e2db4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324568619 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.2324568619 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1018668673 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 4694340936 ps |
| CPU time | 748.12 seconds |
| Started | Aug 09 08:22:23 PM PDT 24 |
| Finished | Aug 09 08:34:52 PM PDT 24 |
| Peak memory | 609060 kb |
| Host | smart-f4b10347-b34c-43cc-9349-b0648bd7093e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101 8668673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.1018668673 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.4160139767 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 8936430995 ps |
| CPU time | 493.2 seconds |
| Started | Aug 09 08:20:27 PM PDT 24 |
| Finished | Aug 09 08:28:40 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-d484fae8-32dc-473d-b219-79d5ec6df0ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160139767 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.4160139767 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3698018861 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 6251316540 ps |
| CPU time | 659.43 seconds |
| Started | Aug 09 08:22:19 PM PDT 24 |
| Finished | Aug 09 08:33:18 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-5ddb1822-eb03-4ed1-93f9-95e7f8156ad0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698018861 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.3698018861 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2735013818 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5267456936 ps |
| CPU time | 650.71 seconds |
| Started | Aug 09 08:21:36 PM PDT 24 |
| Finished | Aug 09 08:32:27 PM PDT 24 |
| Peak memory | 641312 kb |
| Host | smart-0176cd16-285a-4ad2-8e2c-77aa60fcf17f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2735013818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.2735013818 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1577397863 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 3310743534 ps |
| CPU time | 279.85 seconds |
| Started | Aug 09 08:26:14 PM PDT 24 |
| Finished | Aug 09 08:30:55 PM PDT 24 |
| Peak memory | 609520 kb |
| Host | smart-aedfdbb2-1530-4488-8f71-4d82d56882f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577397863 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.1577397863 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3727822986 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 3656819080 ps |
| CPU time | 366.38 seconds |
| Started | Aug 09 08:20:15 PM PDT 24 |
| Finished | Aug 09 08:26:22 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-de184f0a-0186-426e-88d7-43ca9b6996f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727822986 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.3727822986 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2720553618 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 3163947662 ps |
| CPU time | 179.92 seconds |
| Started | Aug 09 08:22:07 PM PDT 24 |
| Finished | Aug 09 08:25:09 PM PDT 24 |
| Peak memory | 608260 kb |
| Host | smart-df351348-3352-4a04-8765-256c9e6276bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720553618 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.2720553618 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1834991829 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3268207505 ps |
| CPU time | 302.42 seconds |
| Started | Aug 09 08:23:13 PM PDT 24 |
| Finished | Aug 09 08:28:16 PM PDT 24 |
| Peak memory | 608724 kb |
| Host | smart-a73b1aea-c8f2-40ca-a268-cd2ff7c5d9a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834991829 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.1834991829 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2107789814 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 5604491984 ps |
| CPU time | 928.61 seconds |
| Started | Aug 09 08:19:20 PM PDT 24 |
| Finished | Aug 09 08:34:49 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-538e016b-b499-49c2-80e7-316f2a04a163 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2107789814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.2107789814 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1417665017 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6088779198 ps |
| CPU time | 698.61 seconds |
| Started | Aug 09 08:23:49 PM PDT 24 |
| Finished | Aug 09 08:35:28 PM PDT 24 |
| Peak memory | 620324 kb |
| Host | smart-4de7f0ab-6af8-4de1-9d14-8f309ccb938d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417665017 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.1417665017 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3689582609 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5899588086 ps |
| CPU time | 587.9 seconds |
| Started | Aug 09 08:29:01 PM PDT 24 |
| Finished | Aug 09 08:38:49 PM PDT 24 |
| Peak memory | 619484 kb |
| Host | smart-fb0b35f7-0aaf-484f-82c4-630eaa77701a |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368958 2609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3689582609 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.801004037 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 2639250968 ps |
| CPU time | 248.99 seconds |
| Started | Aug 09 08:27:01 PM PDT 24 |
| Finished | Aug 09 08:31:11 PM PDT 24 |
| Peak memory | 609536 kb |
| Host | smart-c18aaca2-268c-4455-8ff3-a02c8e5fab50 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801004037 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rv_plic_smoketest.801004037 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.2900407774 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2804518550 ps |
| CPU time | 384.46 seconds |
| Started | Aug 09 08:21:10 PM PDT 24 |
| Finished | Aug 09 08:27:35 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-a142a25d-228b-4359-8947-0c11d90d323a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900407774 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.2900407774 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1607991951 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 3618333280 ps |
| CPU time | 284.35 seconds |
| Started | Aug 09 08:26:41 PM PDT 24 |
| Finished | Aug 09 08:31:26 PM PDT 24 |
| Peak memory | 609476 kb |
| Host | smart-917895d5-eff6-4c46-8364-0847d07bca67 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607991951 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.1607991951 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.673332530 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2600436728 ps |
| CPU time | 231.8 seconds |
| Started | Aug 09 08:23:42 PM PDT 24 |
| Finished | Aug 09 08:27:34 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-98b0ea2f-300e-4c5a-b1c7-3f9d7078b888 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6733325 30 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.673332530 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1339045986 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3187473808 ps |
| CPU time | 300.25 seconds |
| Started | Aug 09 08:19:32 PM PDT 24 |
| Finished | Aug 09 08:24:33 PM PDT 24 |
| Peak memory | 608784 kb |
| Host | smart-9cd55a1e-ca18-4d0c-97ac-44cd3e26bb8c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339045986 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.1339045986 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.4123407374 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 7884521910 ps |
| CPU time | 1025.31 seconds |
| Started | Aug 09 08:19:09 PM PDT 24 |
| Finished | Aug 09 08:36:15 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-19a1f890-6d80-4956-b9f6-75e70f604574 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123407374 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.4123407374 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3755519808 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 7594480030 ps |
| CPU time | 738.33 seconds |
| Started | Aug 09 08:22:03 PM PDT 24 |
| Finished | Aug 09 08:34:21 PM PDT 24 |
| Peak memory | 610468 kb |
| Host | smart-1bd3eab3-1d35-47fc-8206-ad2c9b1f4a3d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755519808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.3755519808 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.4059484166 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 5616897966 ps |
| CPU time | 552.72 seconds |
| Started | Aug 09 08:21:04 PM PDT 24 |
| Finished | Aug 09 08:30:17 PM PDT 24 |
| Peak memory | 624640 kb |
| Host | smart-b1739060-b419-4466-9722-8c39aaca2b27 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059484166 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.4059484166 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.165238553 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3838389470 ps |
| CPU time | 489.93 seconds |
| Started | Aug 09 08:19:09 PM PDT 24 |
| Finished | Aug 09 08:27:20 PM PDT 24 |
| Peak memory | 624568 kb |
| Host | smart-1d87cc1c-b03f-42bb-8a49-d0b94127bd12 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165238553 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.165238553 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.2398850503 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4131165072 ps |
| CPU time | 429.07 seconds |
| Started | Aug 09 08:23:42 PM PDT 24 |
| Finished | Aug 09 08:30:51 PM PDT 24 |
| Peak memory | 619416 kb |
| Host | smart-3e4796c5-f751-43c5-9e2b-5c0c54c383e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398850503 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2398850503 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1433207634 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2798941308 ps |
| CPU time | 277.26 seconds |
| Started | Aug 09 08:24:20 PM PDT 24 |
| Finished | Aug 09 08:28:58 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-6213dfc7-2d8d-445d-b3c7-f13eb8a8355e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433207634 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1433207634 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1453030700 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 5120644555 ps |
| CPU time | 629.92 seconds |
| Started | Aug 09 08:22:31 PM PDT 24 |
| Finished | Aug 09 08:33:02 PM PDT 24 |
| Peak memory | 611080 kb |
| Host | smart-2823ca60-312f-430f-bd86-0b6d53f25647 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453030700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1453030700 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.323926708 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 4683237428 ps |
| CPU time | 561.47 seconds |
| Started | Aug 09 08:23:34 PM PDT 24 |
| Finished | Aug 09 08:32:56 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-55bd1792-c063-4137-a5cb-06d4e6ac686e |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323926708 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.323926708 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1912114604 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2757149350 ps |
| CPU time | 233.39 seconds |
| Started | Aug 09 08:28:08 PM PDT 24 |
| Finished | Aug 09 08:32:01 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-b3ef6f1e-fb90-4af3-92dd-e77f90ffd52e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912114604 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.1912114604 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2672627859 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 20935518527 ps |
| CPU time | 3771.4 seconds |
| Started | Aug 09 08:20:38 PM PDT 24 |
| Finished | Aug 09 09:23:31 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-4e34f202-2f9d-4e43-b69a-1ce1fbd79aa5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672627859 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.2672627859 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4262699734 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4165146510 ps |
| CPU time | 657.21 seconds |
| Started | Aug 09 08:20:12 PM PDT 24 |
| Finished | Aug 09 08:31:12 PM PDT 24 |
| Peak memory | 613236 kb |
| Host | smart-37ea1690-fd57-476a-819e-fedee3d9b659 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262699734 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.4262699734 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3882553087 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3285392930 ps |
| CPU time | 302.89 seconds |
| Started | Aug 09 08:20:06 PM PDT 24 |
| Finished | Aug 09 08:25:10 PM PDT 24 |
| Peak memory | 613124 kb |
| Host | smart-04fde3ef-73d4-4a33-8918-ecd76a9febbe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882553087 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.3882553087 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1779801929 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 3153608420 ps |
| CPU time | 339.71 seconds |
| Started | Aug 09 08:21:38 PM PDT 24 |
| Finished | Aug 09 08:27:19 PM PDT 24 |
| Peak memory | 609140 kb |
| Host | smart-085ee82d-479e-498d-9a1e-a62ec0c964c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779801929 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.1779801929 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1798295674 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 20938584380 ps |
| CPU time | 1738.25 seconds |
| Started | Aug 09 08:22:08 PM PDT 24 |
| Finished | Aug 09 08:51:08 PM PDT 24 |
| Peak memory | 614732 kb |
| Host | smart-3aebbc37-39a8-4a92-bbd3-cfab82e5b0ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17982956 74 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.1798295674 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.143746386 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7254616570 ps |
| CPU time | 677.16 seconds |
| Started | Aug 09 08:23:15 PM PDT 24 |
| Finished | Aug 09 08:34:33 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-8870319a-5a92-40a6-a70d-70048b98ce5d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143746386 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.143746386 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1220556171 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 8206512200 ps |
| CPU time | 1617.52 seconds |
| Started | Aug 09 08:19:20 PM PDT 24 |
| Finished | Aug 09 08:46:18 PM PDT 24 |
| Peak memory | 623456 kb |
| Host | smart-4c90f55a-b068-47b1-944a-6ec9c7b6bb88 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1220556171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1220556171 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.3130704326 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 2775815398 ps |
| CPU time | 256.89 seconds |
| Started | Aug 09 08:24:57 PM PDT 24 |
| Finished | Aug 09 08:29:15 PM PDT 24 |
| Peak memory | 614552 kb |
| Host | smart-aa1e802d-6c76-48ee-b873-a8cb4313585b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130704326 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.3130704326 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.1268878851 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 4255147440 ps |
| CPU time | 596.42 seconds |
| Started | Aug 09 08:19:44 PM PDT 24 |
| Finished | Aug 09 08:29:41 PM PDT 24 |
| Peak memory | 623644 kb |
| Host | smart-65683212-6e91-444d-b77f-028253580c5a |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268878851 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1268878851 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1818528932 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 13851425039 ps |
| CPU time | 1796.04 seconds |
| Started | Aug 09 08:19:36 PM PDT 24 |
| Finished | Aug 09 08:49:32 PM PDT 24 |
| Peak memory | 618900 kb |
| Host | smart-6097ee8e-2bed-47cf-9b16-e47093c0acf4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818528932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1818528932 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2612667316 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 78431310400 ps |
| CPU time | 13210.2 seconds |
| Started | Aug 09 08:21:46 PM PDT 24 |
| Finished | Aug 10 12:01:58 AM PDT 24 |
| Peak memory | 633908 kb |
| Host | smart-c28b8cb1-fd11-4be5-98c3-45f99f603a57 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2612667316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.2612667316 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1382192435 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 4949810360 ps |
| CPU time | 778.95 seconds |
| Started | Aug 09 08:21:00 PM PDT 24 |
| Finished | Aug 09 08:34:01 PM PDT 24 |
| Peak memory | 624020 kb |
| Host | smart-21bb27cb-e40f-4731-ae79-81ad75318fab |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382192435 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.1382192435 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.315863861 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 4769983992 ps |
| CPU time | 632.36 seconds |
| Started | Aug 09 08:20:19 PM PDT 24 |
| Finished | Aug 09 08:30:52 PM PDT 24 |
| Peak memory | 624076 kb |
| Host | smart-7f6105ff-fc11-4205-aaeb-19cf587691af |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315863861 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.315863861 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.794212455 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 3609095299 ps |
| CPU time | 221.54 seconds |
| Started | Aug 09 08:21:40 PM PDT 24 |
| Finished | Aug 09 08:25:21 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-283705e5-f73c-4314-b4f3-3f8bf03ccf61 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794212455 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.794212455 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.1299877871 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 12399683148 ps |
| CPU time | 3191.93 seconds |
| Started | Aug 09 08:19:10 PM PDT 24 |
| Finished | Aug 09 09:12:23 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-98a44407-aaff-4c24-a92c-53964b2c1acb |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1299877871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.1299877871 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2801904551 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 31398371360 ps |
| CPU time | 6926.29 seconds |
| Started | Aug 09 08:19:22 PM PDT 24 |
| Finished | Aug 09 10:14:49 PM PDT 24 |
| Peak memory | 608748 kb |
| Host | smart-892cae51-81f7-4833-aa12-3c4e8a94e79a |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2801904551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2801904551 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.1353277126 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3313539680 ps |
| CPU time | 320.33 seconds |
| Started | Aug 09 08:21:10 PM PDT 24 |
| Finished | Aug 09 08:26:31 PM PDT 24 |
| Peak memory | 608284 kb |
| Host | smart-3f598d26-2754-4cf2-a99d-92dca3ffa7c3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353277126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.1353277126 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.997626044 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3930327500 ps |
| CPU time | 642.85 seconds |
| Started | Aug 09 08:23:57 PM PDT 24 |
| Finished | Aug 09 08:34:41 PM PDT 24 |
| Peak memory | 609520 kb |
| Host | smart-d1cffe72-54ca-47c7-bfc8-8bfbc8a860db |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997626044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.997626044 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.2077159024 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 19172796320 ps |
| CPU time | 4210.43 seconds |
| Started | Aug 09 08:21:53 PM PDT 24 |
| Finished | Aug 09 09:32:05 PM PDT 24 |
| Peak memory | 609088 kb |
| Host | smart-24d555a2-511b-4a0e-b502-9f1e9cc61b75 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2077159024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.2077159024 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.3061341764 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 2772757864 ps |
| CPU time | 222.04 seconds |
| Started | Aug 09 08:21:05 PM PDT 24 |
| Finished | Aug 09 08:24:48 PM PDT 24 |
| Peak memory | 609556 kb |
| Host | smart-18fefddc-3a19-41aa-9106-e1363724dfd5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061341764 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3061341764 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.1790680110 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 2484724845 ps |
| CPU time | 125.03 seconds |
| Started | Aug 09 08:21:50 PM PDT 24 |
| Finished | Aug 09 08:23:55 PM PDT 24 |
| Peak memory | 623140 kb |
| Host | smart-34b7cd59-40b6-48b2-a7d3-c14915edd058 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790680110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.1790680110 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.2994290810 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 15907714216 ps |
| CPU time | 3457.55 seconds |
| Started | Aug 09 08:26:41 PM PDT 24 |
| Finished | Aug 09 09:24:20 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-192054c0-1995-4aad-948f-bffa31214a24 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994290810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.2994290810 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.4052062382 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 15961797156 ps |
| CPU time | 4216.07 seconds |
| Started | Aug 09 08:29:29 PM PDT 24 |
| Finished | Aug 09 09:39:46 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-cc0285fb-ac3e-4d9b-a878-51b4a6e06b63 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052062382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.4052062382 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.563653255 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 15606372996 ps |
| CPU time | 3460.26 seconds |
| Started | Aug 09 08:25:21 PM PDT 24 |
| Finished | Aug 09 09:23:02 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-156e3e77-344f-49a3-b2d0-98497a4e0dfe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563653255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.rom_e2e_asm_init_prod_end.563653255 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.1447021917 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 14262526920 ps |
| CPU time | 3798.6 seconds |
| Started | Aug 09 08:29:58 PM PDT 24 |
| Finished | Aug 09 09:33:17 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-0c0ecb54-b14e-45fa-a271-956a4309f166 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447021917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.1447021917 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3700528529 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 10686880122 ps |
| CPU time | 2852.96 seconds |
| Started | Aug 09 08:29:56 PM PDT 24 |
| Finished | Aug 09 09:17:30 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-addf9621-8fe0-44d6-af7f-7ce9a69ea363 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700528529 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.3700528529 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1516005861 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 24113197000 ps |
| CPU time | 5435.13 seconds |
| Started | Aug 09 08:31:01 PM PDT 24 |
| Finished | Aug 09 10:01:37 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-f41ea836-6fb5-42f8-949f-c5487c6107cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1516005861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1516005861 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.616147654 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 23488545672 ps |
| CPU time | 6659.19 seconds |
| Started | Aug 09 08:29:08 PM PDT 24 |
| Finished | Aug 09 10:20:08 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-02373e8e-db81-4b52-bc84-2b9e55ec9d41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=616147654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.616147654 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1171561500 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 22983084862 ps |
| CPU time | 5500.7 seconds |
| Started | Aug 09 08:29:44 PM PDT 24 |
| Finished | Aug 09 10:01:26 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-1a1feace-f617-4dcf-a7ae-17521ade7cf2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1171561500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1171561500 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3993676535 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 18271702644 ps |
| CPU time | 5691.51 seconds |
| Started | Aug 09 08:28:13 PM PDT 24 |
| Finished | Aug 09 10:03:05 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-73b9688d-026e-4b95-a499-c5734372c42e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993676535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3993676535 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3082995169 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 15254877590 ps |
| CPU time | 4119.31 seconds |
| Started | Aug 09 08:28:53 PM PDT 24 |
| Finished | Aug 09 09:37:33 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-7fd84086-2b74-4e4f-adb6-96881f7ca230 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3082995169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3082995169 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.748747439 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 15497893382 ps |
| CPU time | 3594.03 seconds |
| Started | Aug 09 08:30:04 PM PDT 24 |
| Finished | Aug 09 09:29:59 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-d3b58b22-af41-47f0-ac1b-9cc0d719ec53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=748747439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.748747439 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2283229559 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 15272054648 ps |
| CPU time | 3696.75 seconds |
| Started | Aug 09 08:30:44 PM PDT 24 |
| Finished | Aug 09 09:32:22 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-33c4b31f-0685-4f5e-ae3d-15ba5882849a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2283229559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2283229559 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2384021899 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 14896876794 ps |
| CPU time | 4210.51 seconds |
| Started | Aug 09 08:28:33 PM PDT 24 |
| Finished | Aug 09 09:38:44 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-ca811225-3b13-4333-9939-41cb9a60d589 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2384021899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2384021899 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1500213333 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 11486619666 ps |
| CPU time | 3328.67 seconds |
| Started | Aug 09 08:29:00 PM PDT 24 |
| Finished | Aug 09 09:24:29 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-471083e4-7574-482f-91e4-1ff9111959e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500213333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1500213333 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2791689984 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 16282425524 ps |
| CPU time | 3934.03 seconds |
| Started | Aug 09 08:28:20 PM PDT 24 |
| Finished | Aug 09 09:33:54 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-64f0e5a9-0f2b-428d-b6e2-25839befd317 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791689984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2791689984 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2050466168 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 15857709842 ps |
| CPU time | 3704.27 seconds |
| Started | Aug 09 08:27:17 PM PDT 24 |
| Finished | Aug 09 09:29:02 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-3c4d46a3-e465-402e-868d-e57af740504a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050466168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2050466168 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3455889613 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 15384920290 ps |
| CPU time | 3713.39 seconds |
| Started | Aug 09 08:27:48 PM PDT 24 |
| Finished | Aug 09 09:29:42 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-320d69f8-a4c3-4d7f-936c-e02a9ec66c6d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345588 9613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3455889613 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1725392513 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 14374842368 ps |
| CPU time | 3847.52 seconds |
| Started | Aug 09 08:30:10 PM PDT 24 |
| Finished | Aug 09 09:34:18 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-f7d3de4d-91e5-4f90-a96a-e607c933faf3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725392513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1725392513 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2716084027 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 11845012504 ps |
| CPU time | 2797.09 seconds |
| Started | Aug 09 08:31:44 PM PDT 24 |
| Finished | Aug 09 09:18:22 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-d663861a-5721-4e6e-a380-4ee21054d1dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2716084027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2716084027 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2867673534 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 11932071792 ps |
| CPU time | 2111.56 seconds |
| Started | Aug 09 08:24:39 PM PDT 24 |
| Finished | Aug 09 08:59:52 PM PDT 24 |
| Peak memory | 624364 kb |
| Host | smart-d44cc78f-0329-4799-84cd-caf0ab034b9e |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28676 73534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.2867673534 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3078316996 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 10929417864 ps |
| CPU time | 1598.48 seconds |
| Started | Aug 09 08:23:32 PM PDT 24 |
| Finished | Aug 09 08:50:11 PM PDT 24 |
| Peak memory | 624348 kb |
| Host | smart-5e77a3b8-706f-45c4-b56c-6f06fcbf6e18 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3078316996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.3078316996 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1049034887 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 32024923626 ps |
| CPU time | 2714.74 seconds |
| Started | Aug 09 08:24:44 PM PDT 24 |
| Finished | Aug 09 09:09:59 PM PDT 24 |
| Peak memory | 620860 kb |
| Host | smart-51a01d36-df53-46ec-87c0-40c4b67ce56c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1049034887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.1049034887 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2599467177 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 23900835376 ps |
| CPU time | 3059.58 seconds |
| Started | Aug 09 08:28:10 PM PDT 24 |
| Finished | Aug 09 09:19:10 PM PDT 24 |
| Peak memory | 620148 kb |
| Host | smart-eb26d065-076c-46f5-92ff-8e06eb21be3e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2599467177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.2599467177 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2121331520 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 30507505196 ps |
| CPU time | 2644.88 seconds |
| Started | Aug 09 08:23:43 PM PDT 24 |
| Finished | Aug 09 09:07:48 PM PDT 24 |
| Peak memory | 620928 kb |
| Host | smart-6a0cd26d-903c-430c-90ec-29cbf9e13b7a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121331520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.2121331520 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1671718106 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 15845993206 ps |
| CPU time | 4161.91 seconds |
| Started | Aug 09 08:26:00 PM PDT 24 |
| Finished | Aug 09 09:35:23 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-c352a3b7-04d2-4e4d-92c2-f2fbfe6166f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671718106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1671718106 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2417183164 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 15325827448 ps |
| CPU time | 3760.63 seconds |
| Started | Aug 09 08:31:45 PM PDT 24 |
| Finished | Aug 09 09:34:27 PM PDT 24 |
| Peak memory | 609996 kb |
| Host | smart-1ee818ae-63db-47e2-806a-afabddbecae5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417183164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2417183164 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.16454092 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 15160276472 ps |
| CPU time | 3789.91 seconds |
| Started | Aug 09 08:31:30 PM PDT 24 |
| Finished | Aug 09 09:34:40 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-36d85815-d221-4316-a032-ece2316177f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16454092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_n o_meas.16454092 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.4062497179 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 26408731810 ps |
| CPU time | 5454.41 seconds |
| Started | Aug 09 08:28:36 PM PDT 24 |
| Finished | Aug 09 09:59:31 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-03f7c779-50bc-45b5-9734-37c32dcf32ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062497179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.4062497179 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.768019177 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 14220817024 ps |
| CPU time | 3614.37 seconds |
| Started | Aug 09 08:27:43 PM PDT 24 |
| Finished | Aug 09 09:27:58 PM PDT 24 |
| Peak memory | 611464 kb |
| Host | smart-b1d13d7f-d14b-466c-a8de-94137953f2a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768019177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_s hutdown_exception_c.768019177 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.2417268381 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 28995052540 ps |
| CPU time | 3360.55 seconds |
| Started | Aug 09 08:32:59 PM PDT 24 |
| Finished | Aug 09 09:29:00 PM PDT 24 |
| Peak memory | 611444 kb |
| Host | smart-9e78280b-3e32-4de2-a5b7-7bb96972e45d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417268381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.2417268381 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3542657239 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 22561477901 ps |
| CPU time | 5779.44 seconds |
| Started | Aug 09 08:30:55 PM PDT 24 |
| Finished | Aug 09 10:07:15 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-362f0af9-6b0e-4870-8c68-2fc786d4934d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3542657239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.3542657239 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.58713609 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 23853916968 ps |
| CPU time | 5290.16 seconds |
| Started | Aug 09 08:31:03 PM PDT 24 |
| Finished | Aug 09 09:59:14 PM PDT 24 |
| Peak memory | 611024 kb |
| Host | smart-764f59d7-3c77-4508-8717-a8e931003e2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=58713609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ba d_b_bad_prod_end.58713609 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1387365847 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 23238413533 ps |
| CPU time | 6480.62 seconds |
| Started | Aug 09 08:31:40 PM PDT 24 |
| Finished | Aug 09 10:19:42 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-e7fadf13-a984-4eb3-9388-e9830ed380c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1387365847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.1387365847 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1844074122 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 18002882814 ps |
| CPU time | 4844.69 seconds |
| Started | Aug 09 08:29:53 PM PDT 24 |
| Finished | Aug 09 09:50:38 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-7ff68a2c-28e3-4866-803f-e586652f49db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1844074122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.1844074122 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3140900763 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 14585084074 ps |
| CPU time | 3873.47 seconds |
| Started | Aug 09 08:31:43 PM PDT 24 |
| Finished | Aug 09 09:36:17 PM PDT 24 |
| Peak memory | 611076 kb |
| Host | smart-32b8c2c5-ae57-413e-9736-e48ee0cb637a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140900763 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3140900763 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.268305871 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 15180609929 ps |
| CPU time | 3749.06 seconds |
| Started | Aug 09 08:30:26 PM PDT 24 |
| Finished | Aug 09 09:32:55 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-fa6bd53c-cd82-4a97-800e-b74b0380b694 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268305871 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.268305871 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3635634639 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 14551987780 ps |
| CPU time | 3928.44 seconds |
| Started | Aug 09 08:30:40 PM PDT 24 |
| Finished | Aug 09 09:36:09 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-f06febfb-21b0-400a-ab67-5c468ac0cc1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635634639 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3635634639 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1223148793 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 13700225240 ps |
| CPU time | 3609.96 seconds |
| Started | Aug 09 08:31:11 PM PDT 24 |
| Finished | Aug 09 09:31:21 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-547998f0-f9da-4592-90c9-7e107d7fd6c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223148793 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1223148793 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1189457828 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 11427219951 ps |
| CPU time | 2773.19 seconds |
| Started | Aug 09 08:29:58 PM PDT 24 |
| Finished | Aug 09 09:16:12 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-dcb1880d-3a1a-40a6-8823-422da77a36af |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189457828 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1189457828 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1635945966 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 14966219325 ps |
| CPU time | 4011.97 seconds |
| Started | Aug 09 08:30:57 PM PDT 24 |
| Finished | Aug 09 09:37:50 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-f9345098-c4c9-4670-9f81-13dca95635eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635945966 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1635945966 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1542072268 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 15455601950 ps |
| CPU time | 4221.91 seconds |
| Started | Aug 09 08:30:51 PM PDT 24 |
| Finished | Aug 09 09:41:14 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-3c3e2bfd-788b-43ec-8de6-7fa93cc5603b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542072268 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1542072268 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2258782664 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 15265753014 ps |
| CPU time | 3660.75 seconds |
| Started | Aug 09 08:28:44 PM PDT 24 |
| Finished | Aug 09 09:29:46 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-50b94e1b-4a5b-48fa-b5bc-fbb5d3cdb9da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258782664 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2258782664 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1167563731 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 13646490366 ps |
| CPU time | 3476.5 seconds |
| Started | Aug 09 08:29:37 PM PDT 24 |
| Finished | Aug 09 09:27:35 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-d7ce4b9b-d392-4d7d-a488-a67dd22e09ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167563731 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1167563731 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3212670442 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 11292914281 ps |
| CPU time | 3149.69 seconds |
| Started | Aug 09 08:31:10 PM PDT 24 |
| Finished | Aug 09 09:23:40 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-df21f640-3609-49bc-a623-003256f5461d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212670442 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3212670442 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.686703296 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 15283629816 ps |
| CPU time | 4178.64 seconds |
| Started | Aug 09 08:29:14 PM PDT 24 |
| Finished | Aug 09 09:38:54 PM PDT 24 |
| Peak memory | 609900 kb |
| Host | smart-d4732773-3e64-4e94-b4d0-c7049322e499 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=686703296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.686703296 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.1830179140 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 16332628062 ps |
| CPU time | 4285.48 seconds |
| Started | Aug 09 08:30:19 PM PDT 24 |
| Finished | Aug 09 09:41:46 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-a86d5b68-812e-47e0-ba6a-3277b2d4f6e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830179140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.1830179140 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.2382623702 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 5173871448 ps |
| CPU time | 576.79 seconds |
| Started | Aug 09 08:23:09 PM PDT 24 |
| Finished | Aug 09 08:32:47 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-4e29298b-1418-4f40-b381-80e66165ec4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382623702 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.2382623702 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.1726456712 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 6022879923 ps |
| CPU time | 270.78 seconds |
| Started | Aug 09 08:27:03 PM PDT 24 |
| Finished | Aug 09 08:31:34 PM PDT 24 |
| Peak memory | 619684 kb |
| Host | smart-8323c7de-6f1e-4da6-ab86-9ccd8350e639 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1726456712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.1726456712 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.4220745389 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2432240913 ps |
| CPU time | 119.61 seconds |
| Started | Aug 09 08:23:53 PM PDT 24 |
| Finished | Aug 09 08:25:53 PM PDT 24 |
| Peak memory | 616876 kb |
| Host | smart-929bfa06-8da8-407e-bbdb-10d8feae9110 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220745389 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.4220745389 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.1906352151 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 13883461632 ps |
| CPU time | 1223.12 seconds |
| Started | Aug 09 08:24:28 PM PDT 24 |
| Finished | Aug 09 08:44:52 PM PDT 24 |
| Peak memory | 607752 kb |
| Host | smart-4000417e-3729-4de7-b73f-b7b202d58961 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906352151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.1 906352151 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.926635546 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 4257561118 ps |
| CPU time | 603.22 seconds |
| Started | Aug 09 08:31:23 PM PDT 24 |
| Finished | Aug 09 08:41:26 PM PDT 24 |
| Peak memory | 609096 kb |
| Host | smart-c2ba42dd-fa13-4d83-b99e-bf52eec5bb55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926635546 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_10.926635546 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1170235293 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3621501798 ps |
| CPU time | 540.87 seconds |
| Started | Aug 09 08:32:41 PM PDT 24 |
| Finished | Aug 09 08:41:42 PM PDT 24 |
| Peak memory | 619624 kb |
| Host | smart-fc2f5242-6720-42ad-b878-10c3c016f7de |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 170235293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.1170235293 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.2246118464 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 2600913496 ps |
| CPU time | 242.26 seconds |
| Started | Aug 09 08:25:50 PM PDT 24 |
| Finished | Aug 09 08:29:52 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-4f6a89b0-04e1-42e7-aea2-79e11f36cc2c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2246118464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.2246118464 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4180653133 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 18078007374 ps |
| CPU time | 357.46 seconds |
| Started | Aug 09 08:27:15 PM PDT 24 |
| Finished | Aug 09 08:33:13 PM PDT 24 |
| Peak memory | 619260 kb |
| Host | smart-e5d366ef-b48f-4eed-a20a-ac7086bbd897 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4180653133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4180653133 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.1396250880 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 2541100280 ps |
| CPU time | 185.09 seconds |
| Started | Aug 09 08:25:42 PM PDT 24 |
| Finished | Aug 09 08:28:47 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-609d489e-feaa-4a1d-8868-a87fc7c479d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396250880 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.1396250880 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1593831752 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 3161286606 ps |
| CPU time | 256.3 seconds |
| Started | Aug 09 08:28:31 PM PDT 24 |
| Finished | Aug 09 08:32:47 PM PDT 24 |
| Peak memory | 608356 kb |
| Host | smart-ad655861-a7f9-4590-9003-ac820a2df37c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593 831752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1593831752 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4096883427 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2888396740 ps |
| CPU time | 229.07 seconds |
| Started | Aug 09 08:34:24 PM PDT 24 |
| Finished | Aug 09 08:38:13 PM PDT 24 |
| Peak memory | 608572 kb |
| Host | smart-419d0184-72f3-418b-a0cf-1531fc007ff4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096883427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.4096883427 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.3904019032 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 3651953302 ps |
| CPU time | 272.83 seconds |
| Started | Aug 09 08:28:10 PM PDT 24 |
| Finished | Aug 09 08:32:43 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-0e4ea84e-4e39-4337-a7c9-37a4c115f26d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904019032 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.3904019032 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.3185589768 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 2656702648 ps |
| CPU time | 280.93 seconds |
| Started | Aug 09 08:26:00 PM PDT 24 |
| Finished | Aug 09 08:30:41 PM PDT 24 |
| Peak memory | 609104 kb |
| Host | smart-aca992af-d2d4-44cb-9225-df6b284a92ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185589768 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.3185589768 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.3911631428 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 3152407701 ps |
| CPU time | 336.64 seconds |
| Started | Aug 09 08:27:22 PM PDT 24 |
| Finished | Aug 09 08:32:58 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-f7401b51-653d-4564-aa73-f7adbe24dc2d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911631428 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.3911631428 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.3940346793 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 2182448514 ps |
| CPU time | 239.61 seconds |
| Started | Aug 09 08:34:50 PM PDT 24 |
| Finished | Aug 09 08:38:50 PM PDT 24 |
| Peak memory | 609496 kb |
| Host | smart-184aebc7-e8f4-4025-b37a-a30b247eccb6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940346793 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.3940346793 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1173163125 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3464389763 ps |
| CPU time | 348.85 seconds |
| Started | Aug 09 08:27:01 PM PDT 24 |
| Finished | Aug 09 08:32:50 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-1e7b6780-7632-449b-9f95-4be428bad18f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1173163125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.1173163125 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.994011949 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 6244698510 ps |
| CPU time | 664 seconds |
| Started | Aug 09 08:28:35 PM PDT 24 |
| Finished | Aug 09 08:39:39 PM PDT 24 |
| Peak memory | 619512 kb |
| Host | smart-5daa572d-572e-4806-bb19-b2bd4f4fbb93 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=994011949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.994011949 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.291870574 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 8802757434 ps |
| CPU time | 2208.15 seconds |
| Started | Aug 09 08:32:40 PM PDT 24 |
| Finished | Aug 09 09:09:28 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-d8c302e7-55a1-4721-b73c-0ae03f08bb18 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=291870574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.291870574 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3370246362 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 6663914640 ps |
| CPU time | 1330.03 seconds |
| Started | Aug 09 08:31:00 PM PDT 24 |
| Finished | Aug 09 08:53:11 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-66db49df-3089-4048-90ea-bfb84a37422d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370246362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.3370246362 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.886159437 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 11630855576 ps |
| CPU time | 1263.76 seconds |
| Started | Aug 09 08:27:31 PM PDT 24 |
| Finished | Aug 09 08:48:35 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-05d20d14-a645-4a31-9ca9-2ca919347b54 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886159437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.886159437 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2521370733 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 7648456652 ps |
| CPU time | 1578.27 seconds |
| Started | Aug 09 08:26:38 PM PDT 24 |
| Finished | Aug 09 08:52:57 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-16769a3e-3ce0-4dc2-ae5c-e6a38a62e4ea |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2521370733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.2521370733 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.311809815 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 3907579624 ps |
| CPU time | 319.81 seconds |
| Started | Aug 09 08:29:55 PM PDT 24 |
| Finished | Aug 09 08:35:15 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-49dcc13b-a8a9-4cd8-b5f5-c8e9e7c3642c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=311809815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.311809815 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3760525498 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 255938029528 ps |
| CPU time | 12535.7 seconds |
| Started | Aug 09 08:27:08 PM PDT 24 |
| Finished | Aug 09 11:56:05 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-c2ccdedf-2a69-4d3c-a6b3-64466d7b0246 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760525498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3760525498 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.3422913500 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3298166334 ps |
| CPU time | 393.17 seconds |
| Started | Aug 09 08:28:45 PM PDT 24 |
| Finished | Aug 09 08:35:19 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-014bfd01-b54d-41e3-b18b-6d7759fb785d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422913500 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.3422913500 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.1344255273 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 4287121900 ps |
| CPU time | 410.82 seconds |
| Started | Aug 09 08:29:49 PM PDT 24 |
| Finished | Aug 09 08:36:40 PM PDT 24 |
| Peak memory | 609448 kb |
| Host | smart-dd7eef34-e608-48fd-bf0a-b1f99a7193d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344255273 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.1344255273 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3395771468 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 6481628916 ps |
| CPU time | 347.88 seconds |
| Started | Aug 09 08:26:20 PM PDT 24 |
| Finished | Aug 09 08:32:08 PM PDT 24 |
| Peak memory | 609052 kb |
| Host | smart-896473b8-4db3-4a35-89a8-78e3c372b1a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3395771468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3395771468 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2747480894 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 3510127228 ps |
| CPU time | 373.98 seconds |
| Started | Aug 09 08:35:11 PM PDT 24 |
| Finished | Aug 09 08:41:26 PM PDT 24 |
| Peak memory | 609536 kb |
| Host | smart-e1044d5f-7279-46c9-95c8-db7c311dfb62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747480894 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.2747480894 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3751187514 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 7995316616 ps |
| CPU time | 747.97 seconds |
| Started | Aug 09 08:26:58 PM PDT 24 |
| Finished | Aug 09 08:39:26 PM PDT 24 |
| Peak memory | 609428 kb |
| Host | smart-41d34750-dbdb-4323-aec5-f3dad66ee6e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3751187514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.3751187514 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2936856612 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 6541308816 ps |
| CPU time | 571.93 seconds |
| Started | Aug 09 08:26:43 PM PDT 24 |
| Finished | Aug 09 08:36:16 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-c29623d4-fbd4-4dc3-99cc-d480fba99ba9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2936856612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.2936856612 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2139068694 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 7016566278 ps |
| CPU time | 1074.23 seconds |
| Started | Aug 09 08:31:14 PM PDT 24 |
| Finished | Aug 09 08:49:08 PM PDT 24 |
| Peak memory | 616784 kb |
| Host | smart-3ae75fb9-d1da-44c8-bd83-94313f816147 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139068694 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2139068694 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2653472815 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 25506899546 ps |
| CPU time | 4191.5 seconds |
| Started | Aug 09 08:33:30 PM PDT 24 |
| Finished | Aug 09 09:43:23 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-a98753e0-a240-47d5-ba1c-021201858840 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653472815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.2653472815 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3544537538 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 6144072763 ps |
| CPU time | 637.37 seconds |
| Started | Aug 09 08:30:15 PM PDT 24 |
| Finished | Aug 09 08:40:53 PM PDT 24 |
| Peak memory | 620352 kb |
| Host | smart-521c041d-25fe-441f-a0eb-78d25c501f5c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3544537538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.3544537538 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2605620490 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3347241762 ps |
| CPU time | 593.19 seconds |
| Started | Aug 09 08:32:01 PM PDT 24 |
| Finished | Aug 09 08:41:54 PM PDT 24 |
| Peak memory | 611916 kb |
| Host | smart-5fe12802-79d6-4bf0-88c5-d736d4a07ff0 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605620490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2605620490 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3939884029 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 4295205210 ps |
| CPU time | 696.02 seconds |
| Started | Aug 09 08:31:06 PM PDT 24 |
| Finished | Aug 09 08:42:42 PM PDT 24 |
| Peak memory | 612724 kb |
| Host | smart-57a69451-b9b4-42c2-b906-4d7d94525811 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939884029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3939884029 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.650634163 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 4691306650 ps |
| CPU time | 609.97 seconds |
| Started | Aug 09 08:30:52 PM PDT 24 |
| Finished | Aug 09 08:41:02 PM PDT 24 |
| Peak memory | 612068 kb |
| Host | smart-add9c519-93ab-4860-a117-1cd6869fc3a7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650634163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.650634163 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.426975427 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 5173586850 ps |
| CPU time | 665.15 seconds |
| Started | Aug 09 08:31:02 PM PDT 24 |
| Finished | Aug 09 08:42:07 PM PDT 24 |
| Peak memory | 612000 kb |
| Host | smart-5298b8b6-dbe3-4ca3-8914-ab62e6551059 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426975427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.426975427 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2051045250 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 5036697100 ps |
| CPU time | 565.12 seconds |
| Started | Aug 09 08:32:14 PM PDT 24 |
| Finished | Aug 09 08:41:39 PM PDT 24 |
| Peak memory | 612676 kb |
| Host | smart-f8938ac8-6643-417f-9a30-a2178218489a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051045250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2051045250 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1794854173 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 4686553384 ps |
| CPU time | 697.2 seconds |
| Started | Aug 09 08:32:12 PM PDT 24 |
| Finished | Aug 09 08:43:50 PM PDT 24 |
| Peak memory | 612040 kb |
| Host | smart-d554ab84-20a2-4be5-8169-8d7ca0d67b87 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794854173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1794854173 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.860689967 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 2426326168 ps |
| CPU time | 233.86 seconds |
| Started | Aug 09 08:34:04 PM PDT 24 |
| Finished | Aug 09 08:37:59 PM PDT 24 |
| Peak memory | 609128 kb |
| Host | smart-65c95958-be19-40a9-a61e-31ff47b3d132 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860689967 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_clkmgr_jitter.860689967 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3630541866 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 3248700344 ps |
| CPU time | 365.13 seconds |
| Started | Aug 09 08:32:20 PM PDT 24 |
| Finished | Aug 09 08:38:25 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-a4584e1e-3cc2-429c-a827-e0a81829e8ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630541866 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.3630541866 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1490399814 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 2636753982 ps |
| CPU time | 266.58 seconds |
| Started | Aug 09 08:34:18 PM PDT 24 |
| Finished | Aug 09 08:38:45 PM PDT 24 |
| Peak memory | 609424 kb |
| Host | smart-4a9ab779-9bcd-4f7b-84dc-3fda361673fd |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490399814 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1490399814 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1283791303 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 4200803960 ps |
| CPU time | 461.93 seconds |
| Started | Aug 09 08:32:44 PM PDT 24 |
| Finished | Aug 09 08:40:26 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-edf57f8b-d5e0-409a-9f80-2a50d3e47f85 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283791303 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.1283791303 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.463137443 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5127740720 ps |
| CPU time | 588.9 seconds |
| Started | Aug 09 08:31:58 PM PDT 24 |
| Finished | Aug 09 08:41:47 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-49d0bc63-5002-49d8-9123-dc1c09718362 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463137443 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.463137443 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1954701154 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 4886200600 ps |
| CPU time | 573.28 seconds |
| Started | Aug 09 08:30:20 PM PDT 24 |
| Finished | Aug 09 08:39:53 PM PDT 24 |
| Peak memory | 609136 kb |
| Host | smart-71610fc2-bd39-4b50-af07-09c75a7d222d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954701154 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.1954701154 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3479433300 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 4901633982 ps |
| CPU time | 625.8 seconds |
| Started | Aug 09 08:30:55 PM PDT 24 |
| Finished | Aug 09 08:41:21 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-720218d5-be31-4ca2-9270-844d9ce024d7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479433300 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.3479433300 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1330259722 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 9621456880 ps |
| CPU time | 1249.89 seconds |
| Started | Aug 09 08:31:15 PM PDT 24 |
| Finished | Aug 09 08:52:06 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-a58a1d36-b6aa-4286-8fd2-2344a6ddefb9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330259722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.1330259722 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3975331646 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3425061060 ps |
| CPU time | 407.96 seconds |
| Started | Aug 09 08:31:16 PM PDT 24 |
| Finished | Aug 09 08:38:04 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-14b60163-e0e2-4194-8c58-c1f3669babf4 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975331646 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.3975331646 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2980392879 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 4038430400 ps |
| CPU time | 588.34 seconds |
| Started | Aug 09 08:32:14 PM PDT 24 |
| Finished | Aug 09 08:42:02 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-9dc5ba9a-c78f-4656-8d8d-bcbe7d97f6c5 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980392879 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2980392879 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.987192350 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2846106480 ps |
| CPU time | 256.27 seconds |
| Started | Aug 09 08:34:26 PM PDT 24 |
| Finished | Aug 09 08:38:42 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-ffc7a3ef-cb7d-4ee6-b9e9-eb1b20537cc8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987192350 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_clkmgr_smoketest.987192350 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.481132287 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 12550113458 ps |
| CPU time | 3842.67 seconds |
| Started | Aug 09 08:28:44 PM PDT 24 |
| Finished | Aug 09 09:32:47 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-00afeddf-a2ae-49c2-900d-818e8bb9e082 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481132287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.481132287 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3970062735 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 22497091919 ps |
| CPU time | 3806.72 seconds |
| Started | Aug 09 08:34:42 PM PDT 24 |
| Finished | Aug 09 09:38:09 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-c44cc04e-f867-421c-a14b-5dbbeebea676 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3970062735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.3970062735 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.158807050 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4282918110 ps |
| CPU time | 373.26 seconds |
| Started | Aug 09 08:28:06 PM PDT 24 |
| Finished | Aug 09 08:34:20 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-4e4daf70-0b44-4ce8-9215-6f8f64b5855a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15880 7050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.158807050 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.3215958229 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2885439452 ps |
| CPU time | 241.24 seconds |
| Started | Aug 09 08:28:38 PM PDT 24 |
| Finished | Aug 09 08:32:39 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-ab355f1e-643b-4b9b-9aab-d1b8c2e95563 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215958229 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.3215958229 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.476401075 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 7560290002 ps |
| CPU time | 728.99 seconds |
| Started | Aug 09 08:30:11 PM PDT 24 |
| Finished | Aug 09 08:42:21 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-f1a7171a-8e23-4e75-8d0c-f16ddb373d2b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476401075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrn g_lc_hw_debug_en_test.476401075 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.2246515504 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 3137144432 ps |
| CPU time | 220.4 seconds |
| Started | Aug 09 08:36:43 PM PDT 24 |
| Finished | Aug 09 08:40:24 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-e75a1575-16c8-4392-8af6-389c46ec10db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246515504 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.2246515504 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2134560344 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 6222974960 ps |
| CPU time | 954.86 seconds |
| Started | Aug 09 08:28:33 PM PDT 24 |
| Finished | Aug 09 08:44:28 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-63ad1054-e95e-402c-bea5-9f61e24efabb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2134560344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.2134560344 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.1166919146 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 4790676648 ps |
| CPU time | 1154.44 seconds |
| Started | Aug 09 08:30:39 PM PDT 24 |
| Finished | Aug 09 08:49:54 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-78d31bca-cac6-4572-b4b0-14ec5769ee17 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166919146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.1166919146 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.1650344699 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3530307136 ps |
| CPU time | 629.82 seconds |
| Started | Aug 09 08:28:14 PM PDT 24 |
| Finished | Aug 09 08:38:44 PM PDT 24 |
| Peak memory | 609592 kb |
| Host | smart-2a75c8d5-198d-40a9-9ac9-a4544a5d963a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650344699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.1650344699 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.942392930 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 7479816920 ps |
| CPU time | 1152.62 seconds |
| Started | Aug 09 08:27:49 PM PDT 24 |
| Finished | Aug 09 08:47:02 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-d7b6ef1a-bd9c-4614-8b4a-45761b5b2672 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=942392930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.942392930 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2160204966 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 7405964017 ps |
| CPU time | 1236.04 seconds |
| Started | Aug 09 08:30:25 PM PDT 24 |
| Finished | Aug 09 08:51:01 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-76f34b0b-a059-46ee-9b8b-7099fbb71289 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160204966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.2160204966 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.3137269784 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 3430496100 ps |
| CPU time | 599.08 seconds |
| Started | Aug 09 08:27:44 PM PDT 24 |
| Finished | Aug 09 08:37:44 PM PDT 24 |
| Peak memory | 615336 kb |
| Host | smart-cfb52a59-b438-457c-a678-0cc3889462df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137269784 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3137269784 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.2102835170 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 10224086436 ps |
| CPU time | 2356.12 seconds |
| Started | Aug 09 08:29:46 PM PDT 24 |
| Finished | Aug 09 09:09:03 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-497071f4-5191-4dcc-906d-771327441547 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102835170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.2102835170 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1640312805 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 2778637464 ps |
| CPU time | 247.97 seconds |
| Started | Aug 09 08:30:57 PM PDT 24 |
| Finished | Aug 09 08:35:05 PM PDT 24 |
| Peak memory | 609460 kb |
| Host | smart-bda127db-9c2e-408b-b061-7c3a4ad92227 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16 40312805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.1640312805 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2406472624 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2707165808 ps |
| CPU time | 206.86 seconds |
| Started | Aug 09 08:28:41 PM PDT 24 |
| Finished | Aug 09 08:32:08 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-14b125c0-b834-453d-8ab9-220f417f59f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406472624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2406472624 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3157343344 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 3656797720 ps |
| CPU time | 721.03 seconds |
| Started | Aug 09 08:35:40 PM PDT 24 |
| Finished | Aug 09 08:47:42 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-70e9d668-3b4d-4e8f-b0be-4e37d1dc6c14 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3157343344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.3157343344 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.546609077 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3479633150 ps |
| CPU time | 294.78 seconds |
| Started | Aug 09 08:27:34 PM PDT 24 |
| Finished | Aug 09 08:32:29 PM PDT 24 |
| Peak memory | 608232 kb |
| Host | smart-33928c42-386a-4101-be42-fb4542eb3d18 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546609077 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.546609077 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.3477361339 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 2607866408 ps |
| CPU time | 220.34 seconds |
| Started | Aug 09 08:26:15 PM PDT 24 |
| Finished | Aug 09 08:29:56 PM PDT 24 |
| Peak memory | 609468 kb |
| Host | smart-3aa51bba-e24b-4e38-b473-f893f81ffd4c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477361339 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.3477361339 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.270864088 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 3342979080 ps |
| CPU time | 211.12 seconds |
| Started | Aug 09 08:24:31 PM PDT 24 |
| Finished | Aug 09 08:28:03 PM PDT 24 |
| Peak memory | 609512 kb |
| Host | smart-fd435956-8bf3-4d9d-b6f5-5524f7e8349b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270864088 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_example_manufacturer.270864088 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.3741799374 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3057735464 ps |
| CPU time | 127.13 seconds |
| Started | Aug 09 08:23:32 PM PDT 24 |
| Finished | Aug 09 08:25:39 PM PDT 24 |
| Peak memory | 608920 kb |
| Host | smart-19d16dad-80e3-4c45-a52a-57e3237712d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741799374 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.3741799374 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.627037124 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 59156112424 ps |
| CPU time | 10201.4 seconds |
| Started | Aug 09 08:27:43 PM PDT 24 |
| Finished | Aug 09 11:17:48 PM PDT 24 |
| Peak memory | 624812 kb |
| Host | smart-1f779e68-6204-41ee-a2db-eb4360e6e847 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=627037124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.627037124 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.2621325118 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 4587384550 ps |
| CPU time | 634.26 seconds |
| Started | Aug 09 08:34:11 PM PDT 24 |
| Finished | Aug 09 08:44:45 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-8b0f3f86-0ccd-45d4-8ea5-1dac70ba66c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2621325118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.2621325118 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2430735491 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 5900413472 ps |
| CPU time | 1043.26 seconds |
| Started | Aug 09 08:27:45 PM PDT 24 |
| Finished | Aug 09 08:45:08 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-afd2011d-0945-40ea-a500-f1988d769bcf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430735491 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.2430735491 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1599880067 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 6680275512 ps |
| CPU time | 1207.65 seconds |
| Started | Aug 09 08:25:42 PM PDT 24 |
| Finished | Aug 09 08:45:50 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-36d4ee2d-03c7-4d23-b550-a537498ab3d0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599880067 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1599880067 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2691695230 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 7187702736 ps |
| CPU time | 1127.23 seconds |
| Started | Aug 09 08:34:06 PM PDT 24 |
| Finished | Aug 09 08:52:54 PM PDT 24 |
| Peak memory | 608844 kb |
| Host | smart-dfb9d73e-97b4-4628-81e5-da92f7c32001 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691695230 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2691695230 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.899463090 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 5592777422 ps |
| CPU time | 934.01 seconds |
| Started | Aug 09 08:27:53 PM PDT 24 |
| Finished | Aug 09 08:43:27 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-33034502-2818-46ae-a376-363fcb537c6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899463090 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.899463090 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2117567462 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3004688478 ps |
| CPU time | 293.41 seconds |
| Started | Aug 09 08:27:53 PM PDT 24 |
| Finished | Aug 09 08:32:47 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-f9afaa54-d5d8-4cba-b2d9-7b8a930377b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117567462 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.2117567462 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.777888757 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 5364145480 ps |
| CPU time | 1138.85 seconds |
| Started | Aug 09 08:34:34 PM PDT 24 |
| Finished | Aug 09 08:53:33 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-b36f6249-481a-4fd7-92e2-cdfb25e74998 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777888757 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.777888757 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3065741723 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4058092140 ps |
| CPU time | 738.67 seconds |
| Started | Aug 09 08:30:25 PM PDT 24 |
| Finished | Aug 09 08:42:44 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-c91de6ef-5e9b-4ac7-8180-04bd32cedfcf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065741723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.3065741723 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1899702753 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 4610514894 ps |
| CPU time | 642.25 seconds |
| Started | Aug 09 08:28:49 PM PDT 24 |
| Finished | Aug 09 08:39:32 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-33ae3b42-676c-4009-a3a5-263983e8a69a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1899702753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.1899702753 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1217717416 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 5745289081 ps |
| CPU time | 904.87 seconds |
| Started | Aug 09 08:34:47 PM PDT 24 |
| Finished | Aug 09 08:49:53 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-6f14bc55-2d8d-43a8-9302-0adbe87e8f6e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1217717416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1217717416 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1971299032 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 3094832364 ps |
| CPU time | 391.25 seconds |
| Started | Aug 09 08:34:37 PM PDT 24 |
| Finished | Aug 09 08:41:09 PM PDT 24 |
| Peak memory | 608380 kb |
| Host | smart-e872e37d-98a4-419e-8787-ebeedc5960d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971299 032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.1971299032 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.1275436014 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 20602372650 ps |
| CPU time | 1767.78 seconds |
| Started | Aug 09 08:26:29 PM PDT 24 |
| Finished | Aug 09 08:55:58 PM PDT 24 |
| Peak memory | 614228 kb |
| Host | smart-4148f51f-6ad1-4329-a7ed-8b2c012e83d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275436014 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1275436014 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2488944395 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 24978827286 ps |
| CPU time | 2098.93 seconds |
| Started | Aug 09 08:32:46 PM PDT 24 |
| Finished | Aug 09 09:07:45 PM PDT 24 |
| Peak memory | 613924 kb |
| Host | smart-80144886-c3b5-4a0f-972e-b575a97ef2ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2488944395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.2488944395 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1254823655 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2950026188 ps |
| CPU time | 227.46 seconds |
| Started | Aug 09 08:38:26 PM PDT 24 |
| Finished | Aug 09 08:42:13 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-121ecec1-6fea-49b6-98eb-e4e7598b3383 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1254823655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.1254823655 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.2098704510 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4671411156 ps |
| CPU time | 588.45 seconds |
| Started | Aug 09 08:25:59 PM PDT 24 |
| Finished | Aug 09 08:35:48 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-ad6a23ac-deb7-4a54-ad96-0c49007ea3e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098704510 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.2098704510 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.1196949901 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 2948939359 ps |
| CPU time | 252.92 seconds |
| Started | Aug 09 08:34:37 PM PDT 24 |
| Finished | Aug 09 08:38:50 PM PDT 24 |
| Peak memory | 609608 kb |
| Host | smart-275d5a2c-c154-44ec-88c7-452f0134c86b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196949901 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.1196949901 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.77856835 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2799304016 ps |
| CPU time | 241.54 seconds |
| Started | Aug 09 08:31:32 PM PDT 24 |
| Finished | Aug 09 08:35:35 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-a12874cc-df28-4cb6-ad75-75eccabb66e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77856835 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_hmac_enc.77856835 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.108257107 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 3060791092 ps |
| CPU time | 260.1 seconds |
| Started | Aug 09 08:30:56 PM PDT 24 |
| Finished | Aug 09 08:35:17 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-0ddfd973-77e2-4ede-8244-cdebab553fc0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108257107 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_hmac_enc_idle.108257107 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.988509810 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 2672219899 ps |
| CPU time | 290.21 seconds |
| Started | Aug 09 08:31:53 PM PDT 24 |
| Finished | Aug 09 08:36:44 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-5576f412-3852-40ed-8a28-14f927304674 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988509810 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.988509810 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3617311222 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 2824000181 ps |
| CPU time | 240.82 seconds |
| Started | Aug 09 08:35:18 PM PDT 24 |
| Finished | Aug 09 08:39:19 PM PDT 24 |
| Peak memory | 608308 kb |
| Host | smart-8f47c745-8fcb-49c5-8fe1-08bb5bf405df |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617311222 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.3617311222 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.778428998 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 7264186512 ps |
| CPU time | 1749.29 seconds |
| Started | Aug 09 08:30:15 PM PDT 24 |
| Finished | Aug 09 08:59:25 PM PDT 24 |
| Peak memory | 608680 kb |
| Host | smart-6a8f826e-c693-4cdc-bf95-713989b53e16 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778428998 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_hmac_multistream.778428998 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.185466051 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 2832646432 ps |
| CPU time | 452.35 seconds |
| Started | Aug 09 08:30:14 PM PDT 24 |
| Finished | Aug 09 08:37:47 PM PDT 24 |
| Peak memory | 609128 kb |
| Host | smart-87d8c269-01a9-496d-8b06-b3ee159dd5f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185466051 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.185466051 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.4264101087 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 3224822248 ps |
| CPU time | 406.34 seconds |
| Started | Aug 09 08:37:53 PM PDT 24 |
| Finished | Aug 09 08:44:39 PM PDT 24 |
| Peak memory | 609548 kb |
| Host | smart-b6b4c2fb-9b28-4e98-be20-1e489d5d8260 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264101087 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.4264101087 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2122691615 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 3826434608 ps |
| CPU time | 446.67 seconds |
| Started | Aug 09 08:24:17 PM PDT 24 |
| Finished | Aug 09 08:31:44 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-d7ecba5f-0b00-4b8d-8702-28cbaefaa71a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122691615 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.2122691615 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1583638712 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4416852252 ps |
| CPU time | 835.69 seconds |
| Started | Aug 09 08:26:10 PM PDT 24 |
| Finished | Aug 09 08:40:06 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-bea1d747-d349-4ca1-a1fa-7afd77acaa40 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583638712 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.1583638712 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3556256843 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 4705388824 ps |
| CPU time | 807.41 seconds |
| Started | Aug 09 08:27:22 PM PDT 24 |
| Finished | Aug 09 08:40:51 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-4a01464f-75f4-490b-8d75-b6fa072eca7c |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556256843 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.3556256843 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1221604210 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 4876713304 ps |
| CPU time | 968.72 seconds |
| Started | Aug 09 08:26:39 PM PDT 24 |
| Finished | Aug 09 08:42:48 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-e2fef751-457a-451a-9553-b09d49278e96 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221604210 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1221604210 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2238267777 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 63367175230 ps |
| CPU time | 11420.4 seconds |
| Started | Aug 09 08:26:31 PM PDT 24 |
| Finished | Aug 09 11:36:53 PM PDT 24 |
| Peak memory | 624628 kb |
| Host | smart-d753f4e5-f60e-4cdc-be12-96e66b40c441 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2238267777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.2238267777 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3705524234 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 8204778880 ps |
| CPU time | 1527.53 seconds |
| Started | Aug 09 08:30:18 PM PDT 24 |
| Finished | Aug 09 08:55:45 PM PDT 24 |
| Peak memory | 617704 kb |
| Host | smart-bdab7de8-602f-4a7b-be32-ccb1b1a976d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705 524234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.3705524234 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1862739359 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 12191826919 ps |
| CPU time | 2370.66 seconds |
| Started | Aug 09 08:28:49 PM PDT 24 |
| Finished | Aug 09 09:08:20 PM PDT 24 |
| Peak memory | 616992 kb |
| Host | smart-427d078b-3f1d-4ae6-bec4-8d330af73e71 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1862739359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.1862739359 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.71621507 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 10163007268 ps |
| CPU time | 1943.64 seconds |
| Started | Aug 09 08:30:20 PM PDT 24 |
| Finished | Aug 09 09:02:44 PM PDT 24 |
| Peak memory | 617684 kb |
| Host | smart-b75fedee-8320-4e32-960e-d9aacde38f69 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=71621507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.71621507 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.107989878 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 7267639336 ps |
| CPU time | 1451.59 seconds |
| Started | Aug 09 08:28:29 PM PDT 24 |
| Finished | Aug 09 08:52:41 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-aca85628-86a8-4b4d-bb46-82306bc2f680 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107989 878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.107989878 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3145450912 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 13380300620 ps |
| CPU time | 2428.63 seconds |
| Started | Aug 09 08:31:03 PM PDT 24 |
| Finished | Aug 09 09:11:32 PM PDT 24 |
| Peak memory | 611040 kb |
| Host | smart-5d943f9e-9e04-47ed-8df3-98fb99c6d8b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31454 50912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.3145450912 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.4048384624 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 13803527384 ps |
| CPU time | 3569.97 seconds |
| Started | Aug 09 08:32:33 PM PDT 24 |
| Finished | Aug 09 09:32:04 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-6c0a992e-ff1f-4ab3-ba99-df94618c1b8b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40483 84624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.4048384624 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.2802477242 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2922145480 ps |
| CPU time | 233.43 seconds |
| Started | Aug 09 08:30:12 PM PDT 24 |
| Finished | Aug 09 08:34:06 PM PDT 24 |
| Peak memory | 608196 kb |
| Host | smart-862a8a16-ea9b-4b4b-92f9-20c4a6c7a1fb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802477242 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.2802477242 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.131143725 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 2653285740 ps |
| CPU time | 262.85 seconds |
| Started | Aug 09 08:29:19 PM PDT 24 |
| Finished | Aug 09 08:33:42 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-2ad9aeaa-57bc-40fc-94e8-0e61db3efce4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131143725 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_kmac_entropy.131143725 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.3460986545 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 2674359690 ps |
| CPU time | 221.5 seconds |
| Started | Aug 09 08:30:45 PM PDT 24 |
| Finished | Aug 09 08:34:27 PM PDT 24 |
| Peak memory | 609460 kb |
| Host | smart-d8774cb4-ce13-44a5-981a-d6c6ea0c2dd5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460986545 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.3460986545 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1427443106 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 3124099860 ps |
| CPU time | 264.49 seconds |
| Started | Aug 09 08:30:02 PM PDT 24 |
| Finished | Aug 09 08:34:27 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-ab805559-ea65-4969-b76a-f3369b8c89db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427443106 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.1427443106 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.228996231 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2521994160 ps |
| CPU time | 336.09 seconds |
| Started | Aug 09 08:28:47 PM PDT 24 |
| Finished | Aug 09 08:34:23 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-e02ebfb0-5db8-4ca2-8cae-d76c4deb3a17 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228996231 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_kmac_mode_kmac.228996231 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2711040318 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 2841884305 ps |
| CPU time | 261.34 seconds |
| Started | Aug 09 08:30:22 PM PDT 24 |
| Finished | Aug 09 08:34:43 PM PDT 24 |
| Peak memory | 609512 kb |
| Host | smart-ea1b727c-fb06-4676-a37a-8d26795bcf5e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711040318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.2711040318 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.863492083 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 3072334345 ps |
| CPU time | 330.27 seconds |
| Started | Aug 09 08:35:01 PM PDT 24 |
| Finished | Aug 09 08:40:31 PM PDT 24 |
| Peak memory | 609556 kb |
| Host | smart-65f71082-d38d-48a6-8ad4-b0333729889e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86349208 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.863492083 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.3065297798 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 2553329054 ps |
| CPU time | 322.03 seconds |
| Started | Aug 09 08:35:32 PM PDT 24 |
| Finished | Aug 09 08:40:54 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-76623567-ba1a-4a36-bb0c-c2f7f0a22ca8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065297798 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.3065297798 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3080692496 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 2241439380 ps |
| CPU time | 221.96 seconds |
| Started | Aug 09 08:25:29 PM PDT 24 |
| Finished | Aug 09 08:29:11 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-fa865579-0067-4a76-bf62-ee1412811eff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080692496 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.3080692496 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1546031090 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 5013199456 ps |
| CPU time | 423.05 seconds |
| Started | Aug 09 08:32:27 PM PDT 24 |
| Finished | Aug 09 08:39:30 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-b0644b79-a236-418c-8568-709f6ebbef4f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1546031090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.1546031090 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1438066670 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 10130509569 ps |
| CPU time | 1321.24 seconds |
| Started | Aug 09 08:27:18 PM PDT 24 |
| Finished | Aug 09 08:49:20 PM PDT 24 |
| Peak memory | 620996 kb |
| Host | smart-f96079ad-fa9a-4978-a527-a786b0bd1f59 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438066670 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.1438066670 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.536973892 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2909779598 ps |
| CPU time | 106.42 seconds |
| Started | Aug 09 08:24:01 PM PDT 24 |
| Finished | Aug 09 08:25:47 PM PDT 24 |
| Peak memory | 617804 kb |
| Host | smart-958d7e86-2b76-42a8-93fc-1c8daa5128ab |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=536973892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.536973892 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4148360007 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 2618123850 ps |
| CPU time | 121.72 seconds |
| Started | Aug 09 08:27:46 PM PDT 24 |
| Finished | Aug 09 08:29:48 PM PDT 24 |
| Peak memory | 616960 kb |
| Host | smart-9b720cfa-2b8b-4ce6-9a4f-526b75182645 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148360007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4148360007 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.677103575 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 48243026674 ps |
| CPU time | 5506.42 seconds |
| Started | Aug 09 08:26:13 PM PDT 24 |
| Finished | Aug 09 09:58:00 PM PDT 24 |
| Peak memory | 620440 kb |
| Host | smart-2591f01f-a8e2-4a19-a9a1-120f182eb2a7 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677103575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_prod.677103575 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1544351371 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 8406585155 ps |
| CPU time | 935.64 seconds |
| Started | Aug 09 08:26:39 PM PDT 24 |
| Finished | Aug 09 08:42:15 PM PDT 24 |
| Peak memory | 619908 kb |
| Host | smart-2cf0e222-0d2e-438b-991f-151dc0a26afe |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544351371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1544351371 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1065971946 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 47829925312 ps |
| CPU time | 4996.96 seconds |
| Started | Aug 09 08:26:21 PM PDT 24 |
| Finished | Aug 09 09:49:39 PM PDT 24 |
| Peak memory | 620496 kb |
| Host | smart-81d00a20-1186-4d0c-98c9-d5eab26b3f54 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065971946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1065971946 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.868894117 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 35942286152 ps |
| CPU time | 2803.34 seconds |
| Started | Aug 09 08:30:15 PM PDT 24 |
| Finished | Aug 09 09:16:59 PM PDT 24 |
| Peak memory | 620388 kb |
| Host | smart-37ffb451-8fc2-4f03-91f3-bb5016c5562d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=868894117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunl ocks.868894117 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4120297369 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 17001429090 ps |
| CPU time | 3301.66 seconds |
| Started | Aug 09 08:28:54 PM PDT 24 |
| Finished | Aug 09 09:23:57 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-f56e2aea-2475-49fc-9079-f3ab72bbf6d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=4120297369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.4120297369 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.236745439 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 19551778003 ps |
| CPU time | 3521.9 seconds |
| Started | Aug 09 08:28:47 PM PDT 24 |
| Finished | Aug 09 09:27:30 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-54026374-3b26-4dbc-af04-127f7639be73 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=236745439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.236745439 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.765484853 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 24911110873 ps |
| CPU time | 3768.93 seconds |
| Started | Aug 09 08:35:18 PM PDT 24 |
| Finished | Aug 09 09:38:08 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-f6741f21-1984-4379-826c-e29c24cfbf7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765484853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.765484853 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.478900422 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 3950422300 ps |
| CPU time | 398.55 seconds |
| Started | Aug 09 08:26:44 PM PDT 24 |
| Finished | Aug 09 08:33:22 PM PDT 24 |
| Peak memory | 609604 kb |
| Host | smart-cb0e8d82-0f66-4c4e-b4e1-8ece83e9ce37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478900422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.478900422 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.4077754102 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 5910221540 ps |
| CPU time | 1131.56 seconds |
| Started | Aug 09 08:31:08 PM PDT 24 |
| Finished | Aug 09 08:50:00 PM PDT 24 |
| Peak memory | 609104 kb |
| Host | smart-c3914148-7e15-4015-b2ed-674c5c931407 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4077754102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.4077754102 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.3308952484 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 10736236680 ps |
| CPU time | 2102.34 seconds |
| Started | Aug 09 08:34:43 PM PDT 24 |
| Finished | Aug 09 09:09:45 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-9ea60a4c-ff48-4e52-9115-4d975080407d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308952484 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.3308952484 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2544963684 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 3312635223 ps |
| CPU time | 251.7 seconds |
| Started | Aug 09 08:27:14 PM PDT 24 |
| Finished | Aug 09 08:31:26 PM PDT 24 |
| Peak memory | 608948 kb |
| Host | smart-2e6b4af8-0f7c-40ed-9978-166de158c9d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544963684 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.2544963684 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3007374482 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 9734775520 ps |
| CPU time | 1268.87 seconds |
| Started | Aug 09 08:23:44 PM PDT 24 |
| Finished | Aug 09 08:44:54 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-d22c0501-53dd-499d-9e34-0f028a96b126 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3007374482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3007374482 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3116433122 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 8437504480 ps |
| CPU time | 1191.3 seconds |
| Started | Aug 09 08:24:42 PM PDT 24 |
| Finished | Aug 09 08:44:34 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-86a6ad63-853c-46af-97f9-b2ccda5ed234 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3116433122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.3116433122 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1586239836 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 9220682312 ps |
| CPU time | 1467.2 seconds |
| Started | Aug 09 08:27:16 PM PDT 24 |
| Finished | Aug 09 08:51:43 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-201a19fd-bde0-4561-b533-8b0dc3bef1eb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1586239836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.1586239836 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1468773139 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 4336551964 ps |
| CPU time | 663.69 seconds |
| Started | Aug 09 08:29:09 PM PDT 24 |
| Finished | Aug 09 08:40:13 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-c11ddddd-27ed-4a96-bed3-3bf2d4af21ac |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1468773139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1468773139 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1428484011 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 2530313948 ps |
| CPU time | 262.41 seconds |
| Started | Aug 09 08:36:10 PM PDT 24 |
| Finished | Aug 09 08:40:34 PM PDT 24 |
| Peak memory | 609100 kb |
| Host | smart-05edac91-6c98-462f-8094-f302ce7753fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428484011 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.1428484011 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.115578629 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 2766663296 ps |
| CPU time | 245.49 seconds |
| Started | Aug 09 08:25:41 PM PDT 24 |
| Finished | Aug 09 08:29:47 PM PDT 24 |
| Peak memory | 612164 kb |
| Host | smart-f697d298-6815-46f9-9336-7f6bfe436e6d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115578629 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.115578629 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.2958098542 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2989668714 ps |
| CPU time | 178.24 seconds |
| Started | Aug 09 08:30:30 PM PDT 24 |
| Finished | Aug 09 08:33:28 PM PDT 24 |
| Peak memory | 609448 kb |
| Host | smart-115e7103-886d-4da0-a6b1-a3ad2a714179 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958098542 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.2958098542 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.3314648731 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 4629877896 ps |
| CPU time | 618.93 seconds |
| Started | Aug 09 08:33:55 PM PDT 24 |
| Finished | Aug 09 08:44:14 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-cf49d6e4-4c14-4d63-b3dc-c28a97900a78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314648731 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.3314648731 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.3060622069 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 9822196456 ps |
| CPU time | 676.72 seconds |
| Started | Aug 09 08:34:08 PM PDT 24 |
| Finished | Aug 09 08:45:26 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-f321a48e-bb56-4499-a171-7c7b0fea5112 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060622069 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.3060622069 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.4191200240 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 8391431368 ps |
| CPU time | 1425.56 seconds |
| Started | Aug 09 08:24:37 PM PDT 24 |
| Finished | Aug 09 08:48:23 PM PDT 24 |
| Peak memory | 611352 kb |
| Host | smart-99ba2890-f6c9-4842-8bac-277e65d79d77 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191 200240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.4191200240 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3134497937 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 26866625163 ps |
| CPU time | 2579.37 seconds |
| Started | Aug 09 08:29:57 PM PDT 24 |
| Finished | Aug 09 09:12:57 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-803c252e-cea8-4516-be11-3681215f9d7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313 4497937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.3134497937 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.500732141 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 15588449699 ps |
| CPU time | 1810.79 seconds |
| Started | Aug 09 08:29:14 PM PDT 24 |
| Finished | Aug 09 08:59:25 PM PDT 24 |
| Peak memory | 611424 kb |
| Host | smart-50038e01-c78d-4226-bebe-d39ab0f33382 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=500732141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.500732141 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2278058085 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 24854683832 ps |
| CPU time | 1648.73 seconds |
| Started | Aug 09 08:32:56 PM PDT 24 |
| Finished | Aug 09 09:00:26 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-7428af3c-ef61-4dca-a79a-c20388a57ca9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2278058085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2278058085 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1173272292 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 8206211612 ps |
| CPU time | 622.44 seconds |
| Started | Aug 09 08:24:29 PM PDT 24 |
| Finished | Aug 09 08:34:51 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-6f3b66d9-425f-4bb9-a8bf-c5428a1adcef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173272292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.1173272292 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.403430651 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 6946607028 ps |
| CPU time | 625.76 seconds |
| Started | Aug 09 08:26:16 PM PDT 24 |
| Finished | Aug 09 08:36:42 PM PDT 24 |
| Peak memory | 616356 kb |
| Host | smart-8dbac3f1-bc74-4484-aa07-72d270e1eaa6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=403430651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.403430651 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.212805450 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 8062082140 ps |
| CPU time | 555.99 seconds |
| Started | Aug 09 08:25:31 PM PDT 24 |
| Finished | Aug 09 08:34:47 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-0adedd07-0948-492c-8ac8-cf40692b6b18 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212805450 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.212805450 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.378708216 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4123396370 ps |
| CPU time | 396.83 seconds |
| Started | Aug 09 08:34:38 PM PDT 24 |
| Finished | Aug 09 08:41:15 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-ab9bac3d-5504-4792-9386-12dd4b598f8b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378708216 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.378708216 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.956494505 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 4532432470 ps |
| CPU time | 482.01 seconds |
| Started | Aug 09 08:27:42 PM PDT 24 |
| Finished | Aug 09 08:35:44 PM PDT 24 |
| Peak memory | 616384 kb |
| Host | smart-06157566-1b69-4b29-9b5f-56328bf616af |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=956494505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.956494505 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3008253392 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 11463500386 ps |
| CPU time | 1631.16 seconds |
| Started | Aug 09 08:28:47 PM PDT 24 |
| Finished | Aug 09 08:55:59 PM PDT 24 |
| Peak memory | 611116 kb |
| Host | smart-a79fa697-0cac-4a0f-86be-a813c092406d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008253392 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3008253392 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.755025366 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 7421378140 ps |
| CPU time | 397.46 seconds |
| Started | Aug 09 08:33:19 PM PDT 24 |
| Finished | Aug 09 08:39:56 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-2fd3210a-cd91-4615-bf72-eeb553ddb68f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755025366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.755025366 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2934830816 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 7095785665 ps |
| CPU time | 686.59 seconds |
| Started | Aug 09 08:27:25 PM PDT 24 |
| Finished | Aug 09 08:38:52 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-7550f7a0-e70c-43e9-ab05-aad8ae7cec62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934830816 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.2934830816 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3068016093 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 22525721827 ps |
| CPU time | 2345.99 seconds |
| Started | Aug 09 08:25:34 PM PDT 24 |
| Finished | Aug 09 09:04:40 PM PDT 24 |
| Peak memory | 611348 kb |
| Host | smart-03f30ac8-33d7-4058-b42e-5037b4c70d17 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3068016093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3068016093 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2289749571 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 21656433230 ps |
| CPU time | 1489.89 seconds |
| Started | Aug 09 08:33:00 PM PDT 24 |
| Finished | Aug 09 08:57:51 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-69c5992d-bfeb-4d8e-aa31-0a1180c2c39a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2289749571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2289749571 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2203650800 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 35587171271 ps |
| CPU time | 2819.6 seconds |
| Started | Aug 09 08:25:34 PM PDT 24 |
| Finished | Aug 09 09:12:34 PM PDT 24 |
| Peak memory | 611712 kb |
| Host | smart-5ef023af-9ec1-4967-9bb7-7f185a831c70 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203650800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2203650800 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.228936508 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 5384669926 ps |
| CPU time | 434.85 seconds |
| Started | Aug 09 08:31:33 PM PDT 24 |
| Finished | Aug 09 08:38:48 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-f05159f1-005b-4457-a4c7-45d765a9de6f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=228936508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.228936508 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2203604657 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2563718936 ps |
| CPU time | 246.6 seconds |
| Started | Aug 09 08:28:57 PM PDT 24 |
| Finished | Aug 09 08:33:04 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-e05956ce-cd68-4d91-a81d-f28de65a87d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203604657 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.2203604657 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.585737971 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 6245576750 ps |
| CPU time | 589.11 seconds |
| Started | Aug 09 08:27:17 PM PDT 24 |
| Finished | Aug 09 08:37:06 PM PDT 24 |
| Peak memory | 616672 kb |
| Host | smart-da53276a-3bf5-458d-864e-793fd61f5833 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=585737971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.585737971 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2372418498 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 5136424150 ps |
| CPU time | 510.48 seconds |
| Started | Aug 09 08:32:17 PM PDT 24 |
| Finished | Aug 09 08:40:48 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-a16cae82-66bd-4832-86da-c6ff7fad18ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23724184 98 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2372418498 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2879495666 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 7127994952 ps |
| CPU time | 614.58 seconds |
| Started | Aug 09 08:32:48 PM PDT 24 |
| Finished | Aug 09 08:43:03 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-41caa88c-c39d-4d7f-b170-1957f9f4e91f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2879495666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2879495666 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1355728839 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 5528005080 ps |
| CPU time | 403.22 seconds |
| Started | Aug 09 08:36:21 PM PDT 24 |
| Finished | Aug 09 08:43:05 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-ea6d9c87-c5be-4336-bba8-e5da0a4925fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355728839 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1355728839 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.618251723 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 5501186451 ps |
| CPU time | 1076.31 seconds |
| Started | Aug 09 08:26:20 PM PDT 24 |
| Finished | Aug 09 08:44:16 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-6e3c7382-b43b-40c1-b8b3-293d38207733 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618251723 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.618251723 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2936123359 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 4823477912 ps |
| CPU time | 470.4 seconds |
| Started | Aug 09 08:25:15 PM PDT 24 |
| Finished | Aug 09 08:33:06 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-f9ea218d-ca95-4efe-8542-73e34636abb9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936123359 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2936123359 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3429101806 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 5454371686 ps |
| CPU time | 578.96 seconds |
| Started | Aug 09 08:38:43 PM PDT 24 |
| Finished | Aug 09 08:48:22 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-9644231f-6b36-4954-9668-adbf74e07dcb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429101806 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.3429101806 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2134601482 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 4437249242 ps |
| CPU time | 562.83 seconds |
| Started | Aug 09 08:26:23 PM PDT 24 |
| Finished | Aug 09 08:35:46 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-3f81b5d3-7776-4702-8012-c5c6e3701de9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213 4601482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.2134601482 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2649048363 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 8847429030 ps |
| CPU time | 638.13 seconds |
| Started | Aug 09 08:29:21 PM PDT 24 |
| Finished | Aug 09 08:39:59 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-fef06b8a-d983-4c50-b574-81d24f4e58bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649048363 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.2649048363 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3648783113 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 10368407448 ps |
| CPU time | 1632.27 seconds |
| Started | Aug 09 08:31:25 PM PDT 24 |
| Finished | Aug 09 08:58:38 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-7b1052db-4654-41a2-aa96-dc08eba22117 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3648783113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3648783113 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2801897951 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 6591230528 ps |
| CPU time | 691.69 seconds |
| Started | Aug 09 08:30:19 PM PDT 24 |
| Finished | Aug 09 08:41:51 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-4804f68e-764e-458a-8ca5-fc6b3f11dcab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801897951 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.2801897951 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1910630657 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 4827596876 ps |
| CPU time | 622.32 seconds |
| Started | Aug 09 08:24:42 PM PDT 24 |
| Finished | Aug 09 08:35:04 PM PDT 24 |
| Peak memory | 641512 kb |
| Host | smart-0cb81e1d-61dd-44e4-a91d-0be54d22bdaf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1910630657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1910630657 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2792319767 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 2535766860 ps |
| CPU time | 188.39 seconds |
| Started | Aug 09 08:35:11 PM PDT 24 |
| Finished | Aug 09 08:38:19 PM PDT 24 |
| Peak memory | 609108 kb |
| Host | smart-b4ea2258-12ff-4fcf-9e39-cff686a8b36a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792319767 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.2792319767 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2720400055 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 5589474330 ps |
| CPU time | 440.5 seconds |
| Started | Aug 09 08:25:16 PM PDT 24 |
| Finished | Aug 09 08:32:37 PM PDT 24 |
| Peak memory | 608848 kb |
| Host | smart-2a9c7b80-e98b-4f51-9a3f-b6ca10bee15e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720400055 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.2720400055 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1871085649 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 2647504820 ps |
| CPU time | 270 seconds |
| Started | Aug 09 08:27:21 PM PDT 24 |
| Finished | Aug 09 08:31:51 PM PDT 24 |
| Peak memory | 609096 kb |
| Host | smart-3051b602-34de-496c-abf5-37e861d23fc1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871085649 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.1871085649 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.793625284 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3646553400 ps |
| CPU time | 394.96 seconds |
| Started | Aug 09 08:34:15 PM PDT 24 |
| Finished | Aug 09 08:40:50 PM PDT 24 |
| Peak memory | 609504 kb |
| Host | smart-1b2e2cda-b9a6-4923-ac55-871ae096e17e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=793625284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.793625284 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1117323711 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2613873240 ps |
| CPU time | 257.54 seconds |
| Started | Aug 09 08:33:15 PM PDT 24 |
| Finished | Aug 09 08:37:33 PM PDT 24 |
| Peak memory | 608596 kb |
| Host | smart-2f5f3db4-a638-496d-9f08-43daf7ad859b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117323711 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1117323711 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1824219693 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 5558820684 ps |
| CPU time | 1003.5 seconds |
| Started | Aug 09 08:26:43 PM PDT 24 |
| Finished | Aug 09 08:43:27 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-8c99db32-a101-4081-b408-a151acb52bde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18242 19693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1824219693 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2371228175 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 5465770692 ps |
| CPU time | 981.73 seconds |
| Started | Aug 09 08:28:43 PM PDT 24 |
| Finished | Aug 09 08:45:05 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-8d00a28a-5aba-4be0-88b1-dd085b9d0df3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2371228175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.2371228175 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4053661844 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 4525699878 ps |
| CPU time | 731.48 seconds |
| Started | Aug 09 08:33:45 PM PDT 24 |
| Finished | Aug 09 08:45:56 PM PDT 24 |
| Peak memory | 624044 kb |
| Host | smart-3ffe0679-2934-4523-a1dd-08e8b47befa5 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053661844 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.4053661844 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.146672348 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 5740901248 ps |
| CPU time | 565.46 seconds |
| Started | Aug 09 08:32:58 PM PDT 24 |
| Finished | Aug 09 08:42:23 PM PDT 24 |
| Peak memory | 621384 kb |
| Host | smart-efb2d396-25c0-480d-9ede-fb4827b75ba6 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146672348 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.146672348 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2886373793 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 5258699028 ps |
| CPU time | 530.57 seconds |
| Started | Aug 09 08:32:37 PM PDT 24 |
| Finished | Aug 09 08:41:28 PM PDT 24 |
| Peak memory | 621476 kb |
| Host | smart-f537fb28-6772-4e8e-a0db-4572c6b8a7fa |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288637 3793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2886373793 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.517639490 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 2447036072 ps |
| CPU time | 309.02 seconds |
| Started | Aug 09 08:36:32 PM PDT 24 |
| Finished | Aug 09 08:41:41 PM PDT 24 |
| Peak memory | 608224 kb |
| Host | smart-3b5f8a91-dfed-427f-ab3c-43f85a5cda70 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517639490 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rv_plic_smoketest.517639490 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.557949853 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3006468232 ps |
| CPU time | 278.1 seconds |
| Started | Aug 09 08:26:51 PM PDT 24 |
| Finished | Aug 09 08:31:30 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-b590fcac-fab9-49e5-bc65-7874fe8edb9d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557949853 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_irq.557949853 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2887836434 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2762383704 ps |
| CPU time | 298.81 seconds |
| Started | Aug 09 08:38:44 PM PDT 24 |
| Finished | Aug 09 08:43:43 PM PDT 24 |
| Peak memory | 608232 kb |
| Host | smart-44ebe573-9d1e-442f-b7bc-b9bce1eba511 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887836434 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2887836434 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.504921333 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3045282083 ps |
| CPU time | 311.17 seconds |
| Started | Aug 09 08:31:15 PM PDT 24 |
| Finished | Aug 09 08:36:27 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-4980feb7-ae79-435f-804d-62abc1141707 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5049213 33 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.504921333 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3895283866 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3764947836 ps |
| CPU time | 267.67 seconds |
| Started | Aug 09 08:25:50 PM PDT 24 |
| Finished | Aug 09 08:30:18 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-80564ae1-d364-4ab5-89fd-67653bb93f03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895283866 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.3895283866 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1605554682 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 7965861250 ps |
| CPU time | 1244.92 seconds |
| Started | Aug 09 08:24:27 PM PDT 24 |
| Finished | Aug 09 08:45:13 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-a46ce12b-48d9-4a83-9d59-0d41a4068630 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605554682 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1605554682 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3541808768 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 7028201630 ps |
| CPU time | 849.38 seconds |
| Started | Aug 09 08:30:39 PM PDT 24 |
| Finished | Aug 09 08:44:49 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-7c66131b-b0db-44c6-bf7e-ec07335a1266 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541808768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.3541808768 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2157009545 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 8604158212 ps |
| CPU time | 724.42 seconds |
| Started | Aug 09 08:31:40 PM PDT 24 |
| Finished | Aug 09 08:43:45 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-84f78e9c-95bd-47ba-83b6-956a55d3753e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157009545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.2157009545 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1402531111 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8021608544 ps |
| CPU time | 992.47 seconds |
| Started | Aug 09 08:30:18 PM PDT 24 |
| Finished | Aug 09 08:46:51 PM PDT 24 |
| Peak memory | 624764 kb |
| Host | smart-616c693b-b7cb-4de7-9b74-381a2f735484 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402531111 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.1402531111 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3758639354 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 4325314893 ps |
| CPU time | 545.76 seconds |
| Started | Aug 09 08:24:31 PM PDT 24 |
| Finished | Aug 09 08:33:37 PM PDT 24 |
| Peak memory | 624544 kb |
| Host | smart-2dbf21f9-5138-4861-9f66-a09205252e19 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758639354 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.3758639354 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2367032554 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3781868896 ps |
| CPU time | 296.97 seconds |
| Started | Aug 09 08:27:46 PM PDT 24 |
| Finished | Aug 09 08:32:43 PM PDT 24 |
| Peak memory | 618904 kb |
| Host | smart-53222bb1-fe95-458d-99a0-98e16fc97465 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367032554 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.2367032554 |
| Directory | /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1960687768 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3668723533 ps |
| CPU time | 425.2 seconds |
| Started | Aug 09 08:28:49 PM PDT 24 |
| Finished | Aug 09 08:35:55 PM PDT 24 |
| Peak memory | 619312 kb |
| Host | smart-82d0a40d-3594-4610-9381-0d8a2dbb1653 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960687768 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1960687768 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2796057398 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2486953776 ps |
| CPU time | 274.57 seconds |
| Started | Aug 09 08:25:10 PM PDT 24 |
| Finished | Aug 09 08:29:45 PM PDT 24 |
| Peak memory | 608764 kb |
| Host | smart-3ccebec7-0d62-4976-8cab-ed153a441164 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796057398 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.2796057398 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3958679995 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5979773403 ps |
| CPU time | 510.06 seconds |
| Started | Aug 09 08:30:41 PM PDT 24 |
| Finished | Aug 09 08:39:11 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-6b8d5cfa-4eff-4023-b034-88263fb77778 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958679995 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3958679995 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2833007069 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5496170520 ps |
| CPU time | 722.49 seconds |
| Started | Aug 09 08:31:20 PM PDT 24 |
| Finished | Aug 09 08:43:23 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-a83a7adb-e7af-4544-b569-36ff71d9f496 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833007069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.2833007069 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3128400307 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 5742546190 ps |
| CPU time | 599.85 seconds |
| Started | Aug 09 08:29:46 PM PDT 24 |
| Finished | Aug 09 08:39:46 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-b06e7909-1a0a-4dc1-b018-14b75d44c268 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128400307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3128400307 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.43055765 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 5185041573 ps |
| CPU time | 648.77 seconds |
| Started | Aug 09 08:34:07 PM PDT 24 |
| Finished | Aug 09 08:44:58 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-4dba2b51-ece9-455c-aab7-f5a6bdb67a8e |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43055765 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.43055765 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.144080836 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 2491421644 ps |
| CPU time | 176.8 seconds |
| Started | Aug 09 08:36:54 PM PDT 24 |
| Finished | Aug 09 08:39:52 PM PDT 24 |
| Peak memory | 609100 kb |
| Host | smart-4862882f-c083-41aa-82bf-21dfe7cf4d2c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144080836 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sram_ctrl_smoketest.144080836 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.608314529 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 20715107924 ps |
| CPU time | 4368.83 seconds |
| Started | Aug 09 08:26:49 PM PDT 24 |
| Finished | Aug 09 09:39:39 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-a3ed322a-2a24-4e8e-9a70-9cda0b9cf2f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608314529 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.608314529 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1345218226 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 5077615779 ps |
| CPU time | 720.65 seconds |
| Started | Aug 09 08:28:11 PM PDT 24 |
| Finished | Aug 09 08:40:15 PM PDT 24 |
| Peak memory | 613528 kb |
| Host | smart-48e73d28-664a-4760-8574-5e2cc91798d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345218226 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1345218226 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.697298521 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3613782122 ps |
| CPU time | 288.21 seconds |
| Started | Aug 09 08:27:44 PM PDT 24 |
| Finished | Aug 09 08:32:33 PM PDT 24 |
| Peak memory | 612912 kb |
| Host | smart-74dc82db-d604-4a88-bd8f-ef49ee9f9d61 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697298521 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.697298521 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2148200796 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 24121096188 ps |
| CPU time | 1501.5 seconds |
| Started | Aug 09 08:25:49 PM PDT 24 |
| Finished | Aug 09 08:50:51 PM PDT 24 |
| Peak memory | 614644 kb |
| Host | smart-0433f681-ad5d-4af5-8537-5ac1e6e80cf2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21482007 96 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.2148200796 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1506047631 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4607636320 ps |
| CPU time | 539.15 seconds |
| Started | Aug 09 08:28:11 PM PDT 24 |
| Finished | Aug 09 08:37:11 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-9431d285-a927-402e-ab0a-6b41037c0418 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506047631 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1506047631 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2060705312 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 8558070770 ps |
| CPU time | 1776.46 seconds |
| Started | Aug 09 08:27:49 PM PDT 24 |
| Finished | Aug 09 08:57:28 PM PDT 24 |
| Peak memory | 623556 kb |
| Host | smart-17c709cf-e989-4752-872b-6eb78a3af4d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2060705312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.2060705312 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.2688294562 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 3007486696 ps |
| CPU time | 436.08 seconds |
| Started | Aug 09 08:38:53 PM PDT 24 |
| Finished | Aug 09 08:46:09 PM PDT 24 |
| Peak memory | 614824 kb |
| Host | smart-223188cc-6eb4-4be2-a975-6e17fd2a6373 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688294562 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.2688294562 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.794945835 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 4708203800 ps |
| CPU time | 725.23 seconds |
| Started | Aug 09 08:25:03 PM PDT 24 |
| Finished | Aug 09 08:37:08 PM PDT 24 |
| Peak memory | 623804 kb |
| Host | smart-72da8ac4-4a82-404d-b744-bed8c9bf9f28 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794945835 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.794945835 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1368527116 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 3707621191 ps |
| CPU time | 552.17 seconds |
| Started | Aug 09 08:26:02 PM PDT 24 |
| Finished | Aug 09 08:35:15 PM PDT 24 |
| Peak memory | 623448 kb |
| Host | smart-eca9e8a1-f326-4152-9e17-627fd00edcbe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368527116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.1368527116 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.643865444 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 8551494939 ps |
| CPU time | 1316.66 seconds |
| Started | Aug 09 08:24:45 PM PDT 24 |
| Finished | Aug 09 08:46:43 PM PDT 24 |
| Peak memory | 624532 kb |
| Host | smart-c358ba7b-0002-44f2-ad9a-faf5935d87a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643865444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.643865444 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.488923677 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 78720901050 ps |
| CPU time | 13180.6 seconds |
| Started | Aug 09 08:23:28 PM PDT 24 |
| Finished | Aug 10 12:03:11 AM PDT 24 |
| Peak memory | 635912 kb |
| Host | smart-9a275775-4fa5-4e94-8a06-3d54d2954712 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=488923677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.488923677 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1847364732 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 4078059160 ps |
| CPU time | 651.49 seconds |
| Started | Aug 09 08:24:44 PM PDT 24 |
| Finished | Aug 09 08:35:36 PM PDT 24 |
| Peak memory | 623636 kb |
| Host | smart-9dd73abd-c8e0-4aa2-a5c4-b4865c273781 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847364732 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.1847364732 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1492820236 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 4322178900 ps |
| CPU time | 587.41 seconds |
| Started | Aug 09 08:26:43 PM PDT 24 |
| Finished | Aug 09 08:36:31 PM PDT 24 |
| Peak memory | 623964 kb |
| Host | smart-c2e86f45-ec02-42c3-9f18-c8cd896d7afd |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492820236 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1492820236 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2485481615 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4336259456 ps |
| CPU time | 671.16 seconds |
| Started | Aug 09 08:24:35 PM PDT 24 |
| Finished | Aug 09 08:35:46 PM PDT 24 |
| Peak memory | 623692 kb |
| Host | smart-b6afd6a6-0c47-449d-ac9e-893786a73a07 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485481615 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.2485481615 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.1752590112 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4016843725 ps |
| CPU time | 290.41 seconds |
| Started | Aug 09 08:31:14 PM PDT 24 |
| Finished | Aug 09 08:36:05 PM PDT 24 |
| Peak memory | 624136 kb |
| Host | smart-44c8a4e0-c83c-441a-b271-3473d43ca1dc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1752590112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.1752590112 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.1658950822 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 2977437606 ps |
| CPU time | 184.06 seconds |
| Started | Aug 09 08:34:40 PM PDT 24 |
| Finished | Aug 09 08:37:44 PM PDT 24 |
| Peak memory | 623092 kb |
| Host | smart-0b4bf9a8-5616-415b-be4a-1b8f1fce4219 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658950822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.1658950822 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.108485088 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 3217991391 ps |
| CPU time | 150.15 seconds |
| Started | Aug 09 08:32:08 PM PDT 24 |
| Finished | Aug 09 08:34:38 PM PDT 24 |
| Peak memory | 620892 kb |
| Host | smart-b0f9b06b-9ab4-4821-8c3e-28cd56ce2f9b |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108485088 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.108485088 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.2452081068 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 8602104328 ps |
| CPU time | 844.88 seconds |
| Started | Aug 09 08:32:05 PM PDT 24 |
| Finished | Aug 09 08:46:10 PM PDT 24 |
| Peak memory | 624832 kb |
| Host | smart-9aa524c4-cbb9-4b29-a0d3-9860c2889b89 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452081068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.2452081068 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.1810940071 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 15369179695 ps |
| CPU time | 3160.57 seconds |
| Started | Aug 09 08:37:54 PM PDT 24 |
| Finished | Aug 09 09:30:35 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-2d3dc9a4-d829-4bed-b9ca-2a4537a7cf12 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810940071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.1810940071 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.3956261934 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 15916545551 ps |
| CPU time | 4091.6 seconds |
| Started | Aug 09 08:39:09 PM PDT 24 |
| Finished | Aug 09 09:47:21 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-9aedcba3-8ea5-4ab5-b0cc-ee4b02e7ae82 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956261934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.3956261934 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1122105813 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 15920510580 ps |
| CPU time | 4278.81 seconds |
| Started | Aug 09 08:40:04 PM PDT 24 |
| Finished | Aug 09 09:51:24 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-70cdce35-7c20-4afe-aec8-dd67a4678323 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122105813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.1122105813 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.343472508 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 14822063712 ps |
| CPU time | 3448.34 seconds |
| Started | Aug 09 08:37:33 PM PDT 24 |
| Finished | Aug 09 09:35:01 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-7768962d-6571-48f5-b33d-594709a19ef4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343472508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_rma.343472508 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3563753035 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 10899372734 ps |
| CPU time | 3002.02 seconds |
| Started | Aug 09 08:40:15 PM PDT 24 |
| Finished | Aug 09 09:30:17 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-5b1a9575-2924-4deb-8819-ce084aeca619 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563753035 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.3563753035 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1143983800 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 14743306224 ps |
| CPU time | 3366.68 seconds |
| Started | Aug 09 08:41:26 PM PDT 24 |
| Finished | Aug 09 09:37:35 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-cad08f5d-9ccc-4eb7-902d-36c18e6cf54f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143983800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1143983800 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1336703685 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 15076344380 ps |
| CPU time | 3227 seconds |
| Started | Aug 09 08:38:51 PM PDT 24 |
| Finished | Aug 09 09:32:38 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-0e83a864-6cf9-4a54-978b-e09e7d82fe4c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336703685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1336703685 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4238956066 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 15679198776 ps |
| CPU time | 3795.76 seconds |
| Started | Aug 09 08:41:12 PM PDT 24 |
| Finished | Aug 09 09:44:28 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-65bf32e7-b7de-4edd-a8da-4462605741ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238956066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.4238956066 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.2613888445 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 26775972888 ps |
| CPU time | 5921.37 seconds |
| Started | Aug 09 08:43:03 PM PDT 24 |
| Finished | Aug 09 10:21:45 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-41bd1125-2cd9-4c5e-9c54-eeb340c94830 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613888445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.2613888445 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1137813398 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 14497663060 ps |
| CPU time | 3685.79 seconds |
| Started | Aug 09 08:39:54 PM PDT 24 |
| Finished | Aug 09 09:41:20 PM PDT 24 |
| Peak memory | 611208 kb |
| Host | smart-bbae9a89-0476-49e2-9e0f-28fe878a1fbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137813398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.1137813398 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.3213399627 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 25573862490 ps |
| CPU time | 3708.73 seconds |
| Started | Aug 09 08:38:16 PM PDT 24 |
| Finished | Aug 09 09:40:06 PM PDT 24 |
| Peak memory | 611356 kb |
| Host | smart-58027096-86f4-4618-bd59-a9682f7d7d80 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213399627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.3213399627 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.2869316878 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 14592967352 ps |
| CPU time | 4215.69 seconds |
| Started | Aug 09 08:38:51 PM PDT 24 |
| Finished | Aug 09 09:49:07 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-27a9dbed-906d-471e-acfa-7ad0ffe3a6e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2869316878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2869316878 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.580046750 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 17708938600 ps |
| CPU time | 3794.02 seconds |
| Started | Aug 09 08:41:11 PM PDT 24 |
| Finished | Aug 09 09:44:26 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-f11f895b-1a57-42c1-8900-890e84094de7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580046750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.580046750 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.2221485391 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 5356225324 ps |
| CPU time | 472.35 seconds |
| Started | Aug 09 08:37:56 PM PDT 24 |
| Finished | Aug 09 08:45:48 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-f88fb9d6-6bbd-45f0-b996-739a3840bd03 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221485391 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.2221485391 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.1533966450 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 4339834345 ps |
| CPU time | 215.52 seconds |
| Started | Aug 09 08:37:05 PM PDT 24 |
| Finished | Aug 09 08:40:40 PM PDT 24 |
| Peak memory | 619924 kb |
| Host | smart-b15ae9da-efd6-42d5-9184-e7f9e61b3387 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1533966450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.1533966450 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.3081526888 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3014303955 ps |
| CPU time | 127.8 seconds |
| Started | Aug 09 08:37:25 PM PDT 24 |
| Finished | Aug 09 08:39:33 PM PDT 24 |
| Peak memory | 617408 kb |
| Host | smart-2cd19e6f-b3b9-49fe-a9ad-2e1897b2bff7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081526888 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.3081526888 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3268512871 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 5359135407 ps |
| CPU time | 443.23 seconds |
| Started | Aug 09 08:47:53 PM PDT 24 |
| Finished | Aug 09 08:55:17 PM PDT 24 |
| Peak memory | 621012 kb |
| Host | smart-0fb38c30-e3a6-464a-ac1f-aa5b7c2dcb69 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268512871 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.3268512871 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.154231493 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 7939689064 ps |
| CPU time | 1358.09 seconds |
| Started | Aug 09 08:47:40 PM PDT 24 |
| Finished | Aug 09 09:10:18 PM PDT 24 |
| Peak memory | 624444 kb |
| Host | smart-159f0c0a-b762-45e4-8271-4331d067bb56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=154231493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.154231493 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.2769614220 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 4283856992 ps |
| CPU time | 489.94 seconds |
| Started | Aug 09 08:48:14 PM PDT 24 |
| Finished | Aug 09 08:56:24 PM PDT 24 |
| Peak memory | 649948 kb |
| Host | smart-d1e14b61-9c6d-46b2-8e46-af59f9c76c85 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2769614220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.2769614220 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1617787817 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 7074621785 ps |
| CPU time | 389.75 seconds |
| Started | Aug 09 08:50:41 PM PDT 24 |
| Finished | Aug 09 08:57:11 PM PDT 24 |
| Peak memory | 623128 kb |
| Host | smart-56abc0dc-b37e-432e-a1ae-215db65c3ac4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617787817 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1617787817 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1197703268 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4598843322 ps |
| CPU time | 549.22 seconds |
| Started | Aug 09 08:48:08 PM PDT 24 |
| Finished | Aug 09 08:57:17 PM PDT 24 |
| Peak memory | 623272 kb |
| Host | smart-3ef217d6-4e2b-47b3-8d88-c8ce8436216e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1197703268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1197703268 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.4039267338 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 5528953817 ps |
| CPU time | 688.44 seconds |
| Started | Aug 09 08:48:33 PM PDT 24 |
| Finished | Aug 09 09:00:02 PM PDT 24 |
| Peak memory | 624592 kb |
| Host | smart-7101e7ac-3b20-48f8-a99f-4618fea37cc8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039267338 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.4039267338 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3586051758 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 3859986344 ps |
| CPU time | 556.11 seconds |
| Started | Aug 09 08:48:32 PM PDT 24 |
| Finished | Aug 09 08:57:49 PM PDT 24 |
| Peak memory | 624368 kb |
| Host | smart-733eaadf-0f3b-4009-a78f-7625306f16ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3586051758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3586051758 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2441153706 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3549034676 ps |
| CPU time | 433.28 seconds |
| Started | Aug 09 08:48:28 PM PDT 24 |
| Finished | Aug 09 08:55:41 PM PDT 24 |
| Peak memory | 648728 kb |
| Host | smart-39558731-4a0d-4131-843b-bd1afe0eb247 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441153706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2441153706 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.747225791 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 5328440718 ps |
| CPU time | 583.99 seconds |
| Started | Aug 09 08:48:30 PM PDT 24 |
| Finished | Aug 09 08:58:14 PM PDT 24 |
| Peak memory | 616760 kb |
| Host | smart-64e3aad3-10e6-47a8-9122-636374da1e1d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 747225791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.747225791 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2385766273 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 7538182923 ps |
| CPU time | 457.33 seconds |
| Started | Aug 09 08:50:38 PM PDT 24 |
| Finished | Aug 09 08:58:16 PM PDT 24 |
| Peak memory | 622304 kb |
| Host | smart-8b460a3f-c7b0-49de-9e45-310a69bd0e39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385766273 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.2385766273 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.581752434 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 12839690664 ps |
| CPU time | 1952 seconds |
| Started | Aug 09 08:49:10 PM PDT 24 |
| Finished | Aug 09 09:21:42 PM PDT 24 |
| Peak memory | 624408 kb |
| Host | smart-e748aeb7-ddd2-400c-85cc-3d04eba834b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=581752434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.581752434 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.4208472753 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 5111971380 ps |
| CPU time | 680.83 seconds |
| Started | Aug 09 08:49:40 PM PDT 24 |
| Finished | Aug 09 09:01:01 PM PDT 24 |
| Peak memory | 650240 kb |
| Host | smart-92aeed22-773b-4521-96aa-a0bf02298dfc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4208472753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.4208472753 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.379805089 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 10505730036 ps |
| CPU time | 1375.45 seconds |
| Started | Aug 09 08:50:55 PM PDT 24 |
| Finished | Aug 09 09:13:51 PM PDT 24 |
| Peak memory | 621028 kb |
| Host | smart-665ac897-e591-4682-8a74-9cbc782ab51d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379805089 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.379805089 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3238866361 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 8395322760 ps |
| CPU time | 1441.59 seconds |
| Started | Aug 09 08:50:51 PM PDT 24 |
| Finished | Aug 09 09:14:53 PM PDT 24 |
| Peak memory | 624472 kb |
| Host | smart-5293fdca-b070-49e9-b43f-d9702c3480fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3238866361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.3238866361 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1404246487 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8159488644 ps |
| CPU time | 1680.38 seconds |
| Started | Aug 09 08:48:35 PM PDT 24 |
| Finished | Aug 09 09:16:36 PM PDT 24 |
| Peak memory | 624452 kb |
| Host | smart-811c2eb7-2178-4d9d-9369-0bf0e15733a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1404246487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1404246487 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.4200411293 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 5472803152 ps |
| CPU time | 582.59 seconds |
| Started | Aug 09 08:49:40 PM PDT 24 |
| Finished | Aug 09 08:59:22 PM PDT 24 |
| Peak memory | 650056 kb |
| Host | smart-2294de56-53f8-476e-b77a-bc210cac9919 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4200411293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.4200411293 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1967244169 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3162846832 ps |
| CPU time | 474.27 seconds |
| Started | Aug 09 08:50:35 PM PDT 24 |
| Finished | Aug 09 08:58:29 PM PDT 24 |
| Peak memory | 624368 kb |
| Host | smart-e85c4182-4849-47cb-8374-eb202f26c74a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1967244169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.1967244169 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3655780747 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 3933535144 ps |
| CPU time | 255.37 seconds |
| Started | Aug 09 08:47:50 PM PDT 24 |
| Finished | Aug 09 08:52:05 PM PDT 24 |
| Peak memory | 648972 kb |
| Host | smart-5638452e-debf-453c-bc2f-8d052ad4ce16 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655780747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3655780747 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1942077174 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 3885664608 ps |
| CPU time | 663.46 seconds |
| Started | Aug 09 08:49:15 PM PDT 24 |
| Finished | Aug 09 09:00:19 PM PDT 24 |
| Peak memory | 622196 kb |
| Host | smart-f822df62-8ab4-405f-9056-8e6a3e4ac0ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1942077174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1942077174 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4066490178 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 7983544232 ps |
| CPU time | 1124.09 seconds |
| Started | Aug 09 08:52:31 PM PDT 24 |
| Finished | Aug 09 09:11:16 PM PDT 24 |
| Peak memory | 621860 kb |
| Host | smart-72a23d8b-529e-4564-8a1c-4402d6e14c42 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4066490178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.4066490178 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.2621263209 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 5978747092 ps |
| CPU time | 591.93 seconds |
| Started | Aug 09 08:48:29 PM PDT 24 |
| Finished | Aug 09 08:58:22 PM PDT 24 |
| Peak memory | 616796 kb |
| Host | smart-0a877ef8-8b6a-4a83-be74-e34839bcc9ea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2621263209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2621263209 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2943349022 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 12949941216 ps |
| CPU time | 2617.15 seconds |
| Started | Aug 09 08:50:14 PM PDT 24 |
| Finished | Aug 09 09:33:52 PM PDT 24 |
| Peak memory | 623304 kb |
| Host | smart-137540e5-039b-46d1-8592-32674b41daed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2943349022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.2943349022 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.1996419223 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 10614425800 ps |
| CPU time | 971.38 seconds |
| Started | Aug 09 08:34:29 PM PDT 24 |
| Finished | Aug 09 08:50:40 PM PDT 24 |
| Peak memory | 607860 kb |
| Host | smart-7d6a5fa7-5611-4e7c-b1b2-933e3a287c3a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996419223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.1996419223 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.317802732 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 13627935412 ps |
| CPU time | 1409.08 seconds |
| Started | Aug 09 08:34:29 PM PDT 24 |
| Finished | Aug 09 08:57:59 PM PDT 24 |
| Peak memory | 607732 kb |
| Host | smart-00ba8847-5ad2-4678-8671-e4b102ba1dce |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317802732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.317802732 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.35707607 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 4036335850 ps |
| CPU time | 359.88 seconds |
| Started | Aug 09 08:42:43 PM PDT 24 |
| Finished | Aug 09 08:48:44 PM PDT 24 |
| Peak memory | 620796 kb |
| Host | smart-08fe16e7-2911-484c-a589-6dcbf59c2bf6 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 5707607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.35707607 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.1215482817 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 3414728968 ps |
| CPU time | 246.98 seconds |
| Started | Aug 09 08:36:47 PM PDT 24 |
| Finished | Aug 09 08:40:55 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-17177691-14ba-42e6-9ddb-e316e12de871 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1215482817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.1215482817 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1868170467 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 20026442552 ps |
| CPU time | 755.05 seconds |
| Started | Aug 09 08:40:59 PM PDT 24 |
| Finished | Aug 09 08:53:35 PM PDT 24 |
| Peak memory | 619544 kb |
| Host | smart-abe1a7dc-98bc-49cd-9751-1a663b6e43d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1868170467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1868170467 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.3645989002 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3258190104 ps |
| CPU time | 298.56 seconds |
| Started | Aug 09 08:39:06 PM PDT 24 |
| Finished | Aug 09 08:44:05 PM PDT 24 |
| Peak memory | 609400 kb |
| Host | smart-33fe5577-4782-42e2-b2bb-ef649fd4bfd5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645989002 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.3645989002 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.578908022 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 3257456564 ps |
| CPU time | 267.55 seconds |
| Started | Aug 09 08:39:07 PM PDT 24 |
| Finished | Aug 09 08:43:35 PM PDT 24 |
| Peak memory | 608344 kb |
| Host | smart-fe1a6c34-d162-4941-b248-52e0fd27e3d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5789 08022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.578908022 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3178051095 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 3636114304 ps |
| CPU time | 273.39 seconds |
| Started | Aug 09 08:49:05 PM PDT 24 |
| Finished | Aug 09 08:53:39 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-7884e2fc-a2ae-4d8d-8b1c-9c8cedfdc4b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178051095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3178051095 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.365457055 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 3099167632 ps |
| CPU time | 269.88 seconds |
| Started | Aug 09 08:39:39 PM PDT 24 |
| Finished | Aug 09 08:44:09 PM PDT 24 |
| Peak memory | 609424 kb |
| Host | smart-1752168e-b733-4d12-a4aa-7d1a91cd4039 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365457055 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.365457055 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.2384518842 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 2801063436 ps |
| CPU time | 229.84 seconds |
| Started | Aug 09 08:40:48 PM PDT 24 |
| Finished | Aug 09 08:44:38 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-c8c24cc9-29e2-4937-b9e2-41a83c668812 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384518842 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2384518842 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.1901099724 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 3280287037 ps |
| CPU time | 379.09 seconds |
| Started | Aug 09 08:39:49 PM PDT 24 |
| Finished | Aug 09 08:46:08 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-a7a5c652-384a-4edc-bc60-c324600dc1f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901099724 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.1901099724 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.3983406862 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3060038654 ps |
| CPU time | 286.02 seconds |
| Started | Aug 09 08:44:44 PM PDT 24 |
| Finished | Aug 09 08:49:30 PM PDT 24 |
| Peak memory | 609460 kb |
| Host | smart-bacc040f-f6b5-41a0-b048-f58ddcbbd452 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983406862 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.3983406862 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.300382999 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 3500812277 ps |
| CPU time | 400.77 seconds |
| Started | Aug 09 08:39:19 PM PDT 24 |
| Finished | Aug 09 08:46:00 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-9f044efd-81a4-4690-baf6-a89e1ead743c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=300382999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.300382999 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2204078922 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 5620710650 ps |
| CPU time | 624.09 seconds |
| Started | Aug 09 08:39:58 PM PDT 24 |
| Finished | Aug 09 08:50:23 PM PDT 24 |
| Peak memory | 619256 kb |
| Host | smart-af54a3bf-efc4-4443-8d47-b1e5b6a8e9a0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2204078922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2204078922 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.148326864 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 5822812878 ps |
| CPU time | 1131.52 seconds |
| Started | Aug 09 08:42:52 PM PDT 24 |
| Finished | Aug 09 09:01:44 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-b2b28778-3b0e-4a8d-8c56-a8f3da2a4fa0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=148326864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.148326864 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4214928793 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 7897935904 ps |
| CPU time | 1398.28 seconds |
| Started | Aug 09 08:43:33 PM PDT 24 |
| Finished | Aug 09 09:06:52 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-ca12e399-1952-407c-8224-cf9359efaab2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214928793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.4214928793 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.259664709 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3964321498 ps |
| CPU time | 438.67 seconds |
| Started | Aug 09 08:39:22 PM PDT 24 |
| Finished | Aug 09 08:46:41 PM PDT 24 |
| Peak memory | 649068 kb |
| Host | smart-787b421e-bc67-45c6-9854-b9606329e9e8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259664709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _alert_handler_lpg_sleep_mode_alerts.259664709 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3463920932 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 8252632360 ps |
| CPU time | 1373.34 seconds |
| Started | Aug 09 08:38:54 PM PDT 24 |
| Finished | Aug 09 09:01:48 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-1dda9d1a-d769-4877-901b-cf040531d660 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3463920932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.3463920932 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2376095758 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3778424912 ps |
| CPU time | 325.76 seconds |
| Started | Aug 09 08:41:24 PM PDT 24 |
| Finished | Aug 09 08:46:50 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-09b13866-1ca4-49f0-8aaa-337de7590f2b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2376095758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.2376095758 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1078273276 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 255315765384 ps |
| CPU time | 11347.9 seconds |
| Started | Aug 09 08:41:26 PM PDT 24 |
| Finished | Aug 09 11:50:35 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-d28495f6-67ec-4b9a-a61e-5b6b3b6d6934 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078273276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1078273276 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.3331379259 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2536778428 ps |
| CPU time | 337.7 seconds |
| Started | Aug 09 08:39:40 PM PDT 24 |
| Finished | Aug 09 08:45:18 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-01ae10f2-1c79-41fe-a158-4ebe2a196c89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331379259 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.3331379259 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.3782858042 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 4636868360 ps |
| CPU time | 331.31 seconds |
| Started | Aug 09 08:40:07 PM PDT 24 |
| Finished | Aug 09 08:45:38 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-6aea1921-0115-4b66-a9f7-31c5708b3bd5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782858042 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3782858042 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1376352539 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 7798700778 ps |
| CPU time | 425.4 seconds |
| Started | Aug 09 08:39:55 PM PDT 24 |
| Finished | Aug 09 08:47:01 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-efa58ce6-1711-4818-a498-d8e30498f89c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1376352539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1376352539 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3813651599 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2441525636 ps |
| CPU time | 239.5 seconds |
| Started | Aug 09 08:47:35 PM PDT 24 |
| Finished | Aug 09 08:51:35 PM PDT 24 |
| Peak memory | 609540 kb |
| Host | smart-ccaf13e4-37fb-4757-94f0-6a60e31ade75 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813651599 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.3813651599 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.320748305 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 8000588490 ps |
| CPU time | 921.29 seconds |
| Started | Aug 09 08:41:04 PM PDT 24 |
| Finished | Aug 09 08:56:26 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-2b9c8643-ef71-48f7-b08f-9aa88eb78f98 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 320748305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.320748305 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2566495596 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 5375746576 ps |
| CPU time | 539.51 seconds |
| Started | Aug 09 08:39:15 PM PDT 24 |
| Finished | Aug 09 08:48:15 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-6e3a8223-239f-404c-b66c-f36f1167bd3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2566495596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.2566495596 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2133301479 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 8788120976 ps |
| CPU time | 904.72 seconds |
| Started | Aug 09 08:41:36 PM PDT 24 |
| Finished | Aug 09 08:56:41 PM PDT 24 |
| Peak memory | 616904 kb |
| Host | smart-8664afab-a389-42cb-a3b4-74d71cdf6cb3 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133301479 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.2133301479 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1796302067 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 25068693499 ps |
| CPU time | 3179.51 seconds |
| Started | Aug 09 08:43:02 PM PDT 24 |
| Finished | Aug 09 09:36:02 PM PDT 24 |
| Peak memory | 610980 kb |
| Host | smart-23b11758-9b1f-4c01-a9a6-208650afc06c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796302067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.1796302067 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1592505336 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 6374072299 ps |
| CPU time | 543.15 seconds |
| Started | Aug 09 08:42:58 PM PDT 24 |
| Finished | Aug 09 08:52:01 PM PDT 24 |
| Peak memory | 621156 kb |
| Host | smart-9794456c-8a53-4ceb-89de-45eac82ad53d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1592505336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1592505336 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2996175053 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 4017437778 ps |
| CPU time | 743.25 seconds |
| Started | Aug 09 08:41:02 PM PDT 24 |
| Finished | Aug 09 08:53:25 PM PDT 24 |
| Peak memory | 612884 kb |
| Host | smart-d13f2402-a3b3-4c5a-bf46-507f7e39694c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996175053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2996175053 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.662799570 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 3935003880 ps |
| CPU time | 806.4 seconds |
| Started | Aug 09 08:41:19 PM PDT 24 |
| Finished | Aug 09 08:54:46 PM PDT 24 |
| Peak memory | 611908 kb |
| Host | smart-346db0bb-3fc9-4cc2-9231-d3dbf3280e65 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662799570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.662799570 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2678105975 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 3944728924 ps |
| CPU time | 630.8 seconds |
| Started | Aug 09 08:41:52 PM PDT 24 |
| Finished | Aug 09 08:52:23 PM PDT 24 |
| Peak memory | 611928 kb |
| Host | smart-c44483cb-ec60-45bd-988e-36111f8bf2f2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678105975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2678105975 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4246165019 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 5585457116 ps |
| CPU time | 694.96 seconds |
| Started | Aug 09 08:41:25 PM PDT 24 |
| Finished | Aug 09 08:53:00 PM PDT 24 |
| Peak memory | 612028 kb |
| Host | smart-31d0f8d1-717d-484b-8935-bd40b79130da |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246165019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.4246165019 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3863476144 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 4409187390 ps |
| CPU time | 636.46 seconds |
| Started | Aug 09 08:41:39 PM PDT 24 |
| Finished | Aug 09 08:52:16 PM PDT 24 |
| Peak memory | 611968 kb |
| Host | smart-d3485573-f333-42d7-8743-3132df6baa24 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863476144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3863476144 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2589552193 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 4830615758 ps |
| CPU time | 673.63 seconds |
| Started | Aug 09 08:42:51 PM PDT 24 |
| Finished | Aug 09 08:54:05 PM PDT 24 |
| Peak memory | 612076 kb |
| Host | smart-c21d28ab-7b00-4427-938e-6faa60311e16 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589552193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2589552193 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3134604577 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 3259446508 ps |
| CPU time | 183.65 seconds |
| Started | Aug 09 08:41:17 PM PDT 24 |
| Finished | Aug 09 08:44:21 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-d79320ec-4072-4aa5-a24c-c85b11ab8d74 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134604577 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.3134604577 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3712859111 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3408621618 ps |
| CPU time | 375.06 seconds |
| Started | Aug 09 08:41:58 PM PDT 24 |
| Finished | Aug 09 08:48:14 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-02975697-5486-492b-8ad8-40b85732047b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712859111 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.3712859111 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1942600219 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 2708149050 ps |
| CPU time | 181.29 seconds |
| Started | Aug 09 08:42:17 PM PDT 24 |
| Finished | Aug 09 08:45:18 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-e0cf8588-5ff4-4da9-ba65-84ccb15ba94d |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942600219 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.1942600219 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2789829688 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 4709295336 ps |
| CPU time | 444.73 seconds |
| Started | Aug 09 08:41:31 PM PDT 24 |
| Finished | Aug 09 08:48:56 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-9db7f6c2-99c5-4ad0-b77c-1e9ad7588d02 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789829688 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2789829688 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.251728377 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 5116724472 ps |
| CPU time | 537.62 seconds |
| Started | Aug 09 08:43:05 PM PDT 24 |
| Finished | Aug 09 08:52:03 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-110dd27c-8552-4478-be5a-82adb5e8ad8d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251728377 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.251728377 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3641454876 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 4139101728 ps |
| CPU time | 328.9 seconds |
| Started | Aug 09 08:41:22 PM PDT 24 |
| Finished | Aug 09 08:46:52 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-aa3d22a6-62b4-447a-9b49-f2b867e91556 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641454876 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.3641454876 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.569750449 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 5674817168 ps |
| CPU time | 685.57 seconds |
| Started | Aug 09 08:42:45 PM PDT 24 |
| Finished | Aug 09 08:54:11 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-28f953c6-dc71-492d-b030-85bfdf7fd13a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569750449 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.569750449 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3778195996 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 9511458200 ps |
| CPU time | 1205.35 seconds |
| Started | Aug 09 08:41:52 PM PDT 24 |
| Finished | Aug 09 09:01:58 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-0de8e1aa-a7df-4820-9991-73036742987a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778195996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3778195996 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1343827643 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 3290010816 ps |
| CPU time | 470.97 seconds |
| Started | Aug 09 08:41:34 PM PDT 24 |
| Finished | Aug 09 08:49:26 PM PDT 24 |
| Peak memory | 608524 kb |
| Host | smart-b4e894af-98e8-4311-a1c1-0364b005af1f |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343827643 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1343827643 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.202707847 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 4632440448 ps |
| CPU time | 947 seconds |
| Started | Aug 09 08:41:02 PM PDT 24 |
| Finished | Aug 09 08:56:49 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-7ce48566-af7e-4524-8230-08f638adc3dc |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202707847 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.202707847 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.886866332 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 3432547074 ps |
| CPU time | 295.81 seconds |
| Started | Aug 09 08:44:45 PM PDT 24 |
| Finished | Aug 09 08:49:42 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-367f03d7-972d-4b44-bf65-ef764032cdf5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886866332 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_clkmgr_smoketest.886866332 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3464909923 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 22490107148 ps |
| CPU time | 5146.72 seconds |
| Started | Aug 09 08:40:03 PM PDT 24 |
| Finished | Aug 09 10:05:50 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-39021527-47ac-4a08-b909-8f23e9373928 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464909923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.3464909923 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2036701069 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 21746592440 ps |
| CPU time | 3405.59 seconds |
| Started | Aug 09 08:44:14 PM PDT 24 |
| Finished | Aug 09 09:41:00 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-3a9de0d0-52c2-4aa8-a058-2251823282c2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2036701069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.2036701069 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3389448211 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 3327425318 ps |
| CPU time | 394.89 seconds |
| Started | Aug 09 08:41:48 PM PDT 24 |
| Finished | Aug 09 08:48:23 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-f64c996b-92e4-487d-97f2-8dcc6b06f0ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33894 48211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3389448211 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.3389136834 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 2769710560 ps |
| CPU time | 285.77 seconds |
| Started | Aug 09 08:39:44 PM PDT 24 |
| Finished | Aug 09 08:44:29 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-f89e795c-1b3b-41c4-9cbd-9728ff936d0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389136834 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.3389136834 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.4014699158 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 2670953774 ps |
| CPU time | 191.89 seconds |
| Started | Aug 09 08:45:13 PM PDT 24 |
| Finished | Aug 09 08:48:25 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-b4b5eb6c-3a25-4b93-8757-d40d23bb60a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014699158 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.4014699158 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3093891146 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 6261741150 ps |
| CPU time | 596.49 seconds |
| Started | Aug 09 08:35:06 PM PDT 24 |
| Finished | Aug 09 08:45:03 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-906893b9-8327-4444-8f9e-7d2935435209 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3093891146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.3093891146 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.3093375080 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 6162263904 ps |
| CPU time | 1608.54 seconds |
| Started | Aug 09 08:40:29 PM PDT 24 |
| Finished | Aug 09 09:07:18 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-00ec5b78-d21a-4f1d-935e-c7836af73f56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093375080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.3093375080 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.2304673583 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 3166666392 ps |
| CPU time | 672.02 seconds |
| Started | Aug 09 08:40:59 PM PDT 24 |
| Finished | Aug 09 08:52:11 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-811d4e0c-d0c8-479a-b3f2-ec7be395e118 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304673583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.2304673583 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.4287263642 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 6117450296 ps |
| CPU time | 1077.68 seconds |
| Started | Aug 09 08:39:25 PM PDT 24 |
| Finished | Aug 09 08:57:23 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-49667771-3100-4825-9552-1f056f013b89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4287263642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.4287263642 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1875052575 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5564769932 ps |
| CPU time | 1006.73 seconds |
| Started | Aug 09 08:42:29 PM PDT 24 |
| Finished | Aug 09 08:59:15 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-725049fe-dcb7-46a9-b880-b0dcc8ecbbfb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875052575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.1875052575 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.201832795 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 3429057780 ps |
| CPU time | 652.03 seconds |
| Started | Aug 09 08:40:05 PM PDT 24 |
| Finished | Aug 09 08:50:57 PM PDT 24 |
| Peak memory | 615428 kb |
| Host | smart-de699639-3bfe-4cbb-bec2-738a83ebaae6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201832795 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_edn_kat.201832795 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.2239032183 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 9686938864 ps |
| CPU time | 1583.84 seconds |
| Started | Aug 09 08:40:23 PM PDT 24 |
| Finished | Aug 09 09:06:47 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-5b9a7b3e-26a4-460b-ba98-a79b4cbc085a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239032183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.2239032183 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1096589716 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2804013780 ps |
| CPU time | 255.85 seconds |
| Started | Aug 09 08:39:45 PM PDT 24 |
| Finished | Aug 09 08:44:01 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-2da0481e-2bc5-48bf-972f-a3dece73b806 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10 96589716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1096589716 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3209339601 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 8295564998 ps |
| CPU time | 1663.69 seconds |
| Started | Aug 09 08:41:08 PM PDT 24 |
| Finished | Aug 09 09:08:52 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-0fa0c9ec-6b38-4fb2-9c2f-5bf6f3ed85de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3209339601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.3209339601 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2669872863 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 3216328600 ps |
| CPU time | 171.24 seconds |
| Started | Aug 09 08:39:02 PM PDT 24 |
| Finished | Aug 09 08:41:54 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-95d6b4f2-2c5d-4956-a5d5-b79a212d8dc0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669872863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2669872863 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.841236071 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 3561449886 ps |
| CPU time | 587.94 seconds |
| Started | Aug 09 08:43:53 PM PDT 24 |
| Finished | Aug 09 08:53:41 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-564b417a-f10e-406d-8cd4-9aea36085fce |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=841236071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.841236071 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.2672868288 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 2471178432 ps |
| CPU time | 240.63 seconds |
| Started | Aug 09 08:35:38 PM PDT 24 |
| Finished | Aug 09 08:39:39 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-49efd041-2c75-46d3-8756-8d6de34e2868 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672868288 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.2672868288 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.4258178763 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 2942035224 ps |
| CPU time | 254.14 seconds |
| Started | Aug 09 08:35:38 PM PDT 24 |
| Finished | Aug 09 08:39:52 PM PDT 24 |
| Peak memory | 608188 kb |
| Host | smart-7c68c7d2-0f19-40d5-9860-8fde7aafecc2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258178763 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.4258178763 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.1042820248 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2593492304 ps |
| CPU time | 222.31 seconds |
| Started | Aug 09 08:37:55 PM PDT 24 |
| Finished | Aug 09 08:41:38 PM PDT 24 |
| Peak memory | 609036 kb |
| Host | smart-e8ed34e2-c87c-4b3b-8cd6-047426c3c2e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042820248 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.1042820248 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.1321837527 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 3116154032 ps |
| CPU time | 137.62 seconds |
| Started | Aug 09 08:35:02 PM PDT 24 |
| Finished | Aug 09 08:37:19 PM PDT 24 |
| Peak memory | 607776 kb |
| Host | smart-709beb49-6c78-4b19-b4d3-ee5eb007d665 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321837527 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.1321837527 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3780954874 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 58851688850 ps |
| CPU time | 10355.5 seconds |
| Started | Aug 09 08:38:05 PM PDT 24 |
| Finished | Aug 09 11:30:41 PM PDT 24 |
| Peak memory | 624684 kb |
| Host | smart-459f592d-7abc-4a51-80a1-cbc13c21a59e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3780954874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.3780954874 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.695993512 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 6259678252 ps |
| CPU time | 748.62 seconds |
| Started | Aug 09 08:42:20 PM PDT 24 |
| Finished | Aug 09 08:54:49 PM PDT 24 |
| Peak memory | 611080 kb |
| Host | smart-a454f603-e024-4327-9b48-dd7a5ffe0ae3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=695993512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.695993512 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1724234927 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 5424362750 ps |
| CPU time | 1097.18 seconds |
| Started | Aug 09 08:37:49 PM PDT 24 |
| Finished | Aug 09 08:56:07 PM PDT 24 |
| Peak memory | 609212 kb |
| Host | smart-85c30f90-117c-4612-b6f7-00e4e88bf035 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724234927 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.1724234927 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.150395337 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 5977993361 ps |
| CPU time | 1106.08 seconds |
| Started | Aug 09 08:38:47 PM PDT 24 |
| Finished | Aug 09 08:57:14 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-edf38ae1-b838-4588-9662-9c431b2c6f8a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150395337 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.150395337 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2252697789 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 6802712564 ps |
| CPU time | 1050.04 seconds |
| Started | Aug 09 08:43:08 PM PDT 24 |
| Finished | Aug 09 09:00:39 PM PDT 24 |
| Peak memory | 608772 kb |
| Host | smart-8532478c-78cc-41d1-b599-6c098defdfad |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252697789 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2252697789 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1463824503 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 6420597064 ps |
| CPU time | 1289.4 seconds |
| Started | Aug 09 08:37:35 PM PDT 24 |
| Finished | Aug 09 08:59:05 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-66420fcf-1d98-400e-99fe-6753d97adf33 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463824503 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.1463824503 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3726676501 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3181640266 ps |
| CPU time | 420.55 seconds |
| Started | Aug 09 08:38:17 PM PDT 24 |
| Finished | Aug 09 08:45:18 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-46d3ac0c-4933-43f5-915e-9e027c0cda0d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726676501 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.3726676501 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3100490601 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 4198057330 ps |
| CPU time | 485.9 seconds |
| Started | Aug 09 08:37:01 PM PDT 24 |
| Finished | Aug 09 08:45:07 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-a89c30b0-fd6a-42bc-84d1-4b4630cd7f55 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31 00490601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.3100490601 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3958039868 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 5983233358 ps |
| CPU time | 1397.91 seconds |
| Started | Aug 09 08:43:47 PM PDT 24 |
| Finished | Aug 09 09:07:05 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-d0eedcd7-9038-4603-8176-73370e50a30c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958039868 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.3958039868 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1694355610 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3318953394 ps |
| CPU time | 602.48 seconds |
| Started | Aug 09 08:39:33 PM PDT 24 |
| Finished | Aug 09 08:49:36 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-cf16ff1f-5b60-415f-8ff9-834a21d54774 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694355610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.1694355610 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3903998033 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4610927530 ps |
| CPU time | 572.54 seconds |
| Started | Aug 09 08:36:48 PM PDT 24 |
| Finished | Aug 09 08:46:20 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-d26153eb-f0d2-4ab0-8f82-1d615e260bc2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3903998033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.3903998033 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4021479349 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 4570659645 ps |
| CPU time | 778.55 seconds |
| Started | Aug 09 08:43:36 PM PDT 24 |
| Finished | Aug 09 08:56:35 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-0e4bd505-b53e-4237-bbb4-13b245e8ffa2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=4021479349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4021479349 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1841497284 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 3681088632 ps |
| CPU time | 412.71 seconds |
| Started | Aug 09 08:42:36 PM PDT 24 |
| Finished | Aug 09 08:49:30 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-6251175b-dd1c-4161-ae91-d0b57ba927e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841497 284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.1841497284 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3590863228 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 20556541651 ps |
| CPU time | 2386.01 seconds |
| Started | Aug 09 08:44:19 PM PDT 24 |
| Finished | Aug 09 09:24:06 PM PDT 24 |
| Peak memory | 612420 kb |
| Host | smart-902148fe-e790-462a-89a8-adc1e58fca63 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3590863228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.3590863228 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1584931335 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 2888780152 ps |
| CPU time | 241.48 seconds |
| Started | Aug 09 08:48:49 PM PDT 24 |
| Finished | Aug 09 08:52:51 PM PDT 24 |
| Peak memory | 609496 kb |
| Host | smart-258cfb02-87ad-4258-972d-c790bf9af68f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1584931335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1584931335 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.601520918 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 2722623219 ps |
| CPU time | 272.63 seconds |
| Started | Aug 09 08:47:22 PM PDT 24 |
| Finished | Aug 09 08:51:56 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-35f4002a-e66e-4e69-9b50-05a131d0bfc7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601520918 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_gpio_smoketest.601520918 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.3152070330 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2923889114 ps |
| CPU time | 340.94 seconds |
| Started | Aug 09 08:41:12 PM PDT 24 |
| Finished | Aug 09 08:46:54 PM PDT 24 |
| Peak memory | 609560 kb |
| Host | smart-8b1b2f46-747a-4d2d-b8f4-a81f3459a304 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152070330 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.3152070330 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1583568824 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 2922093104 ps |
| CPU time | 217.8 seconds |
| Started | Aug 09 08:40:08 PM PDT 24 |
| Finished | Aug 09 08:43:46 PM PDT 24 |
| Peak memory | 608228 kb |
| Host | smart-f771a7fb-255a-4d36-80c1-48a6b9e710bf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583568824 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.1583568824 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2764405982 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3048022150 ps |
| CPU time | 389.42 seconds |
| Started | Aug 09 08:40:51 PM PDT 24 |
| Finished | Aug 09 08:47:21 PM PDT 24 |
| Peak memory | 609520 kb |
| Host | smart-52587436-0d5d-4196-b01c-ea31311ee1ff |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764405982 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.2764405982 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4137358176 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 2781251958 ps |
| CPU time | 263.61 seconds |
| Started | Aug 09 08:43:39 PM PDT 24 |
| Finished | Aug 09 08:48:03 PM PDT 24 |
| Peak memory | 609596 kb |
| Host | smart-d0676cab-d043-4e05-90bb-ea3cdd9d4f65 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137358176 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.4137358176 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.1714576837 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 7987033448 ps |
| CPU time | 1640.25 seconds |
| Started | Aug 09 08:42:03 PM PDT 24 |
| Finished | Aug 09 09:09:24 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-876811a6-6047-4879-9d97-a1fbb7c06889 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714576837 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.1714576837 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.1512285157 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3301683080 ps |
| CPU time | 443.53 seconds |
| Started | Aug 09 08:42:22 PM PDT 24 |
| Finished | Aug 09 08:49:46 PM PDT 24 |
| Peak memory | 609104 kb |
| Host | smart-cbb26a96-305e-41e9-a246-21f41a6c85c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512285157 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.1512285157 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.2742649884 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3516819722 ps |
| CPU time | 281.93 seconds |
| Started | Aug 09 08:47:57 PM PDT 24 |
| Finished | Aug 09 08:52:39 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-7782a005-54e9-493c-9924-ec3280912632 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742649884 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.2742649884 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.748236824 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4614257588 ps |
| CPU time | 738.59 seconds |
| Started | Aug 09 08:37:44 PM PDT 24 |
| Finished | Aug 09 08:50:03 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-a89649b5-8c5e-43cd-9a8a-2972b60400ca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748236824 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.748236824 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1086107406 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 5505701334 ps |
| CPU time | 769.71 seconds |
| Started | Aug 09 08:37:08 PM PDT 24 |
| Finished | Aug 09 08:49:58 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-60beb80d-de43-4ee9-88f9-597027c32e25 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086107406 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.1086107406 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2600020778 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 5271679876 ps |
| CPU time | 727.65 seconds |
| Started | Aug 09 08:37:55 PM PDT 24 |
| Finished | Aug 09 08:50:04 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-e35efc2f-c1f0-40d2-bde9-c1f904888550 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600020778 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.2600020778 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1598964091 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 65043384958 ps |
| CPU time | 12153.8 seconds |
| Started | Aug 09 08:37:41 PM PDT 24 |
| Finished | Aug 10 12:00:17 AM PDT 24 |
| Peak memory | 624652 kb |
| Host | smart-d07ee45d-b310-42ba-baa5-4a14800ec05f |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1598964091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.1598964091 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2954166993 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 9592478540 ps |
| CPU time | 2115.77 seconds |
| Started | Aug 09 08:40:30 PM PDT 24 |
| Finished | Aug 09 09:15:46 PM PDT 24 |
| Peak memory | 616440 kb |
| Host | smart-472bc5f6-7376-42ee-a0eb-fbb528ebb6d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954 166993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.2954166993 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3892711891 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 10646167985 ps |
| CPU time | 1906.8 seconds |
| Started | Aug 09 08:40:37 PM PDT 24 |
| Finished | Aug 09 09:12:24 PM PDT 24 |
| Peak memory | 617740 kb |
| Host | smart-784cc32b-7fcb-451e-bde7-92627ab29a02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3892711891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.3892711891 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.123710683 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 12448171625 ps |
| CPU time | 1384.65 seconds |
| Started | Aug 09 08:46:01 PM PDT 24 |
| Finished | Aug 09 09:09:06 PM PDT 24 |
| Peak memory | 616728 kb |
| Host | smart-6076961c-2d4f-47ac-9473-03efd36cc2db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=123710683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.123710683 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.737038238 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 10055741000 ps |
| CPU time | 1782.53 seconds |
| Started | Aug 09 08:39:57 PM PDT 24 |
| Finished | Aug 09 09:09:40 PM PDT 24 |
| Peak memory | 616684 kb |
| Host | smart-d4006dab-4fb2-458e-961f-f337260ab6ac |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=737038238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.737038238 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2632598233 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 9169121232 ps |
| CPU time | 1378.96 seconds |
| Started | Aug 09 08:39:56 PM PDT 24 |
| Finished | Aug 09 09:02:55 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-fc9c7ad1-d0e4-44bb-b0ef-218d6b131833 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26325 98233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.2632598233 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2148573064 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 15359315190 ps |
| CPU time | 3126.44 seconds |
| Started | Aug 09 08:42:16 PM PDT 24 |
| Finished | Aug 09 09:34:23 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-438ac410-f4c8-43fa-b5c2-8e7d72bdf43a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21485 73064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2148573064 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.1919880763 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 2358951186 ps |
| CPU time | 165.87 seconds |
| Started | Aug 09 08:40:55 PM PDT 24 |
| Finished | Aug 09 08:43:41 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-74dce6d0-ae0c-425d-9b04-9a68bad7fe5f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919880763 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.1919880763 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.3585438236 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3356832840 ps |
| CPU time | 202.46 seconds |
| Started | Aug 09 08:37:33 PM PDT 24 |
| Finished | Aug 09 08:40:56 PM PDT 24 |
| Peak memory | 608272 kb |
| Host | smart-6a940bd5-d7b2-4c56-89e5-34877492b985 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585438236 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.3585438236 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.2122207942 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2781319276 ps |
| CPU time | 222.6 seconds |
| Started | Aug 09 08:41:22 PM PDT 24 |
| Finished | Aug 09 08:45:05 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-bbba24a4-e902-44d4-9cdd-7c8377b2b00b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122207942 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.2122207942 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1931224297 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 2615343480 ps |
| CPU time | 249.55 seconds |
| Started | Aug 09 08:42:15 PM PDT 24 |
| Finished | Aug 09 08:46:26 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-7a27b022-80a7-48fd-8e47-bee4b16bc5b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931224297 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.1931224297 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1450038603 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 3051575416 ps |
| CPU time | 358.51 seconds |
| Started | Aug 09 08:41:34 PM PDT 24 |
| Finished | Aug 09 08:47:32 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-8b8a86a6-41f4-4517-acc2-f7e74bbefd92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450038603 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.1450038603 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.675205319 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 3348395447 ps |
| CPU time | 343.45 seconds |
| Started | Aug 09 08:46:16 PM PDT 24 |
| Finished | Aug 09 08:51:59 PM PDT 24 |
| Peak memory | 609088 kb |
| Host | smart-793ae2f0-0a6e-4fde-a993-bb3a084f77d2 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675205319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.675205319 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.964908134 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 3314037557 ps |
| CPU time | 251 seconds |
| Started | Aug 09 08:45:04 PM PDT 24 |
| Finished | Aug 09 08:49:15 PM PDT 24 |
| Peak memory | 609592 kb |
| Host | smart-b4fe2de6-a743-4ac5-a6ea-081db4b3af24 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96490813 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.964908134 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.3117599549 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 3063929160 ps |
| CPU time | 265.45 seconds |
| Started | Aug 09 08:47:25 PM PDT 24 |
| Finished | Aug 09 08:51:51 PM PDT 24 |
| Peak memory | 609496 kb |
| Host | smart-841690c0-f6ee-45dd-a4a8-fac29a6506aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117599549 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.3117599549 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3690603344 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 3561356040 ps |
| CPU time | 420.2 seconds |
| Started | Aug 09 08:37:06 PM PDT 24 |
| Finished | Aug 09 08:44:07 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-fc2e6028-e885-4a1f-a5d3-d8018e9b6c5f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690603344 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.3690603344 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2825572140 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4639151670 ps |
| CPU time | 706.32 seconds |
| Started | Aug 09 08:43:19 PM PDT 24 |
| Finished | Aug 09 08:55:06 PM PDT 24 |
| Peak memory | 610904 kb |
| Host | smart-972d319a-acd7-4bbf-84a7-f55f5b8d68af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2825572140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.2825572140 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2597293333 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 3276533779 ps |
| CPU time | 132.44 seconds |
| Started | Aug 09 08:37:07 PM PDT 24 |
| Finished | Aug 09 08:39:20 PM PDT 24 |
| Peak memory | 619916 kb |
| Host | smart-a3f1bcb0-07b1-42c4-b8ab-59a47fe836d2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25972933 33 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.2597293333 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2573215425 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 5304786748 ps |
| CPU time | 429.16 seconds |
| Started | Aug 09 08:37:40 PM PDT 24 |
| Finished | Aug 09 08:44:50 PM PDT 24 |
| Peak memory | 621012 kb |
| Host | smart-d0f77113-dae1-459d-a908-844cc67e98c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573215425 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.2573215425 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.145293251 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2534544902 ps |
| CPU time | 115.91 seconds |
| Started | Aug 09 08:38:01 PM PDT 24 |
| Finished | Aug 09 08:39:57 PM PDT 24 |
| Peak memory | 616900 kb |
| Host | smart-24874220-fb7f-4d3e-a4e4-237082545340 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=145293251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.145293251 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4052870882 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 2452497305 ps |
| CPU time | 145.03 seconds |
| Started | Aug 09 08:36:59 PM PDT 24 |
| Finished | Aug 09 08:39:24 PM PDT 24 |
| Peak memory | 616792 kb |
| Host | smart-9c17ea21-8bf3-4b72-83ed-dc9ca8c4ac74 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052870882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4052870882 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1903984936 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 49843269248 ps |
| CPU time | 5608.07 seconds |
| Started | Aug 09 08:42:19 PM PDT 24 |
| Finished | Aug 09 10:15:49 PM PDT 24 |
| Peak memory | 620644 kb |
| Host | smart-f8912469-09f9-42f2-9975-c462fba96b8d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903984936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.1903984936 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.6236752 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 48501318195 ps |
| CPU time | 5281.37 seconds |
| Started | Aug 09 08:42:47 PM PDT 24 |
| Finished | Aug 09 10:10:50 PM PDT 24 |
| Peak memory | 619692 kb |
| Host | smart-01a141a7-b78f-402e-8c5a-366b90cadc1d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6236752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_lc_walkthrough_prod.6236752 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.4221472310 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 47648841284 ps |
| CPU time | 5310.97 seconds |
| Started | Aug 09 08:38:03 PM PDT 24 |
| Finished | Aug 09 10:06:35 PM PDT 24 |
| Peak memory | 620212 kb |
| Host | smart-32ea8ca2-0954-4af8-b61c-3451bc80630d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221472310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.4221472310 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2511518510 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 24762760494 ps |
| CPU time | 2629.59 seconds |
| Started | Aug 09 08:39:08 PM PDT 24 |
| Finished | Aug 09 09:22:58 PM PDT 24 |
| Peak memory | 619708 kb |
| Host | smart-e139a02d-f2ab-4fd5-b365-92399107258d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2511518510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.2511518510 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2571868289 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 17502679450 ps |
| CPU time | 2987.71 seconds |
| Started | Aug 09 08:39:23 PM PDT 24 |
| Finished | Aug 09 09:29:11 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-221e7fc2-8416-4de9-a846-47060c91def8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2571868289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.2571868289 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3532358779 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 18272407700 ps |
| CPU time | 3348.15 seconds |
| Started | Aug 09 08:40:33 PM PDT 24 |
| Finished | Aug 09 09:36:22 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-059b64a2-1ca5-48d2-9e61-e35e3fc89306 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3532358779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3532358779 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3353054731 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 25415127591 ps |
| CPU time | 3237.82 seconds |
| Started | Aug 09 08:43:44 PM PDT 24 |
| Finished | Aug 09 09:37:43 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-a9f6b738-3a9c-43b8-86e7-39c6404ca380 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353054731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3353054731 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3661355289 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3564430044 ps |
| CPU time | 474.48 seconds |
| Started | Aug 09 08:41:01 PM PDT 24 |
| Finished | Aug 09 08:48:55 PM PDT 24 |
| Peak memory | 609524 kb |
| Host | smart-0797bf65-c961-480f-bcff-00b0b36adcb9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661355289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.3661355289 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.4119331017 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 5903908526 ps |
| CPU time | 1038.55 seconds |
| Started | Aug 09 08:39:03 PM PDT 24 |
| Finished | Aug 09 08:56:22 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-9bd898e1-0e82-4e3b-a47c-89d79a77b347 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4119331017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.4119331017 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.1362214344 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 5720232168 ps |
| CPU time | 826.47 seconds |
| Started | Aug 09 08:46:57 PM PDT 24 |
| Finished | Aug 09 09:00:44 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-7f937fc0-3dc0-4eb4-9af5-b95999db34cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362214344 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.1362214344 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1693926952 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 2877961534 ps |
| CPU time | 231.65 seconds |
| Started | Aug 09 08:38:47 PM PDT 24 |
| Finished | Aug 09 08:42:39 PM PDT 24 |
| Peak memory | 608404 kb |
| Host | smart-287f36d1-78ac-4231-8f74-c9b2463670da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693926952 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.1693926952 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2100957294 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 9232324700 ps |
| CPU time | 1553.41 seconds |
| Started | Aug 09 08:39:27 PM PDT 24 |
| Finished | Aug 09 09:05:21 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-7b2f3b88-378f-430f-a586-8a6b77f4a702 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2100957294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.2100957294 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2612722138 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 9835777018 ps |
| CPU time | 1557.72 seconds |
| Started | Aug 09 08:37:12 PM PDT 24 |
| Finished | Aug 09 09:03:10 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-335dc336-d0b7-4530-b026-ce8b3ce55408 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2612722138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.2612722138 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3945097033 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 8007261028 ps |
| CPU time | 1357.06 seconds |
| Started | Aug 09 08:38:07 PM PDT 24 |
| Finished | Aug 09 09:00:45 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-e1292b49-5106-4796-b569-6f4a8e7dfe23 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3945097033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.3945097033 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.697112420 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 5078700328 ps |
| CPU time | 648.2 seconds |
| Started | Aug 09 08:36:23 PM PDT 24 |
| Finished | Aug 09 08:47:11 PM PDT 24 |
| Peak memory | 608976 kb |
| Host | smart-7260a11f-bdb7-4119-bac7-2677a597638a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=697112420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.697112420 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2254139333 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 3297772480 ps |
| CPU time | 303.26 seconds |
| Started | Aug 09 08:44:50 PM PDT 24 |
| Finished | Aug 09 08:49:54 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-7cba431a-7fbb-4e35-be6e-a18bd79b3564 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254139333 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.2254139333 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.4136063563 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2798095736 ps |
| CPU time | 281.48 seconds |
| Started | Aug 09 08:35:24 PM PDT 24 |
| Finished | Aug 09 08:40:07 PM PDT 24 |
| Peak memory | 612168 kb |
| Host | smart-19325faa-73a3-439c-b12e-f00de366a922 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136063563 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.4136063563 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.3909661413 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2245768600 ps |
| CPU time | 267.01 seconds |
| Started | Aug 09 08:42:59 PM PDT 24 |
| Finished | Aug 09 08:47:26 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-105d178c-305f-48f1-a660-0baf2835c28f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909661413 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.3909661413 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.28381572 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 4496494802 ps |
| CPU time | 627.51 seconds |
| Started | Aug 09 08:44:09 PM PDT 24 |
| Finished | Aug 09 08:54:36 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-5a6d880a-155c-4536-be85-cd51642e0ce1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28381572 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.28381572 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.1502260052 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 11519827816 ps |
| CPU time | 637.86 seconds |
| Started | Aug 09 08:45:31 PM PDT 24 |
| Finished | Aug 09 08:56:10 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-2c24aedd-67e5-44b9-8a1c-d77e95ecc808 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502260052 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.1502260052 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_virus.3900345245 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5625513990 ps |
| CPU time | 1522.05 seconds |
| Started | Aug 09 08:48:24 PM PDT 24 |
| Finished | Aug 09 09:13:46 PM PDT 24 |
| Peak memory | 624928 kb |
| Host | smart-e8019c47-18c7-4657-bbe3-6cb6bfe5ec89 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3900345245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.3900345245 |
| Directory | /workspace/2.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2275270860 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 11451760231 ps |
| CPU time | 1372.15 seconds |
| Started | Aug 09 08:42:18 PM PDT 24 |
| Finished | Aug 09 09:05:11 PM PDT 24 |
| Peak memory | 611260 kb |
| Host | smart-0cb5969d-9dc1-4c54-ac9d-5b1da43f18a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275 270860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.2275270860 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.4274845452 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 25571754790 ps |
| CPU time | 1919.07 seconds |
| Started | Aug 09 08:40:37 PM PDT 24 |
| Finished | Aug 09 09:12:37 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-40fe993b-4712-41ff-90bd-011c3390ece2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427 4845452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.4274845452 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3085754483 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 10086341424 ps |
| CPU time | 852.04 seconds |
| Started | Aug 09 08:38:25 PM PDT 24 |
| Finished | Aug 09 08:52:37 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-c0e3c18a-5800-45ba-98c8-f3a7061bd8e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085754483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.3085754483 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1084774447 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 5709747450 ps |
| CPU time | 470.69 seconds |
| Started | Aug 09 08:39:17 PM PDT 24 |
| Finished | Aug 09 08:47:08 PM PDT 24 |
| Peak memory | 617336 kb |
| Host | smart-687d1a2b-3849-4cc9-bfd7-70a5b5e9e7b4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1084774447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1084774447 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3029638680 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 7925021402 ps |
| CPU time | 497.53 seconds |
| Started | Aug 09 08:43:19 PM PDT 24 |
| Finished | Aug 09 08:51:37 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-8d2974a3-2341-42a6-8dd6-6ed9b3eab58a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029638680 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.3029638680 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.957941916 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 5252272252 ps |
| CPU time | 455.94 seconds |
| Started | Aug 09 08:38:12 PM PDT 24 |
| Finished | Aug 09 08:45:48 PM PDT 24 |
| Peak memory | 616464 kb |
| Host | smart-5b728543-3b78-4182-ab50-e8d8d180202d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=957941916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.957941916 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.220214148 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 11894784788 ps |
| CPU time | 1478.42 seconds |
| Started | Aug 09 08:38:11 PM PDT 24 |
| Finished | Aug 09 09:02:49 PM PDT 24 |
| Peak memory | 611352 kb |
| Host | smart-337c0b72-a868-4270-ac3b-800774d31471 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220214148 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.220214148 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.396822054 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 6811800040 ps |
| CPU time | 400.22 seconds |
| Started | Aug 09 08:42:25 PM PDT 24 |
| Finished | Aug 09 08:49:06 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-3f063add-121d-40f6-a886-bca976a7b3d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396822054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.396822054 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.4266703276 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 4711908548 ps |
| CPU time | 314.6 seconds |
| Started | Aug 09 08:37:39 PM PDT 24 |
| Finished | Aug 09 08:42:53 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-96697cf3-9171-4bfa-8cd3-814908ebab4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266703276 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.4266703276 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1882414664 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 23554235900 ps |
| CPU time | 1448.09 seconds |
| Started | Aug 09 08:37:28 PM PDT 24 |
| Finished | Aug 09 09:01:36 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-fc5f1200-c26e-4621-b5c2-4c8d6fba962f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1882414664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1882414664 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2098820288 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 21690229992 ps |
| CPU time | 1277.32 seconds |
| Started | Aug 09 08:43:25 PM PDT 24 |
| Finished | Aug 09 09:04:43 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-c7ac39d7-8c18-4a36-b608-10c4f219d79d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2098820288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2098820288 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2774997837 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 31100249384 ps |
| CPU time | 3094.45 seconds |
| Started | Aug 09 08:38:47 PM PDT 24 |
| Finished | Aug 09 09:30:22 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-be203106-860d-4880-810e-8869f9ebe62b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774997837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2774997837 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3902811730 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 5766819418 ps |
| CPU time | 539.91 seconds |
| Started | Aug 09 08:43:21 PM PDT 24 |
| Finished | Aug 09 08:52:22 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-436e368b-c60f-4d49-a0d4-ded26b0ba37d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3902811730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3902811730 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3503993763 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2734029672 ps |
| CPU time | 303.3 seconds |
| Started | Aug 09 08:40:42 PM PDT 24 |
| Finished | Aug 09 08:45:45 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-a76413f9-ee23-4e4b-b3b4-5697aa28de25 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503993763 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.3503993763 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3335375545 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5913269360 ps |
| CPU time | 577.13 seconds |
| Started | Aug 09 08:41:15 PM PDT 24 |
| Finished | Aug 09 08:50:52 PM PDT 24 |
| Peak memory | 608860 kb |
| Host | smart-7767c565-ea02-4f18-968c-c704f1b27d88 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33353755 45 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3335375545 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2121427257 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 5927569000 ps |
| CPU time | 632.05 seconds |
| Started | Aug 09 08:43:56 PM PDT 24 |
| Finished | Aug 09 08:54:28 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-16d9e6fa-fc54-43a0-94a1-fcf2fd716ee8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2121427257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.2121427257 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3754694588 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 7169585840 ps |
| CPU time | 441.12 seconds |
| Started | Aug 09 08:44:55 PM PDT 24 |
| Finished | Aug 09 08:52:16 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-d385e245-c57a-44ac-879a-8d62ed5f2a8d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754694588 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.3754694588 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2807293400 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 5261043382 ps |
| CPU time | 601.75 seconds |
| Started | Aug 09 08:39:39 PM PDT 24 |
| Finished | Aug 09 08:49:40 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-7764254d-04bb-4d53-8a62-4a693a1feff6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807293400 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2807293400 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.4262705783 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 6202508886 ps |
| CPU time | 445.82 seconds |
| Started | Aug 09 08:44:28 PM PDT 24 |
| Finished | Aug 09 08:51:54 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-e0e20d0e-ce05-4072-b53f-58c21380cc5c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262705783 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.4262705783 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2357862750 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 4245328952 ps |
| CPU time | 744.9 seconds |
| Started | Aug 09 08:40:27 PM PDT 24 |
| Finished | Aug 09 08:52:52 PM PDT 24 |
| Peak memory | 609996 kb |
| Host | smart-2495bb22-449e-4871-9e17-18ec4afe2539 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235 7862750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.2357862750 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2873222503 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 9376626796 ps |
| CPU time | 525.03 seconds |
| Started | Aug 09 08:41:23 PM PDT 24 |
| Finished | Aug 09 08:50:09 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-379c1134-d13e-4482-ace5-a7e58670c3c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873222503 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.2873222503 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1051678115 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 5680494014 ps |
| CPU time | 597.16 seconds |
| Started | Aug 09 08:37:56 PM PDT 24 |
| Finished | Aug 09 08:47:53 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-aedce8ee-3262-4550-b8dd-f72fb6247c35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051678115 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1051678115 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2292008995 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 5367117862 ps |
| CPU time | 670.16 seconds |
| Started | Aug 09 08:35:59 PM PDT 24 |
| Finished | Aug 09 08:47:10 PM PDT 24 |
| Peak memory | 642060 kb |
| Host | smart-c4dabf43-441c-4baf-ba75-f834b085adf9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2292008995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2292008995 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3904238043 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 3421779288 ps |
| CPU time | 286.43 seconds |
| Started | Aug 09 08:44:56 PM PDT 24 |
| Finished | Aug 09 08:49:42 PM PDT 24 |
| Peak memory | 609092 kb |
| Host | smart-8d3d3250-be09-4bc2-8e59-751753a58d00 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904238043 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.3904238043 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.426550950 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 3750742462 ps |
| CPU time | 533.29 seconds |
| Started | Aug 09 08:37:03 PM PDT 24 |
| Finished | Aug 09 08:45:57 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-a470792a-f131-4f40-a636-1598e9083401 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426550950 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rstmgr_sw_req.426550950 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3344706539 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 3010718078 ps |
| CPU time | 321.04 seconds |
| Started | Aug 09 08:39:38 PM PDT 24 |
| Finished | Aug 09 08:45:00 PM PDT 24 |
| Peak memory | 609128 kb |
| Host | smart-02020f65-9463-433d-8ad9-2391a2f5f0e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344706539 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3344706539 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3548851742 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 3016907490 ps |
| CPU time | 313.86 seconds |
| Started | Aug 09 08:43:21 PM PDT 24 |
| Finished | Aug 09 08:48:35 PM PDT 24 |
| Peak memory | 608508 kb |
| Host | smart-8cb95a96-635e-46a9-af15-c006f655d5f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3548851742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.3548851742 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.550219476 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2609090858 ps |
| CPU time | 270.05 seconds |
| Started | Aug 09 08:42:23 PM PDT 24 |
| Finished | Aug 09 08:46:53 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-28be423a-8dac-4f5d-93fb-54d1bc4b459e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550219476 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.550219476 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4034024199 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 4714611918 ps |
| CPU time | 752.18 seconds |
| Started | Aug 09 08:39:38 PM PDT 24 |
| Finished | Aug 09 08:52:10 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-5f9ce9b2-f4d0-4550-a7b1-c6b209b6a911 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40340 24199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.4034024199 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2389883132 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 5564605784 ps |
| CPU time | 922.62 seconds |
| Started | Aug 09 08:40:12 PM PDT 24 |
| Finished | Aug 09 08:55:35 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-9ff33c80-8e1e-4cec-b9ad-0438af6529eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2389883132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.2389883132 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3844451269 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 4285616357 ps |
| CPU time | 638.03 seconds |
| Started | Aug 09 08:43:41 PM PDT 24 |
| Finished | Aug 09 08:54:19 PM PDT 24 |
| Peak memory | 624128 kb |
| Host | smart-54a3f1d4-7fda-4e00-8520-5980655971c6 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844451269 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.3844451269 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.797976083 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 6175066694 ps |
| CPU time | 519.77 seconds |
| Started | Aug 09 08:41:42 PM PDT 24 |
| Finished | Aug 09 08:50:22 PM PDT 24 |
| Peak memory | 621280 kb |
| Host | smart-ae20f952-3979-4f09-955d-9bb733e92a99 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797976083 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.797976083 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2664064388 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4384705674 ps |
| CPU time | 408.25 seconds |
| Started | Aug 09 08:43:26 PM PDT 24 |
| Finished | Aug 09 08:50:15 PM PDT 24 |
| Peak memory | 619172 kb |
| Host | smart-b346f567-0173-4dad-8c81-f4701bdeb5a5 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266406 4388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2664064388 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3290902043 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 2555590140 ps |
| CPU time | 275.9 seconds |
| Started | Aug 09 08:44:06 PM PDT 24 |
| Finished | Aug 09 08:48:42 PM PDT 24 |
| Peak memory | 609128 kb |
| Host | smart-39131510-a8af-4bce-a028-d8e7262f586e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290902043 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.3290902043 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.1940999083 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 3204910442 ps |
| CPU time | 209.62 seconds |
| Started | Aug 09 08:39:44 PM PDT 24 |
| Finished | Aug 09 08:43:14 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-86efc1d9-074e-4c4f-87d6-60c5dbf92c92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940999083 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.1940999083 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1784966891 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 3065839616 ps |
| CPU time | 327.23 seconds |
| Started | Aug 09 08:45:26 PM PDT 24 |
| Finished | Aug 09 08:50:54 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-8b9e71ff-33ed-4b20-bde3-838a10db8980 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784966891 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.1784966891 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3126617840 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 9134047200 ps |
| CPU time | 1358.75 seconds |
| Started | Aug 09 08:38:23 PM PDT 24 |
| Finished | Aug 09 09:01:02 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-d5a0f4b8-c126-4758-9ac5-95ecb4aaf6df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126617840 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.3126617840 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3601811819 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 7837477500 ps |
| CPU time | 581.84 seconds |
| Started | Aug 09 08:42:37 PM PDT 24 |
| Finished | Aug 09 08:52:19 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-299feebb-2cfa-4388-b885-1779423411a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601811819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.3601811819 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1838977808 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 7634389800 ps |
| CPU time | 608.51 seconds |
| Started | Aug 09 08:47:28 PM PDT 24 |
| Finished | Aug 09 08:57:37 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-20e15c39-717c-46fd-9021-5f8a3e83412a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838977808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.1838977808 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3386090471 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 6001839400 ps |
| CPU time | 651.61 seconds |
| Started | Aug 09 08:36:41 PM PDT 24 |
| Finished | Aug 09 08:47:33 PM PDT 24 |
| Peak memory | 624708 kb |
| Host | smart-1c5fd4d8-d1b0-4efa-945f-9594730fd40d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386090471 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3386090471 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2955166605 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 5002427237 ps |
| CPU time | 602.35 seconds |
| Started | Aug 09 08:36:04 PM PDT 24 |
| Finished | Aug 09 08:46:06 PM PDT 24 |
| Peak memory | 624636 kb |
| Host | smart-be6a2a10-61e5-4a33-b252-65327bbe2dd5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955166605 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.2955166605 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3851795393 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3623407597 ps |
| CPU time | 323.55 seconds |
| Started | Aug 09 08:37:19 PM PDT 24 |
| Finished | Aug 09 08:42:43 PM PDT 24 |
| Peak memory | 618904 kb |
| Host | smart-a150c0e5-69e7-44a0-8c13-f25df64e06a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851795393 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.3851795393 |
| Directory | /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.1205423792 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3506447064 ps |
| CPU time | 353.12 seconds |
| Started | Aug 09 08:36:21 PM PDT 24 |
| Finished | Aug 09 08:42:14 PM PDT 24 |
| Peak memory | 619400 kb |
| Host | smart-b1398956-5875-41c8-bae9-20f140e05c63 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205423792 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.1205423792 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.359962641 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 8065425976 ps |
| CPU time | 1041.25 seconds |
| Started | Aug 09 08:40:22 PM PDT 24 |
| Finished | Aug 09 08:57:44 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-6386c225-d9ac-4d61-b9bf-bdedb84e6639 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359962641 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.359962641 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.943380463 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 5798018130 ps |
| CPU time | 785.46 seconds |
| Started | Aug 09 08:41:18 PM PDT 24 |
| Finished | Aug 09 08:54:24 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-46aea0cd-6a8b-470f-b520-72a237a02f24 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943380463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ sram_ctrl_scrambled_access.943380463 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1794953970 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 5049314270 ps |
| CPU time | 531.13 seconds |
| Started | Aug 09 08:40:59 PM PDT 24 |
| Finished | Aug 09 08:49:51 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-fa712995-0fa4-4747-b4b6-010c7d67bfa8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794953970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1794953970 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2385910036 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 4628867965 ps |
| CPU time | 499.49 seconds |
| Started | Aug 09 08:43:48 PM PDT 24 |
| Finished | Aug 09 08:52:07 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-c68c2bc9-5165-4f32-84b5-6f5b00dda41b |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385910036 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2385910036 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1036783390 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3205933792 ps |
| CPU time | 374.45 seconds |
| Started | Aug 09 08:47:22 PM PDT 24 |
| Finished | Aug 09 08:53:36 PM PDT 24 |
| Peak memory | 609536 kb |
| Host | smart-0e506e55-00f7-4cc4-a0d2-371baa5b2ec0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036783390 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.1036783390 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3927745925 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 20056864645 ps |
| CPU time | 3548.32 seconds |
| Started | Aug 09 08:38:24 PM PDT 24 |
| Finished | Aug 09 09:37:33 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-ff411a3b-5ff6-4df6-8cf2-e549137de8c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927745925 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3927745925 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3133535784 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4500201576 ps |
| CPU time | 696.44 seconds |
| Started | Aug 09 08:41:35 PM PDT 24 |
| Finished | Aug 09 08:53:13 PM PDT 24 |
| Peak memory | 613588 kb |
| Host | smart-c6504136-4a6b-48ce-ab33-49033b0beb3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133535784 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.3133535784 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1766669059 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2922624785 ps |
| CPU time | 303.76 seconds |
| Started | Aug 09 08:41:40 PM PDT 24 |
| Finished | Aug 09 08:46:44 PM PDT 24 |
| Peak memory | 612984 kb |
| Host | smart-6cbe84ad-a7ba-4e44-96f2-870adb82d4e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766669059 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.1766669059 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3934368578 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3896545640 ps |
| CPU time | 326.73 seconds |
| Started | Aug 09 08:38:25 PM PDT 24 |
| Finished | Aug 09 08:43:53 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-439973a4-764a-464c-8d8f-1ce67379f9fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934368578 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.3934368578 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2544414273 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6587603136 ps |
| CPU time | 570.32 seconds |
| Started | Aug 09 08:40:17 PM PDT 24 |
| Finished | Aug 09 08:49:48 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-1f30f3df-3066-44d5-b9cc-5e84d37db2db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544414273 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2544414273 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1519902334 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 3925024180 ps |
| CPU time | 564.03 seconds |
| Started | Aug 09 08:35:52 PM PDT 24 |
| Finished | Aug 09 08:45:16 PM PDT 24 |
| Peak memory | 624328 kb |
| Host | smart-2ba2e2c8-09b7-4d23-af99-3aebeec7d0ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1519902334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.1519902334 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.1602908806 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2729792120 ps |
| CPU time | 280.53 seconds |
| Started | Aug 09 08:47:45 PM PDT 24 |
| Finished | Aug 09 08:52:26 PM PDT 24 |
| Peak memory | 614780 kb |
| Host | smart-65f4702f-f2aa-4316-9832-62c5ed64a694 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602908806 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.1602908806 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.494390840 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 4565061090 ps |
| CPU time | 713.05 seconds |
| Started | Aug 09 08:38:00 PM PDT 24 |
| Finished | Aug 09 08:49:54 PM PDT 24 |
| Peak memory | 623732 kb |
| Host | smart-13dc74eb-d154-4bed-b903-bbb921e43802 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494390840 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.494390840 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3588018166 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 13526033616 ps |
| CPU time | 2748.64 seconds |
| Started | Aug 09 08:36:55 PM PDT 24 |
| Finished | Aug 09 09:22:44 PM PDT 24 |
| Peak memory | 623344 kb |
| Host | smart-d85b6776-547e-4003-9720-25f1ce25bb85 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588018166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.3588018166 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3264868429 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 3912607200 ps |
| CPU time | 395.53 seconds |
| Started | Aug 09 08:37:33 PM PDT 24 |
| Finished | Aug 09 08:44:10 PM PDT 24 |
| Peak memory | 623640 kb |
| Host | smart-6f8302d6-3c61-42df-9a72-f634763f6fa1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264868429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3264868429 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2979855007 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 4655761088 ps |
| CPU time | 601.27 seconds |
| Started | Aug 09 08:38:03 PM PDT 24 |
| Finished | Aug 09 08:48:05 PM PDT 24 |
| Peak memory | 623980 kb |
| Host | smart-ad7443ec-62d5-4016-8e0d-c1c28d2939ad |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979855007 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2979855007 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3382306084 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4557919888 ps |
| CPU time | 818.78 seconds |
| Started | Aug 09 08:37:19 PM PDT 24 |
| Finished | Aug 09 08:50:58 PM PDT 24 |
| Peak memory | 624012 kb |
| Host | smart-b02dc5b0-e3d4-4ad1-bced-f7210855517c |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382306084 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3382306084 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3288514132 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 4436404668 ps |
| CPU time | 634.24 seconds |
| Started | Aug 09 08:36:17 PM PDT 24 |
| Finished | Aug 09 08:46:52 PM PDT 24 |
| Peak memory | 623844 kb |
| Host | smart-09695c6a-6580-4193-bddf-c6b4d4dc04c4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288514132 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.3288514132 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.837823780 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4518672991 ps |
| CPU time | 252.63 seconds |
| Started | Aug 09 08:40:52 PM PDT 24 |
| Finished | Aug 09 08:45:04 PM PDT 24 |
| Peak memory | 624036 kb |
| Host | smart-384c9496-2ab2-4d4c-a413-a8c21204ba62 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=837823780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.837823780 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.2522940616 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 13523278971 ps |
| CPU time | 1440.33 seconds |
| Started | Aug 09 08:41:57 PM PDT 24 |
| Finished | Aug 09 09:05:58 PM PDT 24 |
| Peak memory | 624372 kb |
| Host | smart-5023bfba-abd0-4836-91af-97c076729c8c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522940616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.2522940616 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.4085058992 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 3213313487 ps |
| CPU time | 209.17 seconds |
| Started | Aug 09 08:42:08 PM PDT 24 |
| Finished | Aug 09 08:45:37 PM PDT 24 |
| Peak memory | 620928 kb |
| Host | smart-73c25a5d-b79c-459d-8e0d-4ee9e1f23b70 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085058992 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.4085058992 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.1551747146 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3304941132 ps |
| CPU time | 241.74 seconds |
| Started | Aug 09 08:42:15 PM PDT 24 |
| Finished | Aug 09 08:46:17 PM PDT 24 |
| Peak memory | 624680 kb |
| Host | smart-ace44e9c-90bf-4d3a-a26a-10c4a2c03641 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551747146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.1551747146 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.1459886553 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 15130011437 ps |
| CPU time | 3736.23 seconds |
| Started | Aug 09 08:49:37 PM PDT 24 |
| Finished | Aug 09 09:51:54 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-c9358c50-fc17-40ac-b454-604490efe3f8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459886553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.1459886553 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.373789407 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 16214239905 ps |
| CPU time | 4289.38 seconds |
| Started | Aug 09 08:48:28 PM PDT 24 |
| Finished | Aug 09 09:59:58 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-bcc3acc1-45ff-4067-ab4b-da041cf4fc0d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373789407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.373789407 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.114627987 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 16090593099 ps |
| CPU time | 3281.21 seconds |
| Started | Aug 09 08:47:49 PM PDT 24 |
| Finished | Aug 09 09:42:31 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-8abf9e9f-b2a0-4484-9f69-ec696ac208f4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114627987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.rom_e2e_asm_init_prod_end.114627987 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.867741031 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 14258575304 ps |
| CPU time | 2767.24 seconds |
| Started | Aug 09 08:47:41 PM PDT 24 |
| Finished | Aug 09 09:33:49 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-ea0114a2-9c0c-440b-8630-c727602b8cc5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867741031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_rma.867741031 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1781211974 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 11338513426 ps |
| CPU time | 3097.78 seconds |
| Started | Aug 09 08:52:05 PM PDT 24 |
| Finished | Aug 09 09:43:44 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-9ece0ed2-ab03-46de-8290-a1041c919799 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781211974 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.1781211974 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.320504310 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 15299564078 ps |
| CPU time | 4287.8 seconds |
| Started | Aug 09 08:53:00 PM PDT 24 |
| Finished | Aug 09 10:04:29 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-d629490b-0343-43c8-8287-d52eb6ab32d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320504310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.320504310 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1950620892 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14499720768 ps |
| CPU time | 3318.47 seconds |
| Started | Aug 09 08:49:42 PM PDT 24 |
| Finished | Aug 09 09:45:01 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-9f78070f-b92b-4a54-9137-33c0d27a1a89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950620892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.1950620892 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1961971121 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 14286810784 ps |
| CPU time | 3230.17 seconds |
| Started | Aug 09 08:49:39 PM PDT 24 |
| Finished | Aug 09 09:43:29 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-32e7e8cc-0c24-4c15-9a87-b2f03e33e662 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961971121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.1961971121 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.3920272808 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 26642936352 ps |
| CPU time | 5596.51 seconds |
| Started | Aug 09 08:49:02 PM PDT 24 |
| Finished | Aug 09 10:22:19 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-f3de9d4e-ff16-4d1a-9434-415b98a43c1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920272808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.3920272808 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2937111303 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 14810848912 ps |
| CPU time | 2961.57 seconds |
| Started | Aug 09 08:52:39 PM PDT 24 |
| Finished | Aug 09 09:42:01 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-30e9e71f-719c-4bb0-a1a2-104382df8d90 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937111303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.2937111303 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.3873303032 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 23982032018 ps |
| CPU time | 3050.4 seconds |
| Started | Aug 09 08:47:25 PM PDT 24 |
| Finished | Aug 09 09:38:16 PM PDT 24 |
| Peak memory | 611652 kb |
| Host | smart-6ba17833-6575-487f-b6f3-88c6a55162dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873303032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.3873303032 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.741068787 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 14502121698 ps |
| CPU time | 3072.61 seconds |
| Started | Aug 09 08:50:41 PM PDT 24 |
| Finished | Aug 09 09:41:55 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-86e8e76b-c6e1-45a6-a619-8900bc648ef6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=741068787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.741068787 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.3806560650 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 17572989966 ps |
| CPU time | 4065.93 seconds |
| Started | Aug 09 08:53:03 PM PDT 24 |
| Finished | Aug 09 10:00:50 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-5515dace-9e9a-4967-802e-56f9392cc7bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806560650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.3806560650 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.2440194505 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 5513712940 ps |
| CPU time | 737.45 seconds |
| Started | Aug 09 08:43:32 PM PDT 24 |
| Finished | Aug 09 08:55:50 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-6cf750ee-9d20-488e-ad74-c01344554f97 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440194505 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2440194505 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.3418353761 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 5838634042 ps |
| CPU time | 272.94 seconds |
| Started | Aug 09 08:45:35 PM PDT 24 |
| Finished | Aug 09 08:50:08 PM PDT 24 |
| Peak memory | 619688 kb |
| Host | smart-2240ffb5-34dd-4fde-8dd4-c910516332fc |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3418353761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.3418353761 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.3834814327 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 2273181186 ps |
| CPU time | 113.49 seconds |
| Started | Aug 09 08:44:56 PM PDT 24 |
| Finished | Aug 09 08:46:50 PM PDT 24 |
| Peak memory | 616960 kb |
| Host | smart-8da3c4a1-8e8d-4c0e-8e5f-fa2e590f3fd9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834814327 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.3834814327 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.819767050 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 6182359950 ps |
| CPU time | 736.92 seconds |
| Started | Aug 09 08:50:48 PM PDT 24 |
| Finished | Aug 09 09:03:05 PM PDT 24 |
| Peak memory | 650200 kb |
| Host | smart-ee5ea76c-30ea-4444-ade2-a0b5792a73dc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 819767050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.819767050 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.439741117 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 5354856730 ps |
| CPU time | 586.5 seconds |
| Started | Aug 09 08:49:55 PM PDT 24 |
| Finished | Aug 09 08:59:42 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-19798a5b-a291-4b8e-ba89-e66d87ee6dad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 439741117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.439741117 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2717042702 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 4198432250 ps |
| CPU time | 386.96 seconds |
| Started | Aug 09 08:50:38 PM PDT 24 |
| Finished | Aug 09 08:57:05 PM PDT 24 |
| Peak memory | 648872 kb |
| Host | smart-eddc6d87-7892-4866-b9ac-ac75597709bc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717042702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2717042702 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3359217058 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4353499982 ps |
| CPU time | 363.95 seconds |
| Started | Aug 09 08:50:52 PM PDT 24 |
| Finished | Aug 09 08:56:56 PM PDT 24 |
| Peak memory | 649348 kb |
| Host | smart-583c9346-3144-44ed-819b-22f58a1459e0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359217058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3359217058 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2914353275 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 3662644828 ps |
| CPU time | 407.51 seconds |
| Started | Aug 09 08:50:36 PM PDT 24 |
| Finished | Aug 09 08:57:24 PM PDT 24 |
| Peak memory | 648972 kb |
| Host | smart-dd3e375d-bc72-417e-8f52-dca27eb25b00 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914353275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2914353275 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.2648970717 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 6076681040 ps |
| CPU time | 691.5 seconds |
| Started | Aug 09 08:50:04 PM PDT 24 |
| Finished | Aug 09 09:01:36 PM PDT 24 |
| Peak memory | 619452 kb |
| Host | smart-a9d83b3a-b7c2-40a1-be2f-f52e95b10a9e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2648970717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.2648970717 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3259727916 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3591311996 ps |
| CPU time | 378.71 seconds |
| Started | Aug 09 08:45:24 PM PDT 24 |
| Finished | Aug 09 08:51:43 PM PDT 24 |
| Peak memory | 649012 kb |
| Host | smart-88d90d6a-ec0f-49ed-9cd4-d119a10ec07c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259727916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.3259727916 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2246937630 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 7867186688 ps |
| CPU time | 460.13 seconds |
| Started | Aug 09 08:45:19 PM PDT 24 |
| Finished | Aug 09 08:52:59 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-83960308-e7a7-4d69-bb9e-cd49ea32b628 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2246937630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2246937630 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.292340301 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 22286553500 ps |
| CPU time | 4434.99 seconds |
| Started | Aug 09 08:46:35 PM PDT 24 |
| Finished | Aug 09 10:00:31 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-d34ec784-3eb9-4b97-9ea6-e3ffc61f537e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292340301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.292340301 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2971208870 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 7008206664 ps |
| CPU time | 600.93 seconds |
| Started | Aug 09 08:47:43 PM PDT 24 |
| Finished | Aug 09 08:57:44 PM PDT 24 |
| Peak memory | 622296 kb |
| Host | smart-21ab1fe1-a32e-4f9b-bdec-1639fe42d90f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971208870 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.2971208870 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3701123038 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 4807791210 ps |
| CPU time | 491.42 seconds |
| Started | Aug 09 08:45:23 PM PDT 24 |
| Finished | Aug 09 08:53:34 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-158be355-5f0a-4b61-bb17-c6fda545a8e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37011230 38 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3701123038 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.82512480 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 3371862200 ps |
| CPU time | 697.88 seconds |
| Started | Aug 09 08:46:18 PM PDT 24 |
| Finished | Aug 09 08:57:57 PM PDT 24 |
| Peak memory | 624368 kb |
| Host | smart-48400db9-8472-4c56-b998-c2385c4a13e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=82512480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.82512480 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.896441267 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 4197027832 ps |
| CPU time | 558.32 seconds |
| Started | Aug 09 08:44:53 PM PDT 24 |
| Finished | Aug 09 08:54:12 PM PDT 24 |
| Peak memory | 623696 kb |
| Host | smart-bb2514c4-9b21-486c-93a3-658b0f4ed0b3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896441267 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.896441267 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2118768337 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 13897610234 ps |
| CPU time | 2526.76 seconds |
| Started | Aug 09 08:47:48 PM PDT 24 |
| Finished | Aug 09 09:29:56 PM PDT 24 |
| Peak memory | 624528 kb |
| Host | smart-7cd08290-2156-48fa-ad08-a416ecfc2f90 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118768337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.2118768337 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3999765050 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 8458570725 ps |
| CPU time | 833.24 seconds |
| Started | Aug 09 08:45:59 PM PDT 24 |
| Finished | Aug 09 08:59:52 PM PDT 24 |
| Peak memory | 618680 kb |
| Host | smart-2ea6648c-49b1-4cdc-881f-919a7d0f5579 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999765050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3999765050 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3870101567 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 4736321956 ps |
| CPU time | 581.1 seconds |
| Started | Aug 09 08:46:13 PM PDT 24 |
| Finished | Aug 09 08:55:54 PM PDT 24 |
| Peak memory | 623968 kb |
| Host | smart-39d3aeb7-181d-4731-bb86-8b59179bf0ec |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870101567 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.3870101567 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1857347240 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 3766353640 ps |
| CPU time | 552.76 seconds |
| Started | Aug 09 08:46:19 PM PDT 24 |
| Finished | Aug 09 08:55:32 PM PDT 24 |
| Peak memory | 623680 kb |
| Host | smart-1b7e44f3-5420-4702-a548-122f2fc26c18 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857347240 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.1857347240 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1727561874 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 3982203624 ps |
| CPU time | 643 seconds |
| Started | Aug 09 08:45:23 PM PDT 24 |
| Finished | Aug 09 08:56:07 PM PDT 24 |
| Peak memory | 623664 kb |
| Host | smart-c2535b49-9c6e-4d81-ac0d-0fcf085e2043 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727561874 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.1727561874 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.3998832330 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3059721877 ps |
| CPU time | 176.13 seconds |
| Started | Aug 09 08:45:21 PM PDT 24 |
| Finished | Aug 09 08:48:18 PM PDT 24 |
| Peak memory | 620788 kb |
| Host | smart-6db3c600-8324-458f-b4a1-15694a899ca3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3998832330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.3998832330 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3934635711 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 2684254399 ps |
| CPU time | 156.14 seconds |
| Started | Aug 09 08:46:01 PM PDT 24 |
| Finished | Aug 09 08:48:37 PM PDT 24 |
| Peak memory | 623176 kb |
| Host | smart-9b709730-f1df-4934-9983-f3207f98379c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934635711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3934635711 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.1610644604 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2967142306 ps |
| CPU time | 180.59 seconds |
| Started | Aug 09 08:45:24 PM PDT 24 |
| Finished | Aug 09 08:48:25 PM PDT 24 |
| Peak memory | 623392 kb |
| Host | smart-e6e02c27-d793-4e3d-be53-89aecc413a3e |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610644604 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1610644604 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.3136262457 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 5057218843 ps |
| CPU time | 440.41 seconds |
| Started | Aug 09 08:45:46 PM PDT 24 |
| Finished | Aug 09 08:53:07 PM PDT 24 |
| Peak memory | 632984 kb |
| Host | smart-7ac31586-716f-410c-b7ff-fce30e925a31 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3136262457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.3136262457 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935184732 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 4092673986 ps |
| CPU time | 412.21 seconds |
| Started | Aug 09 08:51:12 PM PDT 24 |
| Finished | Aug 09 08:58:05 PM PDT 24 |
| Peak memory | 648864 kb |
| Host | smart-600fb1b5-be38-4af3-81e1-d8d44ce9b8a1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935184732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1935184732 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1460520469 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 3372654122 ps |
| CPU time | 345.68 seconds |
| Started | Aug 09 08:52:51 PM PDT 24 |
| Finished | Aug 09 08:58:37 PM PDT 24 |
| Peak memory | 648932 kb |
| Host | smart-f07fe608-bed0-4b17-847d-17de92c4f4a5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460520469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1460520469 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.3420234272 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 6175267992 ps |
| CPU time | 679.08 seconds |
| Started | Aug 09 08:50:27 PM PDT 24 |
| Finished | Aug 09 09:01:46 PM PDT 24 |
| Peak memory | 650496 kb |
| Host | smart-6644d1dc-4f6f-4df7-91de-620b2eac389e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3420234272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.3420234272 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.4266001159 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 3573624474 ps |
| CPU time | 411.44 seconds |
| Started | Aug 09 08:51:51 PM PDT 24 |
| Finished | Aug 09 08:58:42 PM PDT 24 |
| Peak memory | 649188 kb |
| Host | smart-c00abeff-f538-4f62-ba73-e853050e6481 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266001159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4266001159 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.32140138 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 5532865730 ps |
| CPU time | 602.03 seconds |
| Started | Aug 09 08:49:34 PM PDT 24 |
| Finished | Aug 09 08:59:36 PM PDT 24 |
| Peak memory | 616752 kb |
| Host | smart-17ec39b7-45a8-4d5b-bb72-aa6adc0384bd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 32140138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.32140138 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2380634062 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3682463666 ps |
| CPU time | 417.73 seconds |
| Started | Aug 09 08:51:06 PM PDT 24 |
| Finished | Aug 09 08:58:04 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-7ac06bcc-fa8b-404e-9292-ce47d585fda7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380634062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2380634062 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.2353932367 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4843543016 ps |
| CPU time | 452.76 seconds |
| Started | Aug 09 08:50:10 PM PDT 24 |
| Finished | Aug 09 08:57:43 PM PDT 24 |
| Peak memory | 650396 kb |
| Host | smart-8b253aa1-dd4d-4f01-91a4-ee9ca05522c3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2353932367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2353932367 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.936481247 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 4987919334 ps |
| CPU time | 903.78 seconds |
| Started | Aug 09 08:51:13 PM PDT 24 |
| Finished | Aug 09 09:06:17 PM PDT 24 |
| Peak memory | 649888 kb |
| Host | smart-e44b8ac9-1177-4a5a-8bd0-95f0e7201d81 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 936481247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.936481247 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.1139339075 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 5913217400 ps |
| CPU time | 438.1 seconds |
| Started | Aug 09 08:51:09 PM PDT 24 |
| Finished | Aug 09 08:58:27 PM PDT 24 |
| Peak memory | 650244 kb |
| Host | smart-c910538d-a0f3-40c1-a83a-b88ddd919beb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1139339075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.1139339075 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3642736523 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 3286237840 ps |
| CPU time | 443.41 seconds |
| Started | Aug 09 08:52:56 PM PDT 24 |
| Finished | Aug 09 09:00:21 PM PDT 24 |
| Peak memory | 648612 kb |
| Host | smart-8d55fdb5-9b67-4348-b890-f80d222cba31 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642736523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3642736523 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.1829087212 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 5835737740 ps |
| CPU time | 591.94 seconds |
| Started | Aug 09 08:51:36 PM PDT 24 |
| Finished | Aug 09 09:01:28 PM PDT 24 |
| Peak memory | 649868 kb |
| Host | smart-ac222397-81eb-4904-9607-3f4cb8109b0d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1829087212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1829087212 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2224150877 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3904449454 ps |
| CPU time | 377.45 seconds |
| Started | Aug 09 08:52:10 PM PDT 24 |
| Finished | Aug 09 08:58:27 PM PDT 24 |
| Peak memory | 648668 kb |
| Host | smart-438ba86b-a375-4ae5-b2f6-ef89562241bb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224150877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2224150877 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.551858888 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 5084833720 ps |
| CPU time | 672.22 seconds |
| Started | Aug 09 08:53:31 PM PDT 24 |
| Finished | Aug 09 09:04:43 PM PDT 24 |
| Peak memory | 649852 kb |
| Host | smart-f75edaed-97d3-4579-8274-8cff39d17db4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 551858888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.551858888 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.2008282425 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 4214775776 ps |
| CPU time | 648.21 seconds |
| Started | Aug 09 08:52:25 PM PDT 24 |
| Finished | Aug 09 09:03:14 PM PDT 24 |
| Peak memory | 649788 kb |
| Host | smart-f5fc6106-cb87-4855-96f1-cea8d8bd5b59 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2008282425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2008282425 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3398888983 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 7786614860 ps |
| CPU time | 607.59 seconds |
| Started | Aug 09 08:46:44 PM PDT 24 |
| Finished | Aug 09 08:56:52 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-9207d9af-9940-4f77-b4c3-a45a3cf9e2c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3398888983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3398888983 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3992970535 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 19223719890 ps |
| CPU time | 5371.73 seconds |
| Started | Aug 09 08:46:29 PM PDT 24 |
| Finished | Aug 09 10:16:02 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-027fb944-f65a-441e-96ea-7080c96d33e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992970535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.3992970535 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1818761779 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 5488337000 ps |
| CPU time | 722.59 seconds |
| Started | Aug 09 08:48:07 PM PDT 24 |
| Finished | Aug 09 09:00:10 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-546964f2-c54d-40bd-a6e0-5eeebd77d3f6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1818761779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.1818761779 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1335735952 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 10584549487 ps |
| CPU time | 842.76 seconds |
| Started | Aug 09 08:46:10 PM PDT 24 |
| Finished | Aug 09 09:00:14 PM PDT 24 |
| Peak memory | 624788 kb |
| Host | smart-eddf09e0-fb91-4ae1-8568-fa6aa63e242b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335735952 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.1335735952 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.701041402 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 4959113440 ps |
| CPU time | 524.78 seconds |
| Started | Aug 09 08:47:01 PM PDT 24 |
| Finished | Aug 09 08:55:46 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-0bcc61c1-5165-49a5-9a4a-e50cb9bc5f46 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70104140 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.701041402 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3024265481 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 9340780124 ps |
| CPU time | 1642.87 seconds |
| Started | Aug 09 08:47:11 PM PDT 24 |
| Finished | Aug 09 09:14:35 PM PDT 24 |
| Peak memory | 624492 kb |
| Host | smart-d6285f05-238b-437c-ae6f-a26b55153469 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3024265481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.3024265481 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.3206260004 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 3958076188 ps |
| CPU time | 503.27 seconds |
| Started | Aug 09 08:46:34 PM PDT 24 |
| Finished | Aug 09 08:54:57 PM PDT 24 |
| Peak memory | 623404 kb |
| Host | smart-220459a6-51bf-4396-aa73-c6b7b0ba13e5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206260004 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.3206260004 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1866069203 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 3699681224 ps |
| CPU time | 516 seconds |
| Started | Aug 09 08:47:15 PM PDT 24 |
| Finished | Aug 09 08:55:52 PM PDT 24 |
| Peak memory | 623432 kb |
| Host | smart-2078d0e1-29d1-48bd-8962-7440aff13c6e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866069203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.1866069203 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2841265440 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 4766728510 ps |
| CPU time | 485.75 seconds |
| Started | Aug 09 08:45:47 PM PDT 24 |
| Finished | Aug 09 08:53:53 PM PDT 24 |
| Peak memory | 623464 kb |
| Host | smart-75e43114-1414-4723-8e01-9b716f7f4a74 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841265440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2841265440 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.543838664 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4942309876 ps |
| CPU time | 713.87 seconds |
| Started | Aug 09 08:51:59 PM PDT 24 |
| Finished | Aug 09 09:03:54 PM PDT 24 |
| Peak memory | 624028 kb |
| Host | smart-99608bc3-f7da-4168-9d27-3135a7135d70 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543838664 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.543838664 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2105528782 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 3704764820 ps |
| CPU time | 655.16 seconds |
| Started | Aug 09 08:48:12 PM PDT 24 |
| Finished | Aug 09 08:59:09 PM PDT 24 |
| Peak memory | 622096 kb |
| Host | smart-421cb685-3e91-448d-9803-2d6dda6b8745 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105528782 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.2105528782 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.678481797 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 11359981438 ps |
| CPU time | 1091.12 seconds |
| Started | Aug 09 08:46:26 PM PDT 24 |
| Finished | Aug 09 09:04:37 PM PDT 24 |
| Peak memory | 624648 kb |
| Host | smart-329ec2cc-9be1-4865-ad1a-f97c158b3708 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=678481797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.678481797 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.32452210 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 2321177074 ps |
| CPU time | 191.52 seconds |
| Started | Aug 09 08:47:12 PM PDT 24 |
| Finished | Aug 09 08:50:24 PM PDT 24 |
| Peak memory | 623540 kb |
| Host | smart-7593b00a-0931-468a-803b-dcccb6adadd2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.32452210 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.1364690547 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2393012706 ps |
| CPU time | 124.94 seconds |
| Started | Aug 09 08:47:02 PM PDT 24 |
| Finished | Aug 09 08:49:08 PM PDT 24 |
| Peak memory | 622240 kb |
| Host | smart-68a8b84d-013d-4beb-be25-1568d6d7e390 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364690547 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.1364690547 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.26485081 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 4677327338 ps |
| CPU time | 485.91 seconds |
| Started | Aug 09 08:46:04 PM PDT 24 |
| Finished | Aug 09 08:54:10 PM PDT 24 |
| Peak memory | 632692 kb |
| Host | smart-4428ac1e-82a4-4421-8d31-0c59cb6fc8a8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26485081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.26485081 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3118395590 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 3145436112 ps |
| CPU time | 295.49 seconds |
| Started | Aug 09 08:52:10 PM PDT 24 |
| Finished | Aug 09 08:57:06 PM PDT 24 |
| Peak memory | 648892 kb |
| Host | smart-d65d303c-c31c-4e59-b4e6-f6c5c55a32a8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118395590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3118395590 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.1176042266 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 5527669280 ps |
| CPU time | 589.48 seconds |
| Started | Aug 09 08:52:08 PM PDT 24 |
| Finished | Aug 09 09:01:58 PM PDT 24 |
| Peak memory | 650100 kb |
| Host | smart-ad42dedf-6306-4cdd-8949-7ea5528bdda5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1176042266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.1176042266 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.4008133501 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3837129148 ps |
| CPU time | 332.48 seconds |
| Started | Aug 09 08:52:19 PM PDT 24 |
| Finished | Aug 09 08:57:52 PM PDT 24 |
| Peak memory | 649208 kb |
| Host | smart-8c472831-f2fd-4826-ba20-14a35f3ac380 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008133501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4008133501 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.2695912272 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 6116116016 ps |
| CPU time | 680.57 seconds |
| Started | Aug 09 08:52:45 PM PDT 24 |
| Finished | Aug 09 09:04:06 PM PDT 24 |
| Peak memory | 649972 kb |
| Host | smart-474e2b8e-f32d-42c0-b203-23e7de89a31c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2695912272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.2695912272 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626270406 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 3669618190 ps |
| CPU time | 448.2 seconds |
| Started | Aug 09 08:51:40 PM PDT 24 |
| Finished | Aug 09 08:59:08 PM PDT 24 |
| Peak memory | 648636 kb |
| Host | smart-e187f8f9-6266-4b89-af1b-1ce03b995130 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626270406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2626270406 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.652786893 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3546972920 ps |
| CPU time | 334.87 seconds |
| Started | Aug 09 08:53:04 PM PDT 24 |
| Finished | Aug 09 08:58:39 PM PDT 24 |
| Peak memory | 645856 kb |
| Host | smart-2982a2d3-998b-4eba-a9fc-6f8abad0c406 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652786893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_s w_alert_handler_lpg_sleep_mode_alerts.652786893 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.2924011541 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 4180397820 ps |
| CPU time | 508.78 seconds |
| Started | Aug 09 08:51:53 PM PDT 24 |
| Finished | Aug 09 09:00:22 PM PDT 24 |
| Peak memory | 649816 kb |
| Host | smart-07bd7d94-7bc1-416d-8d04-a6022ed4d286 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2924011541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2924011541 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.1946260502 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 5625379768 ps |
| CPU time | 558.68 seconds |
| Started | Aug 09 08:52:07 PM PDT 24 |
| Finished | Aug 09 09:01:26 PM PDT 24 |
| Peak memory | 619560 kb |
| Host | smart-6b05bdb7-2f00-40ff-9eb5-a1b8fc81d502 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1946260502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.1946260502 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3100266518 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4053722726 ps |
| CPU time | 390.52 seconds |
| Started | Aug 09 08:48:08 PM PDT 24 |
| Finished | Aug 09 08:54:38 PM PDT 24 |
| Peak memory | 649112 kb |
| Host | smart-e44dbb8f-2bf5-40cf-b2c1-357b8ea01463 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100266518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.3100266518 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.4023019116 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 23978761400 ps |
| CPU time | 5150.55 seconds |
| Started | Aug 09 08:46:55 PM PDT 24 |
| Finished | Aug 09 10:12:47 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-db278bb1-a790-4145-83aa-77e9a3320b7d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023019116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.4023019116 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.950606127 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 5131666900 ps |
| CPU time | 783.24 seconds |
| Started | Aug 09 08:46:54 PM PDT 24 |
| Finished | Aug 09 08:59:57 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-2204adad-b389-4fa9-9cd3-f9d8054dc990 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=950606127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.950606127 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1993340057 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 12279945722 ps |
| CPU time | 741.6 seconds |
| Started | Aug 09 08:47:01 PM PDT 24 |
| Finished | Aug 09 08:59:23 PM PDT 24 |
| Peak memory | 624596 kb |
| Host | smart-f196f4dd-8a4c-4d13-8ec8-30594a236a94 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993340057 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1993340057 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.945198309 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3995256670 ps |
| CPU time | 630.28 seconds |
| Started | Aug 09 08:46:41 PM PDT 24 |
| Finished | Aug 09 08:57:11 PM PDT 24 |
| Peak memory | 622368 kb |
| Host | smart-50b43a20-b91c-427f-bcf7-a53840e845a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=945198309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.945198309 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.3125742600 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 5597414800 ps |
| CPU time | 588.58 seconds |
| Started | Aug 09 08:51:52 PM PDT 24 |
| Finished | Aug 09 09:01:41 PM PDT 24 |
| Peak memory | 650184 kb |
| Host | smart-6acb05ac-7d0a-4ee4-b514-f52b10d879e7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3125742600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3125742600 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.1984501864 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 6085646900 ps |
| CPU time | 764.82 seconds |
| Started | Aug 09 08:52:59 PM PDT 24 |
| Finished | Aug 09 09:05:44 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-3a3dbf11-8182-457c-b783-0f66140dc6d4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1984501864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1984501864 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1615782101 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3111114674 ps |
| CPU time | 355.79 seconds |
| Started | Aug 09 08:52:37 PM PDT 24 |
| Finished | Aug 09 08:58:33 PM PDT 24 |
| Peak memory | 649232 kb |
| Host | smart-cc3aa3e0-3e6d-4f9b-95e8-ea47eb655020 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615782101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1615782101 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2973468361 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4199942520 ps |
| CPU time | 414.55 seconds |
| Started | Aug 09 08:53:58 PM PDT 24 |
| Finished | Aug 09 09:00:53 PM PDT 24 |
| Peak memory | 649328 kb |
| Host | smart-c6227e5d-0e4f-4178-93e9-109a1f4fca09 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973468361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2973468361 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.3799673003 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 5504168048 ps |
| CPU time | 697.01 seconds |
| Started | Aug 09 08:55:42 PM PDT 24 |
| Finished | Aug 09 09:07:20 PM PDT 24 |
| Peak memory | 649856 kb |
| Host | smart-e31505ac-1156-4789-8be5-15c38a80dfaf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3799673003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.3799673003 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.605163507 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4844831094 ps |
| CPU time | 574.74 seconds |
| Started | Aug 09 08:52:54 PM PDT 24 |
| Finished | Aug 09 09:02:29 PM PDT 24 |
| Peak memory | 650220 kb |
| Host | smart-bb71b4e4-32a4-405b-958c-4be234898606 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 605163507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.605163507 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1336104813 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 3533543324 ps |
| CPU time | 359.38 seconds |
| Started | Aug 09 08:57:13 PM PDT 24 |
| Finished | Aug 09 09:03:12 PM PDT 24 |
| Peak memory | 648844 kb |
| Host | smart-3312aaa1-1fad-4d93-a8c6-289d7c7b01ad |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336104813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1336104813 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3761249464 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3641869310 ps |
| CPU time | 456.83 seconds |
| Started | Aug 09 08:57:21 PM PDT 24 |
| Finished | Aug 09 09:04:58 PM PDT 24 |
| Peak memory | 649412 kb |
| Host | smart-2fdc903b-d103-405e-acb1-c7a1cfdda4df |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761249464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3761249464 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.537757523 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 5470086574 ps |
| CPU time | 628.99 seconds |
| Started | Aug 09 08:54:02 PM PDT 24 |
| Finished | Aug 09 09:04:31 PM PDT 24 |
| Peak memory | 650280 kb |
| Host | smart-06bb16ed-629d-4ec5-bfff-3bf0ad86a74b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 537757523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.537757523 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.106547650 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 3905184584 ps |
| CPU time | 321.81 seconds |
| Started | Aug 09 08:49:14 PM PDT 24 |
| Finished | Aug 09 08:54:36 PM PDT 24 |
| Peak memory | 618800 kb |
| Host | smart-0b18b9ef-e14e-4bb8-9f5f-8ffb65399779 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106547650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.106547650 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.4000663748 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 4679926640 ps |
| CPU time | 383.44 seconds |
| Started | Aug 09 08:48:06 PM PDT 24 |
| Finished | Aug 09 08:54:30 PM PDT 24 |
| Peak memory | 650496 kb |
| Host | smart-ee4c485b-ae94-40f8-b673-1145721334ab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4000663748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.4000663748 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3941080814 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 17666187664 ps |
| CPU time | 4013.57 seconds |
| Started | Aug 09 08:48:42 PM PDT 24 |
| Finished | Aug 09 09:55:36 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-2fef7025-987f-4645-bda6-e1e605430b86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941080814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.3941080814 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1699977835 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 5550413223 ps |
| CPU time | 636.31 seconds |
| Started | Aug 09 08:47:25 PM PDT 24 |
| Finished | Aug 09 08:58:01 PM PDT 24 |
| Peak memory | 622256 kb |
| Host | smart-341bc073-3963-40e6-b82c-0d133d594fc1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699977835 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.1699977835 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1078708530 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 13441164498 ps |
| CPU time | 1926.27 seconds |
| Started | Aug 09 08:47:58 PM PDT 24 |
| Finished | Aug 09 09:20:04 PM PDT 24 |
| Peak memory | 624400 kb |
| Host | smart-e8013315-120b-4dac-bcb7-ede9f61e511e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1078708530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1078708530 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.318778472 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 4077164400 ps |
| CPU time | 425.49 seconds |
| Started | Aug 09 08:54:06 PM PDT 24 |
| Finished | Aug 09 09:01:12 PM PDT 24 |
| Peak memory | 648904 kb |
| Host | smart-1000e67d-56d2-4968-81b3-0af2652670d6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318778472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_s w_alert_handler_lpg_sleep_mode_alerts.318778472 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.1225440430 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 5518372568 ps |
| CPU time | 516.01 seconds |
| Started | Aug 09 08:53:21 PM PDT 24 |
| Finished | Aug 09 09:01:57 PM PDT 24 |
| Peak memory | 650192 kb |
| Host | smart-b178364a-692c-4239-9710-a468a6520fbe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1225440430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.1225440430 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.3409245935 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 4994585064 ps |
| CPU time | 574.48 seconds |
| Started | Aug 09 08:52:42 PM PDT 24 |
| Finished | Aug 09 09:02:17 PM PDT 24 |
| Peak memory | 650204 kb |
| Host | smart-0f18314e-d620-4856-bedc-5320d0af45d2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3409245935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.3409245935 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.1716558141 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 5339267500 ps |
| CPU time | 634.88 seconds |
| Started | Aug 09 08:54:19 PM PDT 24 |
| Finished | Aug 09 09:04:54 PM PDT 24 |
| Peak memory | 650108 kb |
| Host | smart-2831bcc4-0610-4b3a-b8ad-d198b915569c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1716558141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.1716558141 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3681213801 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4326715740 ps |
| CPU time | 506.52 seconds |
| Started | Aug 09 08:54:26 PM PDT 24 |
| Finished | Aug 09 09:02:53 PM PDT 24 |
| Peak memory | 649284 kb |
| Host | smart-23d8d3b9-d176-4c63-9192-6ecd715d89ea |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681213801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3681213801 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.867319434 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 3932560652 ps |
| CPU time | 461.62 seconds |
| Started | Aug 09 08:56:43 PM PDT 24 |
| Finished | Aug 09 09:04:25 PM PDT 24 |
| Peak memory | 648948 kb |
| Host | smart-a291e5bd-36da-45d4-9fdc-c0629961f29a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867319434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_s w_alert_handler_lpg_sleep_mode_alerts.867319434 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.1531954466 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5391283694 ps |
| CPU time | 517.54 seconds |
| Started | Aug 09 08:53:42 PM PDT 24 |
| Finished | Aug 09 09:02:20 PM PDT 24 |
| Peak memory | 650112 kb |
| Host | smart-d80d8cb0-3f54-434e-890f-2cf5225900eb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1531954466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.1531954466 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.409782547 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3621543792 ps |
| CPU time | 407.99 seconds |
| Started | Aug 09 08:55:12 PM PDT 24 |
| Finished | Aug 09 09:02:00 PM PDT 24 |
| Peak memory | 649132 kb |
| Host | smart-e1a0743e-4a89-478c-aa40-e61ce6f96360 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409782547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_s w_alert_handler_lpg_sleep_mode_alerts.409782547 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.1593427098 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 5017601884 ps |
| CPU time | 487.77 seconds |
| Started | Aug 09 08:53:05 PM PDT 24 |
| Finished | Aug 09 09:01:12 PM PDT 24 |
| Peak memory | 649796 kb |
| Host | smart-5a10a245-df57-4318-b054-ac9755f64665 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1593427098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.1593427098 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1820863074 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3943439832 ps |
| CPU time | 420.48 seconds |
| Started | Aug 09 08:53:44 PM PDT 24 |
| Finished | Aug 09 09:00:45 PM PDT 24 |
| Peak memory | 648924 kb |
| Host | smart-bda686c9-be5d-40b5-a52e-5a66df46e7a7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820863074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1820863074 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.3471118045 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 5223549760 ps |
| CPU time | 788.71 seconds |
| Started | Aug 09 08:54:52 PM PDT 24 |
| Finished | Aug 09 09:08:01 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-7fe43e7a-10bf-4197-9f67-8a9078198bb7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3471118045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.3471118045 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2448729272 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4046111582 ps |
| CPU time | 478.11 seconds |
| Started | Aug 09 08:48:41 PM PDT 24 |
| Finished | Aug 09 08:56:39 PM PDT 24 |
| Peak memory | 648880 kb |
| Host | smart-fd63546a-3954-4f26-8fd5-ba8815affa6a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448729272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.2448729272 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.4011393960 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 5120243428 ps |
| CPU time | 473.99 seconds |
| Started | Aug 09 08:47:22 PM PDT 24 |
| Finished | Aug 09 08:55:16 PM PDT 24 |
| Peak memory | 650128 kb |
| Host | smart-146b68b0-2abc-4192-a0d5-eb4fa8cbd0c9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4011393960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.4011393960 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3165480 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 24138018876 ps |
| CPU time | 4779.83 seconds |
| Started | Aug 09 08:48:03 PM PDT 24 |
| Finished | Aug 09 10:07:44 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-48f6051b-905c-47df-8bb1-8fbaade98862 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165480 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.3165480 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3002600784 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 6657347585 ps |
| CPU time | 550.61 seconds |
| Started | Aug 09 08:47:56 PM PDT 24 |
| Finished | Aug 09 08:57:07 PM PDT 24 |
| Peak memory | 624524 kb |
| Host | smart-25b16c4f-5dc6-4c7b-b8e5-e125641adcc3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002600784 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.3002600784 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1183794767 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4094483354 ps |
| CPU time | 609.18 seconds |
| Started | Aug 09 08:47:35 PM PDT 24 |
| Finished | Aug 09 08:57:45 PM PDT 24 |
| Peak memory | 623324 kb |
| Host | smart-d83ec7c6-1a69-4d15-8950-862cd351152c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1183794767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.1183794767 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.3577018454 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 5217848224 ps |
| CPU time | 674.43 seconds |
| Started | Aug 09 08:54:21 PM PDT 24 |
| Finished | Aug 09 09:05:36 PM PDT 24 |
| Peak memory | 650224 kb |
| Host | smart-42bde34c-f69c-41d3-9711-ee17676d22ce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3577018454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.3577018454 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.709855918 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 4309339928 ps |
| CPU time | 328.75 seconds |
| Started | Aug 09 08:55:25 PM PDT 24 |
| Finished | Aug 09 09:00:54 PM PDT 24 |
| Peak memory | 619136 kb |
| Host | smart-13975848-579c-4177-916a-65fe7f889616 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709855918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_s w_alert_handler_lpg_sleep_mode_alerts.709855918 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.2855531336 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 4810665160 ps |
| CPU time | 505.07 seconds |
| Started | Aug 09 08:53:56 PM PDT 24 |
| Finished | Aug 09 09:02:21 PM PDT 24 |
| Peak memory | 650308 kb |
| Host | smart-e7dab043-a52c-4012-9184-11c895c65c6e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2855531336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2855531336 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3242212357 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 3760714824 ps |
| CPU time | 393.34 seconds |
| Started | Aug 09 08:58:49 PM PDT 24 |
| Finished | Aug 09 09:05:22 PM PDT 24 |
| Peak memory | 648696 kb |
| Host | smart-5ca75533-f5ab-4dbd-b062-bca0b0c26c3c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242212357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3242212357 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.2662034211 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 5465483000 ps |
| CPU time | 657.87 seconds |
| Started | Aug 09 08:56:06 PM PDT 24 |
| Finished | Aug 09 09:07:04 PM PDT 24 |
| Peak memory | 649880 kb |
| Host | smart-5decaf05-bf6f-4b56-aab2-c52543633826 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2662034211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.2662034211 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.2305353124 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5541136216 ps |
| CPU time | 694.32 seconds |
| Started | Aug 09 08:55:15 PM PDT 24 |
| Finished | Aug 09 09:06:50 PM PDT 24 |
| Peak memory | 650176 kb |
| Host | smart-71aac6af-f7b0-40df-87d0-a7d79ecf4063 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2305353124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.2305353124 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.1668160168 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 6366425722 ps |
| CPU time | 642.41 seconds |
| Started | Aug 09 08:54:28 PM PDT 24 |
| Finished | Aug 09 09:05:10 PM PDT 24 |
| Peak memory | 620076 kb |
| Host | smart-715e5eb4-8663-46ae-9c7c-cc863d4483bc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1668160168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1668160168 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.4008855245 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 4342909548 ps |
| CPU time | 604.36 seconds |
| Started | Aug 09 08:53:42 PM PDT 24 |
| Finished | Aug 09 09:03:47 PM PDT 24 |
| Peak memory | 650192 kb |
| Host | smart-add5f29b-76d0-437d-9685-a849477aabd4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4008855245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.4008855245 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2054263367 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 4488028512 ps |
| CPU time | 382.46 seconds |
| Started | Aug 09 08:54:35 PM PDT 24 |
| Finished | Aug 09 09:00:57 PM PDT 24 |
| Peak memory | 649320 kb |
| Host | smart-23264a99-8af8-45cb-8bc7-0f39c82e8fac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054263367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2054263367 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.2714816293 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 5381815860 ps |
| CPU time | 689.21 seconds |
| Started | Aug 09 08:56:08 PM PDT 24 |
| Finished | Aug 09 09:07:37 PM PDT 24 |
| Peak memory | 650540 kb |
| Host | smart-e011900d-fe93-4dc6-84ce-124cfa7f4d21 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2714816293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.2714816293 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860910500 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 3573181116 ps |
| CPU time | 383.23 seconds |
| Started | Aug 09 08:54:40 PM PDT 24 |
| Finished | Aug 09 09:01:04 PM PDT 24 |
| Peak memory | 649000 kb |
| Host | smart-be830bd3-fea9-4494-a040-ce9b57e83b74 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860910500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2860910500 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.3730267262 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4230609872 ps |
| CPU time | 520.54 seconds |
| Started | Aug 09 08:54:27 PM PDT 24 |
| Finished | Aug 09 09:03:08 PM PDT 24 |
| Peak memory | 649764 kb |
| Host | smart-d9d5b44d-2e4b-4917-8517-dd810be2fa25 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3730267262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3730267262 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2388805323 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3726442678 ps |
| CPU time | 436.21 seconds |
| Started | Aug 09 08:58:00 PM PDT 24 |
| Finished | Aug 09 09:05:16 PM PDT 24 |
| Peak memory | 648576 kb |
| Host | smart-d1ad998e-d291-4366-a323-97d318860b40 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388805323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2388805323 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.4140683978 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 4968185896 ps |
| CPU time | 572.96 seconds |
| Started | Aug 09 08:54:28 PM PDT 24 |
| Finished | Aug 09 09:04:01 PM PDT 24 |
| Peak memory | 650248 kb |
| Host | smart-26f48415-f58c-4606-9ed2-9637ceb76c05 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4140683978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.4140683978 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3566820264 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4151487842 ps |
| CPU time | 392.21 seconds |
| Started | Aug 09 08:55:00 PM PDT 24 |
| Finished | Aug 09 09:01:32 PM PDT 24 |
| Peak memory | 648880 kb |
| Host | smart-69e355ce-2631-4197-a1f7-00980599d474 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566820264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3566820264 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.3894183808 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 4996260626 ps |
| CPU time | 516.3 seconds |
| Started | Aug 09 08:58:01 PM PDT 24 |
| Finished | Aug 09 09:06:37 PM PDT 24 |
| Peak memory | 650056 kb |
| Host | smart-c4d60184-923b-45ea-8b44-1ceebd77e8b3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3894183808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3894183808 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3962232750 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3847373280 ps |
| CPU time | 382.35 seconds |
| Started | Aug 09 08:48:02 PM PDT 24 |
| Finished | Aug 09 08:54:25 PM PDT 24 |
| Peak memory | 648952 kb |
| Host | smart-84eb1c42-793f-438c-a001-710b99ee820d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962232750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.3962232750 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.1107274705 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 5874721768 ps |
| CPU time | 865.15 seconds |
| Started | Aug 09 08:48:24 PM PDT 24 |
| Finished | Aug 09 09:02:50 PM PDT 24 |
| Peak memory | 649896 kb |
| Host | smart-cb035fc3-1185-4ac1-8be3-e2924f61ef1f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1107274705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.1107274705 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3091895592 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 14412745746 ps |
| CPU time | 3113.51 seconds |
| Started | Aug 09 08:48:57 PM PDT 24 |
| Finished | Aug 09 09:40:51 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-2aa79d65-e915-476b-9c5e-83acdb3c9d4a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091895592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.3091895592 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3248459007 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 9346729858 ps |
| CPU time | 745.9 seconds |
| Started | Aug 09 08:47:30 PM PDT 24 |
| Finished | Aug 09 08:59:57 PM PDT 24 |
| Peak memory | 624700 kb |
| Host | smart-2dc68c89-d4c7-4147-8316-d7a502029864 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248459007 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3248459007 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.945134017 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 8084359812 ps |
| CPU time | 1481.62 seconds |
| Started | Aug 09 08:47:58 PM PDT 24 |
| Finished | Aug 09 09:12:40 PM PDT 24 |
| Peak memory | 623300 kb |
| Host | smart-bb422d47-f537-452f-bd52-34d4edeb6155 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=945134017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.945134017 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.3854963116 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 5764324344 ps |
| CPU time | 496.19 seconds |
| Started | Aug 09 08:58:05 PM PDT 24 |
| Finished | Aug 09 09:06:22 PM PDT 24 |
| Peak memory | 649744 kb |
| Host | smart-ea295d03-e9cf-495f-8b47-23783d8837f1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3854963116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.3854963116 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1046564797 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 3587537734 ps |
| CPU time | 382.37 seconds |
| Started | Aug 09 08:55:13 PM PDT 24 |
| Finished | Aug 09 09:01:35 PM PDT 24 |
| Peak memory | 648940 kb |
| Host | smart-458684d3-5f30-4c06-b661-544ad83321e5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046564797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1046564797 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.2292486281 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 4729306320 ps |
| CPU time | 637.97 seconds |
| Started | Aug 09 08:59:45 PM PDT 24 |
| Finished | Aug 09 09:10:23 PM PDT 24 |
| Peak memory | 619528 kb |
| Host | smart-3ec0f1bb-276e-42fe-8d0a-07c67a285901 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2292486281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.2292486281 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.1717830573 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 5405684928 ps |
| CPU time | 457.01 seconds |
| Started | Aug 09 08:55:35 PM PDT 24 |
| Finished | Aug 09 09:03:13 PM PDT 24 |
| Peak memory | 649872 kb |
| Host | smart-eb61f880-d551-4efe-bbc3-6c8de72d1d9c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1717830573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1717830573 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2799126563 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3887123328 ps |
| CPU time | 334.67 seconds |
| Started | Aug 09 08:56:47 PM PDT 24 |
| Finished | Aug 09 09:02:22 PM PDT 24 |
| Peak memory | 649024 kb |
| Host | smart-f57ca28b-164e-4f69-93c0-f53201cdff26 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799126563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2799126563 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.2693968669 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 4891465888 ps |
| CPU time | 599.11 seconds |
| Started | Aug 09 08:56:40 PM PDT 24 |
| Finished | Aug 09 09:06:40 PM PDT 24 |
| Peak memory | 650492 kb |
| Host | smart-9d44ae1a-4f5d-49b7-8188-cd65d86bfab4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2693968669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.2693968669 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.355136268 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 4800235592 ps |
| CPU time | 697.59 seconds |
| Started | Aug 09 08:55:39 PM PDT 24 |
| Finished | Aug 09 09:07:17 PM PDT 24 |
| Peak memory | 650440 kb |
| Host | smart-1361e55c-b58a-4212-9ff4-893f7ed46f62 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 355136268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.355136268 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1593130807 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 4175578134 ps |
| CPU time | 419.38 seconds |
| Started | Aug 09 08:54:26 PM PDT 24 |
| Finished | Aug 09 09:01:26 PM PDT 24 |
| Peak memory | 648980 kb |
| Host | smart-fa3a7397-6660-426f-ace0-814b154882e5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593130807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1593130807 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.2976708907 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4984731520 ps |
| CPU time | 481.5 seconds |
| Started | Aug 09 08:55:04 PM PDT 24 |
| Finished | Aug 09 09:03:05 PM PDT 24 |
| Peak memory | 650056 kb |
| Host | smart-0f32c2a4-b1ed-451a-a335-2ffe2f85e9e2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2976708907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2976708907 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3033401990 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3097940532 ps |
| CPU time | 342.11 seconds |
| Started | Aug 09 08:57:58 PM PDT 24 |
| Finished | Aug 09 09:03:40 PM PDT 24 |
| Peak memory | 648644 kb |
| Host | smart-38b28935-ea5d-4d84-bd93-802f148d120a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033401990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3033401990 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.526295505 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3641906328 ps |
| CPU time | 461.43 seconds |
| Started | Aug 09 08:55:40 PM PDT 24 |
| Finished | Aug 09 09:03:22 PM PDT 24 |
| Peak memory | 648888 kb |
| Host | smart-b1f7c921-1511-4c00-b946-8dca5b331cff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526295505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.526295505 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.627954133 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 5674734500 ps |
| CPU time | 523.83 seconds |
| Started | Aug 09 08:55:09 PM PDT 24 |
| Finished | Aug 09 09:03:53 PM PDT 24 |
| Peak memory | 649792 kb |
| Host | smart-1017cc8c-4398-494d-8273-fe0d761fb24b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 627954133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.627954133 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3415199370 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3972893020 ps |
| CPU time | 362.25 seconds |
| Started | Aug 09 08:55:24 PM PDT 24 |
| Finished | Aug 09 09:01:26 PM PDT 24 |
| Peak memory | 649108 kb |
| Host | smart-ac8f5c74-8c59-45d9-aaf4-fe1fdd1b0e63 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415199370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3415199370 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1505506959 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 4344857090 ps |
| CPU time | 438.01 seconds |
| Started | Aug 09 08:55:33 PM PDT 24 |
| Finished | Aug 09 09:02:51 PM PDT 24 |
| Peak memory | 649292 kb |
| Host | smart-ca633f0a-36bb-448f-8a2a-561bd4bd4f78 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505506959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1505506959 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.2620809846 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 5192958800 ps |
| CPU time | 506.41 seconds |
| Started | Aug 09 08:56:24 PM PDT 24 |
| Finished | Aug 09 09:04:51 PM PDT 24 |
| Peak memory | 650136 kb |
| Host | smart-ba1a8396-8146-477e-a64c-5e24d7e81382 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2620809846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2620809846 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3025894961 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3524232386 ps |
| CPU time | 340.12 seconds |
| Started | Aug 09 08:47:51 PM PDT 24 |
| Finished | Aug 09 08:53:31 PM PDT 24 |
| Peak memory | 648936 kb |
| Host | smart-1d08d24d-2a69-4051-9add-c34a4a3f7d0b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025894961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.3025894961 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.2873609929 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4792432888 ps |
| CPU time | 655.8 seconds |
| Started | Aug 09 08:47:57 PM PDT 24 |
| Finished | Aug 09 08:58:53 PM PDT 24 |
| Peak memory | 650220 kb |
| Host | smart-eede2d24-539e-4c83-96f7-5ee35f7d0e33 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2873609929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.2873609929 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1342521077 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 10526389499 ps |
| CPU time | 958.91 seconds |
| Started | Aug 09 08:47:33 PM PDT 24 |
| Finished | Aug 09 09:03:33 PM PDT 24 |
| Peak memory | 620996 kb |
| Host | smart-0e919c05-9cab-4dc3-80a2-f0133980d0f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342521077 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.1342521077 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4026449541 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 13390292428 ps |
| CPU time | 2362.31 seconds |
| Started | Aug 09 08:48:50 PM PDT 24 |
| Finished | Aug 09 09:28:14 PM PDT 24 |
| Peak memory | 624492 kb |
| Host | smart-d1c85f15-18e7-4282-a9c0-8cc508838668 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4026449541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.4026449541 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.3990816979 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 5834171448 ps |
| CPU time | 613.54 seconds |
| Started | Aug 09 08:55:16 PM PDT 24 |
| Finished | Aug 09 09:05:30 PM PDT 24 |
| Peak memory | 650120 kb |
| Host | smart-be70517e-3c1a-4176-8c24-b50c97a43efe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3990816979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3990816979 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.1055834507 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 4841586550 ps |
| CPU time | 403.62 seconds |
| Started | Aug 09 08:55:52 PM PDT 24 |
| Finished | Aug 09 09:02:36 PM PDT 24 |
| Peak memory | 651180 kb |
| Host | smart-beae5595-842c-4d27-b048-318f1ed09027 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1055834507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.1055834507 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.1256017343 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 4970834824 ps |
| CPU time | 517.91 seconds |
| Started | Aug 09 08:54:34 PM PDT 24 |
| Finished | Aug 09 09:03:12 PM PDT 24 |
| Peak memory | 650340 kb |
| Host | smart-5185196c-af1c-4add-8933-f954e24828ec |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1256017343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.1256017343 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.3564436666 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 4867711280 ps |
| CPU time | 541.99 seconds |
| Started | Aug 09 08:55:42 PM PDT 24 |
| Finished | Aug 09 09:04:44 PM PDT 24 |
| Peak memory | 650072 kb |
| Host | smart-31d84863-608a-4904-b88d-1920a4e7ae8f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3564436666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.3564436666 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.3471962444 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 5958492920 ps |
| CPU time | 634.43 seconds |
| Started | Aug 09 08:54:41 PM PDT 24 |
| Finished | Aug 09 09:05:16 PM PDT 24 |
| Peak memory | 650240 kb |
| Host | smart-eeb16b41-92a7-44f1-b024-c2ede7c73eef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3471962444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.3471962444 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.58396329 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 6744570970 ps |
| CPU time | 639.48 seconds |
| Started | Aug 09 08:55:07 PM PDT 24 |
| Finished | Aug 09 09:05:46 PM PDT 24 |
| Peak memory | 650160 kb |
| Host | smart-fc58b3ff-0b45-4e2a-8799-b4adfcaa4470 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 58396329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.58396329 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.2217711352 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 6007309776 ps |
| CPU time | 534.79 seconds |
| Started | Aug 09 08:54:42 PM PDT 24 |
| Finished | Aug 09 09:03:37 PM PDT 24 |
| Peak memory | 649768 kb |
| Host | smart-4bc29354-353f-4ba7-9b40-4927b5f491ce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2217711352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2217711352 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.1570229294 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 5866952664 ps |
| CPU time | 538.89 seconds |
| Started | Aug 09 08:55:05 PM PDT 24 |
| Finished | Aug 09 09:04:04 PM PDT 24 |
| Peak memory | 616744 kb |
| Host | smart-0d45cb98-c941-4b5a-a841-caac8a5e2399 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1570229294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.1570229294 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.2367951363 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4219767516 ps |
| CPU time | 518.6 seconds |
| Started | Aug 09 08:55:01 PM PDT 24 |
| Finished | Aug 09 09:03:40 PM PDT 24 |
| Peak memory | 649752 kb |
| Host | smart-7d446e3a-b8da-494d-9532-9266f6d464ca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2367951363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.2367951363 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2552194750 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4188772340 ps |
| CPU time | 154.58 seconds |
| Started | Aug 09 07:57:30 PM PDT 24 |
| Finished | Aug 09 08:00:04 PM PDT 24 |
| Peak memory | 640812 kb |
| Host | smart-aeb6e422-4401-4320-9e2b-7e235707199b |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552194750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.2552194750 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3652435712 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 4296296873 ps |
| CPU time | 201.63 seconds |
| Started | Aug 09 07:57:32 PM PDT 24 |
| Finished | Aug 09 08:00:54 PM PDT 24 |
| Peak memory | 641984 kb |
| Host | smart-794c30fa-bed5-411a-ac13-7f7902f84a61 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652435712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.3652435712 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3141855507 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 5258844045 ps |
| CPU time | 250.58 seconds |
| Started | Aug 09 07:57:28 PM PDT 24 |
| Finished | Aug 09 08:01:38 PM PDT 24 |
| Peak memory | 640820 kb |
| Host | smart-becba005-5765-45c8-b2f7-6e69507ae966 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141855507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.3141855507 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.756915525 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4123780694 ps |
| CPU time | 231.64 seconds |
| Started | Aug 09 07:57:26 PM PDT 24 |
| Finished | Aug 09 08:01:18 PM PDT 24 |
| Peak memory | 654848 kb |
| Host | smart-5a8395c2-e843-4211-a988-2fb61be684f9 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756915525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.756915525 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2595356250 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4790551840 ps |
| CPU time | 260.52 seconds |
| Started | Aug 09 07:57:31 PM PDT 24 |
| Finished | Aug 09 08:01:51 PM PDT 24 |
| Peak memory | 640976 kb |
| Host | smart-2d1d2ead-52d4-4857-a799-c3e64cc7928d |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595356250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.2595356250 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1914711186 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3966143481 ps |
| CPU time | 239.63 seconds |
| Started | Aug 09 07:57:27 PM PDT 24 |
| Finished | Aug 09 08:01:27 PM PDT 24 |
| Peak memory | 655688 kb |
| Host | smart-525ba610-1648-41ff-b4f1-b1f3421dd0ee |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914711186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.1914711186 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1960929871 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 4976513276 ps |
| CPU time | 342.52 seconds |
| Started | Aug 09 07:57:27 PM PDT 24 |
| Finished | Aug 09 08:03:10 PM PDT 24 |
| Peak memory | 657220 kb |
| Host | smart-e4763af1-3fda-4999-b682-79d276fd16f0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960929871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.1960929871 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2678158112 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3823052766 ps |
| CPU time | 227.85 seconds |
| Started | Aug 09 07:57:28 PM PDT 24 |
| Finished | Aug 09 08:01:16 PM PDT 24 |
| Peak memory | 640844 kb |
| Host | smart-c4e67b3e-0167-44fd-96ad-bd9e5446d109 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678158112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.2678158112 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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