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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.09 95.46 93.86 95.44 94.60 97.53 99.61


Total test records in report: 2935
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T1174 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.320748305 Aug 09 08:41:04 PM PDT 24 Aug 09 08:56:26 PM PDT 24 8000588490 ps
T1175 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3178051095 Aug 09 08:49:05 PM PDT 24 Aug 09 08:53:39 PM PDT 24 3636114304 ps
T1176 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.994011949 Aug 09 08:28:35 PM PDT 24 Aug 09 08:39:39 PM PDT 24 6244698510 ps
T1177 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.616147654 Aug 09 08:29:08 PM PDT 24 Aug 09 10:20:08 PM PDT 24 23488545672 ps
T1178 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2980392879 Aug 09 08:32:14 PM PDT 24 Aug 09 08:42:02 PM PDT 24 4038430400 ps
T1179 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3093375080 Aug 09 08:40:29 PM PDT 24 Aug 09 09:07:18 PM PDT 24 6162263904 ps
T1180 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1640312805 Aug 09 08:30:57 PM PDT 24 Aug 09 08:35:05 PM PDT 24 2778637464 ps
T1181 /workspace/coverage/default/0.chip_sw_otbn_smoketest.415932276 Aug 09 08:24:46 PM PDT 24 Aug 09 08:43:55 PM PDT 24 5186919992 ps
T803 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2388805323 Aug 09 08:58:00 PM PDT 24 Aug 09 09:05:16 PM PDT 24 3726442678 ps
T808 /workspace/coverage/default/75.chip_sw_all_escalation_resets.4008855245 Aug 09 08:53:42 PM PDT 24 Aug 09 09:03:47 PM PDT 24 4342909548 ps
T1182 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.768019177 Aug 09 08:27:43 PM PDT 24 Aug 09 09:27:58 PM PDT 24 14220817024 ps
T1183 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.719788206 Aug 09 08:23:33 PM PDT 24 Aug 09 08:32:10 PM PDT 24 5099795804 ps
T1184 /workspace/coverage/default/1.rom_e2e_smoke.2869316878 Aug 09 08:38:51 PM PDT 24 Aug 09 09:49:07 PM PDT 24 14592967352 ps
T343 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3382306084 Aug 09 08:37:19 PM PDT 24 Aug 09 08:50:58 PM PDT 24 4557919888 ps
T1185 /workspace/coverage/default/0.chip_tap_straps_prod.1790680110 Aug 09 08:21:50 PM PDT 24 Aug 09 08:23:55 PM PDT 24 2484724845 ps
T210 /workspace/coverage/default/1.chip_jtag_mem_access.1906352151 Aug 09 08:24:28 PM PDT 24 Aug 09 08:44:52 PM PDT 24 13883461632 ps
T378 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3902811730 Aug 09 08:43:21 PM PDT 24 Aug 09 08:52:22 PM PDT 24 5766819418 ps
T211 /workspace/coverage/default/0.chip_jtag_mem_access.1739497620 Aug 09 08:13:43 PM PDT 24 Aug 09 08:35:41 PM PDT 24 13506491888 ps
T9 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2123558002 Aug 09 08:27:14 PM PDT 24 Aug 09 08:31:46 PM PDT 24 2851775246 ps
T1186 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2100957294 Aug 09 08:39:27 PM PDT 24 Aug 09 09:05:21 PM PDT 24 9232324700 ps
T1187 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3675092064 Aug 09 08:21:58 PM PDT 24 Aug 09 08:27:02 PM PDT 24 2484013648 ps
T280 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1430348907 Aug 09 08:20:49 PM PDT 24 Aug 09 08:34:58 PM PDT 24 4953452480 ps
T1188 /workspace/coverage/default/4.chip_tap_straps_testunlock0.26485081 Aug 09 08:46:04 PM PDT 24 Aug 09 08:54:10 PM PDT 24 4677327338 ps
T1189 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1330259722 Aug 09 08:31:15 PM PDT 24 Aug 09 08:52:06 PM PDT 24 9621456880 ps
T783 /workspace/coverage/default/2.chip_sw_all_escalation_resets.2548942893 Aug 09 08:36:47 PM PDT 24 Aug 09 08:48:25 PM PDT 24 4666764360 ps
T677 /workspace/coverage/default/1.chip_sw_edn_boot_mode.1650344699 Aug 09 08:28:14 PM PDT 24 Aug 09 08:38:44 PM PDT 24 3530307136 ps
T1190 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3242212357 Aug 09 08:58:49 PM PDT 24 Aug 09 09:05:22 PM PDT 24 3760714824 ps
T1191 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1817325777 Aug 09 08:22:01 PM PDT 24 Aug 09 08:32:59 PM PDT 24 6811237860 ps
T1192 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3398888983 Aug 09 08:46:44 PM PDT 24 Aug 09 08:56:52 PM PDT 24 7786614860 ps
T1193 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1492820236 Aug 09 08:26:43 PM PDT 24 Aug 09 08:36:31 PM PDT 24 4322178900 ps
T1194 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3927745925 Aug 09 08:38:24 PM PDT 24 Aug 09 09:37:33 PM PDT 24 20056864645 ps
T1195 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2792319767 Aug 09 08:35:11 PM PDT 24 Aug 09 08:38:19 PM PDT 24 2535766860 ps
T768 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2717042702 Aug 09 08:50:38 PM PDT 24 Aug 09 08:57:05 PM PDT 24 4198432250 ps
T1196 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1605554682 Aug 09 08:24:27 PM PDT 24 Aug 09 08:45:13 PM PDT 24 7965861250 ps
T1197 /workspace/coverage/default/38.chip_sw_all_escalation_resets.1829087212 Aug 09 08:51:36 PM PDT 24 Aug 09 09:01:28 PM PDT 24 5835737740 ps
T1198 /workspace/coverage/default/2.chip_sw_csrng_smoketest.4014699158 Aug 09 08:45:13 PM PDT 24 Aug 09 08:48:25 PM PDT 24 2670953774 ps
T1199 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2157009545 Aug 09 08:31:40 PM PDT 24 Aug 09 08:43:45 PM PDT 24 8604158212 ps
T356 /workspace/coverage/default/1.chip_sw_pattgen_ios.115578629 Aug 09 08:25:41 PM PDT 24 Aug 09 08:29:47 PM PDT 24 2766663296 ps
T168 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3926043285 Aug 09 08:26:19 PM PDT 24 Aug 09 08:28:16 PM PDT 24 2269226539 ps
T429 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1994743480 Aug 09 08:22:54 PM PDT 24 Aug 09 08:30:12 PM PDT 24 6826406292 ps
T1200 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1899702753 Aug 09 08:28:49 PM PDT 24 Aug 09 08:39:32 PM PDT 24 4610514894 ps
T1201 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2566495596 Aug 09 08:39:15 PM PDT 24 Aug 09 08:48:15 PM PDT 24 5375746576 ps
T766 /workspace/coverage/default/9.chip_sw_all_escalation_resets.2873609929 Aug 09 08:47:57 PM PDT 24 Aug 09 08:58:53 PM PDT 24 4792432888 ps
T1202 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.677103575 Aug 09 08:26:13 PM PDT 24 Aug 09 09:58:00 PM PDT 24 48243026674 ps
T1203 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2720553618 Aug 09 08:22:07 PM PDT 24 Aug 09 08:25:09 PM PDT 24 3163947662 ps
T1204 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3641454876 Aug 09 08:41:22 PM PDT 24 Aug 09 08:46:52 PM PDT 24 4139101728 ps
T1205 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.315863861 Aug 09 08:20:19 PM PDT 24 Aug 09 08:30:52 PM PDT 24 4769983992 ps
T1206 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1857347240 Aug 09 08:46:19 PM PDT 24 Aug 09 08:55:32 PM PDT 24 3766353640 ps
T1207 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4026449541 Aug 09 08:48:50 PM PDT 24 Aug 09 09:28:14 PM PDT 24 13390292428 ps
T1208 /workspace/coverage/default/0.rom_e2e_asm_init_rma.1447021917 Aug 09 08:29:58 PM PDT 24 Aug 09 09:33:17 PM PDT 24 14262526920 ps
T1209 /workspace/coverage/default/0.chip_sw_uart_tx_rx.1268878851 Aug 09 08:19:44 PM PDT 24 Aug 09 08:29:41 PM PDT 24 4255147440 ps
T1210 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.942392930 Aug 09 08:27:49 PM PDT 24 Aug 09 08:47:02 PM PDT 24 7479816920 ps
T163 /workspace/coverage/default/2.chip_plic_all_irqs_10.4155299496 Aug 09 08:42:34 PM PDT 24 Aug 09 08:53:44 PM PDT 24 3574437396 ps
T1211 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3264868429 Aug 09 08:37:33 PM PDT 24 Aug 09 08:44:10 PM PDT 24 3912607200 ps
T1212 /workspace/coverage/default/1.chip_sw_aes_idle.3185589768 Aug 09 08:26:00 PM PDT 24 Aug 09 08:30:41 PM PDT 24 2656702648 ps
T1213 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1779801929 Aug 09 08:21:38 PM PDT 24 Aug 09 08:27:19 PM PDT 24 3153608420 ps
T1214 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2879495666 Aug 09 08:32:48 PM PDT 24 Aug 09 08:43:03 PM PDT 24 7127994952 ps
T1215 /workspace/coverage/default/12.chip_sw_all_escalation_resets.1152666848 Aug 09 08:50:59 PM PDT 24 Aug 09 08:59:40 PM PDT 24 5815690208 ps
T206 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.4059484166 Aug 09 08:21:04 PM PDT 24 Aug 09 08:30:17 PM PDT 24 5616897966 ps
T1216 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1336703685 Aug 09 08:38:51 PM PDT 24 Aug 09 09:32:38 PM PDT 24 15076344380 ps
T788 /workspace/coverage/default/25.chip_sw_all_escalation_resets.355537548 Aug 09 08:50:00 PM PDT 24 Aug 09 08:58:17 PM PDT 24 5226782352 ps
T1217 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3011900336 Aug 09 08:23:49 PM PDT 24 Aug 09 08:49:57 PM PDT 24 7579720440 ps
T1218 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.212805450 Aug 09 08:25:31 PM PDT 24 Aug 09 08:34:47 PM PDT 24 8062082140 ps
T1219 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1592204783 Aug 09 08:20:27 PM PDT 24 Aug 09 08:26:04 PM PDT 24 3016700716 ps
T1220 /workspace/coverage/default/1.chip_tap_straps_prod.1658950822 Aug 09 08:34:40 PM PDT 24 Aug 09 08:37:44 PM PDT 24 2977437606 ps
T1221 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1453030700 Aug 09 08:22:31 PM PDT 24 Aug 09 08:33:02 PM PDT 24 5120644555 ps
T1222 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1593130807 Aug 09 08:54:26 PM PDT 24 Aug 09 09:01:26 PM PDT 24 4175578134 ps
T1223 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3754694588 Aug 09 08:44:55 PM PDT 24 Aug 09 08:52:16 PM PDT 24 7169585840 ps
T1224 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3870101567 Aug 09 08:46:13 PM PDT 24 Aug 09 08:55:54 PM PDT 24 4736321956 ps
T1225 /workspace/coverage/default/1.chip_sw_power_idle_load.3314648731 Aug 09 08:33:55 PM PDT 24 Aug 09 08:44:14 PM PDT 24 4629877896 ps
T1226 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3563753035 Aug 09 08:40:15 PM PDT 24 Aug 09 09:30:17 PM PDT 24 10899372734 ps
T700 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1824505061 Aug 09 08:27:50 PM PDT 24 Aug 09 08:32:23 PM PDT 24 2927248720 ps
T1227 /workspace/coverage/default/4.chip_sw_uart_tx_rx.3206260004 Aug 09 08:46:34 PM PDT 24 Aug 09 08:54:57 PM PDT 24 3958076188 ps
T1228 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.300382999 Aug 09 08:39:19 PM PDT 24 Aug 09 08:46:00 PM PDT 24 3500812277 ps
T790 /workspace/coverage/default/61.chip_sw_all_escalation_resets.1225440430 Aug 09 08:53:21 PM PDT 24 Aug 09 09:01:57 PM PDT 24 5518372568 ps
T368 /workspace/coverage/default/1.chip_sw_hmac_enc.77856835 Aug 09 08:31:32 PM PDT 24 Aug 09 08:35:35 PM PDT 24 2799304016 ps
T1229 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.268305871 Aug 09 08:30:26 PM PDT 24 Aug 09 09:32:55 PM PDT 24 15180609929 ps
T1230 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.654597615 Aug 09 08:21:07 PM PDT 24 Aug 09 08:29:18 PM PDT 24 6244654388 ps
T1231 /workspace/coverage/default/2.rom_volatile_raw_unlock.3834814327 Aug 09 08:44:56 PM PDT 24 Aug 09 08:46:50 PM PDT 24 2273181186 ps
T1232 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2621263209 Aug 09 08:48:29 PM PDT 24 Aug 09 08:58:22 PM PDT 24 5978747092 ps
T1233 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1065971946 Aug 09 08:26:21 PM PDT 24 Aug 09 09:49:39 PM PDT 24 47829925312 ps
T1234 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3700528529 Aug 09 08:29:56 PM PDT 24 Aug 09 09:17:30 PM PDT 24 10686880122 ps
T1235 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2971208870 Aug 09 08:47:43 PM PDT 24 Aug 09 08:57:44 PM PDT 24 7008206664 ps
T780 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3574766774 Aug 09 08:52:08 PM PDT 24 Aug 09 08:57:25 PM PDT 24 3724260222 ps
T1236 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3140900763 Aug 09 08:31:43 PM PDT 24 Aug 09 09:36:17 PM PDT 24 14585084074 ps
T1237 /workspace/coverage/default/2.chip_sw_kmac_smoketest.3117599549 Aug 09 08:47:25 PM PDT 24 Aug 09 08:51:51 PM PDT 24 3063929160 ps
T817 /workspace/coverage/default/7.chip_sw_all_escalation_resets.4011393960 Aug 09 08:47:22 PM PDT 24 Aug 09 08:55:16 PM PDT 24 5120243428 ps
T1238 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3544537538 Aug 09 08:30:15 PM PDT 24 Aug 09 08:40:53 PM PDT 24 6144072763 ps
T687 /workspace/coverage/default/0.chip_tap_straps_dev.4233956898 Aug 09 08:21:31 PM PDT 24 Aug 09 08:32:51 PM PDT 24 6020443102 ps
T1239 /workspace/coverage/default/2.chip_sw_aes_smoketest.3983406862 Aug 09 08:44:44 PM PDT 24 Aug 09 08:49:30 PM PDT 24 3060038654 ps
T249 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1051678115 Aug 09 08:37:56 PM PDT 24 Aug 09 08:47:53 PM PDT 24 5680494014 ps
T1240 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2324568619 Aug 09 08:24:47 PM PDT 24 Aug 09 08:29:36 PM PDT 24 4703209042 ps
T1241 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2079370890 Aug 09 08:23:30 PM PDT 24 Aug 09 08:27:53 PM PDT 24 2653815148 ps
T1242 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1500213333 Aug 09 08:29:00 PM PDT 24 Aug 09 09:24:29 PM PDT 24 11486619666 ps
T268 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3698018861 Aug 09 08:22:19 PM PDT 24 Aug 09 08:33:18 PM PDT 24 6251316540 ps
T207 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2955166605 Aug 09 08:36:04 PM PDT 24 Aug 09 08:46:06 PM PDT 24 5002427237 ps
T1243 /workspace/coverage/default/1.chip_sw_uart_smoketest.2688294562 Aug 09 08:38:53 PM PDT 24 Aug 09 08:46:09 PM PDT 24 3007486696 ps
T1244 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1355728839 Aug 09 08:36:21 PM PDT 24 Aug 09 08:43:05 PM PDT 24 5528005080 ps
T1245 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1598964091 Aug 09 08:37:41 PM PDT 24 Aug 10 12:00:17 AM PDT 24 65043384958 ps
T753 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.4266001159 Aug 09 08:51:51 PM PDT 24 Aug 09 08:58:42 PM PDT 24 3573624474 ps
T1246 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.4123407374 Aug 09 08:19:09 PM PDT 24 Aug 09 08:36:15 PM PDT 24 7884521910 ps
T1247 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.4094197797 Aug 09 08:20:22 PM PDT 24 Aug 09 08:51:10 PM PDT 24 9429591160 ps
T1248 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1993340057 Aug 09 08:47:01 PM PDT 24 Aug 09 08:59:23 PM PDT 24 12279945722 ps
T34 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1506047631 Aug 09 08:28:11 PM PDT 24 Aug 09 08:37:11 PM PDT 24 4607636320 ps
T1249 /workspace/coverage/default/0.chip_sw_otbn_randomness.75260020 Aug 09 08:25:11 PM PDT 24 Aug 09 08:39:13 PM PDT 24 6282014270 ps
T1250 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3320424940 Aug 09 08:21:41 PM PDT 24 Aug 09 08:29:02 PM PDT 24 19292176792 ps
T1251 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2632598233 Aug 09 08:39:56 PM PDT 24 Aug 09 09:02:55 PM PDT 24 9169121232 ps
T54 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3895283866 Aug 09 08:25:50 PM PDT 24 Aug 09 08:30:18 PM PDT 24 3764947836 ps
T1252 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1382192435 Aug 09 08:21:00 PM PDT 24 Aug 09 08:34:01 PM PDT 24 4949810360 ps
T1253 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3290902043 Aug 09 08:44:06 PM PDT 24 Aug 09 08:48:42 PM PDT 24 2555590140 ps
T337 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3377127880 Aug 09 08:37:52 PM PDT 24 Aug 09 09:03:34 PM PDT 24 12840009640 ps
T1254 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3690603344 Aug 09 08:37:06 PM PDT 24 Aug 09 08:44:07 PM PDT 24 3561356040 ps
T1255 /workspace/coverage/default/1.chip_sw_hmac_multistream.778428998 Aug 09 08:30:15 PM PDT 24 Aug 09 08:59:25 PM PDT 24 7264186512 ps
T1256 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1460520469 Aug 09 08:52:51 PM PDT 24 Aug 09 08:58:37 PM PDT 24 3372654122 ps
T1257 /workspace/coverage/default/0.chip_sw_csrng_kat_test.4210237757 Aug 09 08:21:04 PM PDT 24 Aug 09 08:26:22 PM PDT 24 3040708660 ps
T1258 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1122105813 Aug 09 08:40:04 PM PDT 24 Aug 09 09:51:24 PM PDT 24 15920510580 ps
T747 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3003197443 Aug 09 08:52:32 PM PDT 24 Aug 09 08:59:26 PM PDT 24 3155647974 ps
T1259 /workspace/coverage/default/0.chip_sw_aes_smoketest.337988125 Aug 09 08:26:05 PM PDT 24 Aug 09 08:30:47 PM PDT 24 2738566400 ps
T1260 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3100490601 Aug 09 08:37:01 PM PDT 24 Aug 09 08:45:07 PM PDT 24 4198057330 ps
T746 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3033401990 Aug 09 08:57:58 PM PDT 24 Aug 09 09:03:40 PM PDT 24 3097940532 ps
T1261 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.731015711 Aug 09 08:25:35 PM PDT 24 Aug 09 08:32:01 PM PDT 24 4945788072 ps
T1262 /workspace/coverage/default/4.chip_sw_all_escalation_resets.2008282425 Aug 09 08:52:25 PM PDT 24 Aug 09 09:03:14 PM PDT 24 4214775776 ps
T1263 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3068016093 Aug 09 08:25:34 PM PDT 24 Aug 09 09:04:40 PM PDT 24 22525721827 ps
T1264 /workspace/coverage/default/80.chip_sw_all_escalation_resets.3854963116 Aug 09 08:58:05 PM PDT 24 Aug 09 09:06:22 PM PDT 24 5764324344 ps
T1265 /workspace/coverage/default/62.chip_sw_all_escalation_resets.3409245935 Aug 09 08:52:42 PM PDT 24 Aug 09 09:02:17 PM PDT 24 4994585064 ps
T306 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.359962641 Aug 09 08:40:22 PM PDT 24 Aug 09 08:57:44 PM PDT 24 8065425976 ps
T1266 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1345218226 Aug 09 08:28:11 PM PDT 24 Aug 09 08:40:15 PM PDT 24 5077615779 ps
T1267 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.144080836 Aug 09 08:36:54 PM PDT 24 Aug 09 08:39:52 PM PDT 24 2491421644 ps
T1268 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3049175688 Aug 09 08:26:59 PM PDT 24 Aug 09 08:30:56 PM PDT 24 2479458856 ps
T1269 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3128400307 Aug 09 08:29:46 PM PDT 24 Aug 09 08:39:46 PM PDT 24 5742546190 ps
T1270 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3389136834 Aug 09 08:39:44 PM PDT 24 Aug 09 08:44:29 PM PDT 24 2769710560 ps
T1271 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2678105975 Aug 09 08:41:52 PM PDT 24 Aug 09 08:52:23 PM PDT 24 3944728924 ps
T1272 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.4191200240 Aug 09 08:24:37 PM PDT 24 Aug 09 08:48:23 PM PDT 24 8391431368 ps
T1273 /workspace/coverage/default/1.rom_keymgr_functest.2221485391 Aug 09 08:37:56 PM PDT 24 Aug 09 08:45:48 PM PDT 24 5356225324 ps
T349 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3027353257 Aug 09 08:23:35 PM PDT 24 Aug 09 08:31:01 PM PDT 24 3395116050 ps
T1274 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3429101806 Aug 09 08:38:43 PM PDT 24 Aug 09 08:48:22 PM PDT 24 5454371686 ps
T1275 /workspace/coverage/default/0.chip_sw_power_sleep_load.1072384437 Aug 09 08:22:59 PM PDT 24 Aug 09 08:34:00 PM PDT 24 11763942568 ps
T1276 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.868894117 Aug 09 08:30:15 PM PDT 24 Aug 09 09:16:59 PM PDT 24 35942286152 ps
T773 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2914353275 Aug 09 08:50:36 PM PDT 24 Aug 09 08:57:24 PM PDT 24 3662644828 ps
T1277 /workspace/coverage/default/1.chip_sw_hmac_smoketest.4264101087 Aug 09 08:37:53 PM PDT 24 Aug 09 08:44:39 PM PDT 24 3224822248 ps
T1278 /workspace/coverage/default/2.chip_sw_aes_masking_off.1901099724 Aug 09 08:39:49 PM PDT 24 Aug 09 08:46:08 PM PDT 24 3280287037 ps
T1279 /workspace/coverage/default/0.chip_sw_flash_init.741592645 Aug 09 08:20:22 PM PDT 24 Aug 09 09:01:56 PM PDT 24 25331406086 ps
T1280 /workspace/coverage/default/1.chip_tap_straps_rma.108485088 Aug 09 08:32:08 PM PDT 24 Aug 09 08:34:38 PM PDT 24 3217991391 ps
T1281 /workspace/coverage/default/2.rom_e2e_asm_init_dev.1459886553 Aug 09 08:49:37 PM PDT 24 Aug 09 09:51:54 PM PDT 24 15130011437 ps
T67 /workspace/coverage/default/3.chip_tap_straps_rma.1610644604 Aug 09 08:45:24 PM PDT 24 Aug 09 08:48:25 PM PDT 24 2967142306 ps
T443 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2599467177 Aug 09 08:28:10 PM PDT 24 Aug 09 09:19:10 PM PDT 24 23900835376 ps
T1282 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2107789814 Aug 09 08:19:20 PM PDT 24 Aug 09 08:34:49 PM PDT 24 5604491984 ps
T269 /workspace/coverage/default/6.chip_sw_all_escalation_resets.4000663748 Aug 09 08:48:06 PM PDT 24 Aug 09 08:54:30 PM PDT 24 4679926640 ps
T778 /workspace/coverage/default/41.chip_sw_all_escalation_resets.1176042266 Aug 09 08:52:08 PM PDT 24 Aug 09 09:01:58 PM PDT 24 5527669280 ps
T1283 /workspace/coverage/default/1.chip_sw_uart_tx_rx.794945835 Aug 09 08:25:03 PM PDT 24 Aug 09 08:37:08 PM PDT 24 4708203800 ps
T1284 /workspace/coverage/default/2.chip_sw_aes_idle.2384518842 Aug 09 08:40:48 PM PDT 24 Aug 09 08:44:38 PM PDT 24 2801063436 ps
T1285 /workspace/coverage/default/0.rom_keymgr_functest.2382623702 Aug 09 08:23:09 PM PDT 24 Aug 09 08:32:47 PM PDT 24 5173871448 ps
T1286 /workspace/coverage/default/1.rom_raw_unlock.1533966450 Aug 09 08:37:05 PM PDT 24 Aug 09 08:40:40 PM PDT 24 4339834345 ps
T770 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1172245340 Aug 09 08:49:57 PM PDT 24 Aug 09 08:55:41 PM PDT 24 4122318056 ps
T818 /workspace/coverage/default/32.chip_sw_all_escalation_resets.1927914172 Aug 09 08:50:04 PM PDT 24 Aug 09 08:59:02 PM PDT 24 5414057228 ps
T1287 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1533769160 Aug 09 08:21:23 PM PDT 24 Aug 09 08:37:29 PM PDT 24 8069993244 ps
T1288 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.964908134 Aug 09 08:45:04 PM PDT 24 Aug 09 08:49:15 PM PDT 24 3314037557 ps
T259 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3909661413 Aug 09 08:42:59 PM PDT 24 Aug 09 08:47:26 PM PDT 24 2245768600 ps
T1289 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2036701069 Aug 09 08:44:14 PM PDT 24 Aug 09 09:41:00 PM PDT 24 21746592440 ps
T1290 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3229426096 Aug 09 08:22:16 PM PDT 24 Aug 09 08:25:13 PM PDT 24 3345581367 ps
T1291 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.403430651 Aug 09 08:26:16 PM PDT 24 Aug 09 08:36:42 PM PDT 24 6946607028 ps
T1292 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2979855007 Aug 09 08:38:03 PM PDT 24 Aug 09 08:48:05 PM PDT 24 4655761088 ps
T146 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1796302067 Aug 09 08:43:02 PM PDT 24 Aug 09 09:36:02 PM PDT 24 25068693499 ps
T1293 /workspace/coverage/default/14.chip_sw_all_escalation_resets.4208472753 Aug 09 08:49:40 PM PDT 24 Aug 09 09:01:01 PM PDT 24 5111971380 ps
T1294 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3348633063 Aug 09 08:24:40 PM PDT 24 Aug 09 08:29:16 PM PDT 24 2821679849 ps
T701 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3503993763 Aug 09 08:40:42 PM PDT 24 Aug 09 08:45:45 PM PDT 24 2734029672 ps
T1295 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2118722903 Aug 09 08:19:43 PM PDT 24 Aug 09 09:32:17 PM PDT 24 36852386226 ps
T147 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.736796653 Aug 09 08:25:57 PM PDT 24 Aug 09 09:34:33 PM PDT 24 25074142232 ps
T1296 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3635634639 Aug 09 08:30:40 PM PDT 24 Aug 09 09:36:09 PM PDT 24 14551987780 ps
T1297 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2943349022 Aug 09 08:50:14 PM PDT 24 Aug 09 09:33:52 PM PDT 24 12949941216 ps
T1298 /workspace/coverage/default/0.rom_e2e_static_critical.1830179140 Aug 09 08:30:19 PM PDT 24 Aug 09 09:41:46 PM PDT 24 16332628062 ps
T1299 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2118768337 Aug 09 08:47:48 PM PDT 24 Aug 09 09:29:56 PM PDT 24 13897610234 ps
T1300 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3268512871 Aug 09 08:47:53 PM PDT 24 Aug 09 08:55:17 PM PDT 24 5359135407 ps
T693 /workspace/coverage/default/52.chip_sw_all_escalation_resets.938891582 Aug 09 08:53:07 PM PDT 24 Aug 09 09:05:55 PM PDT 24 5246692048 ps
T1301 /workspace/coverage/default/11.chip_sw_all_escalation_resets.2769614220 Aug 09 08:48:14 PM PDT 24 Aug 09 08:56:24 PM PDT 24 4283856992 ps
T1302 /workspace/coverage/default/0.rom_e2e_asm_init_prod.4052062382 Aug 09 08:29:29 PM PDT 24 Aug 09 09:39:46 PM PDT 24 15961797156 ps
T1303 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.578908022 Aug 09 08:39:07 PM PDT 24 Aug 09 08:43:35 PM PDT 24 3257456564 ps
T1304 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.58713609 Aug 09 08:31:03 PM PDT 24 Aug 09 09:59:14 PM PDT 24 23853916968 ps
T1305 /workspace/coverage/default/43.chip_sw_all_escalation_resets.591303066 Aug 09 08:51:25 PM PDT 24 Aug 09 09:01:25 PM PDT 24 5464874208 ps
T1306 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1798295674 Aug 09 08:22:08 PM PDT 24 Aug 09 08:51:08 PM PDT 24 20938584380 ps
T1307 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3126617840 Aug 09 08:38:23 PM PDT 24 Aug 09 09:01:02 PM PDT 24 9134047200 ps
T444 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2121331520 Aug 09 08:23:43 PM PDT 24 Aug 09 09:07:48 PM PDT 24 30507505196 ps
T383 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.526295505 Aug 09 08:55:40 PM PDT 24 Aug 09 09:03:22 PM PDT 24 3641906328 ps
T35 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2544414273 Aug 09 08:40:17 PM PDT 24 Aug 09 08:49:48 PM PDT 24 6587603136 ps
T1308 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1903984936 Aug 09 08:42:19 PM PDT 24 Aug 09 10:15:49 PM PDT 24 49843269248 ps
T1309 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1544351371 Aug 09 08:26:39 PM PDT 24 Aug 09 08:42:15 PM PDT 24 8406585155 ps
T1310 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1593831752 Aug 09 08:28:31 PM PDT 24 Aug 09 08:32:47 PM PDT 24 3161286606 ps
T379 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1696522153 Aug 09 08:27:01 PM PDT 24 Aug 09 08:34:18 PM PDT 24 6322453824 ps
T1311 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3248459007 Aug 09 08:47:30 PM PDT 24 Aug 09 08:59:57 PM PDT 24 9346729858 ps
T410 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2649048363 Aug 09 08:29:21 PM PDT 24 Aug 09 08:39:59 PM PDT 24 8847429030 ps
T779 /workspace/coverage/default/28.chip_sw_all_escalation_resets.1676056577 Aug 09 08:54:42 PM PDT 24 Aug 09 09:06:59 PM PDT 24 4483800420 ps
T1312 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.82215978 Aug 09 08:22:37 PM PDT 24 Aug 09 08:59:12 PM PDT 24 24369267333 ps
T1313 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2691695230 Aug 09 08:34:06 PM PDT 24 Aug 09 08:52:54 PM PDT 24 7187702736 ps
T1314 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.860689967 Aug 09 08:34:04 PM PDT 24 Aug 09 08:37:59 PM PDT 24 2426326168 ps
T1315 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1490399814 Aug 09 08:34:18 PM PDT 24 Aug 09 08:38:45 PM PDT 24 2636753982 ps
T1316 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3134604577 Aug 09 08:41:17 PM PDT 24 Aug 09 08:44:21 PM PDT 24 3259446508 ps
T1317 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2385910036 Aug 09 08:43:48 PM PDT 24 Aug 09 08:52:07 PM PDT 24 4628867965 ps
T791 /workspace/coverage/default/87.chip_sw_all_escalation_resets.627954133 Aug 09 08:55:09 PM PDT 24 Aug 09 09:03:53 PM PDT 24 5674734500 ps
T1318 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1379773224 Aug 09 08:23:38 PM PDT 24 Aug 09 08:33:08 PM PDT 24 7719407097 ps
T1319 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.476401075 Aug 09 08:30:11 PM PDT 24 Aug 09 08:42:21 PM PDT 24 7560290002 ps
T1320 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3007260164 Aug 09 08:20:18 PM PDT 24 Aug 09 08:53:31 PM PDT 24 21341794508 ps
T397 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3541704252 Aug 09 08:42:56 PM PDT 24 Aug 09 08:46:26 PM PDT 24 2828370816 ps
T1321 /workspace/coverage/default/98.chip_sw_all_escalation_resets.1570229294 Aug 09 08:55:05 PM PDT 24 Aug 09 09:04:04 PM PDT 24 5866952664 ps
T1322 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2010008404 Aug 09 08:21:49 PM PDT 24 Aug 09 08:36:01 PM PDT 24 8505826552 ps
T1323 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1607991951 Aug 09 08:26:41 PM PDT 24 Aug 09 08:31:26 PM PDT 24 3618333280 ps
T1324 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1599880067 Aug 09 08:25:42 PM PDT 24 Aug 09 08:45:50 PM PDT 24 6680275512 ps
T1325 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3610232901 Aug 09 08:26:47 PM PDT 24 Aug 09 08:42:41 PM PDT 24 9271048793 ps
T1326 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1684521374 Aug 09 08:20:13 PM PDT 24 Aug 09 08:28:48 PM PDT 24 4614695946 ps
T1327 /workspace/coverage/default/0.chip_sw_hmac_enc.1293372623 Aug 09 08:24:45 PM PDT 24 Aug 09 08:30:43 PM PDT 24 3476313744 ps
T73 /workspace/coverage/default/0.chip_sw_usbdev_pullup.1353277126 Aug 09 08:21:10 PM PDT 24 Aug 09 08:26:31 PM PDT 24 3313539680 ps
T296 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935184732 Aug 09 08:51:12 PM PDT 24 Aug 09 08:58:05 PM PDT 24 4092673986 ps
T805 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3990816979 Aug 09 08:55:16 PM PDT 24 Aug 09 09:05:30 PM PDT 24 5834171448 ps
T1328 /workspace/coverage/default/1.rom_e2e_shutdown_output.3213399627 Aug 09 08:38:16 PM PDT 24 Aug 09 09:40:06 PM PDT 24 25573862490 ps
T1329 /workspace/coverage/default/1.chip_sw_edn_kat.3137269784 Aug 09 08:27:44 PM PDT 24 Aug 09 08:37:44 PM PDT 24 3430496100 ps
T334 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.714265855 Aug 09 08:37:00 PM PDT 24 Aug 09 08:48:55 PM PDT 24 3523053448 ps
T1330 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.697112420 Aug 09 08:36:23 PM PDT 24 Aug 09 08:47:11 PM PDT 24 5078700328 ps
T1331 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1173272292 Aug 09 08:24:29 PM PDT 24 Aug 09 08:34:51 PM PDT 24 8206211612 ps
T1332 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1049034887 Aug 09 08:24:44 PM PDT 24 Aug 09 09:09:59 PM PDT 24 32024923626 ps
T820 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2688442455 Aug 09 08:49:31 PM PDT 24 Aug 09 09:00:23 PM PDT 24 5352959192 ps
T336 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3648783113 Aug 09 08:31:25 PM PDT 24 Aug 09 08:58:38 PM PDT 24 10368407448 ps
T1333 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4214928793 Aug 09 08:43:33 PM PDT 24 Aug 09 09:06:52 PM PDT 24 7897935904 ps
T810 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278161563 Aug 09 08:51:39 PM PDT 24 Aug 09 08:56:05 PM PDT 24 3831901208 ps
T1334 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1137813398 Aug 09 08:39:54 PM PDT 24 Aug 09 09:41:20 PM PDT 24 14497663060 ps
T1335 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.709855918 Aug 09 08:55:25 PM PDT 24 Aug 09 09:00:54 PM PDT 24 4309339928 ps
T208 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3758639354 Aug 09 08:24:31 PM PDT 24 Aug 09 08:33:37 PM PDT 24 4325314893 ps
T1336 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3799673003 Aug 09 08:55:42 PM PDT 24 Aug 09 09:07:20 PM PDT 24 5504168048 ps
T297 /workspace/coverage/default/67.chip_sw_all_escalation_resets.302307295 Aug 09 08:54:47 PM PDT 24 Aug 09 09:04:15 PM PDT 24 6350879544 ps
T314 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2353932367 Aug 09 08:50:10 PM PDT 24 Aug 09 08:57:43 PM PDT 24 4843543016 ps
T1337 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2521370733 Aug 09 08:26:38 PM PDT 24 Aug 09 08:52:57 PM PDT 24 7648456652 ps
T384 /workspace/coverage/default/35.chip_sw_all_escalation_resets.936481247 Aug 09 08:51:13 PM PDT 24 Aug 09 09:06:17 PM PDT 24 4987919334 ps
T1338 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2050466168 Aug 09 08:27:17 PM PDT 24 Aug 09 09:29:02 PM PDT 24 15857709842 ps
T774 /workspace/coverage/default/51.chip_sw_all_escalation_resets.3125742600 Aug 09 08:51:52 PM PDT 24 Aug 09 09:01:41 PM PDT 24 5597414800 ps
T380 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.228936508 Aug 09 08:31:33 PM PDT 24 Aug 09 08:38:48 PM PDT 24 5384669926 ps
T806 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.571691882 Aug 09 08:58:04 PM PDT 24 Aug 09 09:03:02 PM PDT 24 3980289050 ps
T10 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3869773043 Aug 09 08:19:00 PM PDT 24 Aug 09 08:22:51 PM PDT 24 2658709512 ps
T1339 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2385766273 Aug 09 08:50:38 PM PDT 24 Aug 09 08:58:16 PM PDT 24 7538182923 ps
T799 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.867319434 Aug 09 08:56:43 PM PDT 24 Aug 09 09:04:25 PM PDT 24 3932560652 ps
T1340 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3904238043 Aug 09 08:44:56 PM PDT 24 Aug 09 08:49:42 PM PDT 24 3421779288 ps
T1341 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2452081068 Aug 09 08:32:05 PM PDT 24 Aug 09 08:46:10 PM PDT 24 8602104328 ps
T1342 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1635945966 Aug 09 08:30:57 PM PDT 24 Aug 09 09:37:50 PM PDT 24 14966219325 ps
T1343 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1114471811 Aug 09 08:25:52 PM PDT 24 Aug 09 08:32:11 PM PDT 24 3464173824 ps
T236 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2443598046 Aug 09 08:22:51 PM PDT 24 Aug 09 09:18:30 PM PDT 24 12523588900 ps
T1344 /workspace/coverage/default/2.chip_sw_rv_timer_irq.1940999083 Aug 09 08:39:44 PM PDT 24 Aug 09 08:43:14 PM PDT 24 3204910442 ps
T1345 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1842792628 Aug 09 08:19:17 PM PDT 24 Aug 09 08:37:57 PM PDT 24 13527387171 ps
T1346 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3655780747 Aug 09 08:47:50 PM PDT 24 Aug 09 08:52:05 PM PDT 24 3933535144 ps
T1347 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2283229559 Aug 09 08:30:44 PM PDT 24 Aug 09 09:32:22 PM PDT 24 15272054648 ps
T345 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.748236824 Aug 09 08:37:44 PM PDT 24 Aug 09 08:50:03 PM PDT 24 4614257588 ps
T1348 /workspace/coverage/default/0.rom_e2e_shutdown_output.2417268381 Aug 09 08:32:59 PM PDT 24 Aug 09 09:29:00 PM PDT 24 28995052540 ps
T139 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.198646831 Aug 09 08:30:48 PM PDT 24 Aug 09 08:41:29 PM PDT 24 5127121048 ps
T812 /workspace/coverage/default/59.chip_sw_all_escalation_resets.537757523 Aug 09 08:54:02 PM PDT 24 Aug 09 09:04:31 PM PDT 24 5470086574 ps
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