Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_edn1.u_edn_core.gen_ep_blk[7].u_prim_packer_fifo

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	0	0
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00



81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         unreachable    assign clr_d = clr_i;
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T2 T3 T4 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T2 T3 T4 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T2 T3 T4 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T2 T3 T4 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo

	Total	Covered	Percent
Conditions	40	36	90.00
Logical	40	36	90.00
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo

	Line No.	Total	Covered	Percent
Branches		14	12	85.71
TERNARY	142	4	3	75.00
TERNARY	147	3	2	66.67
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00



142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3



147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3



151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3



82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo

	Total	Attempted	Percent	Percent
Assertions	2	2	100.00	0.00
Cover properties	0	0
Cover sequences	0	0
Total	2	2	100.00	0.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	491226693	0	0	999
ValidOPairedWithReadyI_A	491226693	0	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	0	0	999

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	0	0	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.93	100.00	90.00			85.71	0.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.93	100.00	90.00			85.71	0.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children