Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	89.27	77.18			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	89.27	77.18			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_target[0].u_target

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Line No.	Total	Covered	Percent
TOTAL		1258	1123	89.27
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	1	1	100.00
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CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ROUTINE	114	0	0
ROUTINE	125	0	0
CONT_ASSIGN	138	0	0
CONT_ASSIGN	139	0	0

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Total	Covered	Percent
Conditions	3313	2557	77.18
Logical	3313	2557	77.18
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
85	64.00
85	65.04
85	60.91
85	58.70
85	57.93
85-90	83.98
90	100.00
90-91	100.00
91	100.00
91-92	100.00
92	100.00

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Line No.	Total	Covered	Percent
Branches		1320	1320	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
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TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
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TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
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TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
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TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T23
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T23
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T23
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T11,T27
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T11,T27
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T11,T27
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T38,T65
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T38,T65
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T38,T65
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T59,T60
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T59,T60
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T59,T60
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T231,T148
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T231,T148
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T231,T148
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T38
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T38
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T38
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T58,T331
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T58,T331
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T58,T331
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T61,T229
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T61,T229
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T61,T229
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T23,T264
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T23,T264
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T23,T264
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T28,T132
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T28,T132
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T28,T132
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T63,T65
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T63,T65
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T63,T65
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T58,T127
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T58,T127
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T58,T127
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T331,T140
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T331,T140
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T331,T140
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T229,T335
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T229,T335
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T229,T335
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T23,T264
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T23,T264
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T23,T264
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T162,T127,T331
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T162,T127,T331
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T162,T127,T331
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T328
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T328
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T328
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T38,T65
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T38,T65
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T38,T65
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T8,T127
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T8,T127
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T8,T127
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T127,T331
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T127,T331
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T127,T331
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T331,T140
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T331,T140
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T331,T140
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T59,T60,T331
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T59,T60,T331
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T59,T60,T331
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T62
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T62
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T62
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T229,T335,T192
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T229,T335,T192
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T229,T335,T192
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T322,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T322,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T322,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T264,T287,T265
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T264,T287,T265
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T264,T287,T265
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T231,T148
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T231,T148
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T231,T148
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T162,T127,T331
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T162,T127,T331
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T162,T127,T331
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T328
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T328
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T328
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T63
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T63
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T63
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T127,T49
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T127,T49
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T127,T49
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T127,T136
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T127,T136
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T127,T136
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T229,T335,T192
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T229,T335,T192
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T229,T335,T192
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T43,T81,T192
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T43,T81,T192
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T43,T81,T192
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T322,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T322,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T322,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T142,T67,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T142,T67,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T142,T67,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T179,T127,T339
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T179,T127,T339
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T179,T127,T339
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T231,T148,T331
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T231,T148,T331
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T231,T148,T331
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T326,T327,T331
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T326,T327,T331
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T326,T327,T331
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T296
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T296
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T296
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T328
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T328
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T328
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T296
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T296
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T322,T296
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T132,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T38,T65,T322
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T331,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T127,T232
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T127,T232
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T127,T232
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T331,T129
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T331,T140
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T331,T140
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T331,T140
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T59,T60,T331
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T59,T60,T331
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T59,T60,T331
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T331,T141
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T127,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T127,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T127,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T229,T335,T192
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T229,T335,T192
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T229,T335,T192
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T337,T338
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T337,T338
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T337,T338
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T322,T329,T330
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T23,T26
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T23,T26
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T23,T26
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T142,T143,T331
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T142,T143,T331
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T142,T143,T331
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T264,T265,T192
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T264,T265,T192
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T264,T265,T192
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T231,T148
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T231,T148
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T231,T148
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T231,T148,T331
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T231,T148,T331
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T231,T148,T331
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T127,T190,T191
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T340,T332
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T331,T332,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxComputationInvalid_A	491226693	489155967	0	0
MaxComputation_A	491226693	1966084	0	0
MaxIndexComputationInvalid_A	491226693	489155967	0	0
MaxIndexComputation_A	491226693	1966084	0	0
NumSources_A	1010	1010	0	0
ValidInImpliesValidOut_A	491226693	491122051	0	0

MaxComputationInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	489155967	0	0
T1	42275	42213	0	0
T2	91152	90862	0	0
T3	115201	113590	0	0
T4	110863	110808	0	0
T5	83840	81752	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	217952	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

MaxComputation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	1966084	0	0
T2	91152	232	0	0
T3	115201	1556	0	0
T4	110863	0	0	0
T5	83840	2037	0	0
T6	116117	0	0	0
T11	0	8348	0	0
T23	75281	199	0	0
T26	0	202	0	0
T27	0	5411	0	0
T28	0	939	0	0
T30	92780	0	0	0
T68	219320	1317	0	0
T104	98538	0	0	0
T105	67890	0	0	0
T264	0	201	0	0

MaxIndexComputationInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	489155967	0	0
T1	42275	42213	0	0
T2	91152	90862	0	0
T3	115201	113590	0	0
T4	110863	110808	0	0
T5	83840	81752	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	217952	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

MaxIndexComputation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	1966084	0	0
T2	91152	232	0	0
T3	115201	1556	0	0
T4	110863	0	0	0
T5	83840	2037	0	0
T6	116117	0	0	0
T11	0	8348	0	0
T23	75281	199	0	0
T26	0	202	0	0
T27	0	5411	0	0
T28	0	939	0	0
T30	92780	0	0	0
T68	219320	1317	0	0
T104	98538	0	0	0
T105	67890	0	0	0
T264	0	201	0	0

NumSources_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

ValidInImpliesValidOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0