ALERT_HANDLER Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: 748235cbb6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.210m	4.899ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.320s	243.622us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.590s	129.652us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.326m	71.232ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.353m	17.106ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.300s	77.333us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.590s	129.652us	20	20	100.00
		alert_handler_csr_aliasing	5.353m	17.106ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.336m	5.678ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.107m	6.942ms	50	50	100.00
V2	entropy	alert_handler_entropy	48.646m	50.532ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	55.120s	774.560us	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.210m	4.899ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.293m	5.161ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.021m	2.184ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.924m	17.630ms	50	50	100.00
V2	lpg	alert_handler_lpg	53.947m	223.641ms	50	50	100.00
		alert_handler_lpg_stub_clk	53.879m	206.925ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.280h	323.628ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.223m	6.631ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.290s	55.976us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.690s	25.073us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	21.740s	1.416ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	21.740s	1.416ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.320s	243.622us	5	5	100.00
		alert_handler_csr_rw	9.590s	129.652us	20	20	100.00
		alert_handler_csr_aliasing	5.353m	17.106ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.550s	2.751ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.320s	243.622us	5	5	100.00
		alert_handler_csr_rw	9.590s	129.652us	20	20	100.00
		alert_handler_csr_aliasing	5.353m	17.106ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.550s	2.751ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.003m	19.236ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.003m	19.236ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.003m	19.236ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.003m	19.236ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.736m	90.335ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.125m	2.683ms	5	5	100.00
		alert_handler_tl_intg_err	1.425m	2.596ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.425m	2.596ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.003m	19.236ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.210m	4.899ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.210m	4.899ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.210m	4.899ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.210m	4.899ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	55.120s	774.560us	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	53.947m	223.641ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	55.120s	774.560us	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	48.646m	50.532ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	48.646m	50.532ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.125m	2.683ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.125m	2.683ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.125m	2.683ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.125m	2.683ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.125m	2.683ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.125m	2.683ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.125m	2.683ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.125m	2.683ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.125m	2.683ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.336h	247.941ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			850	850	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.68	100.00	100.00	100.00	99.38	99.64

Past Results

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