ALERT_HANDLER Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	59.620s	906.498us	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.250s	442.348us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.970s	519.170us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.647m	37.175ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.866m	14.986ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	10.220s	232.928us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.970s	519.170us	20	20	100.00
		alert_handler_csr_aliasing	4.866m	14.986ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.177m	21.697ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.168m	23.057ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.135m	236.084ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.048m	1.978ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	59.620s	906.498us	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.178m	4.435ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.287m	5.041ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.478m	65.550ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.390m	63.933ms	50	50	100.00
		alert_handler_lpg_stub_clk	53.654m	104.590ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	57.508m	117.986ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.086m	1.609ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.660s	103.544us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.060s	21.445us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	27.560s	456.501us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	27.560s	456.501us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.250s	442.348us	5	5	100.00
		alert_handler_csr_rw	8.970s	519.170us	20	20	100.00
		alert_handler_csr_aliasing	4.866m	14.986ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.190s	703.268us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.250s	442.348us	5	5	100.00
		alert_handler_csr_rw	8.970s	519.170us	20	20	100.00
		alert_handler_csr_aliasing	4.866m	14.986ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.190s	703.268us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.944m	34.655ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.944m	34.655ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.944m	34.655ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.944m	34.655ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	16.130m	51.456ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	2.880s	76.697us	0	5	0.00
		alert_handler_tl_intg_err	1.358m	1.335ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.358m	1.335ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.944m	34.655ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	59.620s	906.498us	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	59.620s	906.498us	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	59.620s	906.498us	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	59.620s	906.498us	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.048m	1.978ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.390m	63.933ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.048m	1.978ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.135m	236.084ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.135m	236.084ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	2.880s	76.697us	0	5	0.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	2.880s	76.697us	0	5	0.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	2.880s	76.697us	0	5	0.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	2.880s	76.697us	0	5	0.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	2.880s	76.697us	0	5	0.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	2.880s	76.697us	0	5	0.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	2.880s	76.697us	0	5	0.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	2.880s	76.697us	0	5	0.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	2.880s	76.697us	0	5	0.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.715h	117.058ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			827	850	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.70	99.86	98.50	90.17	91.94	99.81	97.13	99.48

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
  • Test alert_handler_stress_all_with_rand_reset has 17 failures.

    • 0.alert_handler_stress_all_with_rand_reset.104194117442846369361286300764676357242673383003240521378435978558464090954955
      Line 36853, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 193843839165 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 193843839165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.alert_handler_stress_all_with_rand_reset.60836285420190744474775549374289975537631681454093856330362744331251376723076
      Line 1646, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 980719299 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 980719299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• Offending '(state_q == StateEncodings[esc_state_o])' has 5 failures:
  • Test alert_handler_sec_cm has 5 failures.

    • 0.alert_handler_sec_cm.26308019475437465019246818490337718138024105458460586734656718416374475553708
      Line 273, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest/run.log

            Offending '(state_q == StateEncodings[esc_state_o])'
        UVM_ERROR @  76696506 ps: (alert_handler_esc_timer.sv:429) [ASSERT FAILED] EscStateOut_A
        UVM_INFO @  76696506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.alert_handler_sec_cm.110626869365988975900785639342745827843490470595263377370970133007019076642450
      Line 267, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest/run.log

            Offending '(state_q == StateEncodings[esc_state_o])'
        UVM_ERROR @  11012871 ps: (alert_handler_esc_timer.sv:429) [ASSERT FAILED] EscStateOut_A
        UVM_INFO @  11012871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 3 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
  • Test alert_handler_lpg_stub_clk has 1 failures.

    • 10.alert_handler_lpg_stub_clk.106191889963700325792050794432245805835510967860788205898132240968600940537330
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest/run.log

        Job ID: smart:3e64a546-8bec-480b-8d49-ade3820e1795
      

Past Results

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• 2024.04.24_08.19.08
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• 2024.04.05_04.44.08