ALERT_HANDLER Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.135m	1.056ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.070s	405.586us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	11.120s	489.245us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	4.698m	4.460ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.532m	5.552ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.210s	1.096ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	11.120s	489.245us	20	20	100.00
		alert_handler_csr_aliasing	4.532m	5.552ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.155m	23.645ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.263m	4.964ms	50	50	100.00
V2	entropy	alert_handler_entropy	49.424m	209.225ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.071m	2.842ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.135m	1.056ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.300m	1.347ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.324m	1.775ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.921m	16.191ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.743m	63.192ms	50	50	100.00
		alert_handler_lpg_stub_clk	53.623m	295.093ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.088h	142.645ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.344m	3.895ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.590s	107.778us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.010s	18.885us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	27.720s	1.608ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	27.720s	1.608ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.070s	405.586us	5	5	100.00
		alert_handler_csr_rw	11.120s	489.245us	20	20	100.00
		alert_handler_csr_aliasing	4.532m	5.552ms	5	5	100.00
		alert_handler_same_csr_outstanding	54.350s	8.622ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.070s	405.586us	5	5	100.00
		alert_handler_csr_rw	11.120s	489.245us	20	20	100.00
		alert_handler_csr_aliasing	4.532m	5.552ms	5	5	100.00
		alert_handler_same_csr_outstanding	54.350s	8.622ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.440m	39.642ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.440m	39.642ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.440m	39.642ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.440m	39.642ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.947m	86.185ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	25.070s	3.586ms	5	5	100.00
		alert_handler_tl_intg_err	1.554m	3.584ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.554m	3.584ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.440m	39.642ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.135m	1.056ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.135m	1.056ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.135m	1.056ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.135m	1.056ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.071m	2.842ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.743m	63.192ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.071m	2.842ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	49.424m	209.225ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	49.424m	209.225ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	25.070s	3.586ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	25.070s	3.586ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	25.070s	3.586ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	25.070s	3.586ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	25.070s	3.586ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	25.070s	3.586ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	25.070s	3.586ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	25.070s	3.586ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	25.070s	3.586ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.056h	1.088s	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			829	850	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.69	99.99	98.74	100.00	100.00	100.00	99.38	99.72

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
  • Test alert_handler_stress_all_with_rand_reset has 20 failures.

    • 0.alert_handler_stress_all_with_rand_reset.110951777968682446770716330673933316514301370814731818488493422884087503839542
      Line 59889, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 111881940209 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 111881940209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.alert_handler_stress_all_with_rand_reset.12929168874053822145732979384431162472372286274221103978164077989175870068660
      Line 108459, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1088402744443 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1088402744443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 31.alert_handler_stress_all_with_rand_reset.78537038142134840462521431575923198392312620310277062653945918216199195833975
      Line 11317, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7496158375 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 7496158375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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