ALERT_HANDLER Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: `9f4903e77a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.325m	4.895ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.890s	135.303us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.570s	130.089us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.859m	21.119ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.534m	49.629ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.160s	479.023us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.570s	130.089us	20	20	100.00
		alert_handler_csr_aliasing	4.534m	49.629ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.836m	95.770ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.247m	11.022ms	50	50	100.00
V2	entropy	alert_handler_entropy	46.493m	133.049ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	2.491m	3.841ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.325m	4.895ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.058m	1.976ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.262m	4.449ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.143m	16.339ms	50	50	100.00
V2	lpg	alert_handler_lpg	48.624m	55.776ms	50	50	100.00
		alert_handler_lpg_stub_clk	52.060m	210.546ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.129h	100.097ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	57.330s	8.824ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.320s	50.780us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.080s	25.256us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	31.170s	1.804ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	31.170s	1.804ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.890s	135.303us	5	5	100.00
		alert_handler_csr_rw	9.570s	130.089us	20	20	100.00
		alert_handler_csr_aliasing	4.534m	49.629ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.230s	3.683ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.890s	135.303us	5	5	100.00
		alert_handler_csr_rw	9.570s	130.089us	20	20	100.00
		alert_handler_csr_aliasing	4.534m	49.629ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.230s	3.683ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.631m	5.974ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.631m	5.974ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.631m	5.974ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.631m	5.974ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.149m	17.362ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	14.560s	911.466us	5	5	100.00
		alert_handler_tl_intg_err	1.063m	1.032ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.063m	1.032ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.631m	5.974ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.325m	4.895ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.325m	4.895ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.325m	4.895ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.325m	4.895ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	2.491m	3.841ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	48.624m	55.776ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	2.491m	3.841ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	46.493m	133.049ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	46.493m	133.049ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	14.560s	911.466us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	14.560s	911.466us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	14.560s	911.466us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	14.560s	911.466us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	14.560s	911.466us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	14.560s	911.466us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	14.560s	911.466us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	14.560s	911.466us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	14.560s	911.466us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.718h	138.157ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			828	850	97.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.72	100.00	100.00	100.00	99.38	99.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test alert_handler_stress_all_with_rand_reset has 19 failures.
  - 9.alert_handler_stress_all_with_rand_reset.55657668708479803507387505003344651805458577937723624882941402939673964331288
    Line 18768, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17617032214 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17617032214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.alert_handler_stress_all_with_rand_reset.61298043147656853933725981694931488065246621653727698569780274653302754792191
    Line 3646, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 197255123511 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 197255123511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 15.alert_handler_stress_all_with_rand_reset.31582650058695435127159648582019816845588568771706100944718999917757671097722
    Line 35422, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 132283417555 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 132283417555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.alert_handler_stress_all_with_rand_reset.112261451068853839743620731615649304155975735695619863072693390701216256919764
    Line 164328, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 141209198702 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 141209198702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 36.alert_handler_sig_int_fail.69049701785759714542670038711661496317809928281231825002239267429136409962303
    Line 418, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @  27948196 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @  27948196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9f4903e77a`