ALERT_HANDLER Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.186m	2.423ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.480s	241.006us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.410s	125.107us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	3.974m	12.560ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.786m	4.600ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	11.660s	322.515us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.410s	125.107us	20	20	100.00
		alert_handler_csr_aliasing	4.786m	4.600ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.219m	20.036ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.300m	5.179ms	50	50	100.00
V2	entropy	alert_handler_entropy	51.665m	305.985ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.030m	1.168ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.186m	2.423ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.060m	1.106ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.241m	1.360ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.113m	26.503ms	50	50	100.00
V2	lpg	alert_handler_lpg	53.605m	124.324ms	50	50	100.00
		alert_handler_lpg_stub_clk	53.855m	56.183ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.168h	149.022ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.022m	1.427ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.910s	184.482us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.660s	44.123us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	31.370s	1.693ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	31.370s	1.693ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.480s	241.006us	5	5	100.00
		alert_handler_csr_rw	9.410s	125.107us	20	20	100.00
		alert_handler_csr_aliasing	4.786m	4.600ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.480s	711.139us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.480s	241.006us	5	5	100.00
		alert_handler_csr_rw	9.410s	125.107us	20	20	100.00
		alert_handler_csr_aliasing	4.786m	4.600ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.480s	711.139us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	4.830m	8.870ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	4.830m	8.870ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	4.830m	8.870ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	4.830m	8.870ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.808m	17.193ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	23.050s	539.123us	5	5	100.00
		alert_handler_tl_intg_err	1.420m	1.418ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.420m	1.418ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	4.830m	8.870ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.186m	2.423ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.186m	2.423ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.186m	2.423ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.186m	2.423ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.030m	1.168ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	53.605m	124.324ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.030m	1.168ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	51.665m	305.985ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	51.665m	305.985ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	23.050s	539.123us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	23.050s	539.123us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	23.050s	539.123us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	23.050s	539.123us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	23.050s	539.123us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	23.050s	539.123us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	23.050s	539.123us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	23.050s	539.123us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	23.050s	539.123us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.690h	379.904ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			830	850	97.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.75	100.00	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test alert_handler_stress_all_with_rand_reset has 18 failures.

    • 2.alert_handler_stress_all_with_rand_reset.84669072375052961283163034376708264514215275571744767508211583444454252507135
      Line 2624, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3471154323 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3471154323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.alert_handler_stress_all_with_rand_reset.90745653719429317168341774970370727303639693423559577159661096187069702113775
      Line 440, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 527290346 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 527290346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 6.alert_handler_sig_int_fail.50512252667781929698088680423064731663951373987868449293726042746240402964629
      Line 336, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @  16901185 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @  16901185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 26.alert_handler_stress_all_with_rand_reset.76861416093367521354007132995508306334020683533787184545895061946328107690532
      Line 3854, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6452261459 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 3 [0x3]) reg name: alert_handler_reg_block.classc_state
        UVM_INFO @ 6452261459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.04.16_04.30.33
• 2024.04.05_04.44.08
• 2024.04.03_04.03.04
• 2024.04.01_05.00.05
• 2024.03.29_04.28.58
• 2024.03.27_04.57.27