ALERT_HANDLER Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.136m	2.411ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.220s	110.668us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.490s	495.682us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.000m	5.942ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.679m	1.185ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.430s	152.549us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.490s	495.682us	20	20	100.00
		alert_handler_csr_aliasing	2.679m	1.185ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.399m	10.784ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.052m	5.817ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.045m	225.827ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.204m	8.383ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.136m	2.411ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.002m	19.464ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.092m	4.155ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.794m	15.067ms	50	50	100.00
V2	lpg	alert_handler_lpg	53.037m	234.683ms	50	50	100.00
		alert_handler_lpg_stub_clk	56.739m	95.547ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.039h	199.374ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	55.110s	1.337ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.230s	126.907us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.960s	32.016us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.830s	335.674us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.830s	335.674us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.220s	110.668us	5	5	100.00
		alert_handler_csr_rw	10.490s	495.682us	20	20	100.00
		alert_handler_csr_aliasing	2.679m	1.185ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.370s	1.294ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.220s	110.668us	5	5	100.00
		alert_handler_csr_rw	10.490s	495.682us	20	20	100.00
		alert_handler_csr_aliasing	2.679m	1.185ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.370s	1.294ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.220m	5.872ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.220m	5.872ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.220m	5.872ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.220m	5.872ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.267m	30.898ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	24.150s	842.667us	5	5	100.00
		alert_handler_tl_intg_err	1.233m	909.342us	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.233m	909.342us	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.220m	5.872ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.136m	2.411ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.136m	2.411ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.136m	2.411ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.136m	2.411ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.204m	8.383ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	53.037m	234.683ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.204m	8.383ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.045m	225.827ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.045m	225.827ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	24.150s	842.667us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	24.150s	842.667us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	24.150s	842.667us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	24.150s	842.667us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	24.150s	842.667us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	24.150s	842.667us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	24.150s	842.667us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	24.150s	842.667us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	24.150s	842.667us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.239h	386.041ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			830	850	97.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.64	100.00	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test alert_handler_stress_all_with_rand_reset has 18 failures.

    • 0.alert_handler_stress_all_with_rand_reset.115582157742140794931136826269726030886707914683085600391248251821016266897753
      Line 25110, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 111280323690 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 111280323690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.alert_handler_stress_all_with_rand_reset.24899277736241523212523234838746886589514031623825777123349785617639118697100
      Line 2010, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3843963648 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3843963648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 18.alert_handler_stress_all_with_rand_reset.87561716812699305495188675524957234424228002213549213280445341466763490928892
      Line 117911, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 161081481892 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 161081481892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 42.alert_handler_stress_all_with_rand_reset.112551874256406678861267332532024726352575667483713960039845180001661484843536
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:5ffb5095-0796-49be-8e91-0415a9ca038c
      

Past Results

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