ALERT_HANDLER Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.276m	4.764ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.430s	512.057us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.820s	1.337ms	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.715m	7.419ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.312m	36.030ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.170s	150.013us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.820s	1.337ms	20	20	100.00
		alert_handler_csr_aliasing	4.312m	36.030ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.092m	22.372ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.431m	1.331ms	50	50	100.00
V2	entropy	alert_handler_entropy	51.231m	106.057ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.032m	907.362us	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.276m	4.764ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.285m	5.090ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.318m	4.746ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.409m	60.019ms	50	50	100.00
V2	lpg	alert_handler_lpg	59.692m	254.623ms	50	50	100.00
		alert_handler_lpg_stub_clk	53.987m	399.678ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.121h	69.103ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.501m	2.077ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.260s	108.542us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.860s	20.295us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	28.810s	408.603us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	28.810s	408.603us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.430s	512.057us	5	5	100.00
		alert_handler_csr_rw	9.820s	1.337ms	20	20	100.00
		alert_handler_csr_aliasing	4.312m	36.030ms	5	5	100.00
		alert_handler_same_csr_outstanding	53.200s	4.985ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.430s	512.057us	5	5	100.00
		alert_handler_csr_rw	9.820s	1.337ms	20	20	100.00
		alert_handler_csr_aliasing	4.312m	36.030ms	5	5	100.00
		alert_handler_same_csr_outstanding	53.200s	4.985ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.154m	6.777ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.154m	6.777ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.154m	6.777ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.154m	6.777ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.071m	58.956ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	28.480s	961.488us	5	5	100.00
		alert_handler_tl_intg_err	1.384m	2.389ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.384m	2.389ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.154m	6.777ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.276m	4.764ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.276m	4.764ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.276m	4.764ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.276m	4.764ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.032m	907.362us	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	59.692m	254.623ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.032m	907.362us	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	51.231m	106.057ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	51.231m	106.057ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	28.480s	961.488us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	28.480s	961.488us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	28.480s	961.488us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	28.480s	961.488us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	28.480s	961.488us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	28.480s	961.488us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	28.480s	961.488us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	28.480s	961.488us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	28.480s	961.488us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.384h	403.264ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.68	99.99	98.72	100.00	100.00	100.00	99.38	99.68

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test alert_handler_stress_all_with_rand_reset has 15 failures.
  - 0.alert_handler_stress_all_with_rand_reset.55273714088049072744735073376761438746948678801723904056518565407855242536388
    Line 45801, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44508317382 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 44508317382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.alert_handler_stress_all_with_rand_reset.14055538666265049002514154187098089948076591572246533727401795565397827949905
    Line 7150, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10066641502 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10066641502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state has 2 failures:
- Test alert_handler_sig_int_fail has 2 failures.
  - 2.alert_handler_sig_int_fail.17658094980626667891804003584132452734411510069884011299584793886374934786271
    Line 663, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @  81163246 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 3 [0x3]) reg name: alert_handler_reg_block.classa_state
  UVM_INFO @  81163246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.alert_handler_sig_int_fail.84049293442448295971819025942201249851668193881752478150236960037459197434398
    Line 499, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 1735277240 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 7 [0x7]) reg name: alert_handler_reg_block.classa_state
  UVM_INFO @ 1735277240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 14.alert_handler_stress_all_with_rand_reset.16621895718042808983116432116497743847693963044327583752496222217277108070998
    Line 57658, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 193235137693 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 193235137693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 40.alert_handler_stress_all_with_rand_reset.106655853189066469738780482938592166542003062756906750171543976370978191692463
    Line 88213, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 130952712415 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (117 [0x75] vs 184 [0xb8])
  UVM_INFO @ 130952712415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4fd94db59a`