ae68723071| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.504m | 1.281ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 9.940s | 758.008us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 7.750s | 183.880us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 3.769m | 8.886ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 4.620m | 12.033ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 11.520s | 1.604ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 7.750s | 183.880us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 4.620m | 12.033ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 6.119m | 23.449ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.529m | 9.226ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 57.458m | 52.856ms | 50 | 50 | 100.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.125m | 950.028us | 50 | 50 | 100.00 |
| V2 | clk_skew | alert_handler_smoke | 1.504m | 1.281ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.340m | 2.360ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.135m | 830.294us | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 10.559m | 76.173ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 55.410m | 58.709ms | 49 | 50 | 98.00 |
| alert_handler_lpg_stub_clk | 56.247m | 66.196ms | 50 | 50 | 100.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.068h | 134.089ms | 50 | 50 | 100.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 34.200s | 2.892ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 4.780s | 205.164us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 2.250s | 31.072us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 27.220s | 902.341us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 27.220s | 902.341us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 9.940s | 758.008us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 7.750s | 183.880us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.620m | 12.033ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 42.420s | 2.857ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 9.940s | 758.008us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 7.750s | 183.880us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.620m | 12.033ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 42.420s | 2.857ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 629 | 630 | 99.84 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 5.319m | 9.569ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 5.319m | 9.569ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 5.319m | 9.569ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 5.319m | 9.569ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 17.244m | 17.463ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 2.410s | 17.621us | 0 | 5 | 0.00 |
| alert_handler_tl_intg_err | 1.328m | 5.390ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.328m | 5.390ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 5.319m | 9.569ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.504m | 1.281ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.504m | 1.281ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.504m | 1.281ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.504m | 1.281ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.125m | 950.028us | 50 | 50 | 100.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 55.410m | 58.709ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.125m | 950.028us | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 57.458m | 52.856ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 57.458m | 52.856ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 2.410s | 17.621us | 0 | 5 | 0.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 2.410s | 17.621us | 0 | 5 | 0.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 2.410s | 17.621us | 0 | 5 | 0.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 2.410s | 17.621us | 0 | 5 | 0.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 2.410s | 17.621us | 0 | 5 | 0.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 2.410s | 17.621us | 0 | 5 | 0.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 2.410s | 17.621us | 0 | 5 | 0.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 2.410s | 17.621us | 0 | 5 | 0.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 2.410s | 17.621us | 0 | 5 | 0.00 |
| V2S | TOTAL | 60 | 65 | 92.31 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 2.738h | 447.975ms | 29 | 50 | 58.00 |
| V3 | TOTAL | 29 | 50 | 58.00 | |||
| TOTAL | 823 | 850 | 96.82 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 14 | 93.33 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.64 | 99.86 | 98.50 | 89.82 | 91.94 | 99.81 | 97.13 | 99.44 |
UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
1.alert_handler_stress_all_with_rand_reset.53960534825424497390802039474393731563606974991005809276657859942893913357754
Line 21521, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16451869286 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16451869286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.alert_handler_stress_all_with_rand_reset.99086092060099851997790409042897593612849231133178124417677479117610160665781
Line 63290, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 298598986336 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 298598986336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
Offending '(state_q == StateEncodings[esc_state_o])' has 5 failures:
0.alert_handler_sec_cm.70454651495666795804517295717650426575909918860570951940128169322759791493880
Line 259, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest/run.log
Offending '(state_q == StateEncodings[esc_state_o])'
UVM_ERROR @ 4738188 ps: (alert_handler_esc_timer.sv:429) [ASSERT FAILED] EscStateOut_A
UVM_INFO @ 4738188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.alert_handler_sec_cm.61276579511546963366633245577297498133917184889880894430651282091163411783069
Line 259, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest/run.log
Offending '(state_q == StateEncodings[esc_state_o])'
UVM_ERROR @ 3174798 ps: (alert_handler_esc_timer.sv:429) [ASSERT FAILED] EscStateOut_A
UVM_INFO @ 3174798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
0.alert_handler_stress_all_with_rand_reset.95018035132392200419035311419641341675328050028434789916235371936793381537544
Line 40733, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 56732764435 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (299 [0x12b] vs 402 [0x192])
UVM_INFO @ 56732764435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
21.alert_handler_lpg.18057288551818837130068071635750127317684335509541338811792486881283363450451
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_lpg/latest/run.log
Job ID: smart:fac81276-a3f0-47e9-9c66-b96d1213b5dd
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
22.alert_handler_stress_all_with_rand_reset.6243702151676415613456761498578749035153793745784823580362085625003602431478
Line 585, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4304361252 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 4304361252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---