ALERT_HANDLER Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.258m	4.351ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	12.100s	537.796us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	11.040s	248.612us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.106m	9.010ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.264m	13.477ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.960s	558.321us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	11.040s	248.612us	20	20	100.00
		alert_handler_csr_aliasing	4.264m	13.477ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.473m	6.373ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.377m	4.656ms	50	50	100.00
V2	entropy	alert_handler_entropy	51.574m	108.859ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.148m	4.219ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.258m	4.351ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.281m	3.432ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.241m	4.724ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.746m	63.523ms	50	50	100.00
V2	lpg	alert_handler_lpg	52.383m	106.994ms	50	50	100.00
		alert_handler_lpg_stub_clk	56.183m	126.129ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.085h	587.211ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	51.190s	2.182ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.190s	87.868us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.710s	13.904us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.620s	298.367us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.620s	298.367us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	12.100s	537.796us	5	5	100.00
		alert_handler_csr_rw	11.040s	248.612us	20	20	100.00
		alert_handler_csr_aliasing	4.264m	13.477ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.010s	3.903ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	12.100s	537.796us	5	5	100.00
		alert_handler_csr_rw	11.040s	248.612us	20	20	100.00
		alert_handler_csr_aliasing	4.264m	13.477ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.010s	3.903ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.872m	5.536ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.872m	5.536ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.872m	5.536ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.872m	5.536ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	17.918m	115.430ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.880s	6.492us	0	5	0.00
		alert_handler_tl_intg_err	43.890s	7.453ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	43.890s	7.453ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.872m	5.536ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.258m	4.351ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.258m	4.351ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.258m	4.351ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.258m	4.351ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.148m	4.219ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	52.383m	106.994ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.148m	4.219ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	51.574m	108.859ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	51.574m	108.859ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.880s	6.492us	0	5	0.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.880s	6.492us	0	5	0.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.880s	6.492us	0	5	0.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.880s	6.492us	0	5	0.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.880s	6.492us	0	5	0.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.880s	6.492us	0	5	0.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.880s	6.492us	0	5	0.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.880s	6.492us	0	5	0.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.880s	6.492us	0	5	0.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.297h	416.101ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			829	850	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.68	99.86	98.48	89.99	91.94	99.81	97.13	99.52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
  • Test alert_handler_stress_all_with_rand_reset has 15 failures.

    • 0.alert_handler_stress_all_with_rand_reset.54924294438437953413170016855263396835745012279305696148930760285046408848570
      Line 6508, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12388536048 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12388536048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.alert_handler_stress_all_with_rand_reset.24325535815620908996108579234187815583636847649552599163324290712636814879283
      Line 116735, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 171583788972 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 171583788972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• Offending '(state_q == StateEncodings[esc_state_o])' has 5 failures:
  • Test alert_handler_sec_cm has 5 failures.

    • 0.alert_handler_sec_cm.42790718026497184078861436212939968492246330138493189134708781546108828710459
      Line 259, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest/run.log

            Offending '(state_q == StateEncodings[esc_state_o])'
        UVM_ERROR @   1996361 ps: (alert_handler_esc_timer.sv:429) [ASSERT FAILED] EscStateOut_A
        UVM_INFO @   1996361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.alert_handler_sec_cm.80082045360768541489472531528723128458747735011941975716798870811860543202494
      Line 266, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest/run.log

            Offending '(state_q == StateEncodings[esc_state_o])'
        UVM_ERROR @  48558725 ps: (alert_handler_esc_timer.sv:429) [ASSERT FAILED] EscStateOut_A
        UVM_INFO @  48558725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 3 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 36.alert_handler_stress_all_with_rand_reset.23140871525966766969183459932228829526349481173129010551204466067042638562141
      Line 125406, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 89775291859 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 89775291859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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