ALERT_HANDLER Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.271m	2.332ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.560s	104.221us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.350s	131.563us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.719m	16.477ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.259m	18.527ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.740s	71.358us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.350s	131.563us	20	20	100.00
		alert_handler_csr_aliasing	5.259m	18.527ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.450m	20.351ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.305m	7.537ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.329m	63.950ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.239m	1.167ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.271m	2.332ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.190m	7.175ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.261m	1.315ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.685m	33.849ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.744m	402.482ms	50	50	100.00
		alert_handler_lpg_stub_clk	54.086m	50.072ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.065h	121.966ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.134m	1.684ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.880s	45.301us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.710s	9.690us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	26.500s	719.250us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	26.500s	719.250us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.560s	104.221us	5	5	100.00
		alert_handler_csr_rw	10.350s	131.563us	20	20	100.00
		alert_handler_csr_aliasing	5.259m	18.527ms	5	5	100.00
		alert_handler_same_csr_outstanding	59.240s	761.966us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.560s	104.221us	5	5	100.00
		alert_handler_csr_rw	10.350s	131.563us	20	20	100.00
		alert_handler_csr_aliasing	5.259m	18.527ms	5	5	100.00
		alert_handler_same_csr_outstanding	59.240s	761.966us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.670m	7.192ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.670m	7.192ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.670m	7.192ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.670m	7.192ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.339m	14.758ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.740s	12.477us	0	5	0.00
		alert_handler_tl_intg_err	1.606m	1.359ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.606m	1.359ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.670m	7.192ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.271m	2.332ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.271m	2.332ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.271m	2.332ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.271m	2.332ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.239m	1.167ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.744m	402.482ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.239m	1.167ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.329m	63.950ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.329m	63.950ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.740s	12.477us	0	5	0.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.740s	12.477us	0	5	0.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.740s	12.477us	0	5	0.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.740s	12.477us	0	5	0.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.740s	12.477us	0	5	0.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.740s	12.477us	0	5	0.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.740s	12.477us	0	5	0.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.740s	12.477us	0	5	0.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.740s	12.477us	0	5	0.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.309h	437.389ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.71	99.86	98.49	90.17	91.94	99.81	97.13	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:

  • Test alert_handler_stress_all_with_rand_reset has 10 failures.

    • 2.alert_handler_stress_all_with_rand_reset.69642955065435430332489707277142857095074829815033917655244180377525453387797
      Line 13384, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18928272430 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 18928272430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.alert_handler_stress_all_with_rand_reset.68191703806974483032916873675663570553507304202546332869726160958343003542145
      Line 8724, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8014644197 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8014644197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• Offending '(state_q == StateEncodings[esc_state_o])' has 5 failures:

  • Test alert_handler_sec_cm has 5 failures.

    • 0.alert_handler_sec_cm.31763719858406527270145284890029349167740188704049152690139272852766790368921
      Line 261, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest/run.log

            Offending '(state_q == StateEncodings[esc_state_o])'
        UVM_ERROR @  12476781 ps: (alert_handler_esc_timer.sv:429) [ASSERT FAILED] EscStateOut_A
        UVM_INFO @  12476781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.alert_handler_sec_cm.17151328140162036789268804134414147267376184013800473642934472020622425100577
      Line 259, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest/run.log

            Offending '(state_q == StateEncodings[esc_state_o])'
        UVM_ERROR @   8978039 ps: (alert_handler_esc_timer.sv:429) [ASSERT FAILED] EscStateOut_A
        UVM_INFO @   8978039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 3 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 30.alert_handler_stress_all_with_rand_reset.96276706048857098310744702407898937873307358757683498368631002571340618569065
      Line 1242, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2688983750 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2688983750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.alert_handler_stress_all_with_rand_reset.68577524793111665042969269751618103344514447975615590242463020730370258938444
      Line 68538, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16347048434 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 16347048434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 24.alert_handler_sig_int_fail.75786756775834657267933161084460786574243584328286812188202949816947205004641
      Line 663, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @  70296398 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 3 [0x3]) reg name: alert_handler_reg_block.classb_state
        UVM_INFO @  70296398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_entropy has 1 failures.

    • 43.alert_handler_entropy.88888455256193333605730211497721894434696697799505338017241879408455457785416
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_entropy/latest/run.log

        Job ID: smart:16bd6237-31c0-44c7-8c33-e0d74be7373a
      

Past Results

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