ALERT_HANDLER Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.109m	4.453ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.730s	501.137us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.330s	123.121us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.505m	30.491ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.020m	3.837ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.040s	294.265us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.330s	123.121us	20	20	100.00
		alert_handler_csr_aliasing	4.020m	3.837ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.788m	5.616ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.038m	1.124ms	50	50	100.00
V2	entropy	alert_handler_entropy	52.558m	86.535ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.129m	991.727us	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.109m	4.453ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.197m	4.404ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.218m	4.649ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.916m	15.817ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.179m	116.269ms	50	50	100.00
		alert_handler_lpg_stub_clk	52.215m	300.736ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.070h	274.949ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.455m	2.308ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.630s	56.621us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.650s	12.727us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	20.990s	345.238us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	20.990s	345.238us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.730s	501.137us	5	5	100.00
		alert_handler_csr_rw	8.330s	123.121us	20	20	100.00
		alert_handler_csr_aliasing	4.020m	3.837ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.410s	1.446ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.730s	501.137us	5	5	100.00
		alert_handler_csr_rw	8.330s	123.121us	20	20	100.00
		alert_handler_csr_aliasing	4.020m	3.837ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.410s	1.446ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.800m	4.586ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.800m	4.586ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.800m	4.586ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.800m	4.586ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.170m	67.759ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	28.140s	599.801us	5	5	100.00
		alert_handler_tl_intg_err	1.363m	4.913ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.363m	4.913ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.800m	4.586ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.109m	4.453ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.109m	4.453ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.109m	4.453ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.109m	4.453ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.129m	991.727us	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.179m	116.269ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.129m	991.727us	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	52.558m	86.535ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	52.558m	86.535ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	28.140s	599.801us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	28.140s	599.801us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	28.140s	599.801us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	28.140s	599.801us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	28.140s	599.801us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	28.140s	599.801us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	28.140s	599.801us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	28.140s	599.801us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	28.140s	599.801us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.586h	98.371ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			830	850	97.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.68	100.00	100.00	100.00	99.38	99.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test alert_handler_stress_all_with_rand_reset has 16 failures.
  - 2.alert_handler_stress_all_with_rand_reset.68526904763384316423657455781166739228655774495880370192273829046771794663275
    Line 5439, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4776739636 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4776739636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.alert_handler_stress_all_with_rand_reset.100489755536147099653928074376753787007981129687709030635656853753160245831363
    Line 71369, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 125677201022 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 125677201022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 6.alert_handler_stress_all_with_rand_reset.84600840064252323374328383512035483362595444033800061104168807193005031345785
    Line 39125, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47664527715 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 47664527715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 16.alert_handler_sig_int_fail.34413545185217706079069289804760240544650184861547128128510549522187043849777
    Line 458, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @  42841628 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (192 [0xc0] vs 305 [0x131])
  UVM_INFO @  42841628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 26.alert_handler_stress_all_with_rand_reset.15350458246429083857673136725435929139707591060805928867427502473975599759275
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:31dabbc1-b756-4a12-b2c4-de0e512e0c84
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 34.alert_handler_stress_all_with_rand_reset.103066569505646615831934988917909587456500671035966505047841478974552837987702
    Line 667, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 927532505 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 927532505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d0c52cdadd`