ALERT_HANDLER Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.178m	1.251ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	11.120s	152.055us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.130s	120.343us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.312m	14.263ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.920m	18.006ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.310s	154.477us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.130s	120.343us	20	20	100.00
		alert_handler_csr_aliasing	4.920m	18.006ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.483m	24.974ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.361m	8.854ms	50	50	100.00
V2	entropy	alert_handler_entropy	54.216m	56.297ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.024m	909.719us	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.178m	1.251ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.134m	5.628ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.020m	2.276ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.467m	43.286ms	50	50	100.00
V2	lpg	alert_handler_lpg	59.239m	120.095ms	50	50	100.00
		alert_handler_lpg_stub_clk	50.372m	715.119ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.033h	69.429ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	44.620s	1.159ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.660s	215.202us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.760s	16.028us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	28.730s	1.841ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	28.730s	1.841ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	11.120s	152.055us	5	5	100.00
		alert_handler_csr_rw	9.130s	120.343us	20	20	100.00
		alert_handler_csr_aliasing	4.920m	18.006ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.140s	700.490us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	11.120s	152.055us	5	5	100.00
		alert_handler_csr_rw	9.130s	120.343us	20	20	100.00
		alert_handler_csr_aliasing	4.920m	18.006ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.140s	700.490us	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.622m	6.071ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.622m	6.071ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.622m	6.071ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.622m	6.071ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	17.264m	16.625ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	23.050s	432.722us	5	5	100.00
		alert_handler_tl_intg_err	1.434m	5.178ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.434m	5.178ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.622m	6.071ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.178m	1.251ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.178m	1.251ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.178m	1.251ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.178m	1.251ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.024m	909.719us	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	59.239m	120.095ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.024m	909.719us	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	54.216m	56.297ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	54.216m	56.297ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	23.050s	432.722us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	23.050s	432.722us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	23.050s	432.722us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	23.050s	432.722us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	23.050s	432.722us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	23.050s	432.722us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	23.050s	432.722us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	23.050s	432.722us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	23.050s	432.722us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.495h	401.624ms	40	50	80.00
V3		TOTAL			40	50	80.00
		TOTAL			840	850	98.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.69	100.00	100.00	100.00	99.38	99.52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
  • Test alert_handler_stress_all_with_rand_reset has 9 failures.

    • 3.alert_handler_stress_all_with_rand_reset.3567284146671909090483892252791194210827891391303090773179451441905317449662
      Line 23860, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22935681041 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22935681041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.alert_handler_stress_all_with_rand_reset.42826783296631646781196466153439656462093307543894410899700402493672068135550
      Line 24172, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17423563007 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17423563007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 37.alert_handler_stress_all_with_rand_reset.71027748467831546704089005501975899193942338073212889799059589170113067206817
      Line 28430, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24396035818 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 24396035818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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