ALERT_HANDLER Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	2.380m	1.300ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	17.650s	754.487us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	14.750s	492.854us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.218m	30.827ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	6.502m	9.574ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	24.080s	309.112us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	14.750s	492.854us	20	20	100.00
		alert_handler_csr_aliasing	6.502m	9.574ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.141m	10.524ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.572m	10.764ms	50	50	100.00
V2	entropy	alert_handler_entropy	54.641m	110.376ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.475m	3.372ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	2.380m	1.300ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.534m	4.206ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.759m	2.576ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	15.974m	17.518ms	50	50	100.00
V2	lpg	alert_handler_lpg	59.201m	118.158ms	48	50	96.00
		alert_handler_lpg_stub_clk	57.837m	227.166ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	57.314m	91.282ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.467m	5.270ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	8.030s	246.833us	20	20	100.00
V2	intr_test	alert_handler_intr_test	3.460s	28.822us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	35.900s	311.384us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	35.900s	311.384us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	17.650s	754.487us	5	5	100.00
		alert_handler_csr_rw	14.750s	492.854us	20	20	100.00
		alert_handler_csr_aliasing	6.502m	9.574ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.307m	2.986ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	17.650s	754.487us	5	5	100.00
		alert_handler_csr_rw	14.750s	492.854us	20	20	100.00
		alert_handler_csr_aliasing	6.502m	9.574ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.307m	2.986ms	20	20	100.00
V2		TOTAL			625	630	99.21
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	9.142m	8.535ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	9.142m	8.535ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	9.142m	8.535ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	9.142m	8.535ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.311m	93.564ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	38.040s	432.796us	5	5	100.00
		alert_handler_tl_intg_err	2.010m	13.212ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	2.010m	13.212ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	9.142m	8.535ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	2.380m	1.300ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	2.380m	1.300ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	2.380m	1.300ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	2.380m	1.300ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.475m	3.372ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	59.201m	118.158ms	48	50	96.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.475m	3.372ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	54.641m	110.376ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	54.641m	110.376ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	38.040s	432.796us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	38.040s	432.796us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	38.040s	432.796us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	38.040s	432.796us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	38.040s	432.796us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	38.040s	432.796us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	38.040s	432.796us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	38.040s	432.796us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	38.040s	432.796us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	12.632m	25.858ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			822	850	96.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	11	73.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.99	98.69	97.06	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test alert_handler_stress_all_with_rand_reset has 22 failures.

    • 0.alert_handler_stress_all_with_rand_reset.54107862050467527696270112053326311317378552165659540101813008528368049691884
      Line 986, in log /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4429226893 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4429226893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.alert_handler_stress_all_with_rand_reset.98647337443581493430412437903155548198408443481762249067315336301538862155054
      Line 3268, in log /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42117341403 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 42117341403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• Job timed out after * minutes has 3 failures:

  • Test alert_handler_lpg has 2 failures.

    • 1.alert_handler_lpg.87561701293416762390927049188141220191036824242083172575999283957035639687554
      Log /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_lpg/latest/run.log

        Job timed out after 60 minutes
      

    • 37.alert_handler_lpg.113825919143340858502317138988751320267495304977080534510653923421282196544449
      Log /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_lpg/latest/run.log

        Job timed out after 60 minutes
      

  • Test alert_handler_entropy has 1 failures.

    • 39.alert_handler_entropy.52132248837532194592419981098423938927983847801488836280842800334129921547010
      Log /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_entropy/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 3.alert_handler_stress_all_with_rand_reset.71133326494230441041279040886102806682657376513741068337924988528106053561386
      Line 11958, in log /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6018224596 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 6018224596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 8.alert_handler_sig_int_fail.77332560687287978655539830925542888329779644221310826022221585694731342096109
      Line 231, in log /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 147052726 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 5 [0x5]) reg name: alert_handler_reg_block.classc_state
        UVM_INFO @ 147052726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 12.alert_handler_stress_all.23120700741666262341684392306041362183157969395535241171262580206028080911734
      Line 49243, in log /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 442234143741 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 442234143741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.09.25_11.05.58
• 2024.09.19_09.09.32
• 2024.09.12_10.21.11
• 2024.09.10_08.15.52
• 2024.09.05_04.25.32
• 2024.09.02_11.35.09