ALERT_HANDLER Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.188m	2.800ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.640s	503.652us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	11.690s	128.249us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	10.259m	57.086ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.193m	9.011ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	16.860s	213.999us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	11.690s	128.249us	20	20	100.00
		alert_handler_csr_aliasing	5.193m	9.011ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.257m	23.246ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.431m	2.203ms	50	50	100.00
V2	entropy	alert_handler_entropy	49.971m	92.090ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.318m	848.988us	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.188m	2.800ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.568m	1.250ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.363m	930.102us	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.695m	15.388ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.110m	68.530ms	49	50	98.00
		alert_handler_lpg_stub_clk	51.859m	82.737ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.230h	82.320ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.252m	3.894ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	7.130s	178.255us	20	20	100.00
V2	intr_test	alert_handler_intr_test	3.590s	48.916us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	28.930s	4.343ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	28.930s	4.343ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.640s	503.652us	5	5	100.00
		alert_handler_csr_rw	11.690s	128.249us	20	20	100.00
		alert_handler_csr_aliasing	5.193m	9.011ms	5	5	100.00
		alert_handler_same_csr_outstanding	55.130s	2.534ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.640s	503.652us	5	5	100.00
		alert_handler_csr_rw	11.690s	128.249us	20	20	100.00
		alert_handler_csr_aliasing	5.193m	9.011ms	5	5	100.00
		alert_handler_same_csr_outstanding	55.130s	2.534ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.723m	19.163ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.723m	19.163ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.723m	19.163ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.723m	19.163ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.410m	66.195ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	36.260s	7.276ms	5	5	100.00
		alert_handler_tl_intg_err	1.618m	1.835ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.618m	1.835ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.723m	19.163ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.188m	2.800ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.188m	2.800ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.188m	2.800ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.188m	2.800ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.318m	848.988us	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.110m	68.530ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.318m	848.988us	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	49.971m	92.090ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	49.971m	92.090ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	36.260s	7.276ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	36.260s	7.276ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	36.260s	7.276ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	36.260s	7.276ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	36.260s	7.276ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	36.260s	7.276ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	36.260s	7.276ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	36.260s	7.276ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	36.260s	7.276ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	9.230m	27.554ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			828	850	97.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.22	99.99	98.64	97.06	100.00	100.00	99.38	99.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

  • Test alert_handler_stress_all_with_rand_reset has 17 failures.

    • 7.alert_handler_stress_all_with_rand_reset.33648029308341242171105318006022253334613932855990149818503544423472364208663
      Line 3376, in log /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3114696032 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3114696032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.alert_handler_stress_all_with_rand_reset.58422049892424422569895232790379082640101723232270472330606583400141612422983
      Line 1649, in log /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5621100053 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5621100053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:

  • Test alert_handler_stress_all_with_rand_reset has 3 failures.

    • 12.alert_handler_stress_all_with_rand_reset.3583652403450624043414388470981076950661691841364432266626809082458130994545
      Line 12794, in log /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3430967334 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3430967334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 28.alert_handler_stress_all_with_rand_reset.27499903123290188211137521001017451693214951615818963401620688710654167557618
      Line 2556, in log /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9753178979 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 9753178979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 19.alert_handler_stress_all.30657365218498743397478453382985859176951217854890199782493159238991450545255
      Line 70167, in log /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 107313321334 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 107313321334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test alert_handler_lpg has 1 failures.

    • 42.alert_handler_lpg.69002455153129358703058670437908621426821208563940488272366176701413555812622
      Log /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_lpg/latest/run.log

        Job timed out after 60 minutes
      

Past Results

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• 2024.09.19_09.09.32
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