ALERT_HANDLER Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.651m	1.157ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	15.440s	129.870us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	13.520s	961.865us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	13.983m	28.477ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	6.793m	12.777ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	19.530s	270.606us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	13.520s	961.865us	20	20	100.00
		alert_handler_csr_aliasing	6.793m	12.777ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.906m	7.254ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.514m	2.272ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.316m	394.263ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.616m	2.296ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.651m	1.157ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.419m	4.797ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.588m	1.029ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	14.348m	29.962ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.818m	56.052ms	49	50	98.00
		alert_handler_lpg_stub_clk	56.749m	71.529ms	48	50	96.00
V2	stress_all	alert_handler_stress_all	1.242h	139.641ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.215m	1.175ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	6.370s	91.314us	20	20	100.00
V2	intr_test	alert_handler_intr_test	6.110s	73.990us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	35.960s	1.148ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	35.960s	1.148ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	15.440s	129.870us	5	5	100.00
		alert_handler_csr_rw	13.520s	961.865us	20	20	100.00
		alert_handler_csr_aliasing	6.793m	12.777ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.201m	1.308ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	15.440s	129.870us	5	5	100.00
		alert_handler_csr_rw	13.520s	961.865us	20	20	100.00
		alert_handler_csr_aliasing	6.793m	12.777ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.201m	1.308ms	20	20	100.00
V2		TOTAL			626	630	99.37
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	10.242m	22.181ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	10.242m	22.181ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	10.242m	22.181ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	10.242m	22.181ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	23.181m	47.209ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.246m	1.109ms	5	5	100.00
		alert_handler_tl_intg_err	2.050m	2.591ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	2.050m	2.591ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	10.242m	22.181ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.651m	1.157ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.651m	1.157ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.651m	1.157ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.651m	1.157ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.616m	2.296ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.818m	56.052ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.616m	2.296ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.316m	394.263ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.316m	394.263ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.246m	1.109ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.246m	1.109ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.246m	1.109ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.246m	1.109ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.246m	1.109ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.246m	1.109ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.246m	1.109ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.246m	1.109ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.246m	1.109ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	11.188m	19.785ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			822	850	96.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.23	99.99	98.74	97.09	100.00	100.00	99.38	99.40

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test alert_handler_stress_all_with_rand_reset has 23 failures.

    • 5.alert_handler_stress_all_with_rand_reset.59899642435402522883423444580425721439119016696861243125998519816265730721280
      Line 821, in log /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1174924692 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1174924692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.alert_handler_stress_all_with_rand_reset.4982422508959881143683806185832170202867395903716043434894291147133184823480
      Line 1227, in log /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4203254278 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4203254278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• Job timed out after * minutes has 3 failures:

  • Test alert_handler_lpg_stub_clk has 2 failures.

    • 36.alert_handler_lpg_stub_clk.40388181670983812207184900465524436542614933392444523691668282828804003896071
      Log /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest/run.log

        Job timed out after 60 minutes
      

    • 38.alert_handler_lpg_stub_clk.50139805580630470069020716623942776701004592821350041078756070620657375515926
      Log /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest/run.log

        Job timed out after 60 minutes
      

  • Test alert_handler_lpg has 1 failures.

    • 45.alert_handler_lpg.3732913637058372076011114778410675506420951375559660205200704104348909817336
      Log /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_lpg/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 14.alert_handler_stress_all_with_rand_reset.13683883725110629508355589237538792154389482547115325766956084090787354349633
      Line 4353, in log /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1377813763 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1377813763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 20.alert_handler_stress_all.99262688095927483146849764185338124150789364839617212511612362813591474466998
      Line 96266, in log /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 46995600747 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 6 [0x6]) reg name: alert_handler_reg_block.classb_state
        UVM_INFO @ 46995600747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.10.04_00.46.53
• 2024.09.25_11.05.58
• 2024.09.19_09.09.32
• 2024.09.12_10.21.11
• 2024.09.10_08.15.52
• 2024.09.05_04.25.32