ALERT_HANDLER Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.614m	3.068ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	15.870s	138.909us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	14.650s	1.085ms	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.852m	8.803ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.810m	4.256ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	19.940s	603.358us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	14.650s	1.085ms	20	20	100.00
		alert_handler_csr_aliasing	4.810m	4.256ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	7.275m	5.038ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.912m	5.835ms	50	50	100.00
V2	entropy	alert_handler_entropy	51.848m	163.372ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.604m	3.642ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.614m	3.068ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.643m	1.107ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.919m	2.585ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.956m	12.170ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.360m	61.358ms	50	50	100.00
		alert_handler_lpg_stub_clk	55.164m	245.475ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.371h	316.167ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.120m	1.370ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	7.020s	266.367us	20	20	100.00
V2	intr_test	alert_handler_intr_test	3.670s	30.850us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	36.660s	2.424ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	36.660s	2.424ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	15.870s	138.909us	5	5	100.00
		alert_handler_csr_rw	14.650s	1.085ms	20	20	100.00
		alert_handler_csr_aliasing	4.810m	4.256ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.085m	662.508us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	15.870s	138.909us	5	5	100.00
		alert_handler_csr_rw	14.650s	1.085ms	20	20	100.00
		alert_handler_csr_aliasing	4.810m	4.256ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.085m	662.508us	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.604m	11.221ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.604m	11.221ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.604m	11.221ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.604m	11.221ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	25.317m	20.930ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	46.460s	475.333us	5	5	100.00
		alert_handler_tl_intg_err	1.788m	895.512us	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.788m	895.512us	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.604m	11.221ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.614m	3.068ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.614m	3.068ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.614m	3.068ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.614m	3.068ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.604m	3.642ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.360m	61.358ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.604m	3.642ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	51.848m	163.372ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	51.848m	163.372ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	46.460s	475.333us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	46.460s	475.333us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	46.460s	475.333us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	46.460s	475.333us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	46.460s	475.333us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	46.460s	475.333us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	46.460s	475.333us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	46.460s	475.333us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	46.460s	475.333us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	11.926m	18.876ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			837	850	98.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.23	99.99	98.75	97.09	100.00	100.00	99.38	99.40

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:
  • Test alert_handler_stress_all_with_rand_reset has 12 failures.

    • 6.alert_handler_stress_all_with_rand_reset.91795409424174202601286749649182438739695693202674398489892424391688776615868
      Line 4197, in log /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1288105524 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1288105524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.alert_handler_stress_all_with_rand_reset.41836444203829245992756258648418530944584442492435412963842840931851131220473
      Line 735, in log /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8790769906 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8790769906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 14.alert_handler_stress_all_with_rand_reset.69839936643983095988180160071806808344544936996653736994548987897891416853476
      Line 4336, in log /workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3852422843 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 3852422843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.09.19_09.09.32
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• 2024.09.10_08.15.52
• 2024.09.05_04.25.32
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