ALERT_HANDLER Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.444m	1.113ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	16.370s	192.534us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	14.900s	123.191us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.222m	9.190ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	6.040m	4.104ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	27.670s	194.618us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	14.900s	123.191us	20	20	100.00
		alert_handler_csr_aliasing	6.040m	4.104ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.725m	5.765ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.704m	4.353ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.669m	227.917ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.439m	1.151ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.444m	1.113ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.455m	2.453ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.542m	1.135ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.391m	14.037ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.745m	693.217ms	49	50	98.00
		alert_handler_lpg_stub_clk	49.698m	190.118ms	48	50	96.00
V2	stress_all	alert_handler_stress_all	1.201h	74.075ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	38.700s	1.277ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	7.220s	210.943us	20	20	100.00
V2	intr_test	alert_handler_intr_test	3.320s	26.769us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	31.040s	289.372us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	31.040s	289.372us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	16.370s	192.534us	5	5	100.00
		alert_handler_csr_rw	14.900s	123.191us	20	20	100.00
		alert_handler_csr_aliasing	6.040m	4.104ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.217m	678.230us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	16.370s	192.534us	5	5	100.00
		alert_handler_csr_rw	14.900s	123.191us	20	20	100.00
		alert_handler_csr_aliasing	6.040m	4.104ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.217m	678.230us	20	20	100.00
V2		TOTAL			626	630	99.37
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.274m	5.072ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.274m	5.072ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.274m	5.072ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.274m	5.072ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	22.080m	153.745ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	32.780s	1.610ms	5	5	100.00
		alert_handler_tl_intg_err	1.829m	2.145ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.829m	2.145ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.274m	5.072ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.444m	1.113ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.444m	1.113ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.444m	1.113ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.444m	1.113ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.439m	1.151ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.745m	693.217ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.439m	1.151ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.669m	227.917ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.669m	227.917ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	32.780s	1.610ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	32.780s	1.610ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	32.780s	1.610ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	32.780s	1.610ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	32.780s	1.610ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	32.780s	1.610ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	32.780s	1.610ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	32.780s	1.610ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	32.780s	1.610ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	10.086m	4.938ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			828	850	97.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.99	98.66	97.09	100.00	100.00	99.38	99.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test alert_handler_stress_all_with_rand_reset has 16 failures.
  - 3.alert_handler_stress_all_with_rand_reset.113258052681418848760968987897462404246537542504684717602488208038538325473535
    Line 2647, in log /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2279651568 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2279651568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.alert_handler_stress_all_with_rand_reset.47190926381757616335328083542229588361144943493012160466612556178623722011478
    Line 1728, in log /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5658139412 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5658139412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
Job timed out after * minutes has 2 failures:
- Test alert_handler_lpg_stub_clk has 2 failures.
  - 10.alert_handler_lpg_stub_clk.36665300385683793965166003937890873742446874036472931007539209336658948054205
    Log /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest/run.log
```
  Job timed out after 60 minutes
```
  - 32.alert_handler_lpg_stub_clk.32489497332310315515992933897271325624249706842921964929013328610308560233863
    Log /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (alert_handler_scoreboard.sv:587) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] ==gmv(ral.loc_alert_cause[i]) (* [] vs * [])` has 1 failures:
- Test alert_handler_lpg has 1 failures.
  - 5.alert_handler_lpg.115716621966057836858766928360278893475355971494035831654969689386250434783316
    Line 229, in log /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/5.alert_handler_lpg/latest/run.log
```
  UVM_ERROR @ 228110995 ps: (alert_handler_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 228110995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 18.alert_handler_stress_all_with_rand_reset.98097913456048843279366194723887207663119327252398017047371328153388609565630
    Line 1236, in log /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 935720282 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 935720282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 26.alert_handler_sig_int_fail.30959622401138883517929232927269642999379121545439362799061506617838812516900
    Line 314, in log /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 175157907 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 175157907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 43.alert_handler_stress_all_with_rand_reset.92406342174098066768162914389238271559979482387613725637303131946820213896295
    Line 6733, in log /workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1753318900 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1753318900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `7e34e67ade`